[Elua-svn] r371 - in branches/eagle_mmc: . doc doc/en doc/luadoc doc/pt doc/wb doc/wb_img docs inc inc/newlib romfs src src/lua src/modules src/newlib src/platform src/platform/at91sam7x src/platform/avr32 src/platform/i386 src/platform/lm3s src/platform/lpc288x src/platform/sim src/platform/stm32 src/platform/stm32/FWLib src/platform/stm32/FWLib/library/inc src/platform/stm32/FWLib/library/src src/platform/str7 src/platform/str9 test
jbsnyder at BerliOS
jbsnyder at mail.berlios.de
Thu Jul 30 20:11:29 CEST 2009
Author: jbsnyder
Date: 2009-07-30 20:10:13 +0200 (Thu, 30 Jul 2009)
New Revision: 371
Added:
branches/eagle_mmc/doc/build_dist_doc.sh
branches/eagle_mmc/doc/builddoc.lua
branches/eagle_mmc/doc/en/arch.html
branches/eagle_mmc/doc/en/arch_coding.html
branches/eagle_mmc/doc/en/arch_con_term.html
branches/eagle_mmc/doc/en/arch_ltr.html
branches/eagle_mmc/doc/en/arch_newport.html
branches/eagle_mmc/doc/en/arch_overview.html
branches/eagle_mmc/doc/en/arch_platform.html
branches/eagle_mmc/doc/en/arch_romfs.html
branches/eagle_mmc/doc/en/arch_tcpip.html
branches/eagle_mmc/doc/en/dl_binaries.html
branches/eagle_mmc/doc/en/dl_old.html
branches/eagle_mmc/doc/en/dl_sources.html
branches/eagle_mmc/doc/en/doc.html
branches/eagle_mmc/doc/en/forum.html
branches/eagle_mmc/doc/en/installing.html
branches/eagle_mmc/doc/en/installing_at91sam7x.html
branches/eagle_mmc/doc/en/installing_avr32.html
branches/eagle_mmc/doc/en/installing_i386.html
branches/eagle_mmc/doc/en/installing_lm3s.html
branches/eagle_mmc/doc/en/installing_lpc2888.html
branches/eagle_mmc/doc/en/installing_stm32.html
branches/eagle_mmc/doc/en/installing_str7.html
branches/eagle_mmc/doc/en/installing_str9.html
branches/eagle_mmc/doc/en/refman_gen.html
branches/eagle_mmc/doc/en/toolchains.html
branches/eagle_mmc/doc/luadoc/
branches/eagle_mmc/doc/luadoc/arch_platform_adc.lua
branches/eagle_mmc/doc/luadoc/arch_platform_cpu.lua
branches/eagle_mmc/doc/luadoc/arch_platform_eth.lua
branches/eagle_mmc/doc/luadoc/arch_platform_ll.lua
branches/eagle_mmc/doc/luadoc/arch_platform_pio.lua
branches/eagle_mmc/doc/luadoc/arch_platform_pwm.lua
branches/eagle_mmc/doc/luadoc/arch_platform_spi.lua
branches/eagle_mmc/doc/luadoc/arch_platform_timers.lua
branches/eagle_mmc/doc/luadoc/arch_platform_uart.lua
branches/eagle_mmc/doc/luadoc/refman_gen_adc.lua
branches/eagle_mmc/doc/luadoc/refman_gen_bit.lua
branches/eagle_mmc/doc/luadoc/refman_gen_cpu.lua
branches/eagle_mmc/doc/luadoc/refman_gen_pack.lua
branches/eagle_mmc/doc/luadoc/refman_gen_pd.lua
branches/eagle_mmc/doc/luadoc/refman_gen_pwm.lua
branches/eagle_mmc/doc/luadoc/refman_gen_tmr.lua
branches/eagle_mmc/doc/luadoc/template.lua
branches/eagle_mmc/doc/pt/building.html
branches/eagle_mmc/doc/pt/comunity.html
branches/eagle_mmc/doc/pt/dl_binaries.html
branches/eagle_mmc/doc/pt/dl_old.html
branches/eagle_mmc/doc/pt/dl_sources.html
branches/eagle_mmc/doc/pt/downloads.html
branches/eagle_mmc/doc/pt/examples.html
branches/eagle_mmc/doc/pt/faq.html
branches/eagle_mmc/doc/pt/news.html
branches/eagle_mmc/doc/pt/overview.html
branches/eagle_mmc/doc/pt/platdepmodules.html
branches/eagle_mmc/doc/pt/refman.html
branches/eagle_mmc/doc/pt/status.html
branches/eagle_mmc/doc/pt/tc_386.html
branches/eagle_mmc/doc/pt/tc_arm.html
branches/eagle_mmc/doc/pt/tc_cortex.html
branches/eagle_mmc/doc/pt/tchainbuild.html
branches/eagle_mmc/doc/pt/tut_bootpc.html
branches/eagle_mmc/doc/pt/tut_bootstick.html
branches/eagle_mmc/doc/pt/tut_openocd.html
branches/eagle_mmc/doc/pt/tutorials.html
branches/eagle_mmc/doc/pt/using.html
branches/eagle_mmc/doc/pt/versionhistory.html
branches/eagle_mmc/doc/wb/wb_usr_template.lua
branches/eagle_mmc/doc/wb_img/eLuaLogo.png
branches/eagle_mmc/doc/wb_img/elua_arch.png
branches/eagle_mmc/doc/wb_img/stat_not_applicable.png
branches/eagle_mmc/doc/wb_img/stat_not_implemented.png
branches/eagle_mmc/doc/wb_img/stat_not_tested.png
branches/eagle_mmc/doc/wb_img/stat_ok.png
branches/eagle_mmc/inc/cexcept.h
branches/eagle_mmc/inc/luarpc_rpc.h
branches/eagle_mmc/inc/salloc.h
branches/eagle_mmc/remote-lua.py
branches/eagle_mmc/romfs/adcpoll.lua
branches/eagle_mmc/run_elua_sim.sh
branches/eagle_mmc/src/luarpc_elua_uart.c
branches/eagle_mmc/src/luarpc_posix_serial.c
branches/eagle_mmc/src/modules/can.c
branches/eagle_mmc/src/modules/luarpc.c
branches/eagle_mmc/src/platform/i386/stacks.h
branches/eagle_mmc/src/platform/sim/
branches/eagle_mmc/src/platform/sim/boot.s
branches/eagle_mmc/src/platform/sim/conf.py
branches/eagle_mmc/src/platform/sim/host.c
branches/eagle_mmc/src/platform/sim/host.h
branches/eagle_mmc/src/platform/sim/hostif.h
branches/eagle_mmc/src/platform/sim/hostif_linux.c
branches/eagle_mmc/src/platform/sim/i386.ld
branches/eagle_mmc/src/platform/sim/platform.c
branches/eagle_mmc/src/platform/sim/platform_conf.h
branches/eagle_mmc/src/platform/sim/stacks.h
branches/eagle_mmc/src/platform/sim/type.h
branches/eagle_mmc/src/platform/sim/utils.s
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/misc.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/misc.c
branches/eagle_mmc/src/platform/stm32/core_cm3.c
branches/eagle_mmc/src/platform/stm32/core_cm3.h
branches/eagle_mmc/src/platform/stm32/stacks.h
branches/eagle_mmc/src/platform/stm32/startup_stm32f10x_hd.s
branches/eagle_mmc/src/platform/stm32/stm32f10x.h
branches/eagle_mmc/src/platform/stm32/system_stm32f10x.c
branches/eagle_mmc/src/platform/stm32/system_stm32f10x.h
branches/eagle_mmc/src/salloc.c
branches/eagle_mmc/test/
branches/eagle_mmc/test/test-rpc.lua
Removed:
branches/eagle_mmc/doc/en/platdepmodules.html
branches/eagle_mmc/doc/index_en.html
branches/eagle_mmc/doc/index_pt.html
branches/eagle_mmc/doc/ssSearch.class
branches/eagle_mmc/doc/ssSearchThread.class
branches/eagle_mmc/doc/ssSearch_en.html
branches/eagle_mmc/doc/ssSearch_pt.html
branches/eagle_mmc/doc/template_ssSearch.html
branches/eagle_mmc/doc/wb/wb_usr.lua
branches/eagle_mmc/doc/wb_bar_en.html
branches/eagle_mmc/doc/wb_bar_pt.html
branches/eagle_mmc/doc/wb_img/Thumbs.db
branches/eagle_mmc/doc/wb_img/eLua-logo-80x80.png
branches/eagle_mmc/doc/wb_search_en.txt
branches/eagle_mmc/doc/wb_search_pt.txt
branches/eagle_mmc/doc/wb_title_en.html
branches/eagle_mmc/doc/wb_title_pt.html
branches/eagle_mmc/doc/wb_tree_en.html
branches/eagle_mmc/doc/wb_tree_pt.html
branches/eagle_mmc/docs/eLua_Manual.odt
branches/eagle_mmc/docs/eLua_Manual.pdf
branches/eagle_mmc/src/platform/lpc288x/main.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/cortexm3_macro.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_lib.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_map.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_nvic.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_systick.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_type.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_lib.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_nvic.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_systick.c
branches/eagle_mmc/src/platform/stm32/FWLib/stm32f10x_conf.h
branches/eagle_mmc/src/platform/stm32/stm32f10x_vector.c
Modified:
branches/eagle_mmc/SConstruct
branches/eagle_mmc/cross-lua.py
branches/eagle_mmc/doc/en/building.html
branches/eagle_mmc/doc/en/comunity.html
branches/eagle_mmc/doc/en/downloads.html
branches/eagle_mmc/doc/en/examples.html
branches/eagle_mmc/doc/en/faq.html
branches/eagle_mmc/doc/en/news.html
branches/eagle_mmc/doc/en/overview.html
branches/eagle_mmc/doc/en/refman.html
branches/eagle_mmc/doc/en/status.html
branches/eagle_mmc/doc/en/tc_386.html
branches/eagle_mmc/doc/en/tc_arm.html
branches/eagle_mmc/doc/en/tc_cortex.html
branches/eagle_mmc/doc/en/tchainbuild.html
branches/eagle_mmc/doc/en/tut_bootpc.html
branches/eagle_mmc/doc/en/tut_bootstick.html
branches/eagle_mmc/doc/en/tut_openocd.html
branches/eagle_mmc/doc/en/tutorials.html
branches/eagle_mmc/doc/en/using.html
branches/eagle_mmc/doc/en/versionhistory.html
branches/eagle_mmc/doc/pt/bit_ref.html
branches/eagle_mmc/doc/pt/cpu_ref.html
branches/eagle_mmc/doc/pt/disp_ref.html
branches/eagle_mmc/doc/pt/eluaapi.html
branches/eagle_mmc/doc/pt/gpio_ref.html
branches/eagle_mmc/doc/pt/net_ref.html
branches/eagle_mmc/doc/pt/platdependentmodules.html
branches/eagle_mmc/doc/pt/pwm_ref.html
branches/eagle_mmc/doc/pt/spi_ref.html
branches/eagle_mmc/doc/pt/sys_ref.html
branches/eagle_mmc/doc/pt/term_ref.html
branches/eagle_mmc/doc/pt/uart_ref.html
branches/eagle_mmc/doc/readme.txt
branches/eagle_mmc/doc/style.css
branches/eagle_mmc/doc/wb/wb_build.lua
branches/eagle_mmc/inc/elua_adc.h
branches/eagle_mmc/inc/newlib/genstd.h
branches/eagle_mmc/inc/platform.h
branches/eagle_mmc/inc/term.h
branches/eagle_mmc/inc/utils.h
branches/eagle_mmc/inc/validate.h
branches/eagle_mmc/romfs/LM3S.lua
branches/eagle_mmc/romfs/adcscope.lua
branches/eagle_mmc/romfs/dualpwm.lua
branches/eagle_mmc/romfs/hangman.lua
branches/eagle_mmc/romfs/index.pht
branches/eagle_mmc/romfs/led.lua
branches/eagle_mmc/romfs/lhttpd.lua
branches/eagle_mmc/romfs/morse.lua
branches/eagle_mmc/romfs/piano.lua
branches/eagle_mmc/romfs/pong.lua
branches/eagle_mmc/romfs/pwmled.lua
branches/eagle_mmc/romfs/test.lua
branches/eagle_mmc/romfs/tvbgone.lua
branches/eagle_mmc/src/buf.c
branches/eagle_mmc/src/common.c
branches/eagle_mmc/src/elua_adc.c
branches/eagle_mmc/src/lua/ldump.c
branches/eagle_mmc/src/lua/linit.c
branches/eagle_mmc/src/lua/liolib.c
branches/eagle_mmc/src/lua/lua.c
branches/eagle_mmc/src/lua/luac.c
branches/eagle_mmc/src/lua/luaconf.h
branches/eagle_mmc/src/lua/lundump.c
branches/eagle_mmc/src/lua/lundump.h
branches/eagle_mmc/src/main.c
branches/eagle_mmc/src/modules/adc.c
branches/eagle_mmc/src/modules/auxmods.h
branches/eagle_mmc/src/modules/net.c
branches/eagle_mmc/src/modules/pio.c
branches/eagle_mmc/src/modules/term.c
branches/eagle_mmc/src/modules/uart.c
branches/eagle_mmc/src/newlib/genstd.c
branches/eagle_mmc/src/newlib/stubs.c
branches/eagle_mmc/src/platform/at91sam7x/conf.py
branches/eagle_mmc/src/platform/at91sam7x/flash256.lds
branches/eagle_mmc/src/platform/at91sam7x/flash512.lds
branches/eagle_mmc/src/platform/at91sam7x/platform.c
branches/eagle_mmc/src/platform/at91sam7x/platform_conf.h
branches/eagle_mmc/src/platform/avr32/conf.py
branches/eagle_mmc/src/platform/avr32/platform.c
branches/eagle_mmc/src/platform/avr32/platform_conf.h
branches/eagle_mmc/src/platform/i386/conf.py
branches/eagle_mmc/src/platform/i386/kb.c
branches/eagle_mmc/src/platform/i386/monitor.c
branches/eagle_mmc/src/platform/i386/platform.c
branches/eagle_mmc/src/platform/i386/platform_conf.h
branches/eagle_mmc/src/platform/lm3s/conf.py
branches/eagle_mmc/src/platform/lm3s/disp.c
branches/eagle_mmc/src/platform/lm3s/lm3s.ld
branches/eagle_mmc/src/platform/lm3s/platform.c
branches/eagle_mmc/src/platform/lm3s/platform_conf.h
branches/eagle_mmc/src/platform/lpc288x/conf.py
branches/eagle_mmc/src/platform/lpc288x/lpc2888.lds
branches/eagle_mmc/src/platform/lpc288x/platform_conf.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_adc.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_bkp.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_can.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_crc.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dac.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dbgmcu.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dma.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_exti.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_flash.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_fsmc.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_gpio.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_i2c.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_iwdg.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_pwr.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rcc.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rtc.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_sdio.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_spi.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_tim.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_usart.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_wwdg.h
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_adc.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_bkp.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_can.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_crc.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dac.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dbgmcu.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dma.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_exti.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_flash.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_fsmc.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_gpio.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_i2c.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_iwdg.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_pwr.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rcc.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rtc.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_sdio.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_spi.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_tim.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_usart.c
branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_wwdg.c
branches/eagle_mmc/src/platform/stm32/conf.py
branches/eagle_mmc/src/platform/stm32/fonts.h
branches/eagle_mmc/src/platform/stm32/lcd.h
branches/eagle_mmc/src/platform/stm32/platform.c
branches/eagle_mmc/src/platform/stm32/platform_conf.h
branches/eagle_mmc/src/platform/stm32/stm32.ld
branches/eagle_mmc/src/platform/stm32/stm32f10x_conf.h
branches/eagle_mmc/src/platform/stm32/stm32f10x_it.c
branches/eagle_mmc/src/platform/stm32/stm32f10x_it.h
branches/eagle_mmc/src/platform/stm32/systick.c
branches/eagle_mmc/src/platform/stm32/systick.h
branches/eagle_mmc/src/platform/stm32/type.h
branches/eagle_mmc/src/platform/str7/conf.py
branches/eagle_mmc/src/platform/str7/platform_conf.h
branches/eagle_mmc/src/platform/str7/str711fr2.lds
branches/eagle_mmc/src/platform/str9/conf.py
branches/eagle_mmc/src/platform/str9/platform_conf.h
branches/eagle_mmc/src/platform/str9/str912fw44.lds
branches/eagle_mmc/src/shell.c
branches/eagle_mmc/src/term.c
branches/eagle_mmc/src/xmodem.c
Log:
Merge commit 'remotes/trunk' into local_mmc
Modified: branches/eagle_mmc/SConstruct
===================================================================
--- branches/eagle_mmc/SConstruct 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/SConstruct 2009-07-30 18:10:13 UTC (rev 371)
@@ -3,9 +3,86 @@
cputype = ARGUMENTS.get( 'cpu', '' ).upper()
allocator = ARGUMENTS.get( 'allocator', '' ).lower()
boardname = ARGUMENTS.get( 'board' , '').upper()
+toolchain = ARGUMENTS.get( 'toolchain', '')
optram = int( ARGUMENTS.get( 'optram', '1' ) )
-# ROMFS file list
+# List of toolchains
+toolchain_list = {
+ 'arm-gcc' : {
+ 'compile' : 'arm-elf-gcc',
+ 'link' : 'arm-elf-ld',
+ 'asm' : 'arm-elf-as',
+ 'bin' : 'arm-elf-objcopy',
+ 'size' : 'arm-elf-size'
+ },
+ 'arm-eabi-gcc' : {
+ 'compile' : 'arm-eabi-gcc',
+ 'link' : 'arm-eabi-ld',
+ 'asm' : 'arm-eabi-as',
+ 'bin' : 'arm-eabi-objcopy',
+ 'size' : 'arm-eabi-size'
+ },
+ 'codesourcery' : {
+ 'compile' : 'arm-none-eabi-gcc',
+ 'link' : 'arm-none-eabi-ld',
+ 'asm' : 'arm-none-eabi-as',
+ 'bin' : 'arm-none-eabi-objcopy',
+ 'size' : 'arm-none-eabi-size'
+ },
+ 'avr32-gcc' : {
+ 'compile' : 'avr32-gcc',
+ 'link' : 'avr32-ld',
+ 'asm' : 'avr32-as',
+ 'bin' : 'avr32-objcopy',
+ 'size' : 'avr32-size'
+ },
+ 'i686-gcc' : {
+ 'compile' : 'i686-elf-gcc',
+ 'link' : 'i686-elf-ld',
+ 'asm' : 'nasm',
+ 'bin' : 'i686-elf-objcopy',
+ 'size' : 'i686-elf-size'
+ }
+}
+
+# Toolchain Aliases
+toolchain_list['devkitarm'] = toolchain_list['arm-eabi-gcc']
+
+
+# List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'i386' : { 'cpus' : [ 'I386' ], 'toolchains' : [ 'i686-gcc' ] },
+ 'sim' : { 'cpus' : [ 'LINUX' ], 'toolchains' : [ 'i686-gcc' ] },
+ 'lpc288x' : { 'cpus' : [ 'LPC2888' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'str7' : { 'cpus' : [ 'STR711FR2' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'stm32' : { 'cpus' : [ 'STM32F103ZE', 'STM32F103RE' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'avr32' : { 'cpus' : [ 'AT32UC3A0512' ], 'toolchains' : [ 'avr32-gcc' ] }
+}
+
+# List of board/CPU combinations
+board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ],
+ 'EK-LM3S8962' : [ 'LM3S8962' ],
+ 'EK-LM3S6965' : [ 'LM3S6965' ],
+ 'STR9-COMSTICK' : [ 'STR912FAW44' ],
+ 'PC' : [ 'I386' ],
+ 'SIM' : [ 'LINUX' ],
+ 'LPC-H2888' : [ 'LPC2888' ],
+ 'MOD711' : [ 'STR711FR2' ],
+ 'STM3210E-EVAL' : [ 'STM32F103ZE' ],
+ 'ATEVK1100' : [ 'AT32UC3A0512' ],
+ 'ET-STM32' : [ 'STM32F103RE' ],
+ 'EAGLE-100' : [ 'LM3S6918' ]
+ }
+
+# ROMFS file list "groups"
+# To include a file in a ROMFS build, include it in a group here (or create one
+# if you need) and make sure the group is included on your platform's file_list
+# definition (right after this).
romfs = { 'bisect' : [ 'bisect.lua' ],
'hangman' : [ 'hangman.lua' ],
'lhttpd' : [ 'index.pht', 'lhttpd.lua', 'test.lua' ],
@@ -19,6 +96,7 @@
'morse' : [ 'morse.lua' ],
'dualpwm' : [ 'dualpwm.lua' ],
'adcscope' : [ 'adcscope.lua' ],
+ 'adcpoll' : [ 'adcpoll.lua' ],
'life' : [ 'life.lua' ]
}
@@ -52,11 +130,14 @@
'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
'EAGLE-100' : [ 'led', 'info' ],
'STR9-COMSTICK' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
- 'PC' : [ 'bisect', 'hello', 'info', 'life' ],
+ 'PC' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ],
+ 'SIM' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ],
'LPC-H2888' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
'MOD711' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'dualpwm' ],
'STM3210E-EVAL' : [ 'bisect', 'hello', 'info' ],
- 'ATEVK1100' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ]
+ 'ATEVK1100' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'ET-STM32' : [ 'hello', 'hangman', 'info', 'bisect','adcscope','adcpoll', 'dualpwm', 'pwmled' ],
+ 'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ]
}
# Variants: board = <boardname>
@@ -92,31 +173,40 @@
print "CPU %s not found" % cputype
sys.exit( -1 )
+# Look for the given CPU in the list of platforms
platform = None
-# Look for the given CPU in the list of platforms
-for p, v in cpu_list.items():
- if cputype in v:
+for p, v in platform_list.items():
+ if cputype in v[ 'cpus' ]:
platform = p
break
else:
print "Unknown CPU %s" % cputype
print "List of accepted CPUs: "
- for p, v in cpu_list.items():
+ for p, v in platform_list.items():
print " ", p, "-->",
- for cpu in v:
+ for cpu in v[ 'cpus' ]:
print cpu,
print
sys.exit( -1 )
+# Check the toolchain
+if toolchain != '':
+ if not toolchain in platform_list[ platform ][ 'toolchains' ]:
+ print "Invalid toolchain '%s' for CPU '%s'" % ( toolchain, cputype )
+ sys.exit( -1 )
+else:
+ toolchain = platform_list[ platform ][ 'toolchains' ][ 0 ]
+toolset = toolchain_list[ toolchain ]
+
# CPU/allocator mapping (if allocator not specified)
if allocator == '':
if boardname == 'LPC-H2888' or boardname == 'ATEVK1100':
allocator = 'multiple'
else:
allocator = 'newlib'
-elif allocator not in [ 'newlib', 'multiple' ]:
+elif allocator not in [ 'newlib', 'multiple', 'simple' ]:
print "Unknown allocator", allocator
- print "Allocator can be either 'newlib' or 'multiple'"
+ print "Allocator can be either 'newlib', 'multiple' or 'simple'"
sys.exit( -1 )
@@ -129,7 +219,8 @@
print "Board: ", boardname
print "Platform: ", platform
print "Allocator: ", allocator
- print "Target: ", target
+ print "Target: ", target == 'lua' and 'fplua' or 'target'
+ print "Toolchain: ", toolchain
print "*********************************"
print
@@ -137,27 +228,34 @@
cdefs = '-DELUA_CPU=%s -DELUA_BOARD=%s -DELUA_PLATFORM=%s -D__BUFSIZ__=128' % ( cputype, boardname, platform.upper() )
if allocator == 'multiple':
cdefs = cdefs + " -DUSE_MULTIPLE_ALLOCATOR"
+elif allocator == 'simple':
+ cdefs = cdefs + " -DUSE_SIMPLE_ALLOCATOR"
+# Special macro definitions for the SYM target
+if platform == 'sim':
+ cdefs = cdefs + " -DELUA_SIMULATOR -DELUA_SIM_%s" % cputype
+
# Lua source files and include path
lua_files = """lapi.c lcode.c ldebug.c ldo.c ldump.c lfunc.c lgc.c llex.c lmem.c lobject.c lopcodes.c
lparser.c lstate.c lstring.c ltable.c ltm.c lundump.c lvm.c lzio.c lauxlib.c lbaselib.c
ldblib.c liolib.c lmathlib.c loslib.c ltablib.c lstrlib.c loadlib.c linit.c lua.c lrotable.c"""
if target == 'lualong' or target == 'lua':
lua_full_files = " " + " ".join( [ "src/lua/%s" % name for name in lua_files.split() ] )
- local_include = "-Iinc -Iinc/newlib -Isrc/lua"
+ local_include = ['inc', 'inc/newlib', 'src/lua']
if target == 'lualong':
cdefs = cdefs + ' -DLUA_NUMBER_INTEGRAL'
else:
print "Invalid target", target
sys.exit( 1 )
-local_include = local_include + " -Isrc/modules -Isrc/platform/%s" % platform
+
+local_include += ['src/modules', 'src/platform/%s' % platform]
cdefs = cdefs + " -DLUA_OPTIMIZE_MEMORY=%d" % ( optram != 0 and 2 or 0 )
# Additional libraries
local_libs = ''
# Application files
-app_files = " src/main.c src/romfs.c src/xmodem.c src/shell.c src/term.c src/common.c src/buf.c src/elua_adc.c src/dlmalloc.c "
+app_files = " src/main.c src/romfs.c src/xmodem.c src/shell.c src/term.c src/common.c src/buf.c src/elua_adc.c src/dlmalloc.c src/salloc.c src/luarpc_elua_uart.c "
# Newlib related files
newlib_files = " src/newlib/devman.c src/newlib/stubs.c src/newlib/genstd.c src/newlib/stdtcp.c"
@@ -165,14 +263,14 @@
# UIP files
uip_files = "uip_arp.c uip.c uiplib.c dhcpc.c psock.c resolv.c"
uip_files = " src/elua_uip.c " + " ".join( [ "src/uip/%s" % name for name in uip_files.split() ] )
-local_include = local_include + " -Isrc/uip"
+local_include += ['src/uip']
# FatFs files
app_files = app_files + "src/mmcfs.c src/fatfs/ff.c "
local_include = local_include + " -Isrc/fatfs"
# Lua module files
-module_names = "pio.c spi.c tmr.c pd.c uart.c term.c pwm.c lpack.c bit.c net.c cpu.c adc.c"
+module_names = "pio.c spi.c tmr.c pd.c uart.c term.c pwm.c lpack.c bit.c net.c cpu.c adc.c can.c luarpc.c"
module_files = " " + " ".join( [ "src/modules/%s" % name for name in module_names.split() ] )
# Optimizer flags (speed or size)
@@ -206,10 +304,12 @@
LINKCOM = tools[ platform ][ 'linkcom' ],
OBJSUFFIX = ".o",
PROGSUFFIX = ".elf",
+ CPPPATH = local_include,
ENV = os.environ )
# comp.TargetSignatures( 'content' )
# comp.SourceSignatures( 'MD5' )
-Default( comp.Program( output, Split( source_files ) ) )
+comp[ 'INCPREFIX' ] = "-I"
+Default( comp.Program( target = output, source = Split( source_files ) ) )
Decider( 'MD5' )
# Programming target
Modified: branches/eagle_mmc/cross-lua.py
===================================================================
--- branches/eagle_mmc/cross-lua.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/cross-lua.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,18 +6,17 @@
# Lua source files and include path
lua_files = """lapi.c lcode.c ldebug.c ldo.c ldump.c lfunc.c lgc.c llex.c lmem.c lobject.c lopcodes.c
lparser.c lstate.c lstring.c ltable.c ltm.c lundump.c lvm.c lzio.c lauxlib.c lbaselib.c
- ldblib.c liolib.c lmathlib.c loslib.c ltablib.c lstrlib.c loadlib.c linit.c luac.c print.c"""
+ ldblib.c liolib.c lmathlib.c loslib.c ltablib.c lstrlib.c loadlib.c linit.c luac.c print.c lrotable.c"""
lua_full_files = " " + " ".join( [ "src/lua/%s" % name for name in lua_files.split() ] )
local_include = "-Isrc/lua"
# Compiler/linker options
-cccom = "gcc -O3 %s -Wall %s -c $SOURCE -o $TARGET" % ( local_include, cdefs )
+cccom = "gcc -g %s -Wall %s -c $SOURCE -o $TARGET" % ( local_include, cdefs )
linkcom = "gcc -o $TARGET $SOURCES -lm"
# Env for building the program
comp = Environment( CCCOM = cccom,
LINKCOM = linkcom,
ENV = os.environ )
-comp.TargetSignatures( 'content' )
-comp.SourceSignatures( 'MD5' )
+Decider( 'MD5' )
Default( comp.Program( output, Split( lua_full_files ) ) )
Added: branches/eagle_mmc/doc/build_dist_doc.sh
===================================================================
--- branches/eagle_mmc/doc/build_dist_doc.sh 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/build_dist_doc.sh 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,54 @@
+#!/bin/bash
+# Builds a full documentation package in the "dist/" directory
+
+# Delete and recreate directory
+rm -rf dist
+mkdir dist
+
+# Build platform docs
+lua builddoc.lua
+if [ $? -ne 0 ]
+then
+ exit
+fi
+cd wb
+lua wb_build.lua
+cd ..
+
+# Copy the required files to the dist/ directory
+for lang in en pt
+do
+ cp -R $lang/ dist/
+done
+cp -R wb_img dist/
+for f in wb*.html style.css index*.html
+do
+ echo Copying $f...
+ cp $f dist/
+done
+cp dist/index_en.html dist/index.html
+
+# Remove all version data from dist
+find dist/ -name ".svn" | xargs rm -rf
+
+if [ "$1" != "noclean" ]
+then
+ # Remove unneeded files from base dir
+ echo
+ echo "Cleaning up..."
+ for lang in en pt
+ do
+ rm -f $lang/arch_platform_*.html
+ rm -f $lang/refman_gen_*.html
+ done
+ rm -f index_*.html wb/wb_usr.lua ssSearch*.html wb_bar_*.html
+ rm -f wb_search*.txt wb_title*.html wb_tree*.html
+else
+ echo
+ echo "NOT cleaning base directory!"
+fi
+
+# All done
+echo
+echo "DONE! Enjoy your documentation in dist/ :)"
+
Property changes on: branches/eagle_mmc/doc/build_dist_doc.sh
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/doc/builddoc.lua
===================================================================
--- branches/eagle_mmc/doc/builddoc.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/builddoc.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,374 @@
+-- eLua doc builder tool
+
+-- List here all the sections for which we're generating the documentation
+local doc_sections = { "arch_platform", "refman_gen" }
+
+-- List here all the components of each section
+local components =
+{
+ arch_platform = { "ll", "pio", "spi", "uart", "timers", "pwm", "cpu", "eth", "adc" },
+ refman_gen = { "bit", "pd", "pack", "tmr", "pwm", "cpu", "adc" }
+}
+
+-- List here all languages for the documentation (make sure to keep English ("en") the first one)
+local languages = { "en", "pt" }
+-- Also list here the translation for a bunch of fixed strings
+local overview_tr = { en = "Overview", pt = "##Overview" }
+local structures_tr = { en = "Data structures", pt = "##Data structures" }
+local functions_tr = { en = "Functions", pt = "##Functions" }
+
+-- Format a name to a link by changing all the spaces to "_" and
+-- making all letters lowercase
+local function name2link( str )
+ str = str:gsub( " ", "_" )
+ return str:lower()
+end
+
+-- Returns the part of the string enclosed between two '#' chars
+-- Used for parsing function sig.
+local function namefromsig( str )
+ local _, _, name = str:find( "#(.*)#" )
+ return name
+end
+
+--[[ Process the given string as follows:
+- $string$ becomes <b>string</b>
+- %string% becomes <i>string</i>
+- @ref at text@ becomes <a href="ref">text</a>
+- ^ref^text^ becomes <a target="_blank" href="ref">text</a>
+- $$, %%, @@, ^^ become $, %, @, ^ respectively
+- the string "eLua" becomes <b>eLua</b>
+- strings between two tildas (~~) get special code-like formatting
+- newlines are changed to ' ' if 'keepnl' isn't true
+- '&' is translated to its corresponding HTML code.
+- '<<' and '>>" are also translated to the corresponding HTML codes (note the repetition).
+--]]
+local function format_string( str, keepnl )
+ -- replace double "special chars" with "temps" for later use
+ str = str:gsub( "%$%$", "\001" )
+ str = str:gsub( "%%%%", "\002" )
+ str = str:gsub( "@@", "\003" )
+ str = str:gsub( "%^%^", "\004" )
+ str = str:gsub( "~~", "\005" )
+
+ -- Translate 'special' HTML chars to their equivalents
+ local tr_table =
+ {
+ [ "%&" ] = "&",
+ }
+ for char, rep in pairs( tr_table ) do
+ str = str:gsub( char, rep )
+ end
+
+ -- some double chars are replaced directly with their HTML codes
+ str = str:gsub( "<<", "<" )
+ str = str:gsub( ">>", ">" )
+
+ -- replace eLua with <b>eLua</b>
+ str = str:gsub( "eLua", "<b>eLua</b>" )
+
+ -- $string$ becomes <b>string></b>
+ str = str:gsub( "%$([^%s%$][^%$]*)%$", "<b>%1</b>" )
+
+ -- %string% becomes <i>string</i>
+ str = str:gsub( "%%([^%s%%][^%%]*)%%", "<i>%1</i>" )
+
+ -- @ref at text@ becomes <a href="ref">text</a>
+ str = str:gsub( "@([^%s@][^@]*)@([^%s@][^@]*)@", '<a href="%1">%2</a>' )
+
+ -- ^ref^text^ becomes <a target="_blank" href="ref">text</a>
+ str = str:gsub( "%^([^%s%^][^%^]*)%^([^%s%^][^%^]*)%^", '<a target="_blank" href="%1">%2</a>' )
+
+ -- strings between two tildas (~~) get special code-like formatting
+ str = str:gsub( "~([^%s~][^~]*)~", function( x )
+ x = x:gsub( "\n", "<br>" )
+ x = x:gsub( "%s%s+", function( x ) return ( " " ):rep( #x ) end )
+ return "<p><code>" .. x .. "</code></p>"
+ end )
+ str = str:gsub( "~~", "~" )
+
+ -- other "\n" chars should dissapear now
+ if not keepnl then str = str:gsub( "\n", " " ) end
+
+ -- put back the "temps"
+ str = str:gsub( "\001", "%$" )
+ str = str:gsub( "\002", "%%" )
+ str = str:gsub( "\003", "@" )
+ str = str:gsub( "\004", "%^" )
+ str = str:gsub( "\005", "~" )
+
+ -- all done
+ return str
+end
+
+local header = [[
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>%s</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">]]
+
+-- Build the documentation starting from the given file
+local function build_file( fname )
+ dofile( fname )
+ local res = {}
+
+ for _, lang in pairs( languages ) do
+ res[ lang ] = {}
+ res[ lang ].wb = {}
+ local wb = res[ lang ].wb
+
+ -- we need english always
+ -- the other languages will be substituted with english if not found
+ local resname = string.format( "data_%s", lang )
+ local r = _G[ resname ]
+ if not r then
+ if lang == "en" then
+ return false, "data_en must exist in the description"
+ else
+ print( string.format( "'%s': data for language '%s' not found, defaulting to english", fname, lang ) )
+ r = _G[ "data_en" ]
+ end
+ end
+
+ -- process names
+ if not r.menu_name then
+ return false, "menu_names not found"
+ end
+ wb.name = r.menu_name
+
+ -- process title
+ if not r.title then
+ return false, "title not found"
+ end
+ local page = header:format( r.title ) .. "\n\n"
+
+ -- process overview
+ if not r.overview then
+ return false, "overview not found"
+ end
+ page = page .. '<a name="overview"><h3>Overview</h3></a>\n<p>' .. format_string( r.overview ) .. "</p>\n\n"
+
+ -- process structures if needed
+ if r.structures then
+ local structures = r.structures
+ wb.structs = {}
+ page = page .. '<a name="structures"><h3>Data structures, constants and types</h3></a>\n'
+ for i = 1, #structures do
+ local s = structures[ i ]
+ wb.structs[ #wb.structs + 1 ] = s.name
+ if not s.text or not s.desc or not s.name then
+ return false, "structure without text, desc or name fields"
+ end
+ -- text/name. The link name is ALWAYS the one in ENGLISH.
+ page = page .. string.format( '<a name="%s">', name2link( res.en.wb.structs[ i ] ) )
+ page = page .. "<p><pre><code>" .. format_string( s.text, true ) .. "</code></pre></p>"
+ page = page .. "</a>"
+ -- description
+ page = page .. "\n<p>" .. format_string( s.desc ) .. "</p>\n\n"
+ end
+ end
+
+ -- process functions now
+ if not r.funcs then
+ return false, "funcs not found"
+ end
+ local funcs = r.funcs
+ page = page .. '<a name="funcs"><h3>Functions</h3></a>\n'
+ wb.funcs = {}
+ for i = 1, #funcs do
+ local f = funcs[ i ]
+ if not f.sig or not f.desc then
+ return false, "function without sig or desc fields"
+ end
+ local funcname = namefromsig( f.sig )
+ if not funcname then
+ return false, string.format( "'%s' should contain the function name between '*' chars", f.sig )
+ end
+ wb.funcs[ #wb.funcs + 1 ] = funcname
+ -- signature
+ page = page .. string.format( '<a name="%s">', funcname )
+ page = page .. "<p><pre><code>" .. f.sig:gsub( '#', '' ) .. "</code></pre></p>"
+ page = page .. "</a>"
+ -- description
+ page = page .. "\n<p>" .. format_string( f.desc ) .. "</p>\n"
+ -- arguments
+ page = page .. "<p><b>Arguments</b>: "
+ if f.args then
+ local a = f.args
+ if type( a ) == "string" or ( type( a ) == "table" and #a == 1 ) then
+ local text = type( a ) == "string" and a or a[ 1 ]
+ page = page .. format_string( text )
+ else
+ page = page .. "\n<ul>\n"
+ for i = 1, #a do page = page .. " <li>" .. format_string( a[ i ] ) .. "</li>\n" end
+ page = page .. "</ul>"
+ end
+ else
+ page = page .. "none"
+ end
+ page = page .. "</p>\n"
+ -- return value
+ page = page .. "<p><b>Returns</b>: "
+ if f.ret then
+ local r = f.ret
+ if type( r ) == "string" or ( type( r ) == "table" and #r == 1 ) then
+ local text = type( r ) == "string" and r or r[ 1 ]
+ page = page .. format_string( text )
+ else
+ page = page .. "\n<ul>\n"
+ for i = 1, #r do page = page .. " <li>" .. format_string( r[ i ] ) .. "</li>\n" end
+ page = page .. "</ul>"
+ end
+ else
+ page = page .. "nothing"
+ end
+ page = page .. "</p>\n\n"
+ end
+
+ -- aux data (if any)
+ if r.auxdata then
+ local auxdata = r.auxdata
+ wb.auxdata = {}
+ for i = 1, #auxdata do
+ local a = auxdata[ i ]
+ wb.auxdata[ #wb.auxdata + 1 ] = a.title
+ if not a.title or not a.desc then
+ return false, "auxdata without title or desc"
+ end
+ -- the link name is ALWAYS the one in ENGLISH
+ page = page .. string.format( '<a name="%s">', name2link( res.en.wb.auxdata[ i ] ) )
+ page = page .. "<h3>" .. a.title .. "</h3>"
+ page = page .. "</a>"
+ page = page .. "\n<p>" .. format_string( a.desc ) .. "</p>\n\n"
+ end
+ end
+
+ -- footer
+ page = page .. "</body></html>\n"
+ res[ lang ].page = page
+ end
+ return res
+end
+
+-- Helper function to get strings in all languages when needed
+local function alllangs( getstr )
+ local str = "name = {"
+ for _, lang in pairs( languages ) do
+ str = str .. string.format( ' %s = "%s",', lang, getstr( lang ) )
+ end
+ return str .. " }"
+end
+
+-- Transform the data from the wb dictionary (in 'fulldata') for module 'modname' to a wb string, for section 'sect'
+local function wb2str( fulldata, modname, sect )
+ local relfname = sect .. "_" .. modname .. ".html"
+ local res = fulldata[ modname ]
+ local wbstr = string.format( ' { %s,\n link = "%s",\n folder =\n {\n', alllangs( function( x ) return res[ x ].wb.name end ), relfname )
+
+ -- Overview
+ wbstr = wbstr .. string.format( ' { %s,\n link = "%s#overview"\n },\n', alllangs( function( x ) return overview_tr[ x ] end ), relfname )
+
+ -- Data structures (if needed)
+ if res.en.wb.structs then
+ wbstr = wbstr .. string.format( ' { %s,\n link = "%s#structures",\n folder =\n {\n', alllangs( function( x ) return structures_tr[ x ] end ), relfname )
+ for i = 1, #res.en.wb.structs do
+ local v = res.en.wb.structs[ i ]
+ wbstr = wbstr .. string.format( ' { %s,\n link = "%s#%s",\n },\n', alllangs( function( x ) return res[ x ].wb.structs[ i ] end ), relfname, name2link( v ) )
+ end
+ wbstr = wbstr .. " }\n },\n"
+ end
+
+ -- Functions
+ wbstr = wbstr .. string.format( ' { %s,\n link = "%s#funcs",\n folder =\n {\n', alllangs( function( x ) return functions_tr[ x ] end ), relfname )
+ for _, v in pairs( res.en.wb.funcs ) do
+ wbstr = wbstr .. string.format( ' { name = { en = "%s", pt = "%s" },\n link = "%s#%s",\n },\n', v, v, relfname, name2link( v ) )
+ end
+ wbstr = wbstr .. " }\n },\n"
+
+ -- Aux data (if needed)
+ if res.en.wb.auxdata then
+ for i = 1, #res.en.wb.auxdata do
+ local v = res.en.wb.auxdata[ i ]
+ wbstr = wbstr .. string.format( ' { %s,\n link = "%s#%s"\n },\n', alllangs( function( x ) return res[ x ].wb.auxdata[ i ] end ), relfname, name2link( v ) )
+ end
+ end
+
+ -- Close the structure and return
+ wbstr = wbstr .. " }\n },\n"
+ return wbstr
+end
+
+-- Read our complete template for wb_usr.lua
+local wbloc = "wb/wb_usr_template.lua"
+local realwbloc = "wb/wb_usr.lua"
+local wbf = io.open( wbloc, "rb" )
+if not wbf then
+ print( string.format( "Cannot open %s for reading", wbloc ) )
+ return 1
+end
+local wbdata = wbf:read( "*a" )
+wbf:close()
+-- Open the actual wb_usr.lua in write mode
+local realwbf = io.open( realwbloc, "wb" )
+if not realwbf then
+ print( string.format( "Cannot open %s for writing", realwbloc ) )
+ return 1
+end
+
+-- Generate documentation for each section in part
+for _, section in pairs( doc_sections ) do
+
+ -- Check for pattern in wb_usr_template.lua
+ local pattern = "%$%$" .. section:upper() .. "%$%$"
+ if not wbdata:find( pattern ) then
+ print( string.format( "$$%s$$ not found in wb_usr_template.lua", section:upper(), modname ) )
+ return 1
+ end
+
+ -- Generate documentation for each module in turn
+ local fulldata = {}
+ for _, modname in pairs( components[ section ] ) do
+ local descfname = string.format( "luadoc/%s_%s.lua", section, modname )
+ local res, err = build_file( descfname )
+ if res then
+ fulldata[ modname ] = res
+ -- Write doc for each language
+ for _, lang in pairs( languages ) do
+ local fname = string.format( "%s/%s_%s.html", lang, section, modname )
+ local f = io.open( fname, "wb" )
+ if not f then
+ print( string.format( "Unable to open %s for writing", fname ) )
+ return 1
+ else
+ f:write( res[ lang ].page )
+ f:close()
+ print( ( "Wrote %s" ):format( fname ) )
+ end
+ end
+ else
+ print( string.format( "Error processing module '%s': %s", modname, err ) )
+ return 1
+ end
+ print ""
+ end
+
+ -- Now it's finally time to get our wb/wb_usr.lua
+ local fullwb = ''
+ for _, modname in pairs( components[ section ] ) do
+ local wbstr = wb2str( fulldata, modname, section )
+ fullwb = fullwb .. wbstr
+ end
+
+ -- Substitute our pattern and write everything back to disk
+ wbdata = wbdata:gsub( pattern, fullwb )
+end
+
+-- Write wb_usr.lua to disk (finally)
+realwbf:write( wbdata )
+realwbf:close()
+
+print "All done, remember to run 'lua wb_build.lua' in the 'wb' directory to build your navigation tree"
+
Added: branches/eagle_mmc/doc/en/arch.html
===================================================================
--- branches/eagle_mmc/doc/en/arch.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,15 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua architecture</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>The eLua architecture</h3>
+<p>This section presents in-depth details about the design and implementation of <b>eLua</b>. It's meant as a guide mainly for <b>eLua</b> developers,
+ but it contains information that can be also valuable for <b>eLua</b> users. An example is the <a href="arch_romfs.html">ROM file system</a> chapter.
+ Also, by reading the <a href="arch_overview.html">overview of the eLua architecture</a> you'll get a good view of the overall structure of <b>eLua</b>,
+ which will help no matter if you're a developer or not.</p>
+<p>Before diving into this, go to the <a href="downloads.html">downloads section</a> and download the source code of <b>eLua</b>, it's much easier to
+ follow this section if you look at the source code.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/arch_coding.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_coding.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_coding.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,167 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua coding style</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>The eLua coding style</h3>
+<p>This section presents the <b>eLua</b> coding style that should be followed by every developer working on <b>eLua</b>. The following rules apply:
+<ol>
+ <li>Everything should be spaced out properly. Examples (please note the spacing rules, which is basically "space out everything for readability"):
+ <p><pre><code>i = 3 (not i=3)
+a = ( a + 5 ) / 3
+for( i = 0; i < 10; i ++ ) ...
+if( ( i == 5 ) && ( a == 10 ) ) ...
+unsigned i = ( unsigned )p;
+void func( int arg1, const char* arg2 ) ...</code></pre></p></li>
+ <li><b>Indentation</b>: indent everything at 2 SPACES. Again, <b>SPACES</b>. <b>DO NOT USE TABS</b>; this is important (and fortunately pretty easy to remember :) ).
+ There are too many examples where tabs completely destroyed the readability of source code. Most editors have an "insert tabs instead of spaces" option;
+ use it, and set your "tab size" to 2.<br>
+ Also, indent "{" and "}" on their own lines:
+ <p><pre><code>if( i == 2 )
+{
+ // some code here
+}
+else
+{
+ // some other code here
+}</code></pre></p>
+
+ Or:
+<p><pre><code>void f( int i )
+{
+ // function code
+}</code></pre></p>
+
+Do not enclose single statements in {} when given a choice. For example, do this:
+
+<p><pre><code>if( i == 2 )
+ return;</code></pre></p>
+
+ instead of this:
+<p><pre><code>if( i == 2 )
+{
+ return;
+}</code></pre></p>
+
+Also, follow the "one statement per line" rule. In other words, don't do this:
+
+<p><pre><code>if( i == 2 ) return;</code></pre></p>
+
+Do this instead:
+
+<p><pre><code>if( i == 2 )
+ return;</code></pre></p>
+
+Note that <b>eLua</b> code does not use a space between the function name and its parameter list when calling/defining it (like in the Lua code, for example). So do this:
+
+<p><pre><code>void f( int i )
+{
+ // function code here
+}
+
+f( 2 ); // function call</code></pre></p>
+
+instead of this:
+
+<p><pre><code>void f ( int i )
+{
+ // function code here
+}
+
+f ( 2 ); // function call</code></pre></p></li>
+<li><b>line terminators</b>: <b>THIS IS IMPORTANT TOO!</b> Use UNIX style (LF) line terminators, not DOS (CR/LF) or old Mac (CR) line terminators.</li>
+<li><b>identifier names</b>: use a "GNU-style" here, with underlines and all lowercase:
+
+ <p><pre><code>int simple;
+double another_identifier;
+char yes_this_is_OK_although_quite_stupid;</code></pre></p>
+
+As opposed to:
+
+ <p><pre><code>int Simple1;
+double AnotherIdentifier;
+char DontEvenThinkAboutWritingSomethingLikeThis;</code></pre></p>
+<b>DO NOT USE HUNGARIAN NOTATION</b> (like iNumber, sString, fFloat ... if you don't know what that is, it's fine, as it means that we don't need to worry about it :) ). It has its advantages
+when used properly, it's just not for <b>eLua</b>.
+</li>
+<li><b>constants in code</b>: don't ever write something like this:
+
+ <p><pre><code>if( key == 10 )
+ sys_ok();
+else if( key == 5 )
+ phone_dial( "911" );
+else if( key == 666 )
+{
+ while( user_is_evil() )
+ exorcize_user();
+}
+else if( key == 0 )
+ sys_retry();
+else
+ sys_error();</code></pre></p>
+
+Instead, define some constants with meaningful names (via enums or even #define) and write like this:
+
+ <p><pre><code>if( key == KEY_CODE_OK )
+ sys_ok();
+else if( key == KEY_CODE_FATAL_ERROR )
+ phone_dial( "911" );
+else if( key == KEY_CODE_COMPLETELY_EVIL )
+{
+ while( user_is_evil() )
+ exorcize_user();
+}
+else if( key == KEY_CODE_NONE )
+ sys_retry();
+else
+ sys_error();</code></pre></p>
+You can see in this example an accepted violation of the "one statement per line" rule: it's OK to write "else if (newcondition)" on the same line.</li>
+
+<li>use specific data types as much as possible. In this context, <b>specific data types</b> reffers to generic types that have the same size on all
+ platforms. They are defined by each platform in turn and their meaning is given below:
+ <ul>
+ <li><b>s8</b>: signed 8-bit integer</li>
+ <li><b>u8</b>: unsigned 8-bit integer</li>
+ <li><b>s16</b>: signed 16-bit integer</li>
+ <li><b>u16</b>: unsigned 16-bit integer</li>
+ <li><b>s32</b>: signed 32-bit integer</li>
+ <li><b>u32</b>: unsigned 32-bit integer</li>
+ <li><b>s64</b>: signed 64-bit integer</li>
+ <li><b>u64</b>: unsigned 64-bit integer</li>
+ </ul>
+ By writing your code to take advantage of these specific data types you ensure high portability of the code amongst different hardware platforms. Don't
+ overuse this rule though. For example, a <b>for</b> loop has generally an <b>int</b> index, which is perfectly fine. But when you specify a timeout that
+ must fit in 32 bits, definitely declare it as <b>u32 to</b> instead of <b>unsigned int to</b>.
+</li>
+
+<li><b>endianness</b>: remember that <b>eLua</b> runs on both little endian and big endian architectures, and write your code accordingly.</li>
+
+<li><b>comments</b>: we generally favour C++ style comments (//), but it's perfectly OK to use C style (/**/) comments. Automatic documentation generators like Doxygen aren't encouraged, since
+ they tend to make the programmer overdocument the code to the point where it becomes hard to read because of the documentation alone. Ideally, you'd neither overdocument, nor
+ underdocument your code; just document it as much as you think it's needed, without getting into too much details, but also without omitting important information. In particular, DON'T do this:
+
+ <p><pre><code>// This function returns the sum of two numbers
+// Input: n1 - first number
+// Input: n2 - the second number
+// Output: the sum of n1 and n2
+int sum( int n1, int n2 )
+{
+ return n1 + n2;
+}</code></pre></p>
+
+ When something is self-obvious from the context, documenting it more is pointless and decreases readability.</li>
+<li><b>pseudo name-spaces</b>: since we don't have namespaces in C, I like to "emulate" them by prefixing anything (constants, variables, functions) in a file with something that identifies that
+ file uniquely (most likely its name, but this is not a definite rule). For example, a file called "uart.c" would look like this:
+
+ <p><pre><code>int uart_tx_count, uart_rx_count;
+
+int uart_receive( unsigned limit )...
+unsigned uart_send( const char *buf, unsigned size )...</code></pre></p>
+</li>
+
+</ol></p>
+<p>Also, if you're using 3rd party code (from a library/support package for example) making it follow the above rules is nice, but not mandatory. Focus on functionality and writing your own code properly, and come back to indent other people's code when you really don't have anything better to do with your time.</p>
+</body></html>
+
Added: branches/eagle_mmc/doc/en/arch_con_term.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_con_term.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_con_term.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua consoles and terminals</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>eLua consoles and terminals</h3>
+<p>In <b>eLua</b>, a <b>console</b> and a <b>terminal</b> serve two related, but different purposes:
+<ul>
+ <li>the <b>console</b> takes care of basic user input/output. They come in two flavours: serial consoles and TCP/IP consoles (note that the two can't coexist at the same time).</li>
+ <li>the <b>terminal</b> enhances the console in order to take advantage of ANSI terminals and their advanced control functions, like explicit cursor positioning, clear screen and others. At this
+ time, terminals work only over serial connections, not over TCP/IP (like consoles).</li>
+</ul></p>
+<p>Both components can be enabled and disabled as needed (they don't rely on each other). See <a href="building.html">building eLua</a> for details on how to enable and disable components.</p>
+<h2>Serial consoles</h2>
+<p>The serial console input/output is handled by a generic layer (<i>src/newlib/genstd.c</i>) that can be used to easily adapt the console subsystem to a variety of input/output devices.
+ It needs just two functions, one for displaying characters and another one for receiving input with timeout:</p>
+<p><pre><code>// Send/receive function types
+typedef void ( *p_std_send_char )( int fd, char c );
+typedef int ( *p_std_get_char )( s32 to );
+</code></pre></p>
+<p>(the <b>send</b> faction gets an additional <b>fd</b> parameter that you can use to differentiate between the standard C stdout and stderr output streams).</p>
+<p>To set them, use <b>std_set_send_func</b> and <b>std_set_get_func</b>, both defined in <i>inc/newlib/getstd.h</i>. Usually they are called from <i>src/common.c</i> and configured to work
+ over UART by default:</p>
+<p><pre><code>// *****************************************************************************
+// std functions and platform initialization
+
+static void uart_send( int fd, char c )
+{
+ fd = fd;
+ platform_uart_send( CON_UART_ID, c );
+}
+
+static int uart_recv( s32 to )
+{
+ return platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, to );
+}
+
+void cmn_platform_init()
+{
+ // Set the send/recv functions
+ std_set_send_func( uart_send );
+ std_set_get_func( uart_recv );
+}
+</code></pre></p>
+<p>If you need another type of serial console device (for example a dedicated console running over a SPI connection) just call <i>std_set_send_func/std_set_get_func</i> with the appropriate
+ function pointers.</p>
+<p>To enable serial consoles, define the <b>BUILD_CON_GENERIC</b> macro in your platform's <b>platform_conf.h</b> file.</p>
+<h2>TCP/IP consoles</h2>
+<p>TCP/IP consoles have the same functionality as serial consoles, but they work over a TCP/IP connection using the telnet protocol. As they integrate directly with the TCP/IP subsystem,
+ they don't have the same generic function based mechanism as serial consoles. To enable TCP/IP consoles, define the <b>BUILD_CON_TCP</b> macro in your platform's <b>platform_conf.h</b> file.</p>
+<h2>Terminals</h2>
+<p>Besides standard stdio/stdout/stderr support provided by consoles, <b>eLua</b> uses the "term" module to access ANSI compatible terminal emulators. It is designed to be as flexible as
+ possible, thus allowing a large number of terminal emulators to be used. To enable terminal support, add <b>BUILD_TERM</b> in your platform's <b>platform_conf.h</b> file. To use it, initialize
+ it with a call to <b>term_init</b>:
+<p><pre><code>...........................
+// Terminal output function
+typedef void ( *p_term_out )( u8 );
+// Terminal input function
+typedef int ( *p_term_in )( int );
+// Terminal translate input function
+typedef int ( *p_term_translate )( u8 );
+...........................
+// Terminal initialization
+void term_init( unsigned lines, unsigned cols, p_term_out term_out_func,
+ p_term_in term_in_func, p_term_translate term_translate_func );
+</code></pre></p>
+<p>The initialization function takes the physical size of the terminal emulator window (usually 80 lines and 25 cols) and three function pointers:
+<ul>
+ <li><b>p_term_out</b>: this function will be called to output characters to the terminal. It receives the character to output as its single parameter.</li>
+ <li><b>p_term_in</b>: this function will be called to read a character from the terminal. It receives a parameter that can be either TERM_INPUT_DONT_WAIT (in which case the function returns
+ -1 immediately if no character is available) or TERM_INPUT_WAIT (in which case the function will wait for the character).</li>
+ <li><b>p_term_translate</b>: this function translates terminal-specific codes to "term" codes. The "term" codes are defined in an enum from <i>inc/term.h</i>:
+<p><pre><code>...........................
+_D( KC_UP ),\
+_D( KC_DOWN ),\
+_D( KC_LEFT ),\
+...........................
+_D( KC_ESC ),\
+_D( KC_UNKNOWN )
+...........................</code></pre></p>
+By using this function, it is possible to adapt a very large number of "term emulators" to <b>eLua</b>. For example, you might want to run eLua in a "standalone
+ mode" that does not require a PC at all, just an external LCD display and maybe a keyboard for data input. Your <b>eLua</b> board can connect to this standalone terminal using its
+ I/O pins or built in peripherals, for example via SPI. By writing the three functions described above, the effort of making <b>eLua</b> work with this new type of device is minimal,
+ and also writing an "ANSI emulator" for your terminal device is not hard.</li></ul>
+<p>For an example, see <i>src/main.c</i>, where these functions are implemented for an UART connection with a terminal emulator program running on PC.</p>
+<p><b>eLua</b> also provides a Lua module (called <b>term</b>) that can be used to access ANSI terminal. See <a href="">the term module API</a> for a full description of this module.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/arch_ltr.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_ltr.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_ltr.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,269 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Modules and LTR</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Modules and LTR</h3>
+<p>LTR (Lua Tiny RAM) is a Lua patch (written specifically for <b>eLua</b> by Bogdan Marinescu) that significantly decreases the RAM usage of Lua scripts,
+ thus making it possible to run large Lua programs on systems with limited RAM. This section gives a full description of LTR. If you're writing <b>eLua</b>
+ modules, this page will certainly be of interest to you, as it shows how to interact with LTR in a portable and easy to configure way.</p>
+<h2>Motivation</h2>
+<p>The main thing that drove me to write this patch is the relatively high Lua memory consumption at startup (obtained by running
+ <i>lua -e "print(collectgarbage'count')"</i>). It's about 17k for regular Lua 5.1.4, and more than 25k for some of eLua's platforms. These figures are
+ mainly a result of registering many different modules to Lua. Each time you register a module (via luaL_register) you create a new table and populate
+ it with the module's methods. But a table is a read/write datatype, so luaL_register is quite inefficient if you don't plan to do any write operations
+ on that table later (adding new elements or manipulating existing ones). I found that I almost never have to do any such operations on a module's
+ table after it was created, I just query it for its elements. So, from the perspective of someone worried about memory usage, I'd rather have a
+ different type of table in this case, one that wouldn't need any RAM at all, since it would be read only, so it could reside entirely in ROM.</p>
+ <p>There's one more thing related to this context: Lua's functions. While Lua does have the concept of C functions, they still require data structures
+ that need to be allocated (see lua_pushcclosure in lapi.c for details), as they can have upvalues or environments. Once again, this isn't something I
+ use often with eLua. Most of the times my functions (especially the ones exported by a C module) are very simple, and they don't need upvalues or
+ environments at all. In conclusion, having a "simpler" function type would improve memory usage.
+</p>
+<h2>Details</h2>
+<p>The patch adds two new data types to Lua. Both or them are based on the lightuserdata type already found in Lua, and they share the same basic
+ attributes: they don't need to be dynamically allocated (as they're just pointers on steroids) and they're compared in the same way lightuserdatas
+ are compared (by value). And of course, they are not collectable, so the garbage collector won't have anything to do with them. The new types are:
+<ol>
+<li><b>lightfunctions</b>: these are "simple" functions, in the sense that they can't have upvalues or environments. They are just pointers to regular
+ C functions. Other than that, you can use them from Lua just as you'd use any other function.</li>
+
+<li><b>rotables</b>: these are read-only tables, but unlike the read-only tables that one can already implement in Lua with metamethods, they have a
+ very specific property: they don't need any RAM at all. They are fully constant, so they can be read directly from ROM. They have a number of
+ special features and limitations when compared with a regular table:
+<ul>
+ <li>rotables can only contain values of type "lightfunction", lua_Number or pointers to other rotables.</li>
+ <li>you can't add/delete/modify elements from rotables (obviously). However, rotables will honour the "__newindex" metamethod.</li>
+ <li>you can use rotables as metatables for both "regular" tables and for Lua types (via debug.setmetatable)</li>
+ <li>a rotable can have another rotable (or tself) as a metatable</li>
+ <li>you can iterate over rotables with pairs/ipairs/next just as you do with "regular" tables.</li>
+</ul></li></ol></p>
+<p>Just as with lightuserdata, you can only create lightfunctions and rotables from C code, never from Lua itself.<p>
+<h2>Testing</h2>
+<p>I tested my patch with the (<a target="_blank" href="http://lua-users.org/lists/lua-l/2006-03/msg00723.html">Lua 5.1 test suite</a>). The test suite
+ was an excellent testing tool. I thought I had the patch ready until I found the test suite and ran it. After another week of work, I had something
+ that could be called functional :)</p>
+<p>I tested everything via "make generic", which is how I always build Lua for my embedded environments. This means (among other things) that I didn't
+test pipes and dynamic module loading, although I don't see why they wouldn't work.</p>
+<p>I never tested the patch in a multithreaded environment with more threads running different lua_States. I never even used regular Lua like this,
+so I can't make asumptions about how my patch would behave in a multithreaded environment. It doesn't use any global or static variables, but you
+might encounter other problems with it.</p>
+<h2>Results</h2>
+<p>The table below summarizes the RAM usage in KBytes (as obtained by running <i>lua -e "print(collectgarbage'count')"</i> from the <b>eLua</b> shell).
+ <b>OPT=0</b> is LTR's "compatibility mode" (basically this means that the patch is disabled, so you're running plain Lua) and <b>OPT=2</b> is the
+ patch in action.</p>
+<table style="width: 325px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Platform</th>
+<th style="text-align: center;">OPT=0</th>
+<th style="text-align: center;">OPT=2</th>
+</tr>
+<tr>
+ <td>AVR32</td>
+ <td style="text-align: center;">23.75</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>AT91SAM7X</td>
+ <td style="text-align: center;">25.16</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>STR7</td>
+ <td style="text-align: center;">24.92</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>STR9</td>
+ <td style="text-align: center;">22.23</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>LPC2888</td>
+ <td style="text-align: center;">22.23</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>i386</td>
+ <td style="text-align: center;">16.90</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+<tr>
+ <td>LM3S</td>
+ <td style="text-align: center;">27.14</td>
+ <td style="text-align: center;">5.42</td>
+</tr>
+</tbody>
+</table>
+</p>
+<p>As you can see, the differences are significant, and (more important) it doesn't matter how many modules you load in <b>eLua</b>, the RAM consumption
+ doesn't modify.</p>
+<p>Currently, there aren't any performane measurements related to LTR. It's clear from the implementation that the patch slows down the virtual machine,
+ but a precise performance penalty figure is not known. Experience suggests that the peformance penalty is minimal, and it certainly can't be observed
+ with "regular" (non-computationally intensive) Lua programs.</p>
+<h2>How to enable LTR</h2>
+<p>Enabling LTR is very easy: all you need to do is specify the <b>opt=1</b> as a paramater to scons when bulding <b>eLua</b>, as explained
+ <a href="building.html">here</a>. You don't even to specify this explicitly, as LTR is enabled by default for all <b>eLua</b> targets.</p>
+<p>When <b>optram</b> is 0, LTR is not active. In this mode the patch just tries to keep the modified version as close as possible to the unpatched version
+ in terms of speed and functionality. You might want to use this if you want full Lua compatibility (although this is rarely an issue in practice),
+ or need to overcome the read-only limitations of rotables (but check <a href="faq.html#rotables">this</a> first). If your program behaves weird and you
+ suspect that LTR might be the cause of your problems, recompiling with <b>optram=0</b> is a quick way to eliminate or confirm your suspicions.</p>
+<p>When <b>optram</b> is 1 (default), all the LTR optimizations are enabled. The implementation of the Lua standard libraries is modified to take advantage
+ of the new datatypes. In particular, the IO library is modified to use the registry instead of environments, thus making it more resource-friendly,
+ the side effect being that this mode doesn't support pipes in the <b>io</b> module (which isn't an issue for <b>eLua</b>).
+ It also leaves the <b>_G</b> (globals) table with a single method (<i>__index</i>) and sets it as its own metatable, so all accesses to globals are
+ now sligthly slower because of the <i>__index</i> metamethod call.</p>
+<h2>Writing LTR-compatible modules</h2>
+<p>The LTR patch introduces a specific method for writing modules in such a way that they're fully compatible with both <b>optram=0</b> and <b>optram=1</b>.
+ If you're writing a new <b>eLua</b> module you should use this method, as it keeps code coherency. </p>
+<p>We'll show this method using a simple example. Let's assume that you want to register a simple module called "mod" that has a single function named "f".
+ For regular Lua, you'd do something like this:</p>
+<p><pre><code>static const luaL_reg mod_map[] =
+{
+ { "f", f_implementation },
+ { NULL, NULL }
+};
+
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+ luaL_register( L, "mod", mod_map );
+ return 1;
+}</code></pre></p>
+<p>For the rotables implementation, however, you'd need to define the same thing like this:<p>
+
+<p><pre><code>const luaR_entry mod_map[] = <font color="red">// note: no static this time</font>
+{
+ { LRO_STRKEY( "f" ), LRO_FUNCVAL( f_implementation ) },
+ { LRO_NILKEY, LRO_NILVAL }
+};
+
+<font color="red">// note: in this case the "luaopen_mod" function isn't really needed anymore</font>
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+ return 0;
+}</code></pre></p>
+
+<p>A few points about the rotables example above:
+<ul>
+ <li>a rotable needs a "map" (mod_map) array much like a regular module, but you need to define that array with special macros:
+ <ul>
+ <li><b>for keys</b>: <b>LRO_STRKEY("str")</b> defines a string key, <b>LRO_NUMKEY(n)</b> defines an integer key, and <b>LRO_NILKEY</b> defines a NULL
+ (empty) key</li>
+ <li><b>for values</b>: <b>LRO_FUNCVAL(f)</b> defines a lightfunction value, <b>LRO_NUMVAL(f)</b> defines a number value, <b>LRO_RO(p)</b> defines a
+ rotable value (p is the pointer to the rotable) and <b>LRO_NILVAL</b> defines a NULL (empty) value.</li>
+ </ul>
+ <li>all the "global" rotables in the system (the ones that must be visible from <b>_G</b>, like the rotables of all the modules exported to Lua) must be
+ included in a special array, called <b>lua_rotable</b> (defined in <i>linit.c</i>). Simply including the rotable's definition array (mod_map in this case)
+ in the lua_rotable array makes it visible globally, thus you don't need to call any kind of register function. This is why <b>luaopen_mod</b> now returns
+ 0.</li>
+</ul></p>
+<p>The two forms above (for regular tables and for rotables) are clearly different, but we want to keep them both to be able to work at both <b>optram=0</b>
+ and <b>optram=2</b>. You can use #ifdefs to differentiate between the two cases in different optimization levels, but this becomes really annoying after
+ a (short) while. This is why I added another file called <b>lrodefs.h</b> (<i>src/lua</i>) that can be used to give an "universal" definition to our map
+ arrays. Here's how our example looks after rewriting it to take advantage of <b>lrodefs.h</b>:</p>
+<p><pre><code><font color="red">#define MIN_OPT_LEVEL 2 // the minimum optimization level at which we use rotables</font>
+#include "lrodefs.h"
+const <font color="red"> LUA_REG_TYPE</font> mod_map[] = <font color="red">// note: no more luaL_reg or luaR_entry</font>
+{
+ { LSTRKEY( "f" ), LFUNCVAL( f_implementation ) },
+ { LNILKEY, LNILVAL }
+};
+// <font color="red">note: no more LRO_something, just Lsomething (for example LRO_STRKEY becomes LSTRKEY)</font>
+
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+ <font color="red">LREGISTER</font>( L, "mod", mod_map ); // <font color="red">note: no more luaL_register, no "return 1"</font>
+}</code></pre></p>
+<p>Now, if <b>LUA_OPTIMIZE_MEMORY</b> (a macro defined by the system as 0 when <b>optram=0</b> and as 2 when <b>optram=1</b>) is less than
+ <b>MIN_OPT_LEVEL</b>, the above definition will compile in its "regular table" format. If <b>LUA_OPTIMIZE_MEMORY</b> is 2, it compiles to the
+ rotables format. Problem solved :) <b>LREGISTER</b> will also take care of calling <b>luaL_register</b> and return 1 when <b>optram=0</b> and do
+ absolutely nothing when <b>optram=1</b>. You can see more examples of this in any module from <i>src/modules</i>, and you're encouraged to do so,
+ as this is only a very basic example; <i>src/modules</i> contains real life examples that can serve as a good basis for a new module.</p>
+<p>As you know by now, rotables can have metatables, and also you can set a rotable as a metatable for a regular table. If a rotable must have a
+ metatable, it needs a "__metatable" field to point to its metatable (which is also a rotable, not necessarily another rotable) and the usual
+ metatable functions. For example, let's make our <b>mod</b> rotable its own metatable and declare an <b>__index</b> function. Moreover, let's do
+ this for both <b>optram=0</b> and <b>optram=1</b>.</p>
+<p><pre><code>static int mod_mt_index( lua_State *L )
+{
+ return 0;
+}
+
+#define MIN_OPT_LEVEL 2 // the minimum optimization level at which we use rotables
+#include "lrodefs.h"
+const LUA_REG_TYPE mod_map[] =
+{
+ { LSTRKEY( "f" ), LFUNCVAL( f_implementation ) },
+<font color="red">#if LUA_OPTIMIZE_MEMORY > 0
+ { LSTRKEY( "__metatable" ), LROVAL( mod_map ) },
+#endif</font>
+ { LSTRKEY( "__index" ), LFUNCVAL( mod_mt_index) },
+ { LNILKEY, LNILVAL };
+};
+
+LUALIB_API int luaopen_mod( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ return 0;
+#else
+ luaL_register( L, "mod", mod_map );
+
+ <font color="red">// Set "mod" as its own metatable
+ lua_pushvalue( L, -1 );
+ lua_setmetatable( L, -2 );</font>
+
+ return 1;
+ #endif
+}</code></pre></p>
+<p>If you want to register a module using a regular Lua table, but use lightfunctions instead of regular functions, use <i>luaL_register_light</i> instead
+ of <i>luaL_register</i> (same syntax). </p>
+<p>More important things to keep in mind when working with LTR:
+<ul>
+ <li>currently, <b>MIN_OPT_LEVEL</b> should be always set to 2</li>
+ <li>you need a C99-compatible compiler to use LTR (because of the compile-time explicit union initialization that's needed to declare const rotables).
+ Fortunately this isn't a issue right now, as all current eLua targets use GCC and GCC knows how to handle this.</li>
+ <li>your linker command file should export two symbols: <b>stext</b> and <b>etext</b>. They should be declared before and after the .rodata* section
+ placement (generally you'd declare stext at the beginning of .text definition and etext and the end of .text definition, see for example
+ <i>src/lua/at91sam7x256/flash256.lds</i>). These are needed by the patch to differentiate between a regular table and a rotable (although this is likely
+ to change in a future version of the patch.</li>
+ <li><b><font color="red">remember to declare all you rotable's definition array as 'const'!!</font></b> Forgetting to do so will not only increase
+ memory usage, it will also make the patch not functional, because of the way it recognizes rotables (see above).</li>
+</ul></p>
+<a name="config"><h2>LTR and module configuration at build time</h2></a>
+<p>With unpatched Lua, you can specify what modules to be part of the Lua image by modifying <i>src/lua/linit.c</i>. In the particular case of <b>eLua</b>
+ one had to declare a list of the modules that must be compiled in <i>src/platform/<name>/platform_conf.h</i> like this:</p>
+<p><pre><code>#define LUA_PLATFORM_LIBS\
+ { AUXLIB_PIO, luaopen_pio },\
+ { AUXLIB_TMR, luaopen_tmr },\
+ { AUXLIB_PD, luaopen_pd },\
+ { AUXLIB_UART, luaopen_uart },\
+ { AUXLIB_TERM, luaopen_term },\
+ { AUXLIB_PWM, luaopen_pwm },\
+ { AUXLIB_PACK, luaopen_pack },\
+ { AUXLIB_BIT, luaopen_bit },\
+ { LUA_MATHLIBNAME, luaopen_math }
+</code></pre></p>
+ Things are a bit more complex with LTR, but not by much. The list of modules that must be compiled is declared via a preprocessor macro in
+ <i>src/platform/<name>/platform_conf.h</i> and it looks like this:</p>
+<p><pre><code>#define LUA_PLATFORM_LIBS_ROM\
+ _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+ _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+ _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+ _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
+ _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )</code></pre></p>
+<p>(<b>IMPORTANT NOTE</b>: the fact that there are no commas between two different _ROM declarations (as seen above) is NOT an error;
+ on the contrary, this is very much intended. Try using commas and you'll get in trouble very soon :) ).</p>
+<p>Note the 3rd parameter of the <b>_ROM</b> macro, which is the name of the definition array for the (ro)table. That's it. The code in linit.c will take
+ care of everything else, including initializing the list of modules in LUA_PLATFORM_LIBS_ROM with regular tables instead of rotables at <b>optram=0</b>
+ (to maintain compatilibity with regular Lua). You can also have a list of modules that you want to use with regular tables no matter what the
+ optimization level is. In that case, list it in the <b>LUA_PLATFORM_LIBS_REG</b> macro via the old syntax for <b>LUA_PLATFORM_LIBS</b>, as shown
+ above (the regular Lua syntax for defining a module to be registered with luaL_register). If you want this module to use lightfunctions instead of
+ regular functions (at <b>optram=1</b>), use <i>luaL_register_light</i> instead of <i>luaL_register</i>.
+</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/arch_newport.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_newport.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_newport.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,143 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Porting eLua</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Porting eLua</h3>
+<p>So, you realized how cool <b>eLua</b> is :), and you'd like to give it a try. Unfortunately, <b>eLua</b> doesn't have a port on your CPU or board of choice.
+ The solution is simple: write the port yourself. This might seem as a daunting task at first, but it's actually easier than it sounds. <b>eLua</b> was
+ designed to make the task of implementing new ports as easy and intuitive as possible. This section gives an overview of the porting process. It's not
+ an exhaustive guide, but it should be enough to point you in the right direction. Before diving into this, it's highly recommended that you take a look
+ at the <a href="elua_arch.html">eLua architecture page</a>. </p>
+<h3>Prerequisites</h3>
+<p>Before starting to work on the port, make sure that:
+<ul>
+ <li>your CPU has enough resources to run <b>eLua</b>. A very rough estimation (based on ARM Thumb code only) is that you'd need at least 256k
+ of program memory and 32k of RAM for a complete <b>eLua</b> image, and 128k of program memory for a basic image. It's possible to run <b>eLua</b> in
+ less than 32k of RAM (especially when <a href="arch_ltr.html">LTR</a> is enabled), but you'll probably run out of memory fast.
+ 64k of RAM (or more) is recommended.</li>
+ <li><a target="_blank" href="http://sourceware.org/newlib">Newlib</a> is available for your CPU. <b>eLua</b> depends on Newlib currently
+ (although this limitation will be eliminated in a future version), so if Newlib is not available for your CPU, you're out of luck. </li>
+ <li>you have a C compiler for your target. Ideally you'd use GCC, but if this isn't possible other compilers might work as well. Keep in mind that
+ <a href="arch_ltr.html">LTR</a> needs a C99 C compiler (or at least a partially C99 compliant C compiler than supports C99-style union initialization).
+ </li>
+ <li>you have a platform library (it usually comes from the CPU manufacturer) that you can use to implement (at least part of) the platform interface.
+ It's also highly recommended to gain at least a basic understanding of your platform, it will help a lot while writing the port.</li>
+</ul></p>
+<p>If all of the above are true, you should continue reading this document to bring your port to life. If not, we're sorry, but (at least at this point)
+<b>eLua</b> can't be ported to your CPU. If, on the other hand, you're good to go, please take a bit of time and read
+ <a href="arch_overview.html#platforms">this section</a> first, as it details the structure of a port and might simplify your work quite a bit.</p>
+<a name="newboard"><h3>Adding a new board</h3></a>
+<p>If all you need is to add a new board that uses a CPU already supported by <b>eLua</b> (check <a href="status.html">here</a> for a complete list), it's
+fairly easy to accomplish this:
+<ol>
+ <li>choose a good name for your board :)</li>
+ <li>edit <b>SConstruct</b> and add your board to the <b>board_list</b> dictionary, specifying its CPU. A part of the definition of <b>board_list</b> is given below:
+<p><pre><code># List of board/CPU combinations
+board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ],
+ 'EK-LM3S8962' : [ 'LM3S8962' ],
+ 'EK-LM3S6965' : [ 'LM3S6965' ],
+ ..............................
+ }</code></pre></p>
+ </li>
+ <li>also edit the <b>file_list</b> dictionary in <b>SConstruct</b> to specify the list of ROMFS files that will be compiled for your board (see the
+ <a href="arch_romfs.html">ROMFS section</a> for details). A part of the definition of <b>file_list</b> is given below:
+<p><pre><code># List of board/romfs data combinations
+file_list = { 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
+ 'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ 'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ ...............................
+ }</code></pre></p></li>
+ <li>if your board has external memory, you'll probably want to use the "multiple" allocator by default to take advantage of that (see <a href="building.html">building</a>)
+ for details. If so, you need to modify the CPU/allocator mapping code from <b>SConstruct</b>:
+<p><pre><code># CPU/allocator mapping (if allocator not specified)
+if allocator == '':
+ if <b>boardname == 'LPC-H2888'</b> or <b>boardname == 'ATEVK1100'</b>:
+ allocator = 'multiple'
+ else:
+ allocator = 'newlib'
+elif allocator not in [ 'newlib', 'multiple', 'simple' ]:
+ print "Unknown allocator", allocator
+ print "Allocator can be either 'newlib', 'multiple' or 'simple'"
+ sys.exit( -1 )
+</code></pre></p>
+ </li>
+ <li>customize the <b>eLua</b> image for this new board. You can use the variable <b>boardname</b> in <b>conf.py</b> to define new preprocessor macros specifically for your board
+ (that you can use later in <b>platform_conf.h</b>, for example), or to include or exclude certain files from the build, or change the build flags and so on. An example taken from
+ the <b>lm3s</b> port is given below (part of <b>conf.py</b>):
+<p><pre><code>if boardname == 'EK-LM3S6965' or boardname == 'EK-LM3S8962':
+ specific_files = specific_files + " rit128x96x4.c disp.c"
+ cdefs = cdefs + " -DENABLE_DISP"
+
+# The default for the Eagle 100 board is to start the image at 0x2000,
+# so that the built in Ethernet boot loader can be used to upload it
+if boardname == 'EAGLE-100':
+ linkopts = "-Wl,-Ttext,0x2000"
+else:
+ linkopts = ""
+</code></pre></p>
+</li>
+</ol></p>
+<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board.</p>
+<a name="newcpu"><h3>Adding a new CPU</h3></a>
+<p>If you want to add a new CPU to <b>eLua</b> and the new CPU happens to be supported by a platform on which <b>eLua</b> already runs (see <a href="status.html">here</a> for a full
+list), your task is still quite easy. Follow the steps below:
+<ol>
+ <li>edit <b>SConstruct</b> and add your new CPU to the <b>platform_list</b> dictionary. Use the "official" name of the CPU (as it appears in its datasheet). An example is given below:
+<p><pre><code># List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ ..................
+}</code></pre></p></li>
+ <li>you also need to add a new board to <b>eLua</b> (which makes sense, since you're most likely going to run <b>eLua</b> on a board built around the CPU
+ of your choice, not only on the CPU itself). So follow the instruction from the <a href="arch_newport.html#newboard">previous paragraph</a> to add
+ your new board.</li>
+ <li>customize the <b>eLua</b> image for this new CPU. You can use the variable <b>cputype</b> in <b>conf.py</b> to define new preprocessor macros specifically for your CPU
+ (that you can use later in <b>platform_conf.h</b>, for example), or to include or exclude certain files from the build, or change the build flags and so on. An example taken from
+ the <b>at91sam7x</b> port is given below (part of <b>conf.py</b>):
+<p><pre><code>if cputype == 'AT91SAM7X256':
+ ldscript = "flash256.lds"
+ cdefs = cdefs + " -Dat91sam7x256"
+elif cputype == 'AT91SAM7X512':
+ ldscript = "flash512.lds"
+ cdefs = cdefs + " -Dat91sam7x512"
+else:
+ print "Invalid AT91SAM7X CPU %s" % cputype
+ sys.exit( -1 ) </code></pre></p>
+</ol></p>
+<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board (and implicitly for
+ your new CPU).</p>
+<a name="newplatform"><h3>Adding a new platform</h3></a>
+<p>If you want to add a new CPU to <b>eLua</b> and the new CPU is not supported by a platform on which <b>eLua</b> already runs (see <a href="status.html">here</a> for a full list), you have to
+go the whole way and add a completely new platform to <b>eLua</b>. This is certainly more difficult than the previous cases, but still not that hard. Remember to start small (implement only
+minimal support at first) and don't write everything from scratch, start from an already existing platform implementation and work your way up from there. The <b>i386</b> port is the simplest,
+but also a bit different from the embedded ports. Another port that is quite simple at this point is the <b>lpc2888</b> port, you might take a look at that too. After you "get a feeling" of
+how a port should look like, and after you read about the architecture of <b>eLua</b> and the structure of a port <a href="arch_overview.html">here</a>, follow the steps below:
+<ol>
+ <li>choose the name of your new platform. It should be an easy, descriptive name. For example, all the CPUs from the LM3S series are grouped inside a platform called <b>lm3s</b>.</li>
+ <li>create the <i>src/platform/<name></i> directory, and add all your platform-specific files here. Check <a href="arch_overview.html#platforms">here</a> for specific details.</li>
+ <li>use the instructions from the <a href="arch_newport.html#newcpu">previous paragraph</a> to add your new CPU and board to <b>eLua</b>.</b>
+ <li>implement as much as you need from the <a href="arch_platform.html">platform interface</a>.</li>
+ <li>if your new platform uses a toolchain that wasn't previously configured in <b>eLua</b>, add it now (see <a href="toolchains.html">here</a> for more details about toolchains).</li>
+ <li>let <b>SConstruct</b> know about your new platform by modifying the <b>platform_list</b> variable to add information about the CPU(s) available for your platform and about its toolchains.
+An example is given below:
+<p><pre><code># List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ 'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
+ ..................
+}</code></pre></p></li>
+ </ul></li>
+</ol></p>
+<p>After you edit all the relevant source files, all you have to do is to execute <i>scons board=<boardname></i> and you'll have <b>eLua</b> compiled for your board (and implicitly for
+ your new CPU).</p>
+</body></html>
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===================================================================
--- branches/eagle_mmc/doc/en/arch_overview.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_overview.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,218 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua architecture overview</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<a name="structure"><h3>eLua architecture overview</h3></a>
+<p>The overall logical structure of <b>eLua</b> is shown in the image below:</p>
+<map name="arch">
+<area href="arch_overview.html#common" title="Commond code" shape=rect coords="0, 402, 537, 540">
+<area href="arch_overview.html#platform" title="Platform interface" shape=rect coords="0, 198, 537, 336">
+<area href="arch_overview.html#platforms" title="Platforms" shape=rect coords="9, 0, 537, 132">
+</map>
+<p align="center"><img src="../wb_img/elua_arch.png" usemap="#arch" border=0></img></p>
+<p><b>eLua</b> uses the notion of <b>platform</b> to denote a group of <b>CPUs</b> that share the same core structure, although their specific silicon
+ implementation might differ in terms of intergrated peripherals, internal memory and other such attributes. An <b>eLua</b> port implements one or
+ more CPUs from a given platform. For example, the <b>lm3s port</b> of <b>eLua</b> runs on LM3S8962, LM3S6965 and LM3S6918 CPUs, all of them part of the
+ <b>lm3s</b> platform. Refer to <a href="status.html">the status page</a> for a full list of platforms and CPUs on which <b>eLua</b> runs.</p>
+<p>As can be seen from this image, <b>eLua</b> tries to be as portable as possible between different platforms by using a few simple design
+rules:
+<ul>
+ <li>all code that is platform-independent is <b>common code</b> and it should be written in ANSI C as much as possible, this makes it highly portable
+ among different architectures and compilers, just like Lua itself. </li>
+ <li>all the code that can't possibly be generic (mostly peripheral and CPU specific code) must still be made as portable as possible by using a common
+ interface that must be implemented by all platforms on which <b>eLua</b> runs. This interface is called <b>platform interface</b> and is discussed in
+ detail <a href="arch_platform.html">here</a> (but please see also <a href="arch_overview.html#platform">"The platform interface"</a>
+ paragraph in this document).</li>
+ <li>all platforms (and their peripherals) are not created equal and vary greatly in capabilities. As already mentioned, the platform interface tries
+ to group only common attributes of different platforms. If one needs to access the specific functionality on a given platform (like the loopback support
+ mentioned before) it can do so by using a <b>platform module</b>. These are of course platform specific, and their goal is to fill the gap between the
+ platform interface and the full set of features provided by a platform.</li>
+</ul></p>
+<a name="common"><h3>Common (generic) code</h3></a>
+<p>The following gives an incomplete set of items that can be classified as <b>common code</b>:
+ <ul>
+ <li>the Lua code itself (obviously) plus the <a href="arch_ltr.html">LTR patch</a>.</li>
+ <li>all the <b>components</b> in <b>eLua</b> (like the ROM file system, the XMODEM receive code, the <b>eLua</b> shell, the TCP/IP stack and others).
+ </li>
+ <li>all the <b>generic modules</b>, which are Lua modules used to expose the functionality of the platform to Lua.</li>
+ <li>generic <b>peripheral support code</b>, like the ADC support code (<i>src/common/elua_adc.c</i>) that is <b>independent</b> of the actual ADC
+ hardware.
+ <li>libc code (for example allocators and Newlib stubs).
+ </ul></p>
+<p>This should give you a pretty good idea about what "common code" means in this context. Note that the generic code layer should be as "greedy" as
+possible; that is, it should absorb as much common code as possible. For example:
+<ul>
+ <li>if you want to add a new file system to <b>eLua</b>, this should definitely be generic code. It's likely that this kind of code will have
+ dependencies related to the physical medium on which this file system resides. If you're lucky, you can solve these dependencies using only the functions
+ defined in the <a href="elua_platform.html">platform interface</a> (this would make sense if you're using a SD card controlled over SPI, since the
+ platform interface already has a SPI layer). If not, you should group the platform specific functions in a separate interface that will be implemented by
+ all platform that want to use your new file system. This gives the code maximum portability.</li>
+ <li>if you want to add a driver for a specific ADC chip that works over SPI, the same observations apply: write it as common code as much as you can,
+ and use the <a href="elua_platform.html">platform interface</a> for the specific SPI functions you need.</li>
+</ul></p>
+<p>When designing and implementing a new component, keep in mind other <b>eLua</b> design goal: <b>flexibility</b>. The user should be able to
+ select which components are part of its <b>eLua</b> binary image (as described <a href="building.html">here</a>), and the implementation should take
+ this into consideration. The same thing holds for the generic modules: the user must have a way to choose the set of modules he needs.</p>
+<p>For maximum portability, make your code work in a variety of scenarios if possible (and if that makes sense from a practical point of view).
+ Take for example the code for stdio/stdout/stderr handling (<i>src/newlib/genstd.c</i>): it acknowledges the fact that a terminal can be implemented
+ over a large variety of physical transports (RS-232 for PC, SPI for a separate LCD/keyboard board, a radio link and so on) so it uses pointers for its
+ send/receive functions (see <a href="arch_con_term.html">this link</a> for more details). The impact on speed and resource consumption is minimum, but
+ it matters a lot in the portability department.</p>
+<a name="platform"><h3>Platform interface</h3></a>
+<p>Used properly, the platform interface allows writing extremely portable code over a large variety of different platforms, both from C and from Lua.
+ An important property of the platform interface is that it tries to group only <b>common</b> attributes of different platforms (as much as possible).
+ For example, if a platform supported by <b>eLua</b> has an UART that can work in loopback mode, but the others don't, loopback support won't be included
+ in the platform interface.</p>
+<p>A special emphasis on the platform interface usage: remember to use it not only for Lua, but also for C. The platform interface is mainly used by the
+ generic modules to allow Lua code to access platform peripherals, but this isn't its only use. It can (and it should) also be used by C code that wants
+ to implement a generic module and neeeds access to peripherals. An example was given in the previous section: implementing a new file system.</p>
+<p>The platform interface definition is always in the <i>inc/platform.h</i> header file. For a full description of its functions, check
+ <a href="arch_platform.html">the platform interface documentation.</a></p>
+<a name="platforms"><h3>Platforms and ports</h3></a>
+<p>All the platforms that run <b>eLua</b> (and that implement the platform interface) are implemened in this conceptual layer. A <b>port</b> is a full
+ <b>eLua</b> implementation on a given platform. The two terms can generally be used interchangeably.</p>
+<p>A port can (and generally will) contain specific peripheral drivers, many times taken directly from the platform's CPU support
+ package. These drivers are used to implement the platform interface. Note that:
+<ul>
+ <li>a port isn't required to implement <b>all</b> the platform interface functions, just the ones it needs. As explained
+ <a href="building.html">here</a>, the user must have full control over what's getting built into this <b>eLua</b> image. If you don't need the SPI
+ module, for example, you don't need to implement its platform interface.</li>
+ <li>a part of the platform interface is implemented (at least partially) in a file that is common for all the platforms (<i>src/common.c</i>). It
+ eases the implmentation of some modules (such as the timer module) and also implements common features that are tied to the platform interface,
+ but have a common behaviour on all platforms (for example virtual timers, see <a href="">##here</a> for details). You probably won't need to modify
+ if you're writing platform specific code, but it's best to keep in mind what it does.</li>
+</ul></p>
+<p>A platform implementation might also contain one or more <b>platform dependent modules</b>. As already exaplained, their purpose is to allow Lua
+ to use the full potential of the platform peripherals, not only the functionality covered by the platform interface, as well as functionality that
+ is so specific to the platform that it's not even covered by the platform interface. By convention, all the platform dependent modules should be
+ grouped inside a single module that has the same name as the platform itself. If the platform dependent module augments the functionality of a
+ module already found in the platform interface, it should have the same name, otherwise it should be given a different, but meaningful name. For example:
+<ul>
+ <li>if implementing new functionality on the UART module of the LM3S platform, the corresponding module should be called <b>lm3s.uart</b>.</li>
+ <li>if implementing a peripheral driver that for some reason should be specific to the platform on the LPC2888 platform, for example its dual audio
+ DAC, give it a meaningful name, for example <b>lpc288x.audiodac</b>.</li>
+</ul></p>
+<h2>Structure of a port</h2>
+<p>All the code for platform <i>name</i> (including peripheral drivers) must reside in a directory called <i>src/platform/<name></i> (for example
+<i>src/platform/lm3s</i> for the <i>lm3s</i> platform). Each such platform-specific subdirectory must contain at least these files:</p>
+<ul>
+ <li><b>type.h</b>: this defines the "specific data types", which are integer types with a specific size (see <a href="arch_coding.html">coding style</a>
+ for details. An example from the <b>i386</b> platform:
+<p><pre><code>typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned long u32;
+typedef signed long s32;
+typedef unsigned long long u64;
+typedef signed long long s64;</code></pre></p>
+ </li>
+ <li><b>conf.py</b>: this is the platform specific build configuration file, used by the <a href="building.html">build system</a> for a number of purposes:
+<ul>
+ <li>to get the list of platform-specific files that will be compiled in the <b>eLua</b> image. They are exported in the <i>specific_files</i> string,
+ separated by spaces, and must be prepended with the relative path to the platform subdirectory. An example from the <b>i386</b> platform:
+<p><pre><code>specific_files = "boot.s common.c descriptor_tables.c gdt.s interrupt.s isr.c kb.c monitor.c timer.c platform.c"
+# Prepend with path
+specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )</code></pre></p>
+ </li>
+ <li>to get the full command lines of the different toolchain utilities (linker, assembler, compiler) used to compile <b>eLua</b>. They must be declared
+ inside the <i>tools</i> variable, in a separate dictinoary which key is the same as the platform name, and with specific names for each tool in turn:
+ <b>cccom</b> for the compiler, <b>linkcom</b> for the linker and <b>ascom</b> for the assembler.
+ For example, this is how the <i>tools</i> variable is defined for the <b>i386</b> platform:
+ <p><pre><code># Toolset data
+ tools[ 'i386' ] = {}
+ tools[ 'i386' ][ 'cccom' ] = "%s %s %s -march=i386 -mfpmath=387 -m32 -ffunction-sections -fdata-sections -fno-builtin -fno-stack-protector %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, local_include, cdefs )
+ tools[ 'i386' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib -march=i386 -mfpmath=387 -m32 -T %s -Wl,--gc-sections -Wl,-e,start -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
+ tools[ 'i386' ][ 'ascom' ] = "%s -felf $SOURCE" % toolset[ 'asm' ]</code></pre></p>
+ Note how the definition of <b>tools</b> uses the definition of <b>toolset</b>, a dictionary with the names of the tools in the current toolchain. This
+ is also part of the <b>eLua</b> build system and is documented <a href="toolchains.html">here</a>.</li>
+ <li>to get the name of a <b>programmning function</b> which receives the name of the <b>eLua</b> executable file (the result of the build step) and
+ produces a file suitable for programming on the corresponding hardware platform. The name of this function should also be set in the <i>tools</i>
+ dictionary, as shown below (example taken from the <b>str7</b> platform):
+ <p><pre><code># Programming function for STR7
+ def progfunc_str7( target, source, env ):
+ outname = output + ".elf"
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
+ print "Generating binary image..."
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
+
+ tools[ 'str7' ][ 'progfunc' ] = progfunc_str7</code></pre></p>
+ Note, once again, how this function uses the same <i>toolset</i> variable mentioned in the previous paragraph.
+ </li>
+ </ul>
+ </li>
+<li><b>stacks.h</b>: by convention, the stack(s) size(s) used in the system are declared in this file. An example taken from the <b>at91sam7x</b> platform is given below:
+<p><pre><code>#define STACK_SIZE_USR 2048
+#define STACK_SIZE_IRQ 64
+#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )</code></pre></p></li>
+<li><b>platform.c</b>: by convention, the <a href="arch_platform.html">platform interface</a> is implemented in this file. It also contains the platform-specific
+ initialization function (<i>platform_init</i>, see the description of the <a href="elua_arch.html#boot">eLua boot process</a> for details).</li>
+<li><b>platform_conf.h</b>: this is the platform configuration file, used to give information about both the platform itself and the build configuration for the
+ platform. This is what you can set inside <b>platform_conf.h</b>:
+<ul>
+ <li>the list of <b>components</b> that will be part of the build (see <a href="building.html">building eLua</a> for details).</li>
+ <li>the list of <b>modules</b> that will be part of the build (see <a href="building.html">building eLua</a> and <a href="arch_ltr.html#config">LTR configuration</a>
+ for details.</li>
+ <li>the <b>static configuration data</b> (see <a href="building.html">building eLua</a> for details).</li>
+ <li>the <b>number of peripherals</b> on your CPU. See an example below (taken from <b>lm3s</b>) that also shows how to differentiate between different CPUs that belong to the same
+ platform; the <b>FORxxxx</b> macros are defined in <b>conf.py</b>):
+<p><pre><code></code>// Number of resources (0 if not available/not implemented)
+#define NUM_PIO 7
+#define NUM_SPI 1
+#ifdef FORLM3S6965
+ #define NUM_UART 3
+#else
+ #define NUM_UART 2
+#endif
+#define NUM_TIMER 4
+#ifndef FORLM3S6918
+ #define NUM_PWM 6
+#else
+ #define NUM_PWM 0
+#endif
+#define NUM_ADC 4</pre></p></li>
+ <li><b>specific peripheral configuration</b>: this includes (but it not limited to) enabling buffering on UART, enabling and setting up virtual timers, setting PIO configuration and so on.
+ All these parameters are described in detail in the <a href="arch_platform.html">platform interface section</a>.
+ <li><b>memory configuration</b>: describes the regions of free RAM in the system, which will be later used by the standard system allocator (malloc/realloc/free). Two macros
+ (<b>MEM_START_ADDRESS</b> and <b>MEM_END_ADDRESS</b>) define two arrays with the beginning and the end of all the free RAM memory in the system. If your board has external RAM memory, you
+ should define it here. If not, you can only use the internal memory, and you'll generally need to use the linker-defined symbol <b>end</b> to find out where your free memory starts. Following
+ is an example from the <b>ATEVK1100</b> (AVR32) board that has both on-chip and external RAM:
+<p><pre><code>// Allocator data: define your free memory zones here in two arrays
+// (start address and end address)
+#define MEM_START_ADDRESS { ( void* )end, ( void* )SDRAM }
+#define MEM_END_ADDRESS { ( void* )( 0x10000 - STACK_SIZE_TOTAL - 1 ), ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
+</code></pre></p>
+ </li>
+</ul>
+ If you want to take a look at a real life example of a <b>platform_conf.h</b> file, see for example <i>src/platform/lm3s/platform_conf.h</i>.
+</li>
+ <li><b>networking configuration</b>: if you need TCP/IP on your board, you need to add networking support to <b>eLua</b> (see <a href="building.html">
+ building</a> for a list of configuration options related to TCP/IP). You also need to have another file, called <b>uip-conf.h</b> that configures uIP
+ (the TCP/IP stack in <b>eLua</b>) for your specific architecture. See <a href="arch_tcpip.html">TCP/IP in eLua</a> for details.</li>
+</ul></p>
+<p>Besides the required files, the most common scenario is to include other platform specific files in your port:
+<ul>
+ <li><b>a "startup sequence"</b>, generally written in assembler, that does very low level
+ intialization, sets the stack pointer, zeroes the BSS section, copies ROM to
+ RAM for the DATA section, and then jumps to main.</li>
+ <li>a <b>linker command file</b>.
+ <li>the <b>CPU support package</b> generally comes from the CPU manufacturer, and includes code
+ for accessing peripherals, configuring the core, setting up interrupts and so on.</li>
+</ul></p>
+<a name="boot"><h3>eLua boot process</h3></a>
+<p>This is what happens when you power up your <b>eLua</b> board:
+<ol>
+ <li>the platform initialization code is executed. This is the code that does very low level platform setup (if needed), copies ROM to RAM, zeroes out
+ the BSS section, sets up the stack pointer and jumps to <b>main</b>.</li>
+ <li>the first thing <b>main</b> does is call the platform specific initialization function (<b>platform_init</b>). <b>platform_init</b> must fully
+ initialize the platform and return a result to main, that can be either <b>PLATFORM_OK</b> if the initialization succeded or <b>PLATFORM_ERR</b>
+ otherwise. If <b>PLATFORM_ERR</b> is returned, <b>main</b> blocks immediately in an infinite loop.</li>
+ <li><b>main</b> then initializes the rest of the system: the ROM file system, XMODEM, and term.</li>
+ <li>if <b>/rom/autorun.lua</b> (which is a file called <b>autorun.lua</b> in the <a href="arch_romfs.html">ROM file system</a>) is found, it is
+ executed. If it returns after execution, or if it isn't found, the boot process continues with the next step.</li>
+ <li>if the <a href="using.html#shell">shell</a> was compiled in the image, it is started, otherwise a standard Lua interpreter is started.</li>
+</ol>
+</body></html>
Added: branches/eagle_mmc/doc/en/arch_platform.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_platform.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_platform.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua platform interface</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>The platform interface</h3>
+<p>The platform interface is the part of <b>eLua</b> that makes it easily portable between different hardware platforms by grouping the common elements
+ of all platforms supported by <b>eLua</b> in a common interface. For more details about the platform interface and the overall structure of
+ <b>eLua</b> in general, check <a href="arch_overview.html">this link</a>.</p>
+ <p>The platform interface is defined in the <i>inc/platform.h</i> header file from the <b>eLua</b> source distribution. It is a collection of various
+ components (UART, SPI, timers ...), each of them is detailed in the next subsections. Each such component has an <b>id</b> which is a number that
+ identifies that component in <b>eLua</b>. Generally, numbers are assigned to components in their "natural" order; for example, PORTA will have the id
+ 0, PORTB will have 1 and so on. Similarly, the second SPI interface (SPI1) of the MCU will probably have an id equal to 1. However, this is not a strict
+ rule. The implementation of the platform interface might choose to expose only some of the peripherals (components) of the MCU, thus this rule might be
+ broken. For example, if a board has 3 UARTs, but for some reason the second UART (UART1) is dedicated and can't be touched by <b>eLua</b>, then UART0 will have the id 0 and UART2 will
+ have the id 1, so UART1 won't ever be accesible to the code. Such cases are documented in the <a href="">##specific usage notes</a> section.</p>
+ <p>With some exceptions (most notably the low-level support functions), the different modules supported by the platform interface are
+ mirrored more or less accurately in separate Lua modules that can be used directly from <b>eLua</b>. Check <a href="">the reference manual</a> for a
+ complete description of these modules.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/arch_romfs.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_romfs.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_romfs.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>The ROM file system</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>The ROM file system</h3>
+<p>The ROM file system (ROMFS) is a small, read-only file system built for <b>eLua</b>. It is integrated with the C
+ library, so you can use standard POSIX calls (fopen/fread/fwrite...) to access it. It is also accessible directly from Lua via the <b>io</b> module.
+ The files in the file system are part of the <b>eLua</b> binary image, thus they can't be modified after the image is
+ built. For the seame reason, you can't add/delete files after the image is built. ROMFS doesn't support directories.</p>
+<p>ROMFS is integrated with <a href="building.html">the build system</a> for maximum flexibility on various platforms. As a result, you can select the ROMFS contents for each board on which
+ <b>eLua</b> runs. Moreover, you can specify what <b>applications</b> (instead of individual files) go to the file system, as a real application might need more than a single Lua program
+ to run (for example a HTTP page with all its dependencies).</p>
+<h2>Using ROMFS</h2>
+<p>To use ROMFS, you have to copy the required files to the <i>romfs/</i> directory. Keep in mind that the maximum file name of a ROMFS file is 14 characters, including the dot between the file
+ name and its extension. Make sure that the file names from <i>romfs/</i> follow this rule. Then edit the main build script (<b>SConstruct</b>) to add a new application/modify an existing one.
+ All the applications that can be included in ROMFS are defined in the <b>romfs</b> array in <b>SConstruct</b>. Each application in the <b>romfs</b> array lists its files, as shown below
+ (note that <b>ltthpd</b>, <b>tvbgone</b> and <b>pong</b> applications require more than one file in order to run):</p>
+<p><pre><code>romfs = {
+ 'bisect' : [ 'bisect.lua' ],
+ 'hangman' : [ 'hangman.lua' ],
+ 'lhttpd' : [ 'index.pht', 'lhttpd.lua', 'test.lua' ],
+ 'pong' : [ 'pong.lua', 'LM3S.lua' ],
+ 'led' : [ 'led.lua' ],
+ 'piano' : [ 'piano.lua' ],
+ 'pwmled' : [ 'pwmled.lua' ],
+ 'tvbgone' : [ 'tvbgone.lua', 'codes.bin' ],
+ 'hello' : [ 'hello.lua' ],
+ 'info' : [ 'info.lua' ],
+ 'morse' : [ 'morse.lua' ],
+ 'dualpwm' : [ 'dualpwm.lua' ],
+ 'adcscope' : [ 'adcscope.lua' ],
+ 'life' : [ 'life.lua' ]
+}</code></pre></p>
+<p>After this, you need to decide the application-to-board mapping. This is defined in another array in <b>SConsctruct</b>, named <b>file_list</b>. The definition of this array is shown below,
+ the format is self-explanatory:</p>
+<p><pre><code>file_list = {
+ 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
+ 'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ 'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope' ],
+ 'STR9-COMSTICK' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'PC' : [ 'bisect', 'hello', 'info', 'life' ],
+ 'LPC-H2888' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'MOD711' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'dualpwm' ],
+ 'STM3210E-EVAL' : [ 'bisect', 'hello', 'info' ],
+ 'ATEVK1100' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
+ 'ET-STM32' : [ 'hello', 'hangman', 'info', 'bisect' ],
+ 'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ]
+}
+</code></pre></p>
+<p>What's left to do is <a href="building.html">biuld eLua</a>. As part of the build process, <b>mkfs.py</b> will be called, which will read the contents of the <i>romfs/</i> directory and
+ output a C header file that contains a binary description of the file system. To use ROMFS from C code, whevener you want to access a file, prefix its name with <b>/rom/</b>. For example,
+ if you want to open the <b>a.txt</b> file in ROMFS, you should call fopen like this:</p>
+<p><pre><code>f = fopen( "/rom/a.txt", "rb" )</code></pre></p>
+<p>If you want to execute one file from the ROM file system with Lua, simply do this from the shell:</p>
+ <p><pre><code>eLua# lua /rom/bisect.lua</code></pre></p>
+<p>Or directly from Lua:</p>
+ <p><pre><code>> dofile "/rom/bisect.lua"</code></pre></p>
+</body></html>
+
Added: branches/eagle_mmc/doc/en/arch_tcpip.html
===================================================================
--- branches/eagle_mmc/doc/en/arch_tcpip.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/arch_tcpip.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>TCP/IP in eLua</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>TCP/IP in eLua <font color="red">(WIP)</font></h3>
+<p><b>eLua</b>'s TCP/IP support was designed with flexibility and ease of use in mind. It
+might not provide all the functions of a "full-fledged" TCP/IP stack, but it's
+still fully functional and probably easier to use than a "regular" (POSIX) TCP/IP
+stack. These are the services provided by the TCP/IP stack:
+<ul>
+ <li>a set of functions for network access (defined in inc/elua_net.h)</li>
+ <li>a DHCP client</li>
+ <li>a DNS resolver</li>
+ <li>a module (<a href="m_net.html">net</a>) which can be used from Lua to access the network functions</li>
+ <li>a Telnet miniclient, which is used to support the eLua shell via TCP/IP instead of serial connections.</li>
+</ul>
+</p>
+<h2>TCP/IP configuration</h2>
+<p>To configure the TCP/IP subsystem, <i>edit src/platform/<name>platform_conf.h</i> and:
+<ol>
+<li><b>#define BUILD_UIP</b> to enable TCP/IP support</li>
+<li>if you'll be using the DHCP client, just <b>#define BUILD_DHCPC</b> to build the
+ DHCP client. In any case, you must also define a static network configuration:
+
+<p><b>#define ELUA_CONF_IPADDR0 ... ELUA_CONF_IPADDR3</b> : the IP address<br>
+ <b>#define ELUA_CONF_NETMASK0 ... ELUA_CONF_NETMASK3</b> : the network mask<br>
+ <b>#define ELUA_CONF_DEFGW0 ... ELUA_CONF_DEFGW3</b> : the default gateway<br>
+ <b>#define ELUA_CONF_DNS0 ... ELUA_CONF_DNS3</b> : the DNS server </p>
+
+ Note that you must define both <b>BUILD_DHCPC</b> and the <b>ELUA_CONF_*</b> macros. If the
+ DHCP client fails to obtain a valid IP address, the static configuration will
+ be used instead. To use only the static configuration (and make the eLua image
+ size a bit smaller) don't define the BUILD_DHCPC client.</li>
+
+<li><b>#define BUILD_DNSM</b> if you want support for the DNS server.</li>
+<li><b>#define BUILD_CON_TCP</b> if you want support for shell over telnet instead of
+ serial. Note that you must NOT define <b>BUILD_CON_GENERIC</b> in this case (see
+ <a href="arch_con_term.html">here</a> for details).</li>
+</ol></p>
+<p>You'll also need an uIP configuration file (<i>src/platform/<name>/uip-conf.h</i>) to configure the TCP/IP
+stack. For an example, look at <i>src/platform/<lm3s>/uip-conf.h</i>. The header if quite self-explanatory, below
+you have a list of parameters that you might want to change:
+<ul>
+ <li><b>u8_t, u16_t</b>: define these types to match your platform.</li>
+ <li><b>UIP_CONF_MAX_CONNECTIONS</b>: the maximum number of TCP connections that can be active at a given time.</li>
+ <li><b>UIP_CONF_UDP_CONNS</b>: same thing for UDP connections.</li>
+ <li><b>UIP_CONF_BYTE_ORDER</b>: <b>LITTLE_ENDIAN</b> or <b>BIG_ENDIAN</b>, it's very important to match this with your architecture.</li>
+ <li><b>UIP_CONF_BUFFER_SIZE</b>: the size of the buffer used by uIP for all its connections. You should keep it small to avoid memory consumption,
+ but doing so when you have to transfer large amounts of data will slow the transfer speed. 1k seems to be a good compromise.</li>
+ <li><b>UIP_CONF_UDP</b>: turn off UDP support. While <b>eLua</b> doesn't have support for UDP via its <b>net</b> module at this time, UDP can still
+ be used (for example by DNS/DHCP), so be careful if you disable this.</li>
+ <li><b>ELUA_DHCP_TIMER_ID</b>: the timer ID used for the TCP/IP subsystem. Note that this should be a dedicated timer, not available to the rest
+ of the system (or available in "read-only" mode).</li>
+</ul></p>
+<h2>TCP/IP implementation internals</h2>
+<p>The TCP/IP support was designed in such a way that it doesn't require a specific
+TCP/IP stack implementation. To work with <b>eLua</b>, a TCP/IP stack must simply
+implement all the functions defined in the inc/elua_net.h file. This allows for
+easy integration of more than one TCP/IP stack. Currently only uIP is used in
+eLua, but lwIP (and possibly others) are planned to be added at some point.
+Another key point of the TCP/IP implementation (and of the whole <b>eLua</b> design
+for that matter) is that it should be as platform independent as possible: write
+everything in a platform-independent manner, except for some functions (as few as
+possible and as simple as possible) that must be implemented by each platform.
+To illustrate the above, a short overview of the uIP integration is given below.</p>
+<p><a target="_blank" href="http://www.sics.se/~adam/uip/index.php/Main_Page">uIP</a> is a minimalistic TCP/IP
+stack designed specifically for resource constrained embedded systems. While the
+design and implementation of uIP are an excellent example of what can be done
+with a few kilobytes of memory, it has a number of quirks that make it hard to
+integrate with <b>eLua</b>. First, it uses a callback approach, as opposed to the
+sequential approach of "regular" TCP/IP stacks. It provides a "protosocket"
+library that can be used to write uIP applications in a more "traditional" way,
+but it's quite restrictive. So, to use it with <b>eLua</b>, a translation layer was
+needed. It is implemented in <i>src/elua_uip.c</i>, and its sole purpose is to "adapt"
+the uIP stack to the <B>eLua model</b>: implement the functions in <i>inc/elua_net.h</i> and
+you're ready to use the stack. In this case the "adaption layer" is quite large
+because of uIP's callback-based design.<br>
+To make the uIP implementation as platform-independent as possible, a special
+<a href="">##networking layer</a> is added to the <a href="arch.platform.html">platform interface</a>.
+There are only 4 functions that must be implemented by a backend
+to use the networking layer. They might change as more TCP/IP stacks are added
+to eLua, but probably the networking layer won't get much bigger than it is now.<br>
+For a more in-depth understanding of how the networking layer is implemented,
+look at the LM3S implementation in <i>src/platform/lm3s/platform.c</i>.
+</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/building.html
===================================================================
--- branches/eagle_mmc/doc/en/building.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/building.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,119 +1,399 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Building eLua</title>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<link rel="stylesheet" type="text/css" href="../style.css">
+</head>
<body style="background-color: rgb(255, 255, 255);">
-<h3>Building eLua</h3><br><div class="content">
+<h3>Building eLua</h3>
+<p>If you decide to build your own <b>eLua</b>
+binary image (instead of <a href="downloads.html">downloading
+one</a>) you need to check a few things first:
+</p>
+<ul>
+<li>you're using Linux. Compiling under windows should be
+possible, however this isn't tested. We are in Ubuntu, so what
+we use is "apt-get". If you're using a distro with a different
+package
+manager you'll need to translate the "apt-get" calls to your specific
+distribution.</li>
+<li>you have a toolchain (compiler, linker, assembler and
+standard C libraries) for your target. Check <a href="toolchains.html">the toolchains page</a> for
+toolchain instructions. Please note that even if you already have a
+compiled toolchain, the differences in the Newlib configure flags
+(mainly the --disable-newlib-supplied-syscalls flags) might prevent <b>eLua</b>
+for building properly on your machine.</li>
+<li>you set your platform configuration options properly. Check
+the next paragraph for instructions on how to configure your build.</li>
+<li>Python - It should be already installed. If it's not, use
+apt-get to install it:
+<pre><code>$ sudo apt-get install python</code></pre>
+</li>
+<li>Scons - <b>eLua</b> uses scons instead of make
+and makefiles, because we find scons much more "natural" and easier to
+use than make. To install it:
+<pre><code>$ sudo apt-get install scons</code></pre>
+</li>
+<li>your toolchain's "bin" directory (this is generally
+something like /usr/local/cross-arm/bin, where /usr/local/cross-arm is
+the directory in which you installed your toolchain) must be in $PATH.
+</li>
+<li>if you're building for the i386 platform, you'll also need
+"nasm":
+<pre><code>$ sudo apt-get install nasm</code></pre>
+</li>
+</ul>
+<p>For each platform, <b>eLua</b> assumes a certain
+name for the toolchain components, as shown below.
+</p>
+<p>If your toolchain uses different names, you have to modify the
+toolchain definition in SConstruct. See the <a href="toolchains.html">toolchains instructions</a> for
+details.</p>
+<h3>Configuring the build image</h3>
+<p><b>eLua</b> has a very flexible build system that
+can be used to select the components that are going to be part of the <b>eLua</b>
+binary image and to set the compile time (static) configuration.
+To use it, you need to edit a single configuration file (<i>platform_conf.h</i>)
+located in the platform specific directory (<i>src/platform/<platform
+name>/platform_conf.h)</i>. The configuration parameters
+are described in detail in the next paragraphs.</p>
+<a name="components"><h2>Configuring components</h2></a>
+<p>A <b>component</b> is a feature that can be
+enabled to add functionality to <b>eLua</b> itself,
+without modifying its API (which is the part that the programmer uses
+to write <b>eLua</b> programs). An example of component configuration from
+<i>platform_conf.h</i> is given below:
+<p><pre><code>// *****************************************************************************
+// Define here what components you want for this platform
-<p>Up to date documentation of how to build eLua is always included in the <a href="http://www.eluaproject.net/?p=Downloads">eLua distributions</a>, in the docs directory).</p>
-
-<p>For your convenience, the building instructions are also provided on this page.</p>
-
-<h2>Prerequisites</h2>
-
-<p>Before you start, you might want to check if the list of platform modules and
-eLua components are set according to your needs. See platform_modules
-and elua_components in the distro doc for details. </p>
-
-<h2>Building eLua</h2>
-
-<p>To build <strong>eLua</strong> you'll need:</p>
-
-<ul><li><p>a GCC/Newlib toolchain for your target. Please note that even if
- you already have a compiled toolchain, the differences in the Newlib configure
- flags (mainly the --disable-newlib-supplied-syscalls flags) might prevent
- eLua for building properly on your machine.</p></li><li><p>Linux. Compiling under windows should be possible, however this isn't tested.
- I'm using Ubuntu, so I'm also using "apt-get". If you're using a distro with a
- different package manager you'll need to translate the "apt-get" calls to your
- specific distribution.</p></li><li><p>python. It should be already installed; if it's not:</p>
-
- <p>$ sudo apt-get install python</p></li><li><p>scons. eLua uses scons instead of make and makefiles, because I find scons
- much more "natural" and easier to use than make. To install it:</p>
-
- <p>$ sudo apt-get install scons</p></li><li><p>your toolchain's "bin" directory (this is generally something like
- /usr/local/cross-arm/bin, where /usr/local/cross-arm is the directory in which
- you installed your toolchain) must be in $PATH. </p></li><li><p>if you're building for the i386 platform, you'll also need "nasm":</p>
-
- <p>$ sudo apt-get install nasm</p></li></ul>
-
-<p>For each platform, eLua assumes a certain name for the compiler/linker/assembler
-executable files, as shown below.</p>
-
-<pre><code>================================================================================<br>| Tool | Compiler | Linker | Assembler | <br>|------------|---------------------|----------------------|--------------------| <br>| Platform | | | |<br>|============|=====================|======================|====================|<br>| ARM (all) | arm-elf-gcc | arm-elf-gcc | arm-elf-gcc |<br>|============|=====================|======================|====================|<br>| i386 | i686-elf-gcc | i686-elf-gcc | nasm |<br>|============|=====================|======================|====================|<br>| Cortex-M3 | arm-elf-gcc | arm-elf-gcc | arm-elf-gcc |<br>|============|=====================|======================|====================|<br></code></pre>
-
-<p>If your toolchain uses different names, you have to modify the "conf.py" file
-from src/platform/[your platform].</p>
-
-<p>To build, go to the directory where you unpacked your eLua distribution and
-invoke scons:</p>
-
-<pre><code>$ scons [target=lua | lualong] <br> [cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962 | <br> lm3s6965 | lpc2888 | str711fr2 ]<br> [board=ek-lm3s8962 | ek-lm3s6965 | str9-comstick | sam7-ex256 | lpc-h2888 | <br> | mod711 | pc]<br> [cpumode=arm | thumb] <br> [allocator = newlib | multiple]<br> [prog]<br></code></pre>
-
-<p>Your build target is specified by two paramters: cpu and board. "cpu" gives the
-name of your CPU, and "board" the name of the board. A board can be associated
-with more than one CPU. This allows the build system to be very flexible. You
-can use these two options together or separately, as shown below:</p>
-
-<ul><li>cpu=name: build for the specified CPU. A board name will be assigned by the
- build system automatically.</li><li>board=name: build for the specified board. The CPU name will be inferred by
- the build system automatically.</li><li>cpu=name board=name: build for the specified board and CPU.</li></ul>
-
-<p>For board/CPU assignment look at the beginning of the SConstruct file from the
-base directory, it's self-explanatory.</p>
-
-<p>The other options are as follows:</p>
-
-<ul><li>target=lua | lualong: specify if you want to build full Lua (with floating
- point support) or integer only Lua (lualong). The default is "lua".</li><li>cpumode=arm | thumb: for ARM target (not Cortex) this specifies the
- compilation mode. Its default value is 'thumb' for AT91SAM7X targets and
- 'arm' for STR9 and LPC2888 targets.</li><li>allocator = newlib | multiple: choose between the default newlib allocator
- (newlib) and the multiple memory spaces allocator (multiple). You should
- use the 'multiple' allocator only if you need to support multiple memory
- spaces, as it's larger that the default Newlib allocator (newlib). For more
- information about this reffer to platform_interface. The default value
- is 'newlib' for all CPUs except 'lpc2888', since my lpc-h2888 comes with
- external SDRAM memory and thus it's an ideal target for 'multiple'.</li><li>prog: by default, the above 'scons' command will build only the 'elf' file.
- Specify "prog" to build also the platform-specific programming file where
- appropriate (for example, on a AT91SAM7X256 this results in a .bin file that
- can be programmed in the CPU). </li></ul>
-
-<p>The output will be a file named elua<em>[target]</em>[cpu].elf (and also another
-file with the same name but ending in .bin if "prog" was specified for platforms
-that need .bin files for programming).
-If you want the equivalent of a "make clean", invoke "scons" as shown above,
-but add a "-c" at the end of the command line. "scons -c" is also recommended
-after you change the list of modules/components to build for your target (see
-section "prerequisites" of this document), as scons seems to "overlook" the
-changes to these files on some occasions.</p>
-
-<p>A few examples:</p>
-
+#define BUILD_XMODEM
+#define BUILD_SHELL
+#define BUILD_ROMFS
+#define BUILD_TERM
+#define BUILD_UIP
+#define BUILD_DHCPC
+#define BUILD_DNS
+#define BUILD_CON_GENERIC
+#define BUILD_ADC</code></pre></p>
+<p>The components that can be configured in <b>eLua</b> are:
+</p>
+<table class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Name</th>
+<th style="text-align: center;">Meaning</th>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_XMODEM</td>
+<td>Define this to build support for XMODEM receive. If
+enabled, you can use the "recv" command from the shell to receive a Lua
+file (either source code or precompiled byte code) and run in on the
+target. Works only over RS-232 connections (although in theory it's
+possible to make it work over any kind of transport).
+To enable:
+<p><pre><code>#define BUILD_XMODEM</code></pre></p>
+<a href="building.html#static">Static configuration data dependencies:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID</b>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_SHELL</td>
+<td>This build the <b>eLua</b> shell (see <a href="using.html">using eLua</a> for details on the
+shell). If the shell is not enabled, the code looks for a file called <i>/rom/autorun.lua</i>
+and executes it. If this file is not found, a regular Lua intepreter is
+started on the target.<br>
+To enable the shell over a serial connection:
+<p><pre><code>#define BUILD_SHELL
+#define BUILD_CON_GENERIC</code></pre></p>
+To enable the shell over a TCP/IP connection:
+<p><pre><code>#define BUILD_SHELL
+#define BUILD_CON_TCP</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_ROMFS</td>
+<td>Enable the <b>eLua</b> read-only
+filesystem. See the <a href="arch_romfs.html">ROMFS
+documentation</a> for details about using the ROM file system.
+To enable:
+<p><pre><code>#define BUILD_ROMFS</code></pre></p></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_TERM</td>
+<td>Enable ANSI terminal support. It allows <b>eLua</b>
+to interact with terminals that support ANSI escape sequences (more details <a href="arch_con_term.html">here</a>).
+Currently it works only over RS-232 connections, although this is not a
+strict requirement. You need to enable this if you want to use the <a href="m_term.html">##term module</a>.
+To enable:
+<p><pre><code>#define BUILD_TERM</code></pre></p>
+<a href="building.html#static">Static configuration data dependencies:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID, TERM_LINES, TERM_COLS</b></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_UIP</td>
+<td>Enable TCP/IP networking support. You need to enable
+this if you want to use the <a href="m_net.html">##net
+module</a>. Also, your platform must implement the uIP support
+functions (see the <a href="platform_interface.html">##platform
+interface</a> documentation for details).
+To enable:
+<p><pre><code>#define BUILD_UIP</code></pre></p>
+<a href="building.html#static">Static configuration data dependencies:</a> <b>ELUA_CONF_IPADDR0..3, ELUA_CONF_NETMASK0..3, ELUA_CONF_DEFGW0..3,
+ ELUA_CONF_DNS0..3</b>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_DHCPC</td>
+<td>If BUILD_UIP is enabled, you can enable this to include
+a DHCP client in the TCP/IP networking subsystem.
+To enable:
+<p><pre><code>#define BUILD_UIP
+#define BUILD_DHCPC</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_DNS</td>
+<td>If BUILD_UIP is enabled, you can enable this to include
+a minimal DNS resolver in the TCP/IP networking subsystem.
+To enable:
+<p><pre><code>#define BUILD_UIP
+#define BUILD_DNS</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_CON_GENERIC</td>
+<td>Generic console support (details <a href="arch_con_term.html">here</a>). Enables console access
+(stdio/stdout/stderr) via a serial transport (currently RS-232, but
+others can be supported). Enable this if you want to use console
+input/output over your RS-232 connection. Don't enable this if you need
+console input/ouput over Ethernet (see the next option).
+To enable:
+<p><pre><code>#define BUILD_CON_GENERIC</code></pre></p>
+<a href="building.html#static">Static configuration data dependencies:</a> <b>CON_UART_ID, CON_UART_SPEED, CON_TIMER_ID</b></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_CON_TCP</td>
+<td>Console input/output over TCP/IP connections only (details <a href="arch_con_term.html">here</a>). Use
+this if you want to use your <b>eLua</b> board over a
+telnet session. Don't enable this if you need console input/output over
+serial transports (see the previous option).
+To enable:
+<p><pre><code>#define BUILD_UIP
+#define BUILD_CON_TCP</code></pre></p>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">BUILD_ADC</td>
+<td>Generic ADC support code. You need to enable this if
+you want to use the <a href="m_adc.html">##adc</a>
+module, or simply the ADC functions from the platform interface. You
+don't need it if you're not planning to use the ADC.
+To enable:
+<p><pre><code>#define ##BUILD_ADC</code></pre></p>
+</td>
+</tr>
+</tbody>
+</table>
+<a name="confmodules"><h2>Configuring modules</h2></a>
+<p>You can also choose the modules that are going to be part of
+the <b>eLua</b> image. Unlike components, the modules have
+a direct impact on the <b>eLua</b> API, so choose them
+carefully. Disabling a module will save Flash space (and potentially
+RAM) but will also completely remove the possibility of using that
+module from <b>eLua</b>.</p>
+<p>The modules included in the build are specified by the
+LUA_PLATFORM_LIBS_ROM macro. An example is given below: </p>
+<pre><code>#define LUA_PLATFORM_LIBS_ROM\
+ _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+ _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+ _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+ _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
+ _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
+ _ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
+ ROM( LUA_MATHLIBNAME, luaopen_math, math_map )</code></pre>
+<p>Each module is defined by a <b>_ROM( module_name,
+module_init_function, module_map_array )</b> macro, where:
+</p>
+<ul>
+<li><b>module_name</b> is the name by which the
+module can be used from Lua</li>
+<li><b>module_init_function</b> is a function
+called by the Lua runtime when the module is initialized</li>
+<li><b>module_map_array</b> is a list of all the
+functions and constants exported by a module</li>
+</ul>
+<p>Please note that this notation is specific to LTR (the <b>L</b>ua
+<b>T</b>iny <b>R</b>AM patch) and it's not the
+only way to specify the list of modules included in the build (although
+it is the most common one). Check the <a href="arch_ltr.html#config">LTR
+section</a> for more information about LTR.</p>
+<p>For the full list of modules that can be enabled or disabled
+via <i>platform_conf.h</i> check <a href="">##the
+eLua reference manual</a>.</p>
+<a name="static"><h2>Static configuration data</h2></a>
+<p>"Static configuration" reffers to the compile-time
+configuration. Static configuration parameters are hard-coded in the
+firmware image and can't be changed at run-time. The table below lists
+the static configuration parameters and their semantics.
+</p>
+<table class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Name</th>
+<th style="text-align: center;">Meaning</th>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">CON_UART_ID<br>CON_UART_SPEED<br>CON_TIMER_ID<br></td>
+<td>Used to configure console input/output over UART. The
+specified UART id will be used for console input/output, at the
+specified speed. The data format is always 8N1 (8 data bits, no parity,
+1 stop bits) at this point. The specified timer ID will be used for the console subsystem. These
+variables are also used by the XMODEM and TERM implementations.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">TERM_LINES<br>TERM_COLS<br>
+</td>
+<td>Used to configure the ANSI terminal support (if enabled
+in the build). Used to specify (respectively) the number of lines and
+columns of the ANSI terminal.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">ELUA_CONF_IPADDR0..3<br>
+ELUA_CONF_NETMASK0..3<br>
+ELUA_CONF_DEFGW0..3<br>
+ELUA_CONF_DNS0..3</td>
+<td>Used by the TCP/IP implementation when the DHCP client
+is not enabled, or when it is enabled but can't be contacted. Specifies
+the IP address, network mask, default gateway and DNS server. Only
+needed if BUILD_UIP is enabled.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">VTMR_NUM_TIMERS<br>
+VTMR_FREQ_HZ</td>
+<td>Specify the virtual timers configuration for the
+platform (reffer to <a href="">##the timer module
+documentation</a> for details). Define VTMR_NUM_TIMERS to 0 if
+this feature is not used.</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">PLATFORM_CPU_CONSTANTS</td>
+<td>If the <a href="">##cpu module</a>
+is enabled, this defines a list of platform-specific constants (for
+example interrupt masks) that can be accessed using the
+cpu.<constant name> notation. Each constant name must be
+specified instead of a specific costruct (<i>_C(<constant
+name></i>). For example:
+<pre><code>#define PLATFORM_CPU_CONSTANTS\<br> _C( INT_GPIOA ),\<br> _C( INT_GPIOB ),\<br> _C( INT_GPIOC ),\<br> _C( INT_GPIOD ),\<br> _C( INT_GPIOE )<br></code></pre>
+After compilation, you can access these constants using <i>cpu.INT_GPIOx</i>.
+Note that the implementation of this feature needs virtually no RAM at
+all, so you can define as many constants as you want here. ##TODO: ADC!!</td>
+</tr>
+</tbody>
+</table>
+<p>The rest of the static configuration data parameters are meant
+to be modified mainly by developers and thus they're not listed here.<br>
+One more thing you might want to configure for your build is the
+contents of the ROM file system. See the <a href="">ROMFS
+documentation</a> for details on how to do this.</p>
+<h3>Invoking the build system</h3>
+<p>Once you have everything in place, all you have to do is to
+invoke the build system (scons) with the right arguments. This is a
+fairly easy step, although it might look intimidating because of the
+multitude of options than can be given to scons. They are used to fine
+tune the final image to your specific needs, but unless your needs are
+very special you won't need to modify them, so don't worry about the
+aparent complexity. The examples at the end of this section will show
+how easy it is to use the build system in practice.
+</p>
+<pre><code>$ scons <br> [target=lua | lualong]<br> [cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962 | <br> lm3s6965 | lm3s6918 | lpc2888 | str711fr2 | at32uc3a0512 | stm32f103ze<br> [board=ek-lm3s8962 | ek-lm3s6965 | eagle-100 | str9-comstick | sam7-ex256 | <br> lpc-h2888 | mod711 | pc | atevk1100 | stm3210e-eval ]<br> [cpumode=arm | thumb] <br> [allocator = newlib | multiple | simple]<br> [toolchain = <toolchain name>]<br> [optram = 0 | 1]<br> [prog]<br></code></pre>
+<p>Your build target is specified by two paramters: cpu and
+board. "cpu" gives the name of your CPU, and "board" the name of the
+board. A board can be associated with more than one CPU. This allows
+the build system to be very flexible. You can use these two options
+together or separately, as shown below:</p>
+<ul>
+<li><b>cpu=name</b>: build for the specified CPU. A
+board name will be assigned by the build system automatically.</li>
+<li><b>board=name</b>: build for the specified
+board. The CPU name will be inferred by the build system automatically.</li>
+<li><b>cpu=name board=name</b>: build for the
+specified board and CPU. The build script won't allow invalid CPU/board
+combinations.</li>
+</ul>
+<p>For board/CPU assignment look at the beginning of the
+SConstruct file (the <i>platform_list</i> array), it's
+self-explanatory.<br>
+The other options are as follows:</p>
+<ul>
+<li><b>target=lua | lualong</b>: specify if you
+want to build "regular" Lua (with floating point support) or integer
+only Lua (lualong). The default is "lua". "lualong" runs faster on
+targets that lack a floating point co-processor (which is the case for
+all current <b>eLua</b> targets) but it completely lacks
+support for floating point operations, it can only handle integers.</li>
+<li><b>cpumode=arm | thumb</b>: for ARM targets
+(not Cortex) this specifies the compilation mode. Its default value is
+'thumb' for AT91SAM7X targets and 'arm' for STR9 and LPC2888 targets.</li>
+<li><b>allocator = newlib | multiple | simple</b>:
+choose between the default newlib allocator (newlib) which is an older
+version of dlmalloc, the multiple memory spaces allocator (multiple)
+which is a newer version of dlmalloc that can handle multiple memory
+spaces, and a very simple memory allocator (simple) that is slow and
+doesn't handle fragmentation very well, but it requires very few
+resources (Flash/RAM). You should use the 'multiple' allocator only if
+you need to support multiple memory spaces. The default value is
+'newlib' for all CPUs except 'lpc2888' and 'at32uc3a0512', since the
+LPC-H2888 and ATEVK1100 board come with external SDRAM memory and thus
+are an ideal target for 'multiple'. You should use 'simple' only on
+very resource-constrained systems.
+</li>
+<li><b>toolchain=<toolchain name></b>:
+this specifies the name of the toolchain used to build the image. See <a href="toolchains.html#configuration">this link</a> for
+details.</li>
+<li><b>optram=0 | 1</b>: enables of disables the
+LTR patch, see the <a href="arch_ltr.html">LTR documentation</a>
+for more details. The default is 1, which enables the LTR patch.</li>
+<li><b>prog</b>: by default, the above 'scons'
+command will build only the 'elf' (executable) file. Specify "prog" to
+build also the platform-specific programming file where appropriate
+(for example, on a AT91SAM7X256 this results in a .bin file that can be
+programmed in the CPU). </li>
+</ul>
+<p>The output will be a file named elua_<i>[target]</i>_<i>[cpu]</i>.elf
+(and also another file with the same name but ending in .bin/.hex if
+"prog" was specified for platforms that need these files for
+programming).<br>
+If you want the equivalent of a "make clean", invoke "scons" as shown
+above, but add a "-c" at the end of the command line. "scons -c" is
+also recommended after you reconfigure your build image, as scons seems
+to "overlook" the changes to these files on some occasions.</p>
+<p><b>A few examples:</b></p>
+<pre><code>$ scons cpu=at91sam7x256 -c <br></code></pre>
<p>Clear previously built intermediate files.</p>
-
-<pre><code>$ scons cpu=at91sam7x256 -c <br></code></pre>
-
-<p>Build eLua for the AT91SAM7X256 CPU. The board name is detected as sam7-ex256.</p>
-
<pre><code>$ scons cpu=at91sam7x256<br></code></pre>
-
-<p>Build eLua for the SAM7-EX256 board. The CPU is detected as AT91SAM7X256.</p>
-
+<p>Build eLua for the AT91SAM7X256 CPU. The board name is
+detected as sam7-ex256.</p>
<pre><code>$ scons board=sam7-ex256<br></code></pre>
-
-<p>Build eLua for the SAM7-EX256 board, but "overwrite" the default CPU. This is
-useful when you'd like to see how the specified board would behave with a
-different CPU (in the case of the SAM7-EX256 board it's possible to switch the
-on-board AT91SAM7X256 CPU for an AT91SAM7X512 which has the same pinout but
+<p>Build eLua for the SAM7-EX256 board. The CPU is detected as
+AT91SAM7X256.</p>
+<pre><code>$ scons board=sam7-ex256 cpu=at91sam7x512<br></code></pre>
+<p>Build eLua for the SAM7-EX256 board, but "overwrite" the
+default CPU. This is useful when you'd like to see how the specified
+board would behave (in terms of resources) with a different CPU (in the
+case of the SAM7-EX256 board it's possible to switch the on-board
+AT91SAM7X256 CPU for an AT91SAM7X512 which has the same pinout but
comes with more Flash/RAM memory).</p>
-
-<pre><code>$ scons board=sam7-ex256 cpu=at91sam7x512<br></code></pre>
-
-<p>Build eLua for the lpc2888 CPU. The board name is detected as LPC-H2888. Also,
-the bin file required for target programming is generated.</p>
-
-<pre><code>$ scons cpu=lpc2888 prog <br></code></pre>
-
-
-</div></body></html>
\ No newline at end of file
+<pre><code>$ scons cpu=lpc2888 prog </code></pre>
+<p>Build eLua for the lpc2888 CPU. The board name is detected as
+LPC-H2888. Also,
+the bin file required for target programming is generated. The
+allocator is automatically detected as "multiple".</p>
+<pre><code>$ scons cpu=lm3s8962 toolchain=codesourcery prog</code></pre>
+<p>Build the image for the Cortex LM3S8962 CPU, but use the
+CodeSourcery toolchain instead of the default toolchain (which is a
+"generic" ARM GCC toolchain, usually the one built by following
+the tutorials from this site</p>
+.
+</body></html>
Modified: branches/eagle_mmc/doc/en/comunity.html
===================================================================
--- branches/eagle_mmc/doc/en/comunity.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/comunity.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -5,47 +5,45 @@
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
-<a name="lists"></a><h3>Collaborative Mail
-Lists</h3>
-<p><strong></strong></p><p style="text-align: left;"><strong>eLua</strong> currently has a single<strong> Developper's
-and User's Discussion Mail List</strong>.<br>You are very welcome
-to join it at <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a></p><p style="text-align: left;"></p><p style="text-align: left;">Our devellopment repository is currently maintained in a
-Subversion Server.<br>If you are interested in following daily commitments to the Bleeding
-Edge trunk development, you can also subscribe to the <strong>SVN
-Activity List</strong> at <a href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a></p><p></p><p><a href="https://lists.berlios.de/mailman/listinfo/elua-svn"></a></p>
-<span style="font-style: italic;"><a name="credits"></a></span><h3>Credits</h3>
+<a name="lists"></a><h3>Mail lists</h3>
+<p style="text-align: left;"><strong>eLua</strong> currently has a single<strong> Developers and Users Discussion List</strong>. You are very welcomed
+to join it at <a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.
+Please note that the list is moderated in order to avoid spam, so you
+need to join it if you want to post. Messages from non-members are
+rarely accepted.</p>
+<p style="text-align: left;"></p><p style="text-align: left;">Our development repository is currently maintained in a
+Subversion server. If you want to track SVN activity, you can also subscribe to our <strong>SVN
+Activity List</strong> at <a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a><a href="https://lists.berlios.de/mailman/listinfo/elua-svn"></a></p>
+<a name="forums"></a><h3>eLua forums</h3>
+<b>eLua</b> doesn't have a dedicated forum at this point. However, starting with 22.02.2009, the <b>Developers and Users Discussion List</b> is "mirrored" in a forum-like format at <a href="http://n2.nabble.com/eLua-Development-f2368040.html">this address</a> (using the services provided by <a href="http://www.nable.com">Nabble</a>). If you want to use the forum interface, but don't want to navigate away from this page, click <a href="forum.html">here</a>.
+<span style="font-style: italic;"><a name="credits"></a><br></span><h3>Credits</h3>
<div class="content">
<p>The authors of <strong>eLua</strong> would like
-to thank everyone that helped with developing the project. Here's a
-non-exhaustive list of contributors:</p>
-<p><strong>Alexandre Umino</strong><br>
-OpenOCD</p>
-<p><strong>Cosmin Filip</strong><br>
-News yet to come :)</p>
-<p><strong>Everson Denis</strong><br>
-Site translation to portuguese</p>
-<p><strong>Frédéric Thomas</strong><br>
-Site hosting</p>
-<p><strong>James Snyder</strong><br>
-LM3S6965 patches</p>
-<p><strong>Mike Panetta</strong><br>
-ATM32 porting (comming soon)</p>
-<p><strong>Roberto Ierusalimschy</strong><br>
-for Lua (!!!! :)</p>
-<p><strong>Yuri Takhteyev</strong><br>
-for Sputnik and and site support</p>
-<p><strong>Ricardo Lourival Rosa</strong><br>
-site support</p>
-<p><strong>Caio Percia, Pedro Bittencourt, Fernando Araújo</strong><br>
-testing, testing and testing :)</p>
-<p><strong>Téo Benjamin, Ives Cunha, Rafael Barmak</strong><br>
-Manfredo, a GPS guided robot, powered by eLua.</p>
-<p><strong>And the constant help and support from:</strong><br>
-Alberto Fabiano, André Carregal, Ângelo Santos, Cosmin Filip, Diego Sueiro, Eduardo
-von Ristow, Fabio Mascarenhas, Hisham Muhammad, Marcelo Tílio, Marco
-Meggiolaro, Mauro Schwanke, Mauro Speranza, Raul Nunes</p>
-</div>
+to thank the colaborative help from the comunity for the
+continuous development of the project. Here's an alphabetical
+ordered non-exhaustive list of contributors:</p><ul>
+<li>Alberto Fabiano</li>
+<li>André Carregal</li><li>Cosmin Filip</li>
+<li>Diego Sueiro</li>
+<li>Everson Denis</li>
+<li>Fabio Pereira</li>
+<li>Fernando Araújo</li>
+<li>Frédéric Thomas</li>
+<li>Ives Cunha</li>
+<li>James Snyder</li>
+<li>Marcelo Tílio</li>
+<li>Marco Meggiolaro</li>
+<li>Mike Panetta</li>
+<li>Pedro Bittencourt</li>
+<li>Rafael Barmak</li>
+<li>Rafael Sabbagh</li>
+<li>Ralph Hempel</li>
+<li>Raul Nunes</li>
+<li>Ricardo Rosa</li>
+<li>Roberto Ierusalimschy</li>
+<li>Téo Benjamin</li>
+<li>Yuri Takhteyev</li></ul>
+... and the whole comunity of our Users & Development List at <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a><strong style="font-weight: normal;"></strong></div>
<br><br>
-<a name="galery"></a><h3>Galery</h3>
-<br><br><br><br><a name="projects"></a><h3>Projects</h3>
-</body></html>
\ No newline at end of file
+<a name="galery"></a><a name="projects"></a>
+</body></html>
Added: branches/eagle_mmc/doc/en/dl_binaries.html
===================================================================
--- branches/eagle_mmc/doc/en/dl_binaries.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/dl_binaries.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,140 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css">
+</head>
+<body style="background-color: rgb(255, 255, 255);">
+<br>
+<h3><span class="info"><a name="sources"></a>Downloading
+eLua pre-built binary images</span></h3>
+If you have an eLua capable hardware, you
+don't need to be a professional developer of the embedded
+world
+and to understand the details of the eLua building process, to be
+able to have eLua on your nice kits. <br>
+<br>
+eLua project offers pre-built
+binary images for all the supported platforms.<br>
+<br>
+All you have to do is to chose the
+corresponding image file from the table below, flash it into your
+board, connect a serial terminal (or Ethernet if you board supports)
+and enjoy eLua.<br>
+<br>
+eLua binaries, like the <a href="dl_sources.html">source-code
+distributions</a>,
+include some example programs in it's file system, so you can run and
+play (yes! we have games too! :) them, following the instructions in
+our <a href="using.html">Using eLua</a> page. The
+available example programs are described in our <a href="examples.html" target="_top">Examples page<br></a>
+<br>
+If you need a customized binary image for an already supported
+platform (ie: with an autorun program, with some code of yours in the
+File System, with your LAN IP settings, .....) and you don't know how
+to build eLua, feel free to <a href="overview.html#contacts">write
+us</a> explaining what you need. We may (find some time to :)
+build one for you and eventually make it available here too.
+<br>
+<br>
+To understand what's in a file name (for example
+elua_lualong_lm3s8962.bin) check our <a href="building.html">Building
+eLua</a> page, or at least the last part of it, where the meaning
+of the file names coming from the build system is explained.<br><br><br><span style="color: red; font-weight: bold;">## Let's not forget to include links for fresh v0.6 binaries to all platforms ..........<br>##
+Maybe move the table/contents below to an "old versions" section .....
+Ooops, I just saw I'd done it already. It's on dl_old.html</span><br><div><br>
+<table class="table_center">
+<tbody>
+<tr>
+<th>eLua Version</th>
+<th>Target MCU</th>
+<th>Lua Number</th>
+<th>Memory Usage(KB)</th>
+<th>Remarks</th>
+<th>Download File</th>
+</tr>
+<tr>
+<td>0.5</td>
+<td>Atmel ARM7</td>
+<td>Float</td>
+<td>ROM: ~189<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x256.bin">elua_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>Atmel ARM7</td>
+<td>Float</td>
+<td>ROM: ~189<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x512g.bin">elua_lua_at91sam7x512g.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>Intel x86<br>
+(for fun :)</td>
+<td>Float</td>
+<td> </td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_i386.elf">elua_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>Luminary Micro ARM Cortex M3</td>
+<td>Float</td>
+<td>ROM: ~202<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s6965.bin">elua_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>Luminary Micro ARM Cortex M3</td>
+<td>Float</td>
+<td>ROM: ~202<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s8962.bin">elua_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>NXP ARM7</td>
+<td>Float</td>
+<td>ROM: ~229<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_lpc2888.bin">elua_lua_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>ST Microelectronics ARM7</td>
+<td>Float</td>
+<td>ROM: ~189<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_str711fr2g.bin">elua_lua_str711fr2g.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td>ST Microelectronics ARM 9</td>
+<td>Float</td>
+<td>ROM: ~229<br>
+RAM: 32~64</td>
+<td>Official eLua release</td>
+<td><a href="http://prdownload.berlios.de/elua/elua_lua_str912fw44.bin">elua_lua_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table>
+<br>
+</div>
+<p>Notes:</p>
+<ul>
+<li>Lua Number refers to the built Lua interpreter number type,
+float or integer.</li>
+<li>RAM Memory Usage is based on included Lua examples
+execution.</li>
+</ul>
+</body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/en/dl_old.html
===================================================================
--- branches/eagle_mmc/doc/en/dl_old.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/dl_old.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,292 @@
+<!DOCTYPE HTML PUBLIC "-//W4C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua downloads (old versions)</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Downloading eLua Old Versions</h3>
+<p>The tables below have links to the previous official versions of <b>eLua</b> (both source code and binaries).</p>
+<a name="v041"><h2>0.4.1</h2></a>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.4.1</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua-0.4.1.tgz">elua-0.4.1.tgz</a></td>
+</tr>
+</tbody></table>
+<a name="v04"><h2>0.4</h2></a>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.4</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua_0.4.tgz">elua_0.4.tgz</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x256.bin">elua0.4_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>None</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_at91sam7x512.bin">elua0.4_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>PCs/emulators</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_i386.elf">elua0.4_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a target="_blank" href=http://prdownload.berlios.de/elua/elua0.4_lua_lm3s6965.bin">elua0.4_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_lm3s8962.bin">elua0.4_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_lpc2888.bin">elua0.4_lua_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lua_str912fw44.bin">elua0.4_lua_str912fw44.bin</a></td>
+</tr>
+
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x256.bin">elua0.4_lualong_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>None</td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_at91sam7x512.bin">elua0.4_lualong_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>PCs/emulators</td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_i386.elf">elua0.4_lualong_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href=http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s6965.bin">elua0.4_lualong_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_lm3s8962.bin">elua0.4_lualong_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_lpc2888.bin">elua0.4_lualong_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.4</td>
+<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.4_lualong_str912fw44.bin">elua0.4_lualong_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table>
+
+
+<a name="v03"><h2>0.3</h2></a>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.3</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua_0.3.tgz">elua_0.3.tgz</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x256.bin">elua0.3_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>None</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_at91sam7x512.bin">elua0.3_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>PCs/emulators</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_i386.elf">elua0.3_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s6965.bin">elua0.3_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_lm3s8962.bin">elua0.3_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.3</td>
+<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.3_lua_str912fw44.bin">elua0.3_lua_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table>
+
+
+<a name="v02"><h2>0.2</h2></a>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.2</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua_0.2.tar.gz">elua_0.2.tar.gz</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lua_at91sam7x256.bin">elua0.2_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>PCs/emulators</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lua_i386.elf">elua0.2_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lua_lm3s8962.bin">elua0.2_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lualong_at91sam7x256.bin">elua0.2_lualong_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>PCs/emulators</td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lualong_i386.elf">elua0.2_lualong_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.2</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>integer (32-bit)</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.2_lualong_lm3s8962.bin">elua0.2_lualong_lm3s8962.bin</a></td>
+</tr>
+</tbody>
+</table>
+
+
+<a name="v01"><h2>0.1</h2></a>
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.1</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td>All (source code)</td>
+<td><a target="_blank" href="http://luaforge.net/frs/download.php/3564/elua_0.1.tar.gz">elua_0.1.tar.gz</a></td>
+</tr>
+</body></html>
+
Added: branches/eagle_mmc/doc/en/dl_sources.html
===================================================================
--- branches/eagle_mmc/doc/en/dl_sources.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/dl_sources.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,52 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="sources"></a>Downloading eLua Source Code</span></h3><h2>Official Releases</h2>
+
+<h4>Source code</h4>
+
+<p>The last released version is eLua v0.6 and you can download it here:
+####<br>
+The package includes the complete source code, documentation, building scripts and Lua program examples.<br></p>
+
+
+<p>After downloading and unpacking, you can acess eLua's documentation
+in an offline mode, opening the document index_en.html in the /doc
+folder. It will show you a version of this site at the time eLua v0.6
+was released. The online version is constantly updated though and you
+might check it for <a href="news.html">updated eLua news</a>.</p><p>You will find eLua building instructions on the <a href="building.html">Building eLua</a> page.</p><br><br>
+
+
+<h2><a name="svnpublic"></a>Subversion Public Repository</h2>
+
+<p>If you'd rather have the very last development ("bleeding edge") version, just check it out from our Subversion Repository:</p>
+
+<pre>$ svn checkout svn://svn.berlios.de/elua/trunk<code><br></code></pre>
+
+
+<p>Once checked out, the repository can be easily updated by the svn client command:</p>
+
+<pre>$ svn update<code><br></code></pre>
+<p><br></p>
+
+<h2>Subversion Repository Web Browsing</h2>
+
+If you're looking for an easy and user friendly way of browsing through the SVN repository, use the <a href="http://svn.berlios.de/wsvn/elua">WebSVN interface</a><br><h2></h2><h2><a name="svndev"></a>Subversion Repository for developers</h2>
+
+<p>If you want to contribute to eLua and need write access to the repository, follow these steps:</p>
+
+<ul><li>if you don't have an account on <a href="http://developer.berlios.de/">developer.berlios.de,</a> create one before proceeding.</li><li><a href="../../../../../../websites/elua%20site/www.eluaproject.net/index8603.html?p=Contact">contact us</a>, specifying your BerliOS id and we'll add you to the list of developers.</li></ul>
+
+
+<p>Then checkout the repository:</p>
+
+<pre>$ export SVN_SSH='ssh -l <yourberliosid>'<br style="font-family: Courier New;"><br style="font-family: Courier New;">$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk<code><br></code></pre>
+
+<p>Once checked out, the repository can be easily updated:</p>
+
+<pre>$ svn update<code><br></code></pre>
+
+<p><br></p><br><br><br><p></p><p></p><p></p><p></p></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/en/doc.html
===================================================================
--- branches/eagle_mmc/doc/en/doc.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/doc.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua documentation</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>eLua documentation</h3>
+<p>This section contains the complete <b>eLua</b> documentation for both users and developers, including (but not limited to):
+<ul>
+ <li>how to build <b>eLua</b></li>
+ <li>how to install (or build) the toolchains needed to build <b>eLua</b></li>
+ <li>how to use <b>eLua</b></li>
+ <li>description of the example programs from the <b>eLua</b> source distribution</li>
+</ul></p>
+<p>People who want to contribute to the <b>eLua</b> source code will find a lot of important information here:<ul>
+ <li>a description of the <b>eLua</b> architecture</li>
+ <li>the <b>eLua</b> coding standard</li>
+ <li>how to port <b>eLua</b> to a new platform</li>
+</ul>
+</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/downloads.html
===================================================================
--- branches/eagle_mmc/doc/en/downloads.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/downloads.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,138 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>eLua downloads</title>
-<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick"></a><span class="info">Downloads</span></h3><br></body></html>
\ No newline at end of file
+<link rel="stylesheet" type="text/css" href="../style.css">
+</head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Downloading eLua</h3>
+<p>You have a few options for downloading <b>eLua</b>:
+<ul>
+ <li>download a binary <b>eLua</b> image for your platform of choice. Binary images are provided with each official release. This is generally the best option if you have a bord that's officially
+ supported by <b>eLua</b> (see <a href="status.html">here</a> for details) and you want to have <b>eLua</b> up and running on your board as quickly as possible.</li>
+ <li>download the source code. You can either download the source code of an official release or get the "bleeding edge" version from the SVN repository. Download the source code instead of a
+ binary image if you need to make adjustments to the source code to support your board, or if you want to customize the <b>eLua</b> image, or if you simply want to take a look at what
+ happens behind the <i>eLua# </i> prompt :)</li>
+</ul></p>
+<h3><a name="binaries">Binary images</a></h3>
+<p>Pre-built images of <b>eLua</b> can be downloaded for each official release. Only the latest official <b>eLua</b> release is covered in this paragraph; if you want to download a pre-built
+image from an older release (although this isn't generally advisable), check <a href="dl_old.html">this page</a>. Choose the corresponding image file from the table below, flash it into your
+board, connect a serial terminal (or Ethernet if you board supports) and enjoy <b>eLua</b>. Also note that <b>eLua binaries</b>, like the <a href="#source">source code distribution</a>,
+include some example programs in it's file system, so you can run and play them (yes! we have games too! :), following the instructions in our <a href="using.html">Using eLua</a> page. The
+available example programs are described in our <a href="examples.html">examples page</a>.</p>
+<p>If you need a customized binary image for an already supported platform (for example with an autorun program, with some code of yours in the File System, with your LAN IP settings) and the
+<a href="building.html">instructions for building eLua</a> didn't work for you, feel free to <a href="overview.html#contacts">write us</a> explaining what you need. We may find some time to
+build one for you and eventually make it available here too.</p>
+<p>To understand what's in a file name (for example <i>elua_lualong_lm3s8962.bin</i>) check our <a href="building.html">building eLua</a> page.
+<!-- [NEWVER] -->
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>MCU</th>
+<th>Board</th>
+<th>Lua number type</th>
+<th>Image file</th>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_at91sam7x256.bin">elua0.5_lua_at91sam7x256.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+<td>None</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_at91sam7x512.bin">elua0.5_lua_at91sam7x512.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.intel.com">i386 (generic)</a><br>
+<td>PCs/emulators</td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_i386.elf">elua0.5_lua_i386.elf</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_lm3s6965.bin">elua0.5_lua_lm3s6965.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+<td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_lm3s8962.bin">elua0.5_lua_lm3s8962.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+<td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_lpc2888.bin">elua0.5_lua_lpc2888.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+<td><a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_str711fr2.bin">elua0.5_lua_str711fr2.bin</a></td>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+<td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+<td>double</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua0.5_lua_str912fw44.bin">elua0.5_lua_str912fw44.bin</a></td>
+</tr>
+</tbody>
+</table></p>
+<p><b>NOTE:</b> <i>Lua number type</i> reffers to the built Lua interpreter number type, float or integer, as explained in the <a href="building.html">building eLua</a> page.</p>
+<h3><a name="source">Source code</a></h3>
+<p>If all you want is to take a quick peek at <b>eLua</b>'s source code, but you don't need to download it, it's probably enough to use the
+<a target="_blank" href="http://svn.berlios.de/wsvn/elua">BerliOS WebSVN interface</a>. You can browse through the complete source of <b>eLua</b> using this method.<br>
+If you need to download the source code of <b>eLua</b> you can either:
+<ul>
+ <li>download the source code archive of an official release</li>
+ <li>checkout the latest (bleeding edge) source code from the SVN repository in read-only mode (anonymous) mode</li>
+ <li>checkout the latest (bleeding edge) source code from the SVN repository in read-write mode (for developers)</li>
+</ul></p>
+<a name="official"><h2>Source code archives</h2></a>
+<p>Check the table below for the download link of the source code associated with the latest official release of <b>eLua</b>. If you want to get the source
+code of an older version, check out <a href="dl_old.html">this page</a>.
+<!-- [NEWVER] -->
+<table class="table_center">
+<tbody>
+<tr>
+<th>Version</th>
+<th>Source code archive</th>
+</tr>
+<tr>
+<td>0.5</td>
+<td><a target="_blank" href="http://prdownload.berlios.de/elua/elua-0.5.tgz">eLua 0.5</a></td>
+</tr>
+</tbody></table></p>
+<a name="svnpublic"><h2>SVN public repository (anonymous)</h2></a>
+<p>If you'd rather have the very last development ("bleeding edge") version, just check it out from our Subversion Repository:</p>
+<p><pre>$ svn checkout svn://svn.berlios.de/elua/trunk</pre></p>
+<p>Once checked out, the repository can be easily updated by the svn client command:</p>
+<p><pre>$ svn update</pre></p>
+<a name="svndev"><h2>SVN public repository (r/w, for developers)</h2></a>
+<p>Follow the steps below if you need write access to the <b>eLua</b> repository:
+<ul>
+ <li>if you don't have an account on <a target="_blank" href="http://developer.berlios.de/">developer.berlios.de</a>, create one.</li>
+ <li><a href="overview.html#contacts">contact us</a> specifying your BerliOS ID and we'll give you write access to the repository.</li>
+</ul></p>
+<p>Then checkout the repository:</p>
+<p><pre>$ export SVN_SSH='ssh -l <yourberliosid>
+$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk</pre></p>
+<p>Once checked out, the repository can be easily updated:</p>
+<p><pre>$ svn update</pre></p>
+
+</body></html>
Modified: branches/eagle_mmc/doc/en/examples.html
===================================================================
--- branches/eagle_mmc/doc/en/examples.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/examples.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,130 +1,132 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>eLua examples</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
-<h3>Lua Code Examples</h3>OK, so you built eLua, and even burnt it to your board, but now
-you'd like to see some example programs. They are included in the eLua
-source distribution (see the <a href="http://www.eluaproject.net/en/Downloads">download page</a>
-for details), under the romfs/ subdirectory (which also means that they
-are built into the eLua image and can be run directly, see
-docs/the_rom_file_system.txt for details). Alternatively you can get
-them by using the <a href="http://svn.berlios.de/wsvn/elua/trunk/romfs/#_trunk_romfs_">BerliOS web SVN</a>
-interface.
-As previously explained, you can run them directly from the ROM file
-system, or you can use the eLua shell and send them via XMODEM, as
-described <a href="http://www.eluaproject.net/en/Using_eLua">here</a>.<br><br>
+<h3>Lua Code Examples</h3>
+<p><b>eLua</b> distros come bundled with nice and fun
+(yes! we have games too! :) Lua programs examples in the File System. They are also included in the <b>eLua</b>
+source code distribution, under the <i>/romfs</i> subdirectory. As previously explained, you can run them directly from <b>eLua</b>'s file
+system or you can use the eLua shell and send them via XMODEM, as
+described <a href="using.html#shell">here</a>.</p>
-<h3><a name="hello"></a>hello.lua: the ubiquitous "Hello, World!"</h3>
-
-<p><strong>Runs on: all targets</strong><br>
-To call this a "program" is a gross overstatement, but it's a
-tradition, so we respect it :) It just prints "Hello, World!" and
-returns to the shell. Download it only if you feel too lazy to fire up
+<h3>hello.lua: the ubiquitous "Hello, World!"</h3>
+<p><strong>Runs on: </strong>all targets</p>
+<p><strong>Description: </strong>to call this a "program" is a gross overstatement, but it's a
+tradition, so we respect it :) It just prints "Hello, World!" on the terminal and
+returns to the shell. Run it from the file system only if you feel too lazy to fire up
the lua interpreter inside eLua and write it yourself :)</p>
-<h2><br></h2><h3><a name="info"></a>info.lua: getting the platform data</h3>
-
-<p><strong>Runs on: all targets except i386</strong><br>
-This isn't really more advanced than "Hello, World!", but it does show
-an eLua specific module: the platform data module (pd). You can read
-more about the platform modules in the eLua source distribution
-(docs/platform_modules.txt). The program will display the platform
+<h3>info.lua: getting the platform data</h3>
+<p><strong>Runs on: </strong>all targets</p>
+<p><strong>Description: </strong>this isn't really more advanced than "Hello, World!", but it does show
+an <b>eLua</b> specific module: the platform data module (<b>pd</b>). You can read
+more about the platform modules <a href="">##here</a>. The program will display the platform
name, the CPU name, the board name and the CPU clock and then will exit
-to the shell.</p><p></p>
+to the shell.</p>
+<h3>led.lua: the old LED blinker, the new eLua way</h3>
-<h3><a name="led"></a>led.lua: the old LED blinker, the new eLua way</h3>
-
-<p><strong>Runs on: all targets except i386</strong><br>
-Now we get to do something "more embedded": blink a LED. The code ilustrates a few interesting eLua features:</p>
-
-<ul><li><p>cross platform code: the code assigns a different pin
+<p><strong>Runs on: </strong> all targets except i386</p>
+<p><strong>Description: </strong> now we get to do something "more embedded": blink a LED. The code illustrates a few interesting <b>eLua</b> features:
+<ul><li><b>cross platform code</b>: the code assigns a different pin
to the LED starting from the board name. You can see how the platform
-data module makes it very easy to write such portable code.</p></li><li><p>uart, pio, tmr, pd modules: they are all used here.</p></li></ul>
+data module makes it very easy to write such portable code.</li>
+<li><b>uart, pio, tmr, pd modules</b>: they are all used here.</li></ul></p>
+<p>Watch it blink, then press any key to return to the eLua shell.</p>
-<p>Watch it blink, then press any key to return to the eLua shell.</p><p></p>
-
-<h3><a name="hangman"></a>hangman.lua: taking advantage of your terminal</h3>
-
-<p><strong>Runs on: all targets except i386</strong><br>
-By far the geekiest example from the eLua distribution, it makes use of
-the term module (docs/terminal_support.txt) to let the user play a
-BSD-like "hangman" directly in his terminal emulator. Run the example
+<h3>hangman.lua: taking advantage of your terminal</h3>
+<p><strong>Runs on: </strong>all targets</p>
+<p><strong>Description: </strong>the geekiest example from the <b>eLua</b> distribution (or would it be morse.lua? :), it makes use of
+the <a href="">##term module</a> to let the user play a BSD-like "hangman" directly in his terminal emulator. Run the example
and enjoy. Currently it has a very small list of words, as this was
written mainly as a proof of eLua's capabilities, but it's very easy to
-add new words/replace the existing ones. A screenshot can be seen <a href="http://elua.berlios.de/other/elua_hangman.png">here</a>.</p><p></p>
+add new words/replace the existing ones. A screenshot can be seen <a href="">##here</a>.</p>
-<h3><a name="pwmled"></a>pwmled.lua: LED blinker, advanced class</h3>
-
-<p><strong>Runs on: EK-LM3S8962 and EK-LM3S6965</strong><br>
-This uses the PWM module to fade the on-board LED in and out, in an
+<h3>pwmled.lua: LED blinker, advanced class</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><strong>Description: </strong>this uses the PWM module to fade the on-board LED in and out, in an
infinite loop. Not much to say here, the code is very simple, yet the
results are quite spectacular. Press any key to end the sample and
-return to the shell.</p><p></p>
+return to the shell.</p>
-<h3><a name="tvbgone"></a>tvbgone.lua: yes, eLua can do real time!</h3>
+<h3>dualpwm.lua: because a single LED is just not enough</h3>
+<p><strong>Runs on: </strong>MOD711</p>
+<p><strong>Description: </strong>My <a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711 board</a> needed a
+"motherboard" for a few components (mainly the RS232-TTL level converter and a reset button) so I also added two LEDs to it, connected
+to two different PWM channels. With this program, the two LEDs fade at the same type, but in different directions.</p>
-<p><strong>Runs on: EK-LM3S8962 and EK-LM3S6965</strong><br>
-This is more complex, but also very important for eLua, because it
+<h3>pong.lua: eLua meets a classic</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><strong>Description: </strong>a very simple, incomplete implementation of the famous <a target="_blank" href="http://en.wikipedia.org/wiki/Pong">pong</a>
+game. It uses the display and keys on the EK-LM3S8962 or EK-LM3S6965 boards. It uses a platform dependent module (<b>disp</b>) and also shows how
+<b>require</b> can be used from <b>eLua</b>.You can set different game speeds. Enjoy! :)</p>
+
+<h3>tvbgone.lua: yes, eLua can do real time!</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><strong>Description: </strong>this is more complex, but also very important for <b>eLua</b>, because it
proves that real time applications (with relatively strict timing
-requirements) can run from eLua directly. It's the famous TV-B-Gone
-project adapted from <a href="http://www.ladyada.net/make/tvbgone/">LadyAda's kit</a>.
+requirements) can run from <b>eLua</b> directly. It's the famous TV-B-Gone
+project adapted from <a target="_blank" href="http://www.ladyada.net/make/tvbgone/">LadyAda's kit</a>.
If you're not familiar with TV-B-Gone, it knows how to do one thing
very well: power off your TV :) Basically it contains a lot of remote
control codes (for a lot of TVs) that are continously sent via an IR
-LED. This code uses the PWM module (new in eLua 0.4) and it also does
+LED. This code uses the PWM module (new in <b>eLua</b> 0.4) and it also does
file I/O from Lua, since the remote control codes are kept in a
separate file (which is also part of the ROM file system). To read the
binary file, the "pack" module (also new in 0.4) is used. To ensure
that we don't get any unexpected delays, the Lua garbage collector is
turned off. Take a look at this sample, it's both a very good proof of
-the capabilities of eLua and a good learning resource. To use it on any
-of the Cortex boards (EK-LM3S8962 or EK-LM3S6965) connect an IR LED
+the capabilities of eLua and a good learning resource.<br>
+To use it on EK-LM3S8962 or EK-LM3S6965 connect an IR LED
with a resistor between the "PWM2" and "GND" pins of the extension
connector. Get close to your TV and press the "select" button on your
board to start sending the IR codes. The on-board LED stays lit while
the codes are transmitted and shuts off afterwards. Press the "down"
-button on your board to exit the application and return to the shell.</p><p></p>
+button on your board to exit the application and return to the shell.</p>
-<h3><a name="piano"></a>piano.lua: because PWM is great</h3>
-
-<p><strong>Runs on: EK-LM3S8962, EK-LM3S6965, SAM7-EX256</strong><br>
-Yet another use for the PWM module, this sample can be used to "play"
+<h3>piano.lua: because PWM is great</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965, SAM7-EX256</p>
+<p><strong>Description: </strong>yet another use for the PWM module, this sample can be used to "play"
notes via the on-board speaker using the PC keyboard. The on-screen
keyboard shows what keys you must press for different notes, and you
-can set your octave and inter-note delay. Press ESC to end your eLua
-musical session :) A screenshot can be seen <a href="http://elua.berlios.de/other/elua_piano.png">here</a>.</p><p></p>
+can set your octave and inter-note delay. Press ESC to end your <b>eLua</b>
+musical session :) A screenshot can be seen <a href="##">here</a>.</p>
-<h3><a name="bisect"></a>bisect.lua: floating point at its best</h3>
-
-<p><strong>Runs on: all targets</strong><br>
-This is taken directly from the official Lua distribution, and it's
-here to show that eLua can do floating point just like on a desktop
+<h3>bisect.lua: floating point at its best</h3>
+<p><strong>Runs on: </strong>all targets</p>
+<p><strong>Description: </strong>this is taken directly from the official Lua distribution, and it's
+here to show that <b>eLua</b> can do floating point just like on a desktop
machine, albeit slower. Run it on your target, then run it again, but
-this time on the PC, and compare the results. Yes, they are identical.</p><p></p>
+this time on the PC, and compare the results. Yes, they are identical.</p>
-<h3><a name="morse"></a>morse.lua: because PWM is great, part II</h3>
+<h3>life.lua: the game of life</h3>
+<p><strong>Runs on: </strong>i386</p>
+<p><strong>Description: </strong>another example taken directly from the Lua distribution, this time
+the well known <a target="_blank" href="http://en.wikipedia.org/wiki/Conway%27s_Game_of_Life">game of life</a>.
+Start it and enjoy. Only included on i386 by default because it's faster on i386, but it can run on other
+platform too (although it requires quite a bit of memory, which is not a problem for boards with external
+memory). </p>
-<p><strong>Runs on: EK-LM3S8962, EK-LM3S6965, SAM7-EX256</strong><br>
-This uses the same PWM module for Morse code generation. Just enter a
+<h3>morse.lua: because PWM is great, part II</h3>
+<p><strong>Runs on: </strong> EK-LM3S8962, EK-LM3S6965, SAM7-EX256</p>
+<p><strong>Description: </strong>this uses the same PWM module for Morse code generation. Just enter a
text, and listen to it getting Morsed on your board's speaker and on a blinking Led. The
letters and Morse codes are also shown on the terminal. Use '+' and
'-'' to change the frequency, up and down arrows to change the speed,
-'s' to mute/unmute, and ESC to exit.</p><p></p>
+'s' to mute/unmute, and ESC to exit.</p>
-<h3><a name="lhttpd"></a>lhttpd.lua: only with (e)Lua ...</h3>
-
-<p><strong>Runs on: EK-LM3S8962, EK-LM3S6965</strong><br>
-This is one of those things that can show the real potential of a
-language (and hopefully the real potential of eLua in this case). As
-you have probably guessed by now, it's a web server written in Lua.
-Except it's much more than this: it's a scripting web server! That's
+<h3>lhttpd.lua: only with (e)Lua ...</h3>
+<p><strong>Runs on: </strong>EK-LM3S8962, EK-LM3S6965</p>
+<p><strong>Description: </strong>this is one of those things that can show the real potential of a
+language (and hopefully the real potential of <b>eLua</b> in this case). As
+you have probably guessed by now, it's a web server written in Lua.
+Except that it is much more than this: it's a <b>scripting web server!</b> That's
right, you can embed parts of Lua code into your pages, and the server
-will parse them and replace the Lua code with its output (to output
+will parse them and replace the Lua code with its output. To output
something from Lua code embedded in a web page, simply use "print" in
-your Lua code). You can also write your pages completely in Lua (again,
+your Lua code. You can also write your pages completely in Lua (again,
using "print"), the server knows how to handle this too. When is the
last time you heard about a scripting web server in 256k of Flash/64k
of RAM? </p><p>The full list of features is given below:</p>
@@ -138,6 +140,18 @@
it and sends its output (via "print" statements)</li></ul>
<p>This is still work in progress, but it already works quite well.
-Take a look at romfs/index.pht and romfs/test.lua from the source
+Take a look at <i>romfs/index.pht</i> and <i>romfs/test.lua</i> from the source
distribution for an example of how to include Lua code in your HTML
-files.</p><p></p><p></p><p></p></body></html>
\ No newline at end of file
+files.</p>
+
+<h3>adcscope.lua: ADCs and eLua, part I</h3>
+<p><b>Runs on: </b>##TODO</p>
+<p><b>Description: </b>##TODO
+</p>
+
+
+<h3>adcpoll.lua: ADCs and eLua, part II</h3>
+<p><b>Runs on: </b>##TODO</p>
+<p><b>Description: </b>##TODO
+</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/faq.html
===================================================================
--- branches/eagle_mmc/doc/en/faq.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/faq.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,257 +1,150 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>eLua FAQ</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Frequently Asked Questions</h3><br><div class="content">
+<h3>eLua Frequently Asked Questions</h3><p>Welcome to the official <b>eLua</b> FAQ!
+It is assumed that you already know what <b>eLua</b>, so here's a list of questions (and their answers) that you might find useful.</p>
-<p>Welcome to the official eLua FAQ!
-It is assumed that you already know <a>what eLua is</a>, so here's a list of questions you might find useful while exploring eLua.</p>
-
-<ul><li><p><a href="#learnlua">How can I learn Lua? Is it hard?</a><br></p></li><li><p><a href="#readingorder">I
-see a lot of files in the docs/ directory of the eLua source
-distribution, and I'm not sure how I should read them. Is there a
-recommened reading order?</a><br></p></li><li><p><a href="#helpelua">How can I help eLua?</a><br></p></li><li><p><a href="#comercial">Can I use eLua in my commercial, closed source project?</a><br></p></li><li><p><a href="#fast">Is eLua fast enough?</a><br></p></li><li><p><a href="#minimuns">What are the minimum requirements for eLua?</a><br></p></li><li><p><a href="#portability">Since
-I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I
-trust my peripheral code to run the same on all my platforms?</a><br></p></li><li><p><a href="#luaversions">What's the deal with floating-point Lua and integer only Lua?</a><br></p></li><li><p><a href="#windows">All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</a><br></p></li><li><p><a href="#cygwin">Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</a><br></p></li><li><p><a href="#bytecode">I
-know that Lua can be compiled to bytecode, so I compiled one of the
-eLua examples with luac and tried to run it on my eLua board, but it
-didn't work. Is this a bug in eLua?</a><br></p></li><li><p><a href="#arm">Does eLua run only on ARM based CPUs?</a><br></p></li><li><p><a href="#outofmemory">I get "out of memory" errors when I run my Lua programs, what should I do?</a><br></p></li></ul>
-
-<p><br></p>
-
+<ul>
+ <li><a href="faq.html#learnlua">How can I learn Lua? Is it hard?</a></li>
+ <li><a href="faq.html#helpelua">How can I help eLua?</a>
+ <li><a href="faq.html#comercial">Can I use eLua in my commercial, closed source project?</a>
+ <li><a href="faq.html#fast">Is eLua fast enough?</a>
+ <li><a href="faq.html#minimum">What are the minimum requirements for eLua?</a></li>
+ <li><a href="faq.html#portability">Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the
+ same on all my platforms?</a></li>
+ <li><a href="faq.html#luaversions">What's the deal with floating-point Lua and integer only Lua?</a></li>
+ <li><a href="faq.html#windows">All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools.
+ How come?</a>
+ <li><a href="faq.html#cygwin">Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</a></li>
+ <li><a href="faq.html#bytecode">I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on
+ my eLua board, but it didn't work. Is this a bug in eLua?</li>
+ <li><a href="faq.html#outofmemory">I get "out of memory" errors when I run my Lua programs, what should I do?</li>
+ <li><a href="faq.html#rotables">I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
+ disable LTR if I want write access to these modules?</a>
+</ul>
<hr>
-<p><a name="learnlua"></a>
-<strong>Q: How can I learn Lua? Is it hard?</strong></p>
+<a name="learnlua"><h2>How can I learn Lua? Is it hard?</h2></a>
+<p>Lua is a minimalistic language (yet very powerful) which is quite easy to learn. Once you understand the basic concepts you'll find yourself writing
+ Lua programs in notime. The main resource is the <a target="_blank" href="http://www.lua.org/">Lua homepage</a>. In the
+ <a target="_blank" href="http://www.lua.org/docs.html">documentation page</a> you'll find the reference manual and the first version of the excellent
+ "Programming in Lua" book. I recommend purchasing the second version of this book, since it's likely that this is all you'll ever need to learn
+ Lua. Another very good resource is the <a target="_blank" href="http://lua-users.org/wiki/">Lua wiki</a>. If you need more help, check the
+ <a target="_blank" href="http://www.lua.org/community.html">community page</a>. Lua has a very friendly and active community.</p>
-<p>A: Lua is a minimalistic language (yet very powerful) which is quite
-easy to learn. Once you understand the basic concepts you'll find
-yourself writing Lua programs in notime. The main resource is the <a href="http://www.lua.org/">Lua homepage</a>. In the <a href="http://www.lua.org/docs.html">documentation page</a>
-you'll find the reference manual and the first version of the excellent
-"Programming in Lua" book. I recommend purchasing the second version of
-this book, since it's likely that this is all you'll ever need to learn
-Lua. Another very good resource is the <a href="http://lua-users.org/wiki/">Lua wiki</a>. If you need more help, check the <a href="http://www.lua.org/community.html">community page</a>. Lua has a very friendly and active community.</p>
+<a name="helpelua"><h2>How can I help eLua?</h2></a>
+<p><b>eLua</b> has many ambitious goals, so it would be great to have more people working on it. Take a look at the
+ <a href="status.html#roadmap">roadmap page</a>, and if you see something there that you'd like to work on, don't hesitate to
+ <a href="overview.html#contacts">contact us</a>. Also, if you'd like to make a donation to the project (money, or maybe a development board)
+ rest assured that wwe won't say no :) It also helps a lot if you test <b>eLua</b> on your own board and you find a bug or an
+ incomplete feature. Or if you just thought about a cool feature that you'd like to see in <b>eLua</b>.
+ If so, feel free to <a href="overview.html#contacts">contact us</a>.</p>
-<p><a name="readingorder"></a>
-<strong>Q: I see a lot of files in the docs/ directory of the eLua
-source distribution, and I'm not sure how I should read them. Is there
-a recommened reading order?</strong></p>
+<a name="comercial"><h2>Can I use eLua in my commercial, closed source project?</h2></a>
+<p>Starting with version 0.6, <b>eLua</b> distributed under a MIT license, so you can use it in your close source projects. Prior to this it was
+ distributed under GPL, which restricted its usage to open source applications only. Be careful though, <b>eLua</b> includes some 3rd party libraries,
+ each with its own licensing terms that might be more restrictive than MIT. See <a href="overview.html#license">the eLua license</a> for details.</p>
-<p>A: It depends:</p>
+<a name="fast"></a><h2>Is eLua fast enough?</h2></a>
+<p>This pretty much depends on what you expect. If you expect your Lua code to run as fast as your compiled C code, this won't happen, simply because C
+ is a compiled language, while Lua is an interpreted language. That said, you'll be happy to know that Lua is one of the fastest interpreted languages
+ out there. If you really need both high speed and Lua, you can write your speed critical code sections in C and export them as a Lua module.
+ This way you get the best of both worlds. We don't have any official benchmarks about Lua speed on embedded devices, but you might want to check the
+ TV-B-Gone example on the <a href="examples.html">##examples page</a>.TV-B-Gone is a "software remote control" application coded directly in <b>eLua</b>.
+ If you're familiar with the remote control protocols, you'll know that this kind of application is quite "real time", and delays in the order of
+ milliseconds or even less can make your software remote control fail. Yet this sample runs without problems on a 50MHz Cortex (Thumb2) CPU. This should
+ give you a fairly intuitive view on the speed of eLua.</p>
-<ul><li>if you just want to build eLua, reading building.txt (or, alternatively, <a href="http://www.eluaproject.net/?p=Building_eLua">this page</a>) should be enough.</li><li>if you want to take control of what's getting built in your eLua image, read elua_components.txt and platform_modules.txt.</li><li>if
-you want to know what goodies you're getting from eLua, read
-the_elua_shell.txt, generic_modules.txt, platform_modules.txt,
-the_rom_file_system.txt and tcpip_in_elua.txt.</li><li>if you want to add a new I/O interface to eLua, read console_input_output.txt and terminal_support.txt.</li><li>if you want to add a new platform to eLua, read all of the above plus platform_interface.txt and adding_a_new_platform.txt.</li></ul>
-
-<p><a name="helpelua"></a>
-<strong>Q: How can I help eLua?</strong></p>
-
-<p>A: OK, so I lied, this is NOT a frequently asked question :)
-However, if you really want to help eLua, keep in mind that we're
-looking for developers. eLua has many ambitious goals, so it would be
-great to have more people working on it. Take a look at the <a href="http://www.eluaproject.net/?p=Status">roadmap page</a>, and if you see something there that you'd like to implement, don't hesitate to <a href="http://www.eluaproject.net/?p=Contact">contact us</a>.
-Also, if you'd like to make a donation to the project (money, or maybe
-a development board) rest assured that wwe won't say no :) It also
-helps a lot if you test eLua on your own board and you find a bug or an
-incomplete feature. Or if you just thought about a cool feature that
-you'd like to see in eLua. If so, feel free to <a href="http://www.eluaproject.net/?p=Contact">contact us</a>.</p>
-
-<p><a name="comercial"></a>
-<strong>Q: Can I use eLua in my commercial, closed source project?</strong></p>
-
-<p>A: No. Since eLua is licensed under GPL, you can't use it in a
-commercial closed source project. You can use it in a commercial
-application if you make your source code public. However, if all goes
-as planned, this will change soon enough. I won't give any details just
-yet, but keep on watching the project. You know, just in case ... :)</p>
-
-<p><a name="fast"></a>
-<strong>Q: Is eLua fast enough?</strong></p>
-
-<p>A: This pretty much depends on what you expect. If you expect your
-Lua code to run as fast as your compiled C code, this won't happen,
-simply because C is a compiled language, while Lua is an interpreted
-language. That said, you'll be happy to know that Lua is one of the
-fastest interpreted languages out there. If you really need both high
-speed and Lua, you can write your speed critical code sections in C and
-export them as a Lua module. This way you get the best of both worlds.
-I don't have any official benchmarks about Lua speed on embedded
-devices, but you might want to check the TV-B-Gone example on the <a href="http://www.eluaproject.net/?p=Examples">examples page</a>.
-TV-B-Gone is a "software remote control" application coded directly in
-eLua. If you're familiar with the remote control protocols, you'll know
-that this kind of application is quite "real time", and delays in the
-order of milliseconds or even less can make your software remote
-control fail. Yet this sample runs without problems on a 50MHz Cortex
-(Thumb2) CPU. This should give you a fairly intuitive view on the speed
-of eLua.</p>
-
-<p><a name="minimuns"></a>
-<strong>Q: What are the minimum requirements for eLua?</strong></p>
-
-<p>A: It's hard to give a precise answer to this. As a general rule for
-a 32-bit CPU, I recommend at least 256k of Flash (program memory) and
+<a name="minimum"><h2>What are the minimum requirements for eLua?</h2></a>
+<p>It's hard to give a precise answer to this. As a general rule for
+a 32-bit CPU, we recommend at least 256k of Flash (program memory) and
at least 64k of RAM. However, this isn't a strict requirement. A
stripped down, integer-only version of eLua can definetely fit in 128k
of Flash, and depending on your type of application, 32k of RAM might
prove just fine. It largely depends on your needs.</p>
-<p><a name="portability"></a>
-<strong>Q: Since I'm using the Lua platform modules (uart, spi, pwm,
-tmr...), can I trust my peripheral code to run the same on all my
-platforms?</strong></p>
-
-<p>A: Unfortunately, no. While eLua makes it possible to have a common
-code on different platforms using the platform interface
-(docs/platform_interface.txt), it can't possibly provide the same
-functionality on all platforms, since all CPUs are not created equal.
-It is very recommended (and many times imperative) to have an
-understanding of the peripherals on your particular CPU before you
-write your code. This, of course, is not particular to eLua, but it's
-especially important since the platform interface might give the
-impression that it offers an uniform functionality over all platforms,
-when in fact the only thing in common is often just the interface
-itself (that is, the methods and variables you can access in a given
-module). eLua tries to help here by giving you an error when you try to
-access a physical resource that is not available (for example a timer,
-a PWM channel, or a PIO pin/port), but it doesn't try to cover all the
-possible platform-related issues, since this would increase the code
-size and complexity too much. These are some caveats that come to mind
-(note that these are only a few examples, the complete list is much
-longer):</p>
-
-
-<ul><li>timers: from all the platforms on which eLua runs, only
-the Luminary Cortex CPUs has rock solid 32-bit timers. You can do
-pretty much everything you need with them. All the other platforms have
-16-bit timers, which imposes some limits on the range of delays you can
-achieve with them. Make sure to use tmr.mindelay(id) and
-tmr.maxdelay(id) to check the actual resolution of your timers, and
-adapt your code accordingly. To 'compensate' for this, it's not
-possible to change the base timer frequency on the Cortex CPUs, but it
-is possible on most other platforms :) So be sure to also check the
-result of tmr.setclock(id)</li><li>also, when using timers,
-remember that if you're using XMODEM and/or the "term" module, TMR0 is
-used by both of them. So, if you change the TMR0 base clock in your
-code, be sure to restore the original setting before returning to the
-shell. You can change this static timer assignment by modifying
-src/main.c. It might also be possible to change it dynamically in the
-future, although I see little use for this.</li><li>PWM: the
-Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5
-respectively share the same base clock setting. So, when you're
-changing the base clock for channel 1, you're also changing the base
-clock for channel 0; if channel 0 was already running, you won't like
-what will happen next. This time no eLua function can save you, you
-simply need you know your CPU architecture.</li><li>GPIO: only
-some platform have internal pullups for the GPIO pins, while Cortex is
-the only platform that also provides pulldowns for its GPIOs. However,
-in this case you're safe, as eLua will signal an error if you try to
-execute a pullup operatin on a platform that does not support it.</li></ul>
-
+<a name="portability"><h2>Since I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I trust my peripheral code to run the same on all my
+ platforms?</h2></a>
+<p>Unfortunately, no. While <b>eLua</b> makes it possible to have a common code on different platforms using the <a href="">##platform interface</a>,
+ it can't possibly provide the same functionality on all platforms, since all MCUs are not created equal. It is very recommended
+ (and many times imperative) to have an understanding of the peripherals on your particular MPU before you start writing your code.
+ This, of course, is not particular to <b>eLua</b>, but it's especially important since the platform interface might give the impression that it
+ offers an uniform functionality over all platforms, when in fact the only thing in common is often just the interface itself (that is, the methods and
+ variables you can access in a given module). <b>eLua</b> tries to help here by giving you an error when you try to access a physical resource that is
+ not available (for example a timer, a PWM channel, or a PIO pin/port), but it doesn't try to cover all the possible platform-related issues, since this
+ would increase the code size and complexity too much. These are some caveats that come to mind (note that these are only a few examples, the complete
+ list is much longer):</p>
+<ul>
+ <li><b>timers</b>: from all the platforms on which <b>eLua</b> runs, only the Luminary Cortex CPUs has rock solid 32-bit timers. You can do pretty much
+ everything you need with them. All the other platforms have 16-bit timers, which imposes some limits on the range of delays you can achieve with them.
+ Make sure to use tmr.mindelay(id) and tmr.maxdelay(id) to check the actual resolution of your timers, and adapt your code accordingly. To 'compensate'
+ for this, it's not possible to change the base timer frequency on the Cortex CPUs, but it is possible on most other platforms :) So be sure to also check
+ the result of tmr.setclock(id)</li>
+ <li>also, when using timers, remember that if you're using XMODEM and/or the "term" module, one of them (generall TMR0) is used by both of them. So, if
+ you change the TMR0 base clock in your code, be sure to restore the original setting before returning to the <b>eLua</b> shell.</li>
+ <li><b>PWM</b>: the Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5 respectively share the same base clock setting. So, when you're
+ changing the base clock for channel 1, you're also changing the base clock for channel 0; if channel 0 was already running, you won't like
+ what will happen next. This time no eLua function can save you, you simply need you know your CPU architecture.</li>
+ <li><b>GPIO</b>: only some platform have internal pullups for the GPIO pins (others might also have pulldowns). However, in this case you're safe, as
+ <b>eLua</b> will signal an error if you try to execute a pullup operatin on a platform that does not support it.</li>
+</ul>
<p>The lesson here is clear: understand your platform first!</p>
+<a name="luaversions"><h2>What's the deal with floating-point Lua and integer only Lua?</h2></a>
+<p>Lua is build around a number type. Every number in Lua will have this type. By default, this number type is a double. This means that even if your
+ program only does integer operations, they will still be treated as doubles. On embedded platforms this is a problem, since the floating point
+ operations are generally emulated in software, thus they are very slow. This is why <b>eLua</b> gives you "integer only Lua": a Lua with the default
+ number type changed to long. The advantages are increased speed and smaller code size (since we can force Newlib to "cut" the floating point code from
+ printf/scanf and friends, which has quite a strong impact on the code size) and increased speed. The downside is that you'll loose the ability to do
+ any floating point operations (although a separate module that will partially overcome this limitation will be provided in the future).</p>
-<p><a name="luaversions"></a>
-<strong>Q: What's the deal with floating-point Lua and integer only Lua?</strong></p>
+<a name="windows"><h2>All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</h2></a>
+<p>It's true that we do all the <b>eLua</b> development under Linux, since we find Linux an environment much more suited for development. At the same
+ time it's true that most of the tools that come with my development boards run under Windows. So we choose to use the best of both world: Bogdan runs
+ Linux under a <a target="_blank" href="http://www.virtualbox.org">VirtualBox</a> emulator, and does verything else under Windows. Dado does everything on
+ Linux and runs Windows under <a href="http://www.vmware.com" target="_blank">VMWare</a>. Both options are nice if you master your environment. To make
+ everything even more flexible, Bogdan keeps his VirtualBox Ubuntu image on an external WD passport disk that he can carry with him wherever he goes,
+ so he can work on eLua whenever he has a bit of spare time :)</p>
-<p>A: Lua is build around a number type. Every number in Lua will have
-this type. By default, this number type is a double. This means that
-even if your program only does integer operations, they will still be
-treated as doubles. On embedded platforms this is a problem, since the
-floating point operations are generally emulated in software, thus they
-are very slow. This is why eLua gives you "integer only Lua": a Lua
-with the default number type changed to long. The advantages are
-increased speed and smaller code size (since we can force Newlib to
-"cut" the floating point code from printf/scanf and friends, which has
-quite a strong impact on the code size) and increased speed. The
-downside is that you'll loose the ability to do any floating point
-operations.</p>
+<a name="cygwin"><h2>Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</h2></a>
+<p>Bogdan: If I ever have way too much spare time on my hands, yes. Otherwise, no. There are many reasons for this. As I already mentioned, I favour Linux
+ over Windows when it comes to developing applications. Also, I noticed that the GNU based toolchains are noticeable slower on Cygwin than on Linux, so
+ experimenting with them can prove frustrating. Also, compiling under Linux and Cygwin should be quite similar,so try starting from my Linux based
+ tutorials, they might work as well on Cygwin.</p>
+<a name="bytecode"><h2>I know that Lua can be compiled to bytecode, so I compiled one of the eLua examples with luac and tried to run it on my eLua
+ board, but it didn't work. Is this a bug in eLua?</h2></a>
+<p>This is not a bug in <b>eLua</b>, it's a bit more subtle than that. See <a href="using.html#cross">the cross-compile section</a> for a full discussion
+ about this problem and its fix.</p>
-<p><a name="windows"></a>
-<strong>Q: All your tutorials give instructions on how to compile eLua
-under Linux, yet you seem to use a lot of Windows tools. How come?</strong></p>
+<a name="outofmemory"><h2>I get "out of memory" errors when I run my Lua programs, what should I do?</h2></a>
+<p>There are a number of things you can try to overcome this:</p>
+<ul>
+ <li><b>enable the LTR patch</b>: you can get very significant improvements if you enable the LTR patch in your <b>eLua</b> image. See
+ <a href="arch_ltr.html">here</a> for more details about LTR, and <a href="building.html">here</a> for instructions about enabling LTR.</li>
+ <li><b>precompile your source to bytecode</b>: if you use bytecode instead of source code Lua won't need to compile your source, so you save some RAM.</li>
+ <li><b>try to avoid using too many strings</b>: strings are immutable in Lua. That means that a statement like <i>s = s .. "\n"</i> (where s is a string)
+ will create a new string each time it's called. If this happens a lot (for example in a loop), your memory will quickly run out because of all the
+ strings. If you really need to do frequent string operations, put them in a table and then use
+ <a target="_blank" href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li>
+ <li><b>control Lua's garbage collection manually</b>: if you're still running out of memory, try calling <i>collectgarbage('collect')</i> from your code,
+ which will force a garbage collection and thus might free some memory.</li>
+</ul>
-<p>A: It's true that I do all the eLua development under Linux, since I
-find Linux an environment much more suited for development. At the same
-time it's true that most of the tools that come with my development
-boards run under Windows. So I choose to use the best of both world: I
-run Linux under an emulator and I do everything else under Windows. My
-emulator of choice is <a href="http://www.virtualbox.org/">VirtualBox</a>.
-It runs very well and I can do everything from the emulator without
-problems. And to make everything even more flexible, I keep my
-VirtualBox Ubuntu image on an external WD passport disk that I can
-carry with me wherever I go, so I can work on eLua whenever I have a
-bit of spare time :) (and yes, I know that technically speaking
-VirtualBox is not an emulator, but it makes no sense to get into
-details like this)</p>
-
-
-<p><a name="cygwin"></a>
-<strong>Q: Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</strong></p>
-
-<p>A: If I ever have way too much spare time on my hands, yes.
-Otherwise, no. There are many reasons for this. As I already mentioned,
-I favour Linux over Windows when it comes to developing applications.
-Also, I noticed that the GNU based toolchains are noticeable slower on
-Cygwin than on Linux, so experimenting with them can prove frustrating.
-Also, compiling under Linux and Cygwin should be quite similar, so try
-starting from my Linux based tutorials, they might work as well on
-Cygwin.</p>
-
-
-<p><a name="bytecode"></a>
-<strong>Q: I know that Lua can be compiled to bytecode, so I compiled
-one of the eLua examples with luac and tried to run it on my eLua
-board, but it didn't work. Is this a bug in eLua?</strong></p>
-
-<p>A: This is not a bug in eLua, it's a bit more subtle than that. It's
-true that ARM and i386 are very similar when it comes to data types:
-all the fundamental data types have the same length, and they are both
-little endian. So, in theory, if you compile a Lua source file on PC
-you should be able to run the compiled bytecode on your eLua board
-without any modifications. But there's a problem here: the default
-double precision floating point representation is different on ARM and
-PC. So, while the two data types have the same endianess and size, they
-are represented differently in memory. This means that you can't use
-the "regular" luac compiler for this task. However, starting with
-version 0.5, you can cross-compile Lua code on PC to run on target. See
-docs/crosscompilation.txt if you want to know how to do this.</p>
-
-
-<p><a name="arm"></a>
-<strong>Q: Does eLua run only on ARM based CPUs?</strong></p>
-
-<p>A: Currently, yes, but this is not by design. eLua runs only on ARM
-CPUs right now because that's what I had access to. It can run on any
-other platform as long as there is Newlib support for that platform.
-For example, it could run very well on <a href="http://www.atmel.com/products/AVR32/">AVR32</a>,
-which is a very likely future target for eLua. The main problem here is
-the Newlib dependency. Once this is eliminated, it will be able to run
-on a much larger range of platforms, including 8-bit CPUs (yes, this is
-actually possible, and personally I can't wait to see eLua running on
-my <a href="http://www.zilog.com/index.php?option=com_content&task=view&id=58&businessLine=1&parent_id=77&Itemid=185">eZ80</a> board). But it will probably be a while until I manage to get rid of Newlib and provide a generic libc replacement.</p>
-
-
-<p><a name="outofmemory"></a>
-<strong>Q: I get "out of memory" errors when I run my Lua programs, what should I do?</strong></p>
-
-<p>A: There are a number of things you can try to overcome this:</p>
-
-<ul><li>precompile your source to bytecode: see
-docs/crosscompilation.txt for details. If you use bytecode instead of
-source code Lua won't need to compile your source, so you save some RAM.</li><li>try
-to avoid using too many strings: strings are immutable in Lua. That
-means that a statement like s = s .. "\n" (where s is a string) will
-create a new string each time it's called. If this happens a lot (for
-example in a loop), your memory will quickly run out because of all the
-strings. If you really need to do frequent string operations, put them
-in a table and then use <a href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li><li>call
-'collectgarbage' manually: if you're still running out of memory, try
-calling collectgarbage('collect') from your code, which will force a
-garbage collection and thus might free some memory.</li></ul>
-
-</div></body></html>
\ No newline at end of file
+<a name="rotables"><h2>I enabled the LTR patch, but now all my module tables (math, io, string, spi and so on) are read only. Do I have to
+ disable LTR if I want write access to these modules?</h2></a>
+<p>You don't really have to disable LTR to get write access to your rotables, you can use some simple Lua "tricks" instead. Let's suppose that you need
+ write access to the <b>math</b> module. With LTR enabled, <b>math</b> is a rotable, so you can't change its keys/values. But you can use metatables
+ to overcome this limitation:</p>
+<p><pre><code>local oldmath = math
+math = { __index = oldmath }
+setmetatable( math, math )
+</code></pre></p>
+<p>This way you can use <i>math</i> in "write mode" now (since it is a regular table), but you can still access the keys from the original <i>math</i>
+ rotable. Of course, if you need write access to <b>all</b> your modules (or to most of them) it makes more sense to disable LTR instead, but from our
+ observations this doesn't happen in practice.</p>
+</body></html>
Copied: branches/eagle_mmc/doc/en/forum.html (from rev 269, branches/eagle_mmc/doc/pt/net_ref.html)
===================================================================
--- branches/eagle_mmc/doc/pt/net_ref.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/en/forum.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,12 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua development forum</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css">
+</head>
+<body style="background-color: rgb(255, 255, 255);">
+<a id="nabblelink" href="http://n2.nabble.com/eLua-Development-f2368040.html">eLua Development</a>
+<script src="http://n2.nabble.com/embed/f2368040"></script>
+</body></html>
+
Added: branches/eagle_mmc/doc/en/installing.html
===================================================================
--- branches/eagle_mmc/doc/en/installing.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,11 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Installing eLua</h3>
+<p>After building <b>eLua</b>, you need to install it (flash it to your board of choice) before using it. This section shows specific installation instructions for all the CPU/boards supported by <b>eLua</b>. Make sure that you already have a suitable <b>eLua</b> image for your target (either <a href="downloads.html">dowload one</a> or <a href="building.html">build it yourself</a>), then choose the platform of interest from the "Installing" submenu.</p>
+<p>When building your <b>eLua</b> image, remember to specify "prog" to the scons command line in order to get a binary image file that's suitable for programming.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/installing_at91sam7x.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_at91sam7x.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_at91sam7x.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,52 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on AT91SAM7x CPUs</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+ <h3>Using <b>eLua</b> with the AT91SAM7X CPUs from Atmel</h3>
+ <p><a target="_blank" href="http://www.atmel.com">Atmel</a> is a company that doesn't need any kind of introduction :) Their huge product range include some quite nice ARM7TDMI core implementations.
+ Among them are the <a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a> and
+ <a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a> CPUs. The only difference between them is the ammount of internal memory (256k Flash+64k RAM for
+ AT91SAM7X256 vs. 512k Flash+128k RAM for AT91SAM7X512). Loaded with peripherals, and accompanied by a good support package, they make a perfect host for <b>eLua</b>. For this tutorial
+ I'm going to use the <a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> development board from <a target="_blank" href="http://www.olimex.com">Olimex</a>. It's quite a
+ decent board, and also reasonably priced, although it lacks a proper documentation package in my oppinion. It is equipped with an AT91SAM7X256 CPU. As much as I'd like to get
+ my hands on a board with a AT91SAM7X512 CPU, this didn't happen so far, so I'm going to stick with AT91SAM7X256. Of course, you can still try this tutorial if you have
+ a different AT91SAM7X256 development board. Plus, the instructions should be quite similar for AT91SAM7X512 CPUs.
+ </p>
+ <h3> Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the AT91SAM7X256 CPU, make sure that:</p>
+ <ul>
+ <li>you're using Windows. This isn't actually a strict requirement, it just makes life a bit easier. As the Atmel CPU is supported by the <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a> package, programming it from Linux is definitely possible, as OpenOCD runs equally well on Windows and Linux. However, since I'm forced to use Windows anyway because of the restrictions of
+ some of my other development boards, I'm going to take advantage of this and cover the Atmel programming tool instead of OpenOCD. The advantage is that you don't need a JTAG "dongle"
+ to program your board (which would be the case if you were using OpenOCD). The disadvantage, of course, is that the Atmel tool runs only on Windows. Plus, I personally find OpenOCD
+ tedious to use. If you still want to use it though, you might want to check the forementioned <a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">Olimex page</a>, they have some OpenOCD related links there.
+ That said, from now on I'm going to assume that you use Windows. I'm using XP, Vista should work too.</li>
+ <li>you have installed the <a target="_blank" href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3883">AT91 In-system Programmer (ISP)</a> package from Atmel.</li>
+ <li>you already have your <b>eLua</b> image for the AT91SAM7X256 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
+ </ul>
+ <h3>Programming eLua on the SAM7-EX256 board</h3>
+ <p>This involves some jumper tricks, but it's still easy enough to do. We'll need to play with four jumpers: the "USB/EXT" jumper (located to the right of the USB connector
+ from the bottom left part of the board in its close proximity), the "ERASE" jumper (located at the right of the "UEXT" header connector in the top-left
+ part of the board, right ahead the quartz), and the block of two jumpers located right under the "RS232" connector on the board (the one that is adjacent to the Ethernet connector on its right side,
+ <b>NOT</b> the one labeled "CAN" that is closer to the right edge of the board). </p>
+ <ul>
+ <li>connect your board to your PC using a suitable USB cable.</li>
+ <li>if you have a terminal emulation program connected to the board, close it (or at least disconnect it from its port).</li>
+ <li>make sure that the the block of two jumpers mentioned before is set to positions "RXD0" and "TXD0" respectively, <b>NOT</b> "DRXD" and "DTXD".</li>
+ <li>make sure that the "USB/EXT" connector is set to "USB" (position 1-2) and that the "ERASE" jumper is disconnected.</li>
+ <li>connect the "ERASE" jumper and wait one second or more.</li>
+ <li>disconnect the "USB/EXT" jumper completely, then disconnect the "ERASE" jumper too.</li>
+ <li>connect the "USB/EXT" jumper back in the "USB" position (1-2).</li>
+ <li>fire up the Atmel programming tool. If you haven't installed your board yet, you'll be asked to do so at this point.</li>
+ <li>select "\usb\ARMx" as the connection (for me it's \usb\ARM0) and "AT91SAM7X256-EK" as the board.</li>
+ <li>select the "Flash" tab from the middle tab of the window.</li>
+ <li>in the "Send file name" box select your <b>eLua</b> bin file that you got from the compilation step and then press "Send File".</li>
+ <li>wait for the file to be sent and answer "No" to the "Lock region(s)" dialog.</li>
+ <li>in the window section below ("Scripts") select "Boot from Flash (GPNVM2)" then press "Execute".</li>
+ <li>exit the application.</li>
+ </ul>
+ <p>That's it! A bit tricky, but <b>eLua</b> is now programmed in the CPU, so you can start your terminal emulator and enjoy it, as described in <a href="using.html">using eLua</a>.
+ </p>
+</body></html>
Added: branches/eagle_mmc/doc/en/installing_avr32.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_avr32.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_avr32.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,81 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<meta http-equiv="Content-Language" content="en-us"><title> Installing eLua on AVR32 CPUs</title>
+ <h3>Installing <b>eLua</b> on the AVR32 CPUs from Atmel</h3>
+<p><a target="_blank" href="http://www.atmel.com/products/AVR32/">AVR32</a> is a family of high performance 32-bit CPUs from <a target="_blank"
+ href="http://www.atmel.com">Atmel</a>. They were built as direct competitors for the various ARM core implementation of the market, and offer very good
+ performance (91 MIPS @ 66MHz) and power efficieny (1.3mW/MHz). Atmel claims that their AVR32 core outperforms ARMv5 (in ARM and Thumb mode) in terms of
+ both performance and code size. It's a proprietary architecture (so it's only implemented by Atmel), yet it has a very good support package, and an
+ open source toolchain based on GCC, which made it an ideal candidate for the first non-ARM (and also the first big endian) <b>eLua</b> target. Atmel
+ also sells a number of development boards based on their AVR23 CPUs. The one used for <b>eLua</b> is the
+ <a target="_blank" href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100 board</a>, built around the
+ <a target="_blank" href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512 AVR32 MCU</a> (512k internal Flash/64k internal ARM).
+ It's a very powerful board, featuring (among other things) an external 32 MByte SDRAM memory, which is more than enough to run any <b>eLua</b>
+ program I can think of :).</p>
+<h3>Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the AT32UC3A0512 CPU, make sure that:</p>
+ <ul>
+ <li>you're using Linux or Windows. It's easier to install and use Atmel's programming software on Windows, so use Windows version if you want to save
+ yourself from quite a bit of hassle.</li>
+ <li>you installed Atmel's <a target="_blank" href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">FLIP programming software</a>, which is what you need
+ in order to install your <b>eLua</b> image. Installation in easy under Windows (you just need to run a setup paclage), but quite tricky under Linux.
+ The next paragraph outlines the procedure for installing FLIP in Linux.
+ <li>you already have your <b>eLua</b> image for the AT32UC3A0512 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).
+ Note that unlike other platforms, the ATEVK1100 needs a .hex file for programming, not a .bin.</li>
+ </ul></p>
+<h2>Installing FLIP in Ubuntu Linux</h2>
+<p>Follow the steps below to install FLIP under Linux:
+<ol>
+ <li>download the Linux version of FLIP from <a target="_blank" href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886">the Atmel FLIP page</a>. Save it
+ (or move it later) to your <i>/usr/local/</i> directory (you need to have superuser privileges to do that). At the moment of writing this tutorial, the
+ latest FLIP version is 3.2.1, so this is what we're going to use here.</li>
+ <li>untar the FLIP archive:
+ <p><pre><code>$ cd /usr/local
+$ sudo tar xvzf flip_linux_3-2-1.tgz</code></pre>
+ This will create the <i>/usr/local/flip.3.2.1</i> directory.</li>
+ <li>you need to install OpenJDK if it is not installed:
+ <p><pre><code>$ sudo apt-get install openjdk-6-jre</code></pre></p>
+ </li>
+ <li>edit <i>/usr/local/flip.3.2.1/bin/batchisp3.sh</i> and add the two bolded lines before at the beginning of the file:
+ <p><pre><code>#!/bin/bash -f
+
+<b>export JAVA_HOME=/usr/lib/jvm/java-6-openjdk/jre/
+export FLIP_HOME=/usr/local/flip.3.2.1/bin/</b>
+
+if [ "$FLIP_HOME" = "" ]; then</code></pre></p>
+ </li>
+ <li>you need to edit a binary file this time (<i>/usr/local/flip.3.2.1/libatlibusbdfu.so</i>). This happens because FLIP comes compiled for RedHat by
+ default, and Ubuntu some different system paths. See <a target="_blank" href="http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=56562">this topic</a>
+ for full details. All you have to do is change all the <b>/sys/bus/usb</b> strings inside <i>libatlibusbdfu.so</i> to <b>/dev/bus/usb</b>.</li>
+ <li>add the FLIP directory to your PATH:
+ <p><pre><code>$ export PATH=/usr/local/flip.3.2.1/bin:$PATH</code></pre></p>
+ </li>
+ <li>FLIP interferes with a program that comes pre-installed on Ubuntu system, called <b>brltty</b>. It's meant to help the visually
+ impaired, so if you're not one of them, simply remove it (as it seems to interfere with a lot of other USB devices too):
+ <p><pre><code>$ sudo apt-get remove brltty</code></pre></p>
+ </li>
+</ol>
+</p>
+ <h3>Burning <b>eLua</b> to the EVK1100 board</h3>
+<p>After you installed FLIP and added it to your $PATH, burning the <b>eLua</b> image should be quite easy:
+<ul>
+ <li>connect your ATEVK1100 board with the PC using an USB cable</li>
+ <li>put your board in DFU mode (this is required for FLIP interaction). To do this:
+ <p><ol>
+ <li>press <b>on</b> the on-board joystick (and keep it pressed)</li>
+ <li>press the RESET button on the board briefly</li>
+ <li>release the RESET button</li>
+ <li>release the joystick</li>
+ </ol></p>
+ </li>
+ <li>if you're using Windows and it asks you for a driver, you should install it manually from <i>c:\Program Files\Atmel\Flip <version>\usb</i></li>
+ <li>Execute this from the command line (the command is the same on Windows and Linux, with a single exception: the FLIP executable name is <b>batchisp3</b> in Linux and <b>batchisp</b> (without a 3) in Windows):
+ <p><pre><code>$ batchisp3 -hardware usb -device at32uc3a0512 -operation erase f memory flash blankcheck
+ loadbuffer <image name>.hex program verify start reset 0</code></pre></p>
+</ul></p>
+<p>That's all, your <b>eLua</b> image is (finally) installed on your ATEVK1100 board.</p>
+</body></html>
+
Added: branches/eagle_mmc/doc/en/installing_i386.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_i386.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_i386.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,19 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<meta http-equiv="Content-Language" content="en-us"><title>Using eLua on i386 CPUs</title>
+ <h3>Using eLua with Intel i386 (or better) CPUs</h3>
+ <p>Since the i386 platform was implemented as a proof of concept only, the only things you can do with it are:
+ <ul>
+ <li><a href="tut_boot_lua.html">##Boot your PC in eLua</a></li>
+ <li><a href="tut_lua_usb.html">##Boot eLua from a stick</a></li>
+ </ul></p>
+ <p>If you want to do this, <a href="building.html">build your eLua image</a> or download a precompiled image, as explained in the <a href="downloads.html">download page</a>.<br/ >
+ However, most of the features that you'd find on an embedded platform won't work. You won't be able to upload programs to your i386 <b>eLua</b> box using the
+ XMODEM protocol (not because it's impossible, but simply because this doesn't make sense at all on a desktop PC). Also, you won't be able to control the peripherals that you'd normally find in an
+ embedded CPU (SPI, I2C, PIO and all the others), because they are not present on the i386 platform (they can be emulated via different means, but this is way beyond
+ the scope of <b>eLua</b>). So, until further notice, i386 will be nothing more than a spectacular demo platform for <b>eLua</b>. If you think that you can make something
+ more out of it, please feel free to <a href="overview.html#contacts">contact us</a>. I'm actually very interested in this, but I lack the necessary resources to continue it.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/installing_lm3s.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_lm3s.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_lm3s.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,53 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on LM3S CPUs</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+ <h3>Using <b>eLua</b> with the LM3S (Cortex-M3) CPUs from Luminary Micro</h3>
+ <p><a target="_blank" href="http://www.luminarymicro.com">Luminary Micro</a> is the company that produced the world's first silicon implementation of the Cortex-M3 processor. Their
+ device portfolio is quite impressive, ranging from relatively simple devices to full-featured CPUs (with on-chip USB, EMAC, CAN, and many other peripherals). The support
+ package for these devices is also very good, with drivers for all the CPU peripherals and ports of 3rd party applications. And, on a personal note, I contacted Luminary Micro
+ some while ago with a request to support this project with one of their evaluation kits, and their response was excellent (thanks again, Luminary!). That's how a
+ <a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962K</a> landed on my desk. This is the development board that I'm going
+ to use in this tutorial. <b>eLua</b> also supports the <a target="_blank" href="http://www.luminarymicro.com/products/ekk-lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a> board from Luminary (which can be programmed exactly like the EKx-LM3S8962) and the <a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/77">Eagle 100</a> board from <a target="_blank" href="http://www.micromint.com">Micromint</a>, which uses a different installation procedure.
+</p>
+ <h3>Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the LM3S CPU, make sure that:</p>
+ <ul>
+ <li>you're using Windows. Yes, I really said <b>Windows</b>. The reason is quite simple: we're going to use Luminary's tools to burn <b>eLua</b> to the board,
+ and they're Windows specific. This is the case with many CPUs and vendors out there. You can have Windows installed on your HDD, or under
+ an emulator in Linux, it doesn't matter, you can even try to run it from <a target="_blank" href="http://www.winehq.org/">Wine</a> if you're really, really brave. I'm using XP, Vista should work too.</li>
+ <li>you have installed the LM Flash Programmer tool from Luminary. Look for it on <a target="_blank" href="http://www.luminarymicro.com/products/ekk-lm3s8962_can_ethernet_evaluation_kit.html">this page</a>,
+ for example (the link is in the "Software updates" table).</li>
+ <li>you already have your <b>eLua</b> image for the LM3S8962 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>). </li>
+ </ul>
+ <h3>Installing <b>eLua</b> on EKx-LM3S8962EK and EKx-LM3S6965</h3>
+ <p>Fortunately, this is as easy and painless as possible. One of the nicest things about these two kits is they use the on-board USB port for both firmware downloading and for
+ emulating a serial port (via a hardware USB to UART converter, so you don't need any special software on the CPU to access this UART port). Moreover, it automagically
+ knows how (and when) to switch from the firmware download mode to the UART emulation mode, so you don't need to move jumpers around or anything like this. It's zero effort
+ firmware upgrading at its best. So, let's do it:</p>
+ <ul>
+ <li>connect your board to your PC using a suitable USB cable. If you didn't install the board drivers yet, you'll be asked to install them now.</li>
+ <li>if you're already using the USB connection on the board in the UART emulation mode, close your terminal program (or at least disconnect it from the USB COM port).</li>
+ <li>fire up the "Luminary Micro Flash Programmer" application.</li>
+ <li>in the "Configuration" tab, select "LM3S8962 Ethernet and CAN Evaluation board" or "LM3S6965 Ethernet Evaluation Board" (depending on your board).</li>
+ <li>in the "Program" tab, select the <b>eLua</b> .bin file that you got from the compilation step.</li>
+ <li>select the "Options" as you like (I generally choose "Erase entire flash" and "Reset MCU after program").</li>
+ <li>hit the "Program" button.</li>
+ <li>wait until programming is over, then exit the flash programmer application.</li>
+ </ul>
+<p>It's worth to mention that since these boards come with an USB to JTAG converter it should be possible to use OpenOCD (or a similar package) instead of the Luminary tool to program the image. The Luminary Micro forums are a good place to look for information if you're exploring the OpenOCD option.
+</p>
+<h3>Installing eLua on Eagle 100</h3>
+<p>The Eagle 100 board can also be programmed via JTAG, but it doesn't include an on-board USB to JTAG adapter, so you'd need an external adapter if you
+want to use JTAG for programming. Fortunately, it also comes with an Ethernet bootloader, so you can upload your image via Ethernet. The only requirement
+to use the bootloader is to start your image at address 0x2000 instead of the usual 0x0, since that's where the bootloader jumps. The
+<a href="building.html">eLua build system</a> does this automatically if the "board=eagle-100" parameter is given at build time.<br>
+For a full description of the Ethernet bootloader consult the <a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/54/118">Eagle 100 board manual</a>, or (more specifically) <a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/54/122">this link</a> (look for section 2.7, <b>Firmware Updates using the Ethernet Bootloader</b>).<br>
+You still need the LM Flash Tool to use the Ethernet bootloader, but since the board can use JTAG for firmware uploading, it should be possible to use it
+with OpenOCD (or a similar package) and an external USB to JTAG adapter. The Luminary Micro forums are a good place to look for information if you're exploring the OpenOCD option.
+</p>
+</body></html>
+
Added: branches/eagle_mmc/doc/en/installing_lpc2888.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_lpc2888.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_lpc2888.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,41 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on LPC288xx CPUs</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Installing <b>eLua</b> with the LPC2888 CPU from NXP</h3>
+<p>The <a target="_blank" href="http://www.standardics.nxp.com/products/lpc2000/all/~LPC2888/">LPC2888 CPU</a> from <a target="_blank" href="http://www.nxp.com">NXP</a> packs some interesting features: huge internal 1Mbyte flash memory,
+ on-chip USB 2.0 high speed interface, and the most complex (by far) clocking network that I've ever seen on an ATM7TDMI chip. Also, it implements the USB DFU (Device Firmware Update) profile over
+ its USB interface, so it's quite easy to program it in-circuit. I'm using the <a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">Olimex LPC-H2888</a> development board built around this chip, which packs
+ 32MBytes of external SDRAM and also 2MBytes of external flash, which is more than enough for my needs. However, it does have its fair share of downsides. For starters, its support package (from NXP) is very poot when
+ compared to other targets on which <b>eLua</b> runs. You don't even get drivers for all your peripherals, just a a few (quite incomplete) examples. Its datasheet could be much more explit at times, especially when
+ referring to the clocking section (which is quite complicated). On my board, the DFU download mode (firmware upgrade via USB) stopped working out of the blue, without any apparent reasons, and I was unable to
+ use DFU on the chip since then, I had to resort to using OpenOCD (and come up with a configuration file, since it was impossible to find one for LPC2888). The CPU itself has a very interesting limitation: because of a sillicon
+ error, it's impossible to run Thumb code from the on-chip flash, you can only run regular ARM code (?!). Also, the board that I got from Olimex completely ignores the fact that this chip can run in DFU mode (it doesn't include
+ any kind of jumper and/or switch to enable this mode), so I had to build a support board for it. Which is something I had to do also because the board doesn't export a RS232 interface, I had to build one around a MAX232 chip.
+ All in all, my experience with this chip (and with the Olimex board) wasn't that pleasant, but this doesn't change the fact that the LPC-H2888 is the most powerful (resource-wise) board on which <b>eLua</b> runs.
+ </p>
+ <h3>Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the LPC2888 CPU, make sure that:</p>
+ <ul>
+ <li>if you're going to use DFU for firmware programming, you'll need Windows (although I heard reports of Linux programs that can program this chip in DFU mode, but I won't cover them here). If you're going to use OpenOCD, Linux, Windows,
+ or any other OS that has support for <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a> will do. In this case, you might want to have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
+ <li>also, if you're going to use DFU, you'll need a way to boot the chip in DFU firmware upgrade mode. This is done by pulling up (tie to VCC) the P2.3 pin at startup. On my board I included a switch for this. Press the switch, press RESET
+ while holding the switch pressed, then release the switch. You chip is now in DFU mode.</li>
+ <li>if you're using DFU, you have installed the LPC2888 flash programming utility from <a target="_blank" href="http://www.standardics.nxp.com/support/documents/microcontrollers/zip/flash.utility.mass.dfu.lpc2888.zip">here</a> (the package also
+ contains the Windows DFU drivers).</li>
+ <li>if you're using OpenOCD, you have followed the instructions from my <a href="tut_openocd.html">OpenOCD</a> tutorial.</li>
+ <li>you already have your <b>eLua</b> image for the LPC2888 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
+ </ul>
+ <h3>Burning <b>eLua</b> to the LPC2888 using the DFU tool from NXP</h3>
+ <p>The DFU flashing application doesn't work directly on the .bin files you get after building <b>eLua</b>, you need to run them though NXP's "hostcrypt" program (which is part of the LPC2888 DFU package). After you have your <b>eLua</b> .bin file,
+ do this from a Windows command prompt (make sure that hostcryptv2.exe is in the path):</p>
+ <div class="code"><pre>C:> hostcryptv2 elua_lua_lpc2888.bin elua.ebn -K0 -F0</pre></div>
+ <p>As a result, you'll have a new file (<i>elua.ebn</i>). Now boot your chip in DFU firmware upgrade mode (see above) and use the DFU utility (<i>MassDFUApplication.exe</i>) to load <i>elua.ebn</i> into your chip (the instructions on
+ using MassDFUApplication are in a PDF file that's included in the LPC2888 DFU package). Reset the board and enjoy.
+ </p>
+ <h3>Burning <b>eLua</b> to the LPC2888 using OpenOCD</h3>
+ <p>If you're as lucky as me and your board refuses to use DFU anymore, follow my <a href="tut_openocd.html">OpenOCD tutorial</a> to burn your image using OpenOCD.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/installing_stm32.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_stm32.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_stm32.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,47 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on STM32 CPUs</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+ <h3>Using <b>eLua</b> with the STM32 CPUs from ST</h3>
+ <p>The <a target="_blank" href="http://www.st.com/mcu/inchtml-pages-stm32.html">STM32 family</a> of MCUs from
+ <a target="_blank" href="http://www.st.com">ST</a> is a line of Cortex-M3 based chips with a lot of neat features, including (but not limited to) high
+ amounts of on-chip Flash/RAM (up to 512k Flash and 64k RAM), external memory controller that covers (P)SRAM, NAND Flash and NOR flash, integrated ADC and
+ DACs, advanced timers and many others. They also feature an integrated serial boot loader, so it's extremely easy to program them from anything that has
+ a serial port. ST provides a tool that can be used to download a program to the STM32 using this serial bootloader, but it only works in Windows. Their
+ bootloader protocol is documented in a separate application note though, so one can easily write a programming application for any other OS.</p>
+ <p><b>eLua</b> currently works on two STM32F103 variants of the STM32 family, specifically on these boards:
+ <a target="_blank" href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">the STM3210E-EVAL</a> from
+ <a target="_blank" href="http://www.st.com">ST</a> and the
+ <a target="_blank" href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ETM-STM32 stamp</a>
+ from <a target="_blank" href="http://www.futurlec.com">Futurlec</a>. Instruction for installing <b>eLua</b> on each of them are provided below.
+ </p>
+ <h3> Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the STM32F103 CPU, make sure that:</p>
+ <ul>
+ <li>you're using Windows. As already explained, the software provided by ST for serial firmware downloading works only under Windows. It's quite likely
+ that similar tools for Linux and other operating systems already exist or will be available shortly.</li>
+ <li>you have installed the "Flash loader demonstrator" from <a target="_blank" href="http://www.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=110">
+this page</a> (look for it in the "Software - PC" section).</li>
+ <li>you already have your <b>eLua</b> image for the STM32F103 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
+ </ul>
+ <h3>Programming eLUa on the STM3210E-EVAL board</h3>
+ <p>##TODO</p>
+ <h3>Programming eLua on the ET-STM32 stamp</h3>
+ <p>Follow the steps below to install <b>eLua</b> on your ET-STM32 stamp:
+ <ul>
+ <li>connect the board to one of your PC serial ports using the provided serial cable.</li>
+ <li>put the BOOT1 jumper on your board in the ISP position (it should come like that from the factory, and must likely you won't need to change this).</li>
+ <li>press on the BOOT0 switch. The green "BOOT0=1" LED should light up.</li>
+ <li>reset the board by pressing on the RESET button.</li>
+ <li>start the ST Flash loader demonstrator. Choose your serial port in the first screen, don't change the communication parameters (57600 8E1) and press "Next" 3 times.</li>
+ <li>select the "Download to device" radio button, then choose your <b>eLua</b> image file and hit "Next".</li>
+ <li>wait until programming is over and press "Finish".</li>
+ <li>press on the BOOT0 switch again.</li>
+ <li>reset the board by pressing the RESET button again.</li>
+ </ul>
+ <p>Now you have <b>eLua</b> installed on your board, and you can choose the same port you used for programming as a general purpose serial port for <b>eLua</b>.
+ </p>
+</body></html>
Added: branches/eagle_mmc/doc/en/installing_str7.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_str7.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_str7.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,21 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<meta http-equiv="Content-Language" content="en-us"><title> Installing eLua on STR7 CPUs</title>
+ <h3>Installing <b>eLua</b> on the STR7 CPU family from ST</h3>
+ <p><a target="_blank" href="http://www.st.com/mcu/inchtml-pages-str7.html">STR7</a> is a family of ATM7TDMI based CPUs from <a target="_blank" href="http://www.st.com">ST</a>. They are small, low power MCUs, with a well balanced set of on-chip peripherals. I'm using the <a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711</a> header board from <a target="_blank" href="http://www.sctec.com.br">ScTec</a>. The board is
+based on this STR711FR2 variant of the STR7 family. Since this is not a full-fledged development board, I had to add a few things around it: a MAX3232 RS232 to TTL converter for the serial interface, a couple of LEDs and a reset button. After that, the board was ready for some <b>eLua</b> :) </p>
+ <h3>Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the STR711FR2 CPU, make sure that:</p>
+ <ul>
+ <li>you're using Linux, Windows, or any other OS that has support for <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a>. You might have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
+ <li>you already have your <b>eLua</b> image for the STR711FR2 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
+ </ul>
+ <h3>Burning <b>eLua</b> to the MOD711 board</h3>
+ <p>You need OpenOCD to do this. Just follow the instructions from my <a href="tut_openocd.html">OpenOCD tutorial </a>. On the tutorial page you'll also find links to the OpenOCD
+ configuration files that I'm using for burning <b>eLua</b> to the MOD711 board. And that's it! <b>eLua</b> is now programmed in the CPU, so you can start your terminal emulator and enjoy it, as described in <a href="using.html">using eLua</a>.</p>
+<p><b>IMPORTANT NOTE</b>: for this board you need to set your COM port speed to 38400 baud (as opposed to 115200 baud for the other boards). All the other parameters are the same (8 data bits,
+ no parity, one stop bit).</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/installing_str9.html
===================================================================
--- branches/eagle_mmc/doc/en/installing_str9.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/installing_str9.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,29 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Installing eLua on STR9 CPUs</title>
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Installing <b>eLua</b> on the STR9 CPU family from ST</h3>
+ <p>Among the ARM based MCUs available today, the <a target="_blank" href="http://www.st.com/mcu/inchtml-pages-str9.html">STR9</a> CPUs from <a target="_blank" href="http://www.st.com">ST</a> stand up because of a few unique features.
+ First, their core is an ARM966-E, as opposed to the very popular ARM7TDMI core. This, together with some cleverly chosen on-chip hardware blocks, allows the CPU to run at 96MHz, which is very fast for a
+ general purpose MCU. The particular CPU I'm using (STR912FAW44) ) also has 512k of flash (and another bank of 32k flash) and 96k of internal RAM, so you won't be running out of memory anytime soon. It is accompanied by a very good support library,
+ and ST provides a lot of nice tools for STR9, including a graphical tool that you can use to configure the chip exactly how you want. When I wrote to ST about <b>eLua</b>, they
+ agreed to send me a <a target="_blank" href="http://www.hitex.com/str9-comstick/">STR9-comStick</a> board to run <b>eLua</b> on it. Thank you very much for your help, once again. This is the board that I'm going to
+ use through this tutorial.</p>
+ <h3>Prerequisites</h3>
+ <p>Before you'll be able to use <b>eLua</b> on the STR912FAW44 CPU, make sure that:</p>
+ <ul>
+ <li>you're using Linux, Windows, or any other OS that has support for <a target="_blank" href="http://openocd.berlios.de/web/">OpenOCD</a>. You might have a look at my <a href="tut_openocd.html">OpenOCD tutorial</a> before continuing.</li>
+ <li>if you're on Windows, you have installed the STR9-comStick support package from the accompanying CD.</li>
+ <li>you already have your <b>eLua</b> image for the STR912FAW44 CPU (<a href="building.html">built</a> or <a href="downloads.html">downloaded</a>).</li>
+ </ul>
+ <h3>Burning <b>eLua</b> to the STR9-comStick</h3>
+ <p>You need OpenOCD to do this. Just follow the instructions from my <a href="tut_openocd.html">OpenOCD tutorial </a>. On the tutorial page you'll also find links to the OpenOCD
+ configuration files that I'm using for burning <b>eLua</b> to the comstick.</p>
+ <p><b>IMPORTANT NOTE</b>: for some very strage reasons (probably related to the on-board USB to JTAG converter) my comstick does NOT start to execute the code from its internal flash after being
+ powered up via the USB cable (faulty reset sequence?). To overcome this, you'll find a special OpenOCD configuration file on my <a href="tut_openocd.html">OpenOCD tutorial</a> page. It is called <i>comrst.cfg</i>,
+ and you can use it to reset your comstick after it is powered up.</p>
+ <p>That's it! <b>eLua</b> is now programmed in the CPU, so you can start your terminal emulator and enjoy it, as described in <a href="using.html">using eLua</a>.
+</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/news.html
===================================================================
--- branches/eagle_mmc/doc/en/news.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/news.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -68,7 +68,7 @@
sections to come soon, including a tutorial on how to use eLua with
STR9 CPUs. Here's the changelog for the 0.3 version:</p>
-<ul><li>Now you can play hangman directly from eLua :), thanks to the new "term" module that handles ANSI escape sequences</li><li>Added support for ST STR912FW44</li><li>Added support for Cortex LM3S6965</li><li>More intuitive and flexible build system (new syntax, component selection at build time)</li><li>eLua examples are now part of the repository</li><li>Project documentation updated</li></ul>
+<ul><li>Now you can play hangman directly from eLua :), thanks to the new "term" module that handles ANSI escape sequences</li><li>Added support for ST STR912FAW44</li><li>Added support for Cortex LM3S6965</li><li>More intuitive and flexible build system (new syntax, component selection at build time)</li><li>eLua examples are now part of the repository</li><li>Project documentation updated</li></ul>
<h2>06 August 2008</h2>
@@ -135,4 +135,4 @@
<h2>05 July 2008</h2>
<p>The web page is up! For now you can only read the <a href="http://www.eluaproject.net/?p=Overview">project description</a>. Also, a tutorial about how to compile a GCC toolchain for the Cortex architecture is available <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">here</a>.</p>
</div>
-</body></html>
\ No newline at end of file
+</body></html>
Modified: branches/eagle_mmc/doc/en/overview.html
===================================================================
--- branches/eagle_mmc/doc/en/overview.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/overview.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,89 +6,120 @@
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
<a name="whatis"></a><h3>What is eLua ?</h3>
-<strong>eLua</strong>
+<p><strong>eLua</strong>
stands for <strong>Embedded Lua</strong> and the project
-aims to introduce the programming language <a href="http://www.lua.org/">Lua</a> to the embedded
-software development world. <br><br>
-<strong>Lua</strong> is the perfect example of a
+aims to offer the full set of features of the <a href="http://www.lua.org">Lua Programming Language</a> to the embedded world. </p><p><span style="font-weight: bold;">eLua</span>
+is not a stripped down set of Lua; much on the contrary, it strives to
+offer the same features as the desktop version of Lua, but complementing them with
+specific features for embedded use.
+Besides offering different flavors of the full Lua implementation
+(like the possiblity of choosing between an integer-only and a floating
+point numbers implementation),
+a lot of work was and will be done in the direction of making Lua
+more "embedded-friendly" by augmenting the core language with features
+that allow lower memory requirements.</p>
+<p>Lua is the perfect example of a
minimal, yet fully
functional language. Although generally advertised as a "scripting
language" (and used accordingly especially in the game industry), it is
also fully capable of running stand-alone programs. Its limited
resource requirements make it suitable to a lot of microcontroller
-families.
-The aim of the project is to have a fully functional Lua development
+families. The intrinsic high portability of the original Lua code
+(which is ANSI C and runs virtually on every platform for which an ANSI
+C compiler is available) combined with the highly portable software
+architecture of <b>eLua</b> allow for easy porting of the project to a large variety or architectures. The peripheral access libraries exported by <b>eLua</b> are also portable by design, so one could run a Lua program (without or with very few modifications) on every <span style="font-weight: bold;">eLua</span> supported platform (the <a href="status.html">project status & roadmap</a> shows a constantly growing list of platforms on which <b>eLua</b> is supported). <b>eLua</b> inherits the minimalistic and functional design of Lua, staying in line with the well known <b>KISS</b>, <i>Keep It Small and Simple</i> philosophy.</p>
+<p>The aim of the project is to have a fully functional Lua development
environment <strong>on the microcontroller itself</strong>,
-without the need to install a specific toolchain on the PC side.
+without the need to install a specific development environment on
+the PC side. This includes the ability to both edit and debug programs
+directly on target.
Initially, a PC will still be needed in order to edit the Lua programs
for the microcontroller. But as the project evolves this requirement
will be relaxed, as a basic editor (also residing on the
-microcontroller) will be usable with a variety of input/output devices.<br>
-<br>
-ARM microcontrollers were chosen for the first implementations given
-their popularity, availability and small cost. But support for other
-architectures is on the way. Please check the <a href="http://www.eluaproject.net/en/Status">Status Page</a>
-for updated info on supported platforms and features.<br>
-<br>
-<a name="audience"></a><br><h3>Audience</h3>
-eLua has a wide and varied audience, from highly skilled developers
+microcontroller) will be usable with a variety of input/output devices.</p>
+<p>We can't end this short presentation without presenting our project motto: No matter what you do with <b>eLua</b>, always remember to have fun with it :)</p>
+<a name="features"></a><h3>Features</h3>
+<p>As already stated, <b>eLua</b> allows you to run Lua completely on
+the
+target microcontroller. A fast-growing set of complementary modules is also
+provided, for programming <strong>eLua</strong>'s peripherals. </p>
+<p>The following important features are ready or being implemented:</p>
+<ul>
+<li>a flexible, configurable build system.</li>
+<li>access to the Lua interpreter on the target MCU via a variety of physical transports (RS-232 being the most popular).</li>
+<li>a (mostly) platform independent peripheral library (PIO,
+UART, PWM, SPI, TMR, ADC, NET, I2C...)</li>
+<li>a very low footprint embedded ROM file system, easy to port to different types of memory chips and other storage devices</li>
+<li>a small FAT R/W file system layer for SD cards</li>
+<li>an embedded editor, to edit Lua programs directly via a serial connection or other input devices</li>
+<li>a minimal "shell" (for file operations, environment configuration and other facilities)</li>
+<li>network support</li>
+<li>an embedded http server</li>
+<li>Terminal / Console over Ethernet</li>
+<li>debugging (directly on the MCU or remotely with the PC).
+</li></ul>
+<p>For more information about the functionality (implemented and planned) in <strong>eLua</strong> check <a href="status.html">the status page</a>.</p>
+<p>Porting <strong>eLua</strong> to another compatible platform should be as easy
+and
+painless as possible. Currently this is restricted to platforms for
+which the gcc+newlib combo is available. This restriction will disappear in the near future, as <b>eLua</b> will have its own libc and thus it will be available on a much
+broader range of MCUs.</p>
+<p>The Lua implementation comes in two flavors: "regular Lua"
+(using
+floating point as the number type) and "integer Lua" (using integers).
+"Regular Lua" will be able
+to perform floating point operations (but will be slower because the
+floating point operations will be emulated in software on the MCU),
+while "integer Lua" will only be able to perform operations with
+integer numbers (but support for fixed and even floating point can be
+added with separate modules) and thus will be faster.</p>
+<a name="audience"></a><h3>Audience</h3>
+<p><span style="font-weight: bold;">eLua</span> has a wide and varied audience, starting from newcomers to the embedded world who want an
+easy and powerful environment for prototyping, rapid application
+development and quick production, and ranging towards highly skilled developers
that want to extend their programs with the Lua library facilities and
-portable features, to the newcomer to the embedded world, who wants an
-easy and powerfull environment for prototyping, rapid application
-development, educational or final product quick production.<br><br>eLua
-allows new embedded world programmers to use the simplicity and
-powerfullness of the Lua programming language to hide low-level
-complexities and platform/architecture-dependent features. A whole new
-class of embedded programmers, with no deep knowledge of the peripheral
-details but with powerfull aplications in mind is now possible.<br><br>On
-the other edge of the category, oldtime and skilled embedded developers
-can port modules to new platforms, offering a degree of portability
-to the final user, never dreamed before on the embedded world.<br><br>eLua audience would be among the following categories:<br><ul><li>Embedded developers that are looking for a fast, easy to use and powerful way of coding.</li><li>First-time
+portable features.</p><p><span style="font-weight: bold;">eLua</span>
+allows embedded-oriented programmers to use the simplicity and
+power of the Lua programming language and to hide the low-level
+complexities and platform/architecture-dependent features. With <b>eLua</b>,
+the programmer can focus on the actual implementation of his program,
+without having to worry about accessing the low-level peripheral
+configuration and data registers, as the platform libraries already
+take care of this. This increases productivity and eliminates the often
+frustrating task of dealing with platform-specific drivers. </p>
+<p>The list below summarizes <b>eLua</b>'s target audience:<br></p><ul><li>Embedded developers that are looking for a fast, easy to use and powerful way of coding.</li><li>First-time
embedded programmers (or simply first time programmers) that are
looking for an easy way to "dive" into the embedded programming world.
eLua is a great learning tool.</li><li>People that aren't really
developers, but want to be able to prototype an embedded system
fast and painless, without having to learn C for that.</li><li>Embedded
-developers that need powerfull meta-language mecanisms for complex code
-algorithms and data description, not offered by the languages available
-to the embedded development world.</li><li>Field
-engineers that can go their customer site and debug an eLua module on
+developers who need powerful meta-language mechanisms for complex code
+algorithms and data description.</li><li>Field
+engineers that can go to their customer site and debug an eLua module on
site, without any preparation at all, since the whole development
-environment resides on chip already.</li></ul><br><a name="authors"></a>
+environment resides on chip already.</li></ul><a name="authors"></a>
<h3>Authors</h3>
-<p><strong>eLua</strong> is a joint project of <strong><a href="http://www.eluaproject.net/en/Contact">Bogdan Marinescu</a></strong>,
-a software developer from Bucharest (Romania) and <strong><a href="http://www.eluaproject.net/en/Contact">Dado Sutter</a></strong>,
+<p><strong>eLua</strong> is a joint project of <strong><a href="#contacts">Bogdan Marinescu</a></strong>,
+a software developer from Bucharest (Romania) and <strong><a href="#contacts">Dado Sutter</a></strong>,
head of the Led Lab at <a href="http://www.puc-rio.br/">PUC-Rio
University</a>, in Rio de Janeiro (Brazil). </p>
<p>Its origins come from the <a href="http://www.circuitcellar.com/renesas2005m16c/winners/1685.htm">ReVaLuaTe</a>
project also developed by Bogdan Marinescu (as a contest entry for the
2005 Renesas M16CDesign Contest), and the Volta Project, managed by
Dado Sutter at PUC-Rio from 2005 to 2007.</p>
-<p><strong>eLua</strong> is an Open Source and
-collaborative project and an always growing list of collaborators can
-be found in our <a href="http://www.eluaproject.net/en/Credits">Credits
-Page</a></p><p></p>
-<div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2"><tbody><tr><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>ReVaLuaTe Project</big></td><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>Volta Project</big></td></tr><tr><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="../wb_img/terminalreneseas.jpg"></td><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="../wb_img/volta-small.jpg"></td></tr></tbody></table><div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"!
></span><br><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><br><a name="contacts"></a>
+<p><strong>eLua</strong> is Open Source and an always growing list of collaborators can be found in our <a href="#credits">Credits Page</a></p>
+<div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2"><tbody><tr><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>ReVaLuaTe Project</big></td><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>Volta Project</big></td></tr><tr><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="../wb_img/terminalreneseas.jpg"></td><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="../wb_img/volta-small.jpg"></td></tr></tbody></table><div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"!
></span><br><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><a name="contacts"></a>
<h3>Contacts</h3>
-<p><strong>eLua</strong> authors can be contacted at:</p><p><strong>Bogdan Marinescu:</strong> bogdan dot marinescu at gmail dot com</p>
+<p><strong>eLua</strong> authors can be contacted at:</p><p><strong>Bogdan Marinescu:</strong> bogdan.marinescu -at- gmail.com</p>
-<p><strong>Dado Sutter:</strong> dadosutter at gmail dot com</p> <br> You are also welcome to share your questions and suggestions on our <a href="comunity.html#lists">Mail Discussion List</a>
-<p></p><a name="license"></a>
+<p><strong>Dado Sutter:</strong> dadosutter -at- gmail.com</p><p>You are also welcomed to share your questions and suggestions on our <a href="comunity.html#lists">Mail Discussion List</a></p>
+<a name="license"></a>
<h3>License</h3>
<div class="content">
<p><strong>eLua</strong> is Open Source and is freely
-distributed under the GPL (migrating to BSD soon) licence.</p>
-<p>The Lua code (with slight modifications) is included in the
-source
-tree and is, of course, licensed under the same MIT license that Lua
-uses.</p>
-<p>The terms of each of these licences can be viewed on their own
-pages at:</p>
-<p><a target="_top" href="http://en.wikipedia.org/wiki/GNU_General_Public_License">GPL
-Licence</a></p>
-<p><a target="_top" href="http://en.wikipedia.org/wiki/BSD_license#Terms">BSD
-Licence</a></p>
-<p><a target="_top" href="http://en.wikipedia.org/wiki/MIT_License">MIT
-Licence</a></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p><a href="http://en.wikipedia.org/wiki/MIT_License"></a></p>
+distributed under the MIT licence.</p>
+<p>The Lua code (with all the <b>eLua</b> specific changes) is included in the source tree and is, of course, licensed under the same <a href="http://en.wikipedia.org/wiki/MIT_License">MIT license that Lua uses.</p>
+<p>There may be other components with different licenses in <b>eLua</b>, see <b>COPYING</b> in the source distribution for details.</p>
+</a></p><br><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p>
</div>
-</body></html>
\ No newline at end of file
+</body></html>
Deleted: branches/eagle_mmc/doc/en/platdepmodules.html
===================================================================
--- branches/eagle_mmc/doc/en/platdepmodules.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/platdepmodules.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,17 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html><head>
-<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
-
-<link rel="stylesheet" type="text/css" href="../style.css">
-</head>
-<body style="background-color: rgb(255, 255, 255);">
-<h3><a name="over"></a>eLua Platform Dependent
-Modules</h3>
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-</body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/en/refman.html
===================================================================
--- branches/eagle_mmc/doc/en/refman.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/refman.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,751 +1,22 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>eLua reference manual</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
-<h3>eLua Modules Reference Manual
-</h3>
-<h3><a name="genericmodules"></a>Generic
-Modules</h3><br><h3><a name="bitmodule"></a>bit</h3>
-Bitwise operations in eLua is implemented thru
-the BitLib library, from Reuben Thomas.<br>
-BitLib project is hosted at LuaForge on
-http://luaforge.net/projects/bitlib<br>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bnot"></a>Res = bit.bnot( value )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-unary negation
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_band"></a> Res = bit.band( v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;"><b>bitwise
-</b>"and"
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bor"></a> Res = bit.bor( v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;"><span style="font-weight: bold;"> </span><b class="info" style="font-weight: bold;">bitwise</b><b class="info" style="font-weight: bold;">
-</b><span class="info" style="font-weight: bold;">"or"</span>
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bxor"></a> Res = bit.bxor( v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-<b>bitwise</b><b> </b>"exclusive or"
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_lshift"></a> Res = bit.lshift( value, pos )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-shift "value" left "pos" positions.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_rshift"></a> Res = bit.rshift( value, pos )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-shift "value" right "pos" positions. The sign is not propagated.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_arshift"></a> Res = bit.arshift( value, pos )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-shift "value" right "pos" positions. The sign is propagated
-("arithmetic shift").
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bit"></a> Res = bit.bit( bitno )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-a shortcut for bit.lshift( 1, bitno )
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_set"></a> Res1, Res2, ... = bit.set( bitno, v1,
-v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-set the bit at position "bitno" in v1, v2, ... to 1.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_clear"></a> Res1, Res2, ... = bit.clear( bitno,
-v1, v2, ... )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-set the bit at position "bitno"in v1, v2, ... to 0.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_isset"></a> Res = bit.isset( value, bitno )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-returns true if bit at position "bitno" in "value" is 1, false
-otherwise.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_isclear"></a> Res = bit.isclear( value, bitno )</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-returns true if bit at position "bitno" in "value" is 0, false
-otherwise.
-</p>
-<br style="font-family: Verdana;">
-<br style="font-family: Verdana;">
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-<br>
-<h3><a name="cpumodule"></a>cpu</h3>
-<p class="MsoNormal" style="font-family: Verdana;"><br>
-</p>
-<p style="margin-bottom: 0in;"> </p>
-<font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write32"></a>write32( address, data ) : write
-the 32-bit data at the specified address</font>
-<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write16"></a>write16( address, data ) : write
-the 16-bit data at the specified address</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write8"></a>write8( address, data ) : write the
-8-bit data at the specified address</font> <br>
-</p>
-<p style="margin-bottom: 0in;"><br>
-</p>
-<br>
-<font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read32"></a>Data = read32( address ) :
-reads 32-bit data from the specified address</font>
-<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read16"></a>Data = read16( address ) : reads
-16-bit data from the specified address</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read8"></a>Data = read8( address ) : reads 8-bit
-data from the specified address</font></p>
-<p style="margin-bottom: 0in;"><br>
-</p>
-<br>
-<p style="margin-bottom: 0in;"><a name="cpu_disableinterrupts"></a>
-[cpu.disableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">cli(): disable
-CPU interrupts</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"><a name="cpu_enableinterrupts"></a>
-[cpu.enableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">sei(): enable
-CPU interrupts</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_clockfrequency"></a>[cpu.clockfrequency()]
-Clock = clock(): returns the CPU frequency</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Also, you can
-expose as many CPU constants (for example memory mapped registers)</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">as you want to
-this module. You might want to use this feature to access some </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">CPU memory areas
-(as defined in the CPU header files from the CPU support </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">package)
-directly from Lua. To do this, you'll need to define the </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">PLATFORM_CPU_CONSTANTS
-macro in the platform's platform_conf.h file </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">(src/platform/<platform
-name>/platform_conf.h). Include all your constants in a </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-<constant name> ) definition, and then build your project.</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For example,
-let's suppose that your CPU's interrupt controler has 3 memory</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">mapped
-registers: INT_REG_ENABLE, INT_REG_DISABLE and INT_REG_MASK. If you want</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">to access them
-from Lua, locate the header that defines the values of these</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">registers (I'll
-assume its name is "cpu.h") and add these lines to the</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform_conf.h:</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#include "cpu.h"</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#define
-PLATFORM_CPU_CONSTANTS\</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-INT_REG_ENABLE ),\</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-INT_REG_DISABLE ),\</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C( INT_REG_MASK
-)</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">After this
-you'll be able to access the regs directly from Lua, like this:</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">data = cpu.r32(
-cpu.INT_REG_ENABLE )</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">cpu.w32(
-cpu.INT_REG_ENABLE, data )</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For a
-"real-life" example, see the src/platform/lm3s/platform_conf.h file.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[uart.sendstring]
-uart.sendstr( id, str1, str2, ... ): this is similar to "uart.send",
-but its parameters are string. </font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> </p>
-<h3><a name="gpiomodule">gpio</a></h3>
-<p class="MsoNormal" style="font-family: Verdana;">
-<b>[gpio] pio</b><br>
-</p>
-<br>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinvalue"></a> [gpio.setpinvalue] pio.setpin(
-value, Pin1, Pin2 ... ): set the value to all the pins in the list
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- to "value" (0 or 1).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinhigh"></a> [gpio.setpinhigh] pio.set(
-Pin1, Pin2, ... ): set the value of all the pins in the list to 1.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getpinvalue"></a> [gpio.getpinvalue] Val1, Val2,
-... = pio.get( Pin1, Pin2, ... ): reads one or more pins and returns
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- their values (0 or 1).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinlow"></a> [gpio.setpinlow] pio.clear(
-Pin1, Pin2, ... ): set the value of all the pins in the list to 0.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_configpin"></a> [gpio.configpin(gpio.DIR,
-gpio.DIR_INPUT)] pio.input( Pin1, Pin2, ... ): set the specified pin(s)
-as input(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[gpio.configpin(gpio.DIR, gpio.DIR_OUTPUT)] pio.output( Pin1, Pin2, ...
-): set the specified pin(s) as output(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setportvalue"></a> [gpio.setportvalue]
-pio.setport( value, Port1, Port2, ... ): set the value of all the ports
-in the
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- list to "value".
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getportvalue"></a> [gpio.getportvalue] Val1,
-Val2, ... = pio.getport( Port1, Port2, ... ): reads one or more ports
-and
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
- returns their values.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getportname"></a> [gpio.getportname]
-Port = pio.port( code ): return the physical port number associated
-with the given code. For example, "pio.port( pio.P0_20 )" will return
-0.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getpinnumber"></a> [gpio.getpinnumber] Pin =
-pio.pin( code ): return the physical pin number associated with the
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-given code. For example, "pio.pin( pio.P0_20 )" will return 20.
-</p>
-<br>
-<a name="gpio_togglepin"></a>[gpio.togglepin([Pin1],
-[Pin2], ...)]<br>
-<br>
-<a name="gpio_toogleport"></a>[gpio.toggleport([Port1],
-[Port2], ...)]<br style="font-family: Verdana;">
-<br>
-Another idea (can be added to the above ?)<br>
-[gpio.configport(gpio.[FUNCTION], gpio.MASK, [MASK])]<br>
-Ex:<br>
- gpio.configpin(gpio.DIR,
-gpio.DIR_INPUT) (.DIR_OUTPUT)<br>
- gpio.configpin(gpio.PULL,
-gpio.PULL_UP) (.PULL_DOWN,
-PULL_NO)<br style="font-family: Verdana;">
-<br>
-<p class="MsoNormal" style="font-family: Verdana;">
-[gpio.configport(gpio.DIR, gpio.DIR_INPUT, [Port1], [Port2], ...)]
-pio.port_input( Port1, Port2, ... ): set the specified port(s) as
-input(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[gpio.configport(gpio.DIR, gpio.DIR_OUTPUT, [Port1], [Port2], ...)]
-pio.port_output( Port1, Port2, ... ): set the specified port(s) as
-output(s).
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[gpio.configpin(gpio.PULL, gpio.PULL_UP, [Pin1], [Pin2], ...)]
-pio.pullup( Pin1, Pin2, ... ): enable internal pullups on the specified
-pins.Note that some CPUs might not provide this feature.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[gpio.configpin(gpio.PULL, gpio.PULL_DOWN, [Pin1], [Pin2], ...)]
-pio.pulldown( Pin1, Pin2, ... ): enable internal pulldowns on the
-specified pins. Note that some CPUs might not provide this feature.
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-
-</p>
-<p class="MsoNormal" style="font-family: Verdana;">
-[gpio.configpin(gpio.PULL, gpio.PULL_NO, [Pin1], [Pin2], ...)]
-pio.nopull( Pin1, Pin2, ... ): disable the pullups/pulldowns on the
-specifiedpins. Note that some CPUs might not provide this feature.
-</p>
-<br>
-<h3><a name="netmodule"></a>net</h3>
-<br>
-<h3><a name="pwmmodule"></a>pwm</h3>
-<span style="font-weight: bold;"></span><br>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
-use the PWM blocks on the target CPU.</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><strike><a name="pwm_setup"></a>[pwm.setup]</strike>(</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.setup( id,
-frequency, Active Cycle ) </font><font face="Bitstream Vera Sans Mono, sans-serif">
-Data = pwm.setup( id, frequency, duty ): sets the PWM block 'id' to
-generate the specified frequency with the specified duty cycle (duty is
-an integer number from 0 to 100, specifying the duty cycle in
-percents). It returns the actual frequency set on the PWM block.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> Here there is a bigger
-change on the proposal.
-</p>
-<p style="margin-bottom: 0in;"> The Timer Clock and the
-PWM "frame" frequency would be set up in the same function (.setup)
-</p>
-<p style="margin-bottom: 0in;"> The normal control
-function would only set the active cicle (.setcycle)
-</p>
-<p style="margin-bottom: 0in;"> The original .setup
-function would then be replaced by:
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[pwm.setup( id,
-tmrclock, pwm_frequency )</font> ]<br>
-</p>
-<p style="margin-bottom: 0in;"> <a name="pwm_setcycle"></a>[pwm.setcycle(
-id, active_cycle )]</p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_start"></a>[pwm.start()]
-pwm.start( id ): start the PWM block 'id'.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_stop"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop()]
-</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop(
-id ): stop the PWM block 'id'.</font>
-</p>
-<br>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_setclock"></a>Data = pwm.setclock( id, clock ):
-set the base clock of the PWM block 'id' to</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the given clock.
-In returns the actual clock set on the PWM block.</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[</font><font face="Bitstream Vera Sans Mono, sans-serif"><strike>pwm.getclock</strike>]
-</font><font face="Bitstream Vera Sans Mono, sans-serif">Data
-= pwm.getclock( id ): returns the base clock of the PWM block 'id'.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<h3><a name="spimodule"></a>spi</h3>
-<span style="font-weight: bold;"></span><br>
-<big><span style="font-family: Helvetica,Arial,sans-serif;"></span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_setup"></a>Actual_clock = spi.setup( id,
-spi.MASTER | spi.SLAVE, clock, cpol, cpha,</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>databits):
-set the SPI interface with the given parameters, returns the clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>that
-was set for the interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
-
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_select"></a>spi.select(
-</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>
-): sets the selected spi as active (sets the SS line of the given
-interface).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_unselect"></a>spi.unselect(
-id ): clears the SS line of the given interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_send"></a>spi.send(
-id, Data1, Data2, ... ): sends all the data to the specified SPI</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<span style="font-family: Helvetica,Arial,sans-serif;">
-
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_sendrecv"></a>[</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>spi.sendrecv(</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id,
-Out1, Out2, ...</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>)]
-</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>In1,
-In2, ... = spi.send_recv( id, Out1, Out2, ... ): sends all the "out"
-bytes</big></font><span style="font-family: Helvetica,Arial,sans-serif;"> </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>to
-the specified SPI interface and returts the data read after each sent
-byte.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Returning
-several values in this blocking way would not complicate some queued
-send implementations ? (ok, this could be another function :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
-</span><br style="font-family: Helvetica,Arial,sans-serif;">
-<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Sending multiple data/chars in a single
-call and not in
-a table argument does not allow the data to be built in run time
-(without some string massage, of course :)</big></font><br>
-<br>
-<br>
-<br>
-</big>
-<h3><a name="sysmodule"></a>sys</h3>
-<br>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_platform"></a>[sys.platform()]
-pd.platform(): returns the platform name (f.e. LM3S)</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_mcu"></a>[sys.mcu()]
-pd.cpu(): returns the CPU name (f.e. LM3S8962)</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_cpu"></a>[sys.cpu()]
-would return ARM Cortex M3 in this case.....</font></p>
-<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<font face="Bitstream Vera Sans Mono, sans-serif"> <a name="sys_board"></a>[sys.board()]</font><font face="Bitstream Vera Sans Mono, sans-serif">
-pd.board(): returns the CPU board (f.e. EK-LM3S8962)</font>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<h3><a name="term_termmodule">term</a></h3>
- Terminal support
-<p> <a name="term_clear"></a>[term.clear]
-term.clrscr(): clear the screen </p>
-<p> <br>
-<a name="term_cleareol"></a>[term.cleareol]
-term.clreol(): clear from the current cursor position to the end of the
-line </p>
-<p> </p>
-<p><a name="term_moveto"></a> [term.moveto]
-term.gotoxy( x, y ): position the cursor at the given coordinates<br>
-</p>
-<br>
-<p><a name="term_moveup"></a> [term.moveup]
-term.up( delta ): move the cursor up "delta" lines </p>
-<p> </p>
-<p><a name="term_movedown"></a> [term.movedown]
-term.down( delta ): move the cursor down "delta" lines </p>
-<p> </p>
-<p><a name="term_moveleft"></a> [term.moveleft]
-term.left( delta ): move the cursor left "delta" lines </p>
-<p> <br>
-<a name="term_moveright"></a>[term.moveright] term.right(
-delta ): move the cursor right "delta" lines </p>
-<p> </p>
-<p><a name="term_getlinecount"></a>
-[term.getlinecount] Lines = term.lines(): returns the number of lines </p>
-<p> </p>
-<p><a name="term_getcolcount"></a>
-[term.getcolcount] Cols = term.cols(): returns the number of columns </p>
-<p> </p>
-<br>
-<p><a name="term_printstr"></a> [term.printstr]
-term.putstr( s1, s2, ... ): writes the specified string(s) to the
-terminal<br>
-</p>
-<p> </p>
-<p> [term.printchar] term.put( c1, c2, ... ): writes the
-specified character(s) to the terminal </p>
-<p> </p>
-<p><a name="term_getx"></a> [term.getx] Cx =
-term.cursorx(): return the cursor X position </p>
-<p> </p>
-<p> <a name="term_gety"></a>[term.gety] Cy =
-term.cursory(): return the cursor Y position </p>
-<p> </p>
-<p> <font size="2"><a name="term_inputchar"></a>[term.inputchar]
-c = term.getch( term.WAIT | term.NOWAIT ): returns a char read from the
-</font> </p>
-<font size="2"> terminal.</font>
-<br style="font-family: Verdana;">
-<br>
-<br>
-<h3><a name="tmr_tmrmodule"></a>tmr</h3>
-<span style="font-weight: bold;"></span><big><br>
-</big>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
-execute timer specific operations (delay, read timer value,</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">start timer, get
-time difference).</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_delay"></a>tmr.delay( id, delay ): uses timer
-'id' to wait for 'delay' us.</font>
-</p>
-<p style="margin-bottom: 0in;"> <br>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-style: italic;"><a name="tmr_read"></a></span>Data
-= tmr.read( id ): reads the value of timer 'id'. The returned value is </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform
-dependent.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-style: italic;"><a name="tmr_start"></a></span>Data
-= tmr.start( id ): start the timer 'id', and also returns its value at</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the moment of
-start. The returned value is platform dependent.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_diff"></a>diff
-= tmr.diff( id, end, start ): returns the time difference (in us)
-between</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the timer values
-'end' and 'start' (obtained from calling tmr.start or</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">tmr.read). The
-order of end/start is irrelevant. </font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_mindelay"></a>Data = tmr.mindelay( id ): returns
-the minimum delay (in us ) that can be </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">achieved by
-calling the tmr.delay function. If the return value is 0, the </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform layer
-is capable of executing sub-microsecond delays.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_maxdelay"></a>Data = tmr.maxdelay( id ): returns
-the maximum delay (in us) that can be</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">achieved by
-calling the tmr.delay function.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_setclock"></a>Data = tmr.setclock( id, clock ):
-sets the clock of the given timer. Returns the</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">actual clock set
-for the timer.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_getclock"></a>Data = tmr.getclock( id ): return
-the clock of the given timer.</font>
-</p>
-<br>
-<br>
-<br>
-<br>
-<br>
-<h3><a name="uartmodule"></a>uart</h3>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_setup"></a>[uart.setup(</font><font face="Bitstream Vera Sans Mono, sans-serif"> id, baud,
-databits, </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.PARITY_EVEN
-|uart.</font><font face="Bitstream Vera Sans Mono, sans-serif">PARITY</font><font face="Bitstream Vera Sans Mono, sans-serif">_ODD | uart.</font><font face="Bitstream Vera Sans Mono, sans-serif">PARITY</font><font face="Bitstream Vera Sans Mono, sans-serif">_NONE, </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.STOPBITS_1
-| uart.STOPBITS_1_5 | uart.STOPBITS_2
-)] Actual_baud = uart.setup(
-id, baud, databits, </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.PAR_EVEN
-|uart.PAR_ODD | uart.PAR_NONE, </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.STOP_1 |
-uart.STOP_1_5 | uart.STOP_2 ): set the UART interface with the</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">given
-parameters, returns the baud rate that was set for the UART.</font>
-</p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_send"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">uart.send] </font><font face="Bitstream Vera Sans Mono, sans-serif">uart.send( id,
-Data1, Data2, ... ): send all the data to the specified UART interface.</font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#### Data 1 only
-!?!!<br>
-</font></p>
-<p style="margin-bottom: 0in;">
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
-</font></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_recv"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">uart.recv(</font><font face="Bitstream Vera Sans Mono, sans-serif"> id,
-uart.TIMEOUT_NO | <strike>uart.TIMEOUT_INFINITE</strike> |
-timeout )</font><font face="Bitstream Vera Sans Mono, sans-serif">
- </font><font face="Bitstream Vera Sans Mono, sans-serif">Data =
-uart.recv( id, uart.NO_TIMEOUT | uart.INF_TIMEOUT | timeout ): reads a </font>
-</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">byte from the
-specified UART interface.</font></p>
-<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;">
-</p>
-<h3><a name="platdepmodules"></a>eLua Platform
-Dependent
-Modules</h3><h3><a name="adcmodule"></a>adc</h3>Currently runs on: LM3S <br><br><a name="adc_sample"></a>adc.sample(channel_id) - generate one processed sample<br><br><a name="adc_getsamples"></a>adc.getsamples(channel_id,
-count) - request (count) samples from the buffer. if singular, an
-integer is returned. if multiple, a table of integers is returned. If
-count is either zero or omitted, all available samples are returned.<br><br><a name="adc_maxval"></a>adc.maxval(channel_id) - returns largest integer one can expect for this channel on a given platform (based on bit depth)<br><br><a name="adc_samplesready"></a>adc.samplesready(channel_id) - returns number of samples waiting in the buffer<br><br><a name="adc_dataready"></a>adc.dataready(channel_id)
-- if running in non-blocking mode, this will indicate if all of the
-samples requested from the last sample or <br>burst have been acquired and
-are waiting in the buffer<br><br><a name="adc_setmode"></a>adc.setmode(channel_id,
-mode) - mode: 0 sets mode to blocking (getsamples will wait for
-requested samples to be captured before returning), 1 sets non-blocking<br><br><a name="adc_setsmoothing"></a>adc.setsmoothing(channel_id, length) - set the length of the smoothing filter, this must be a power of 2 (maximum = 128)<br><br><a name="adc_getsmoothing"></a>adc.getsmoothing(channel_id) - get the current smoothing length in use<br><br><a name="adc_burst"></a>adc.burst(
-channel_id, count, timer_id, frequency) - request that (count) samples
-(must be greater than zero and a power of 2) be converted from
-(channel_id), using (timer_id) at (frequency)<br><br>
-<h3><a name="dispmodule"></a>disp</h3>
-<span style="font-weight: bold;"></span>Currently runs on: LM3S <br>
-<p class="MsoNormal"><a name="disp_init"></a>
-disp.init </p>
-<p class="MsoNormal"> <br>
-</p>
-<p class="MsoNormal"><a name="disp_enable"></a>
-disp.enable </p>
-<p class="MsoNormal"> <br>
-</p>
-<p class="MsoNormal"><a name="disp_disable"></a>
-disp.disable </p>
-<p class="MsoNormal"> <br>
-</p>
-<p class="MsoNormal"> <a name="disp_on"></a>disp.on
-</p>
-<p class="MsoNormal"> <br>
-</p>
-<p class="MsoNormal"><a name="disp_off"></a>
-disp.off<br>
-</p>
-<p class="MsoNormal" style="color: rgb(0, 0, 255);">
-<br>
-</p>
- <a name="disp_print"></a>disp.print<br>
-<br>
-<p class="MsoNormal"><a name="disp_draw"></a>
-disp.draw </p>
-</body></html>
\ No newline at end of file
+<h3>The reference manual</h3>
+<p>The <b>eLua</b> reference manual presents in details all the modules that can be used from a Lua program running inside <b>eLua</b>. It doesn't cover the
+standard Lua libraries, as the <a target="_blank" href="http://www.lua.org/manual/5.1/">Lua reference manual</a> already does a very good job at this.
+Instead, it covers <b>eLua</b>-specific modules (most of which are linked with the <a href="arch_platform.html">platform interface</a>) and some generic
+"3rd party" modules that are included in <b>eLua</b> by default. There are two types of modules in <b>eLua</b>, both of which are presented
+in this section:
+<ul>
+ <li><b>generic modules</b>: they are available on all platforms and should behave the same on all platforms.</li>
+ <li><b>platform-depedent modules</b>: they can be found only on specific platforms. Using them sacrifices portability, but gives access to platform
+ internals that aren't covered by the generic modules (for example specific hardware features).</b>
+</ul></p>
+<p>Remember that in order to use a module (generic or not) in <b>eLua</b> you must first include it in your <b>eLua</b> binary image, check
+<a href="building.html#confmodules">here</a> for instructions on how to do this.</p>
+<p>
+</body></html>
Added: branches/eagle_mmc/doc/en/refman_gen.html
===================================================================
--- branches/eagle_mmc/doc/en/refman_gen.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/refman_gen.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,11 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>eLua reference manual - generic modules</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Reference manual - generic modules</h3>
+<p>This part of the reference manual presents the generic modules in <b>eLua</b> (see <a href="refman.html">here</a> for more information about generic
+modules).</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/status.html
===================================================================
--- branches/eagle_mmc/doc/en/status.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/status.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -5,285 +5,547 @@
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
-<h3>Current Project Status</h3><p>As already stated, eLua allows you to run Lua completely on the
-microcontroller. A fast-growing set of complementary modules is also
-provided, with Lua code for using eLua generic peripherals. </p>
+<a name="platforms"></a><h3>eLua platforms and modules status</h3>
+<p>The current status of <b>eLua</b> is given by the list of the
+currently supported platforms, together with a list of
+modules-per-platform and their development phase. For better
+formatting, the lists are organized as tables that use the graphical
+notation given below:
+</p><table style="width: 325px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: center;">Symbol</th>
+<th style="text-align: center;">Meaning</th>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: left;">Implemented and tested</td>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: left;">Implemented, not tested</td>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: left;">Not yet implemented</td>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: left;">Not applicable</td>
+</tr>
+</tbody>
+</table>
+<br>
+<p>The list of CPUs/boards currently supported by <b>eLua</b> is given below:
+</p><table style="text-align: left; width: 620px;" class="table_center">
+<tbody>
+<tr>
+ <th style="text-align: left;">CPU</th>
+ <th style="text-align: center;">Architecture</th>
+ <th style="text-align: center;">Platform name</th>
+ <th style="text-align: center;">Supported boards</th>
+ <th style="text-align: center;">Status</th>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.luminarymicro.com/products/LM3S8962.html">LM3S8962</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">lm3s</td>
+ <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">EKx-LM3S8962</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965.html">LM3S6965</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">lm3s</td>
+ <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html">EKx-LM3S6965</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.luminarymicro.com/products/lm3s6918.html">LM3S6918</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">lm3s</td>
+ <td><a target="_blank" href="http://www.micromint.com/index.php/products/by-family/sbcs/77">Eagle 100</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=3755">AT91SAM7X256</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">at91sam7x</td>
+ <td><a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.atmel.com/dyn/products/Product_card.asp?part_id=4104">AT91SAM7X512</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">at91sam7x</td>
+ <td>None</td>
+ <td><img src="../wb_img/stat_not_tested.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.intel.com">i386 (generic)</a></td>
+ <td>x86</td>
+ <td style="color: rgb(255, 102, 0);">i386</td>
+ <td>PCs/emulators</td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR912FAW44-101.html">STR912FAW44</a></td>
+ <td>ARM966E-S</td>
+ <td style="color: rgb(255, 102, 0);">str9</td>
+ <td><a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.standardics.nxp.com/microcontrollers/to/pip/LPC2880FET180.html">LPC2888</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">lpc288x</td>
+ <td><a target="_blank" href="http://www.olimex.com/dev/lpc-h2888.html">LPC-H2888</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STR711FR2.html">STR711FR2</a></td>
+ <td>ARM7TDMI</td>
+ <td style="color: rgb(255, 102, 0);">str7</td>
+ <td><a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">MOD711</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.atmel.com/dyn/products/product_card.asp?part_id=4117">AT32UC3A0512</a></td>
+ <td>AVR32</td>
+ <td style="color: rgb(255, 102, 0);">avr32</td>
+ <td><a target="_blank" href="http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114">ATEVK1100</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://http://www.st.com/mcu/devicedocs-STM32F103ZE-110.html">STM32F103ZE</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">stm32</td>
+ <td><a target="_blank" href="http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html">STM3210E-EVAL</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+ <td><a target="_blank" href="http://www.st.com/mcu/devicedocs-STM32F103RE-110.html">STM32F103RE</a></td>
+ <td>Cortex-M3</td>
+ <td style="color: rgb(255, 102, 0);">stm32</td>
+ <td><a target="_blank" href="http://www.futurlec.com/ET-STM32_Stamp.shtml">ET-STM32 Stamp</a></td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+</tbody>
+</table>
+<br>
+<p>The following table shows a list of the generic modules currently implemented (and planned to be implemented) in <b>eLua</b>.
+</p><table style="text-align: left; width: 620px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Name</th>
+<th style="text-align: center;">Description</th>
+<th style="text-align: center;">Status</th>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">pio</td>
+<td>Programmable Input/Output</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">tmr</td>
+<td>timers</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">pwm</td>
+<td>Pulse Width Modulation</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">uart</td>
+<td>Universal Asynchronous Receiver Transmitter</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">spi</td>
+<td>Serial Peripheral Interface</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr><td style="color: rgb(255, 102, 0);">net</td>
+<td>TCP/IP networking</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">adc</td>
+<td>Analog to Digital Converter</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">cpu</td>
+<td>low level system access</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">pd</td>
+<td>platform data</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">term</td>
+<td>ANSI terminal access</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">bit</td>
+<td>bitwise operations</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">pack</td>
+<td>pack/unpack binary data</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">cmp</td>
+<td>analog comparator</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">i2c</td>
+<td>I2C bus access module</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">cnt</td>
+<td>event counter</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">can</td>
+<td>Controller Area Network</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+</tr>
+<td style="color: rgb(255, 102, 0);">rpc</td>
+<td>remote procedure call / remote control</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+</tr>
+</tbody>
+</table>
+<br>
+<p>The relationship between a module and its implementation on a particular platform is given in the next table.
+</p><table style="text-align: left; width: 620px;" class="table_center">
+<tbody>
+<tr>
+<th>Module</th>
+<th rowspan="2">pio</th>
+<th rowspan="2">spi</th>
+<th rowspan="2">uart</th>
+<th rowspan="2">tmr</th>
+<th rowspan="2">pwm</th>
+<th rowspan="2">net</th>
+<th rowspan="2">cpu</th>
+<th rowspan="2">adc</th>
+<th rowspan="2">pd</th>
+<th rowspan="2">term</th>
+<th rowspan="2">bit</th>
+<th rowspan="2">pack</th>
+<th rowspan="2">can</th>
+</tr>
+<tr><td style="color: rgb(255, 102, 0);">MCU</td>
+</tr><tr>
+<td style="color: rgb(255, 102, 0);">LM3S8962</td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Implemented" src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Not Tested" src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">LM3S6965</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">LM3S6918</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<p>The following modules are ready or being implemented:</p>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">i386</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<ul><li>a (mostly) platform independent peripheral library (I/O, UART, SPI, I2C...)</li><li>a very low footprint embedded flash file system, easy to port to different types of memory chips and other storage devices</li><li>a small FAT FS layer for SD cards.</li><li>an editor (to edit Lua programs directly via a serial connection or other input devices)</li><li>a minimal "shell" (for file operations, configuration and others)</li><li>network support</li></ul>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">AT91SAM7X256</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<p>Porting eLua to another compatible platform should be as easy and
-painless as possible. Currently this is restricted to platforms for
-which the gcc+newlib combo is available. This might change in the
-future, but please not that this is not a priority of the project at
-this point.</p>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">AT91SAM7X512</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<p>Also, the Lua "core" comes in two flavors: "regular Lua" (using
-floating point as the number type) and "integer Lua" (using "integers"
-as the number type). We'll add more about this in a future tutorial
-about Lua. For now, it's enough to say that "regular Lua" will be able
-to perform floating point operations (but will be slower because the
-floating point operations will be emulated in software on the MCU),
-while "integer Lua" will only be able to perform operations with
-integer numbers (but support for fixed and even floating point can be
-added with separate modules) and thus will be faster.</p>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">STR912FAW44</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<h2>Status of ports</h2>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">LPC2888</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">STR711FR2</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">AT32UC3A0512</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_applicable.png"></td>
-<p>You can see below the status of eLua implementation by platform/module. </p>
+</tr>
+<tr><td style="color: rgb(255, 102, 0);">##STM32F103ZE</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
-<p>Symbol list
-<br></p>
+</tr>
+<tr><td style="color: rgb(255, 102, 0);">##STM32F103RE</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
-<a name="platforms"></a><table class="table_center">
- <tbody><tr>
- <th>Symbol</th>
- <th><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></th>
- <th><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></th>
- <th><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></th>
- <th><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_fail1.png"></th>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">Meaning</td>
- <td>Implemented and tested</td>
- <td>Implemented, not tested</td>
- <td>Not yet implemented</td>
- <td>Not applicable</td>
- </tr>
-</tbody></table>
+</tr>
-<p><br></p>
+</tbody>
+</table>
+<br>
+<p>For some platforms, a number of platform dependent modules are
+implemented (or in the works) and are listed below. To understand the
+difference between generic modules and platform specific modules, check
+<a href="">##the eLua architecture page</a>.
+</p><table style="width: 620px;" class="table_center">
+<tbody>
+<tr>
+ <th style="text-align: left;">Name</th>
+ <th style="text-align: center;">Description</th>
+ <th style="text-align: center;">Boards</th>
+ <th style="text-align: center;">Status</th>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">disp</td>
+ <td>OLED display support</td>
+ <td>EKx-LM3S8962<br>EKx-LM3S6965</td>
+ <td><img src="../wb_img/stat_ok.png"></td>
+</tr>
+</tbody>
+</table>
-<p>eLua ports status</p>
+<h3><a name="roadmap"></a>Status of features and roadmap</h3>
+<p>The following table shows the status of some existing and planned <b>eLua</b> features.
+</p><table style="text-align: left; width: 620px;" class="table_center">
+<tbody><tr>
+<th style="text-align: left;">eLua Features</th>
+<th style="text-align: center;">Status</th>
+</tr>
+<tr>
+<td style="text-align: left;">Full Lua interpreter running on target</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td>Various Lua examples running properly</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Choose floating point or integer Lua</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">XMODEM transfer over UART</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Embedded ROM (Flash) file system</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Terminal / Console over UART or Ethernet</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua command shell</td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua complete interrupt support</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;"><a href="arch_ltr.html">eLua LTR (Lua Tiny RAM) patch</a></td>
+<td style="text-align: center;"><img src="../wb_img/stat_ok.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">FAT File System layer for mmc/sd cards</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_tested.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Minimal R/W file system</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua FP module (for integer Lua)</td>
+<td style="color: rgb(255, 102, 0); text-align: center;"><img src="../wb_img/stat_not_implemented.png">
+</td>
+</tr>
+<tr>
+<td style="text-align: left;">Embedded text editor</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Lua debugging (remote/on target)</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">GUI/IDE interface for eLua</td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">GUI eLua build configuration tool<br></td>
+<td style="text-align: center;"><img src="../wb_img/stat_not_implemented.png"></td>
+</tr>
+<tr>
+<td align="undefined" valign="undefined">Embedded HTTP web server</td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/stat_ok.png"></td></tr>
+</tbody>
+</table><br><br>
-<table class="table_center">
- <tbody><tr>
- <th>Module</th>
- <th rowspan="2">PIO</th>
- <th rowspan="2">SPI</th>
- <th rowspan="2">UART</th>
- <th rowspan="2">TMR</th>
- <th rowspan="2">PWM</th>
- <th rowspan="2">NET</th>
- <th rowspan="2">CPU</th>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">MCU</td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">LM3S8962</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">LM3S6965</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">i386</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_fail1.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_fail1.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_fail1.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_fail1.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">AT91SAM7X256</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">AT91SAM7X512</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">STR912FW44</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">LPC2888</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_fail1.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">STR711FR2</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">AVR32</td>
- <td colspan="7">Comming soon</td>
- </tr>
- <tr>
- <td style="color: rgb(255, 102, 0);">STM32</td>
- <td colspan="7">Comming soon</td>
- </tr>
-</tbody></table><br><br>
-<h3><a name="roadmap"></a>Project Roadmap</h3><h2>Status of features / roadmap</h2>
-
-<p>You can see below the status of the existent and planned eLua
-features. These are generic features (not platform dependent, so they
-should be available on any platform). The list is ordered by feature
-priority, with all the completed features at the top of the list. </p>
-
-<p>eLua features status</p>
-
-
-
- <table class="table_center"><tbody><tr>
- <th>Feature</th>
- <th>Status</th>
- </tr>
- <tr>
- <td>Lua interpreter running on target</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td style="padding-right: 25px; padding-left: 25px;">Various Lua test scripts running properly</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Choose floating point or integer Lua</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua PIO module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua UART module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua timer module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua platform data module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>XMODEM receive</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Embedded ROM file system</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua SPI module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/yellowled.png"></td>
- </tr>
- <tr>
- <td>eLua term module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>eLua shell</td>
- <td style="color: rgb(255, 102, 0);">Partially implemented and tested</td>
- </tr>
- <tr>
- <td>Lua PWM module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua I2C module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Lua ADC/DAC modules</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Lua interrupt support</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Lua bit operations module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua binary pack/unpack module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>eLua "memory limiting" mode</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Networking (LuaSocket or similar)</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>Lua CPU module</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/agt_action_success.png"></td>
- </tr>
- <tr>
- <td>FAT FS layer</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Embedded R/W file system</td>
- <td style="color: rgb(255, 102, 0);">Partially implemented and tested</td>
- </tr>
- <tr>
- <td>Lua FP module (for integer Lua)</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Embedded text editor</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>Lua debugging on target</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td>
- </tr>
- <tr>
- <td>eLua example programs</td>
- <td style="color: rgb(255, 102, 0); padding-right: 25px; padding-left: 25px;">Partially implemented and tested</td>
- </tr>
- <tr>
- <td>GUI interface for eLua</td>
- <td><img src="http://www.eluaproject.net/img/wiki_elua/ksame.png"></td></tr></tbody></table><br><br><br><br>
-</body></html>
\ No newline at end of file
+</body></html>
Modified: branches/eagle_mmc/doc/en/tc_386.html
===================================================================
--- branches/eagle_mmc/doc/en/tc_386.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tc_386.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,17 +1,15 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Building GCC for i386</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Building GCC for i386</a></h3>
-
- <div class="content">
-
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Building GCC for i386</h3>
<p>At first, the idea of an i386 "cross" compiler under Linux seems
strange. After all, you're already running Linux on a i386 compatible
architecture. But the compiler is sometimes tied in misterious ways
-with the operating system it's running on (see for example <a href="http://wiki.osdev.org/GCC_Cross-Compiler">this page</a>
+with the operating system it's running on (see for example <a htarget="_blank" ref="http://wiki.osdev.org/GCC_Cross-Compiler">this page</a>
for some possible symptoms). And after all, you want to use Newlib, not
libc, and to customize your development environment as much as
possible. This tutorial will show you how to do that.</p>
@@ -21,261 +19,111 @@
ways to accomplish what I'm describing here, however I just wanted a
quick and dirty way to build a toolchain, I have no intention in
becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Contact">contact me</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+did is wrong, innacurate, or simply outrageously ugly, feel free to
+<a href="overview.html#contacts">contact us</a> and I'll make the necessary corrections.
+And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
-<h2>› Prerequisites</h2>
+<h2>Prerequisites</h2>
<p>To build your toolchain you'll need:</p>
-<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
-will do as long as you know how to find the equivalent of "apt-get" for
-your distribution. I won't be going into details about this, google it
-and you'll sure find what you need. It is also assumed that the Linux
-system already has a "basic" native toolchain installed (gcc/make and
-related). This is true for Ubuntu after installation. Again, you might
-need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
-At the moment of writing this, the latest versions is 2.18, which for
-some weird reason refuses to compile on my system, so I'm using 2.17
-instead.</li><li>GCC: version 4.3.0 or newer is recommended. As
-I'm writing this, the latest GCC version is 4.3.1 which I'll be using
-for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib: as I'm writing this, the latest official Newlib version is 1.16.0. Download it from the <a href="ftp://sources.redhat.com/pub/newlib/index.html">Newlib FTP directory</a>.</li><li>Also,
-the tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul>
-
-
-<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo</th>
- </tr>
-</tbody></table>
-
-
+<ul>
+<li><b>GNU binutils</b>: as I'm writing this, the latest binutils version is 2.19.1, which
+I'll be using in this tutorial. get it from <a target="_blank" href="http://ftp.gnu.org/gnu/binutils/">here</a>.</li>
+<li><b>GCC</b>:as I'm writing this, the latest GCC version is
+4.3.3, which I'll be using for this tutorial. Download it from <a target="_blank" href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
+<li><b>Newlib</b>: as I'm writing this, the latest official Newlib version is 1.17.0, which I'll be using for this tutorial.
+Download it from <a target="_blank" href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
+<li>The tutorial assumes that you're using bash as your shell. If you use
+something else, you might need to adjust some shell-specific commands. </li></ul></p>
+<p>You need some support programs/libraries in order to compile the toolchain. To install them:</p>
+<p><pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre></p>
<p>Next, decide where you want to install your toolchain. They
-generally go in /usr/local/, so I'm going to assume
-/usr/local/cross-i686 for this tutorial. To save yourself some typing,
-set this path into a shell variable:</p>
+generally go in <i>/usr/local/</i>, so I'm going to assume
+<i>/usr/local/cross-i686</i> for this tutorial. To save yourself some
+typing, set this path into a shell variable:</p>
+<p><pre><code>$ export TOOLPATH=/usr/local/cross-i686</code></pre></p>
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ export TOOLPATH=/usr/local/cross-i686</th>
- </tr>
-</tbody></table>
-
-
<h2>› Step 1: binutils</h2>
<p>This is the easiest step: unpack, configure, build.</p>
-<p><br></p>
+<p><pre><code>$ tar -xvjf binutils-2.19.1.tar.bz2
+$ cd binutils-2.19.1
+$ mkdir build
+$ cd build
+$ ../configure --target=i686-elf --prefix=$TOOLPATH --with-gnu-as --with-gnu-ld --disable-nls
+$ make all
+$ sudo make install
+$ export PATH=${TOOLPATH}/bin:$PATH
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr>
- <th style="text-align: left;">$ tar -xvjf binutils-2.17.tar.bz2</th>
- </tr>
- <tr align="left">
- <th>$ cd binutils-2.17</th>
- </tr>
- <tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$ ../configure --target=i686-elf --prefix=$TOOLPATH --with-gnu-as --with-gnu-ld --disable-nls</th>
- </tr>
- <tr align="left">
- <th>$ make all</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
- <tr align="left">
- <th>$ export PATH=${TOOLPATH}/bin:$PATH</th>
- </tr>
-</tbody></table>
+<p>Now you have your i386 "binutils" (assembler, linker, disassembler ...) in your PATH. </p>
+<h2>Step 2: basic GCC</h2>
-
-
-<p>Now you have your i386 "binutils" (assembler, linker, disassembler ...) in your PATH.</p>
-<h2>› Step 2: basic GCC</h2>
-
<p>In this step we build a "basic" GCC (that is, a GCC without any
support libs, which we'll use in order to build all the libraries for
-our target). But first we need to make a slight modification in the
-configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
-compile properly, giving a very weird "Link tests are not allowed after
-GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
-solution for this:</p>
+our target). Let's compile it (and note that the install step is
+a bit different from Newlib's):</p?
-<p><br></p>
+<p><pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
+$ cd gcc-4.3.3
+$ mkdir build
+$ cd build
+$ ../configure --target=i686-elf --prefix=$TOOLPATH --enable-languages="c,c++" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld
+$ make all-gcc
+$ sudo -s -H
+# export PATH=/usr/local/cross-i686/bin:$PATH
+# make install-gcc
+# exit
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ tar -xvjf gcc-4.3.1.tar.bz2</th>
- </tr>
- <tr align="left">
- <th>$ cd gcc-4.3.1/libstdc++-v3</th>
- </tr>
- <tr align="left">
- <th>$ joe configure.ac</th>
- </tr>
-</tbody></table>
+<h2>Step 3: Newlib</h2>
-
-
-
-<p>I'm using "joe" here as it's my favourite Linux text mode editor,
-you can use any other text editor. Now find the line which says
-"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it: </p>
-
-<pre><code> # AC_LIBTOOL_DLOPEN<br></code></pre>
-
-<p>Save the modified file and exit the text editor</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ autoconf</th>
- </tr>
- <tr align="left">
- <th>$ cd ..</th>
- </tr>
-</tbody></table>
-
-
-
-<p>Great, now we know it will compile, so let's do it:</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=i686-elf --prefix=$TOOLPATH
---enable-languages="c,c++" --with-newlib --without-headers
---disable-shared --with-gnu-as --with-gnu-ld
-</th>
- </tr>
- <tr align="left">
- <th>$ make all-gcc</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install-gcc</th>
- </tr>
-</tbody></table>
-
-
-<p>On my system, the last line above (sudo make install-gcc) terminated
-with errors, because it was unable to find our newly compiled binutils.
-If this happens for any kind of "make install" command, this is a quick
-way to solve it:</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ sudo -s -H</th>
- </tr>
-</tbody></table>
-
-
-<pre><code> # export PATH=/usr/local/cross-i686/bin:$PATH<br> # make install-gcc<br> # exit<br></code></pre>
-
-
-<h2>› Step 3: Newlib</h2>
-
<p>Once again, Newlib is as easy as unpack, configure, build. But I
wanted my library to be as small as possible (as opposed to as fast as
possible) and I only wanted to keep what's needed from it in the final
executable, so I added the "-ffunction-sections -fdata-sections" flags
to allow the linker to perform dead code stripping:</p>
-<p><br></p>
+<p><pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
+$ cd newlib-1.17.0
+$ mkdir build
+$ cd build
+$ ../configure --target=i686-elf --prefix=$TOOLPATH --disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as --disable-shared
+$ make CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections -DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer -D__BUFSIZ__=256"
+$ sudo -s -H
+# export PATH=/usr/local/cross-i686/bin:$PATH
+# make install
+# exit
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ tar xvfz newlib-1.16.0.tar.gz</th>
- </tr>
- <tr align="left">
- <th>$ cd newlib-1.16.0</th>
- </tr>
- <tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=i686-elf --prefix=$TOOLPATH
---disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as
---disable-shared</th>
- </tr>
- <tr align="left">
- <th>$ make
-CFLAGS_FOR_TARGET="-ffunction-sections
--fdata-sections-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os
--fomit-frame-pointer -D__BUFSIZ__=256"</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
+<p>Some notes about the flags used in the above sequence:
+<ul>
+ <li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example
+ <a target="_blank" href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li>
+ <li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li>
+ <li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li>
+ <li><code>-D__BUFSIZ__=256</code>: again Newlib specific, this is the buffer size allocated by default for files opened via fopen(). The default is 1024, which I find too much
+ for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul></p>
+<h2>Step 4: full GCC</h2>
-<p>Some notes about the flags used in the above sequence:</p>
-
-<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256:</code>
-again Newlib specific, this is the buffer size allocated by default for
-files opened via fopen(). The default is 1024, which I find too much
-for an eLua, so I'm using 256 here. Of course, you can change this
-value.</li></ul>
-
-
-<h2>› Step 4: full GCC</h2>
-
<p>Finally, in the last step of our tutorial, we complete the GCC
build. In this stage, a number of compiler support libraries are built
(most notably libgcc.a). Fortunately this is simpler that the Newlib
compilation step:</p>
+<p><pre><code>$ cd gcc-4.3.3/build
+$ make all
+$ sudo make install
+</code></pre></p>
-<p><br></p>
+<h2>Step 5: all done!</h2>
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ cd gcc-4.3.1/build</th>
- </tr>
- <tr align="left">
- <th>$ make all</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
-
-
-
-
-<h2>› Step 5: all done!</h2>
-
-<p>Now you can finally enjoy your i386 toolchain, and compile eLua with
-it :) After you do, you'll be able to boot eLua directly on your PC, as
-described <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Booting_your_PC_in_eLua">here</a>, but you won't need to download the ELF file from the eLua project page, since you just generated it using your own toolchain!
-If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Contact">contact me</a>.</p>
-</div></body></html>
\ No newline at end of file
+<p>Now you can finally enjoy your i386 toolchain, and compile <b>eLua</b> with
+it :) After you do, you'll be able to boot <b>eLua</b> directly on your PC, as
+described <a href="tut_bootpc.html">here</a>, but you won't need to download the ELF file from the <b>eLua</b> project page, since you just generated it using your own toolchain!
+If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="overview.html#contacts">contact us</a>.</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/tc_arm.html
===================================================================
--- branches/eagle_mmc/doc/en/tc_arm.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tc_arm.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,233 +1,95 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Building GCC for ARM</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_ARM" class="local">Building GCC for ARM</a></h3>
-
- <div class="content">
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Building GCC for ARM</h3>
<p> This tutorial explains how you can create a GCC+Newlib toolchain
that can be used to compile programs for the ARM architecture, thus
making it possible to compile programs for the large number of ARM CPUs
out there. You'll need such a toolchain if you want to compile eLua for
-ARM CPUs. This tutorial is similar to many others you'll find on the
-Internet (particulary the one from <a href="http://www.gnuarm.com/">gnuarm</a>, on which it's based), but it's a bit more detailed and shows some "tricks" you can use when compiling Newlib.</p>
+ARM CPUs. Please note that you can also use a
+pre-built toolchain to compile <b>eLua</b> (see <a href="toolchains.html">toolchains</a> for details) so building
+one yourself is not strictly required. This tutorial is similar to many others you'll find on the
+Internet (particulary the one from <a target="_blank" href="http://www.gnuarm.com/">gnuarm</a>, on which it's based), but it's a bit more detailed and shows some "tricks"
+(specifying parameters at compile time) you can use when compiling Newlib.</p>
<p><strong>DISCLAIMER: I'm by no means a specialist in the
GCC/newlib/binutils compilation process. I'm sure that there are better
ways to accomplish what I'm describing here, however I just wanted a
quick and dirty way to build a toolchain, I have no intention in
becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.eluaproject.net/en/Contact">contact me</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="overview.html#contacts">contact us</a> and
+I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
<h2>Prerequisites</h2>
<p>To build your toolchain you'll need:</p>
-<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
+<ul>
+<li><b>a computer running Linux</b>: I use Ubuntu, but any Linux
will do as long as you know how to find the equivalent of "apt-get" for
your distribution. I won't be going into details about this, google it
and you'll sure find what you need. It is also assumed that the Linux
system already has a "basic" native toolchain installed (gcc/make and
related).This is true for Ubuntu after installation. Again, you might
-need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
-At the moment of writing this, the latest versions is 2.18, which for
-some weird reason refuses to compile on my system, so I'm using 2.17
-instead.</li><li>GCC: version 4.3.0 or newer is recommended. As
-I'm writing this, the latest GCC version is 4.3.1 which I'll be using
-for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib: as I'm writing this, the latest official Newlib version is 1.16.0. Download it from the <a href="ftp://sources.redhat.com/pub/newlib/index.html">Newlib FTP directory</a>.</li><li>Also,
-the tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul>
-
-
-<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo</th>
- </tr>
-</tbody></table>
-
-
+need to check your specific distribution.</li>
+<li><b>GNU binutils</b>: get it from <a target="_blank" href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+At the moment of writing this, the latest versions is 2.19.1, but it refuses to compile for ARM. Same goes for
+2.19. In fact, the only newer version of Binutils that seems to work properly is
+2.19.50, it can be downloaded from <a target="_blank" href="ftp://sourceware.org/pub/binutils/snapshots/">here</a>.
+This is the version that we are going to use in this tutorial.</li>
+<li><b>GCC</b>:as I'm writing this, the latest GCC version is
+4.3.3, which I'll be using for this tutorial. Download it from <a target="_blank" href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
+<li><b>Newlib</b>: as I'm writing this, the latest official Newlib version is 1.17.0, which I'll be using for this tutorial.
+Download it from <a target="_blank" href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
+<li>The tutorial assumes that you're using bash as your shell. If you use
+something else, you might need to adjust some shell-specific commands. </li></ul></p>
+<p>You need some support programs/libraries in order to compile the toolchain. To install them:</p>
+<p><pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre></p>
<p>Next, decide where you want to install your toolchain. They
-generally go in /usr/local/, so I'm going to assume
-/usr/local/cross-arm for this tutorial. To save yourself some typing,
-set this path into a shell variable:</p>
+generally go in <i>/usr/local/</i>, so I'm going to assume
+<i>/usr/local/cross-arm</i> for this tutorial. To save yourself some
+typing, set this path into a shell variable:</p>
+<p><pre><code>$ export TOOLPATH=/usr/local/cross-arm</code></pre></p>
-<p><br></p>
+<h2>Step 1: binutils</h2>
-<table class="table_cod">
- <tbody><tr>
- <th>$ export TOOLPATH=/usr/local/cross-arm</th>
- </tr>
-</tbody></table>
-
-
-<h2>› Step 1: binutils</h2>
<p>This is the easiest step: unpack, configure, build.</p>
-<p><br></p>
+<p><pre><code>$ tar -xvjf binutils-2.19.50.tar.bz2
+$ cd binutils-2.19.50
+$ mkdir build
+$ cd build
+$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls
+$ make all
+$ sudo make install
+$ export PATH=${TOOLPATH}/bin:$PATH
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr>
- <th>$ tar -xvjf binutils-2.17.tar.bz2</th>
- </tr>
-</tbody></table>
+<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH. </p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ cd binutils-2.17</th>
- </tr>
-</tbody></table>
-
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ mkdir build</th>
- </tr>
-</tbody></table>
-
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ cd build</th>
- </tr>
-</tbody></table>
-
-
-<table class="table_cod">
- <tbody><tr>
- <th style="text-align: left;">$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --enable-multilib--with-gnu-as --with-gnu-ld --disable-nls</th>
- </tr>
-</tbody></table>
-
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ make all</th>
- </tr>
-</tbody></table>
-
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
-
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ export PATH=${TOOLPATH}/bin:$PATH</th>
- </tr>
-</tbody></table>
-
-
-<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH.</p>
-
<h2>Step 2: basic GCC</h2>
<p>In this step we build a "basic" GCC (that is, a GCC without any
support libs, which we'll use in order to build all the libraries for
-our target). But first we need to make a slight modification in the
-configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
-compile properly, giving a very weird "Link tests are not allowed after
-GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
-solution for this:</p>
+our target). Let's compile it (and note that the install step is
+a bit different from Newlib's):</p?
-<p><br></p>
+<p><pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
+$ cd gcc-4.3.3
+$ mkdir build
+$ cd build
+$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --enable-multilib --enable-languages="c,c++" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld
+$ make all-gcc
+$ sudo -s -H
+# export PATH=/usr/local/cross-arm/bin:$PATH
+# make install-gcc
+# exit
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr>
- <th>$ tar -xvjf gcc-4.3.1.tar.bz2</th>
- </tr>
- <tr>
- <th>$ cd gcc-4.3.1/libstdc++-v3</th>
- </tr>
- <tr>
- <th style="text-align: left;">$ joe configure.ac</th>
- </tr>
-</tbody></table>
-
-
-<p> I'm using "joe" here as it's my favourite Linux text mode editor,
-you can use any other text editor. Now find the line which says
-"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it:</p>
-
-<p><code># AC_LIBTOOL_DLOPEN</code></p>
-
-<p>Save the modified file and exit the text editor</p>
-
-<p><br> </p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ autoconf</th>
- </tr>
- <tr>
- <th style="text-align: left;">$ cd ..</th>
- </tr>
-</tbody></table>
-
-
-
-<p>Great, now we know it will compile, so let's do it:</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
---enable-multilib --enable-languages="c,c++" --with-newlib
---without-headers --disable-shared--with-gnu-as --with-gnu-ld</th>
- </tr>
- <tr align="left">
- <th>$ make all-gcc</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install-gcc</th>
- </tr>
-</tbody></table>
-
-
-
-
-<p>On my system, the last line above (sudo make install-gcc) terminated
-with errors, because it was unable to find our newly compiled binutils.
-If this happens for any kind of "make install" command, this is a quick
-way to solve it:</p>
-
-<p style="text-align: left;"><br></p><div style="text-align: left;">
-
-</div><table class="table_cod">
- <tbody><tr align="left">
- <th>$ sudo -s -H</th>
- </tr>
- <tr align="left">
- <th># export PATH=/usr/local/cross-arm/bin:$PATH</th>
- </tr>
- <tr align="left">
- <th># make install-gcc</th>
- </tr>
- <tr>
- <th style="text-align: left;"># exit</th>
- </tr>
-</tbody></table>
-
-
-
-
<h2>Step 3: Newlib</h2>
<p>Once again, Newlib is as easy as unpack, configure, build. But I
@@ -236,49 +98,28 @@
executable, so I added the "-ffunction-sections -fdata-sections" flags
to allow the linker to perform dead code stripping:</p>
-<p><br></p>
+<p><pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
+$ cd newlib-1.17.0
+$ mkdir build
+$ cd build
+$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as --disable-shared
+$ make CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections -DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer -D__BUFSIZ__=256"
+$ sudo -s -H
+# export PATH=/usr/local/cross-arm/bin:$PATH
+# make install
+# exit
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ tar xvfz newlib-1.16.0.tar.gz</th>
- </tr>
- <tr align="left">
- <th>$ cd newlib-1.16.0</th>
- </tr>
- <tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
---disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as
---disable-shared</th>
- </tr>
- <tr align="left">
- <th>$ make
-CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections
--DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer
--D__BUFSIZ__=256"</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
+<p>Some notes about the flags used in the above sequence:
+<ul>
+ <li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example
+ <a target="_blank" href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li>
+ <li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li>
+ <li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li>
+ <li><code>-D__BUFSIZ__=256</code>: again Newlib specific, this is the buffer size allocated by default for files opened via fopen(). The default is 1024, which I find too much
+ for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul></p>
-
-<p>Some notes about the flags used in the above sequence:</p>
-
-<ul><li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256</code>:
-again Newlib specific, this is the buffer size allocated by default for
-files opened via fopen(). The default is 1024, which I find too much
-for an eLua, so I'm using 256 here. Of course, you can change this
-value.</li></ul>
-
-
<h2>Step 4: full GCC</h2>
<p>Finally, in the last step of our tutorial, we complete the GCC
@@ -286,25 +127,13 @@
(most notably libgcc.a). Fortunately this is simpler that the Newlib
compilation step:</p>
+<p><pre><code>$ cd gcc-4.3.3/build
+$ make all
+$ sudo make install
+</code></pre></p>
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ cd gcc-4.3.1/build</th>
- </tr>
- <tr align="left">
- <th>$ make all</th>
- </tr> <tr align="left">
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
-
-
-
-
<h2>Step 5: all done!</h2>
-<p>Now you can finally enjoy your ARM toolchain, and compile eLua with it :)
-If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="http://www.eluaproject.net/en/Contact">contact me</a>.</p>
-</div></body></html>
\ No newline at end of file
+<p>Now you can finally enjoy your ARM toolchain, and compile <b>eLua</b> with it :)
+If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="overview.html#contacts">contact us</a>.</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/tc_cortex.html
===================================================================
--- branches/eagle_mmc/doc/en/tc_cortex.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tc_cortex.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,263 +1,138 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Bulding GCC for Cortex</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><div class="content">
+<body style="background-color: rgb(255, 255, 255);">
-<h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_Cortex" class="local">Building GCC for Cortex</a></h3><p>This tutorial explains how you can create a GCC+Newlib toolchain
+<h3>Building GCC for Cortex</h3>
+<p>This tutorial explains how you can create a GCC+Newlib toolchain
that can be used to compile programs for the Cortex (Thumb2)
architecture, thus making it possible to use GCC to compile programs
-for the increasingly number of Cortex CPUs out there (<a href="http://www.luminarymicro.com/">Luminary Micro</a>, <a href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>,
-with new Cortex CPUs being announced by Atmel and other companies). I
+for the increasingly number of Cortex CPUs out there (<a target="_blank" href="http://www.luminarymicro.com/">Luminary Micro</a>, i
+<a target="_blank" href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>, with new Cortex CPUs being announced by Atmel and other companies). I
am writing this tutorial because I needed to work on a Cortex CPU for
the eLua project and I couldn't find anywhere a complete set of
instructions for building GCC for this architecture. You'll need such a
-toolchain if you want to compile eLua for Cortex-M3 CPUs.</p>
+toolchain if you want to compile <b>eLua</b> for Cortex-M3 CPUs. Please note that you can also use a
+pre-built toolchain to compile <b>eLua</b> (see <a href="toolchains.html">toolchains</a> for details) so building
+one yourself is not strictly required.</p>
<p><strong>DISCLAIMER: I'm by no means a specialist in the
GCC/newlib/binutils compilation process. I'm sure that there are better
ways to accomplish what I'm describing here, however I just wanted a
quick and dirty way to build a toolchain, I have no intention in
becoming too intimate with the build process. If you think that what I
-did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.eluaproject.net/en/Contact">contact us</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="overview.html#contacts">contact us</a> and I'll make the necessary corrections.
+And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
<h2>Prerequisites</h2>
-<p>To build your toolchain you'll need:</p>
+<p>To build your toolchain you'll need:
-<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
+<ul><li><b>a computer running Linux</b>: I use Ubuntu, but any Linux
will do as long as you know how to find the equivalent of "apt-get" for
your distribution. I won't be going into details about this, google it
and you'll sure find what you need. It is also assumed that the Linux
system already has a "basic" native toolchain installed (gcc/make and
related). This is true for Ubuntu after installation. Again, you might
-need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
-At the moment of writing this, the latest versions is 2.18, which for
-some weird reason refuses to compile on my system, so I'm using 2.17
-instead. <strong>UPDATE</strong>: you MUST use the new binutils 2.19
-distribution for the Cortex toolchain, since it fixes some assembler
-issues. You won't be able to compile eLua 0.5 or higher if you don't
-use binutils 2.19.</li><li>GCC: since support for Cortex (Thumb2)
-was only introduced staring with version 4.3.0, you'll need to download
-version 4.3.0 or newer. As I'm writing this, the latest GCC version is
-4.3.1, which I'll be using for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib:
-as I'm writing this, the latest official Newlib version is 1.16.0.
-However, the CVS version contains some fixes for the Thumb2
-architecture, some of them in very important functions (like
-setjmp/longjmp), so you'll need to fetch the sources from CVS (this
-will most likely change when a new official Newlib version is
-released). So go to <a href="http://sourceware.org/newlib/download.html">http://sourceware.org/newlib/download.html</a> and follow the instructions there in order to get the latest sources from CVS.</li><li>Also,
-the tutorial assumes that you're using bash as your shell. If you use
-something else, you might need to adjust some shell-specific commands. </li></ul>
-
-
-<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</th>
- </tr>
-</tbody></table>
-
-
-
+need to check your specific distribution.</li>
+<li><b>GNU binutils</b>: get it from <a target="_blank" href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+At the moment of writing this, the latest versions is 2.19.1, but it refuses to compile for ARM. Same goes for
+2.19. In fact, the only newer version of Binutils that seems to work properly is
+2.19.50, it can be downloaded from <a target="_blank" href="ftp://sourceware.org/pub/binutils/snapshots/">here</a>.
+This is the version that we are going to use in this tutorial.</li>
+<li><b>GCC</b>:as I'm writing this, the latest GCC version is
+4.3.3, which I'll be using for this tutorial. Download it from <a target="_blank" href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li>
+<li><b>Newlib</b>: as I'm writing this, the latest official Newlib version is 1.17.0, which I'll be using for this tutorial.
+Download it from <a target="_blank" href="ftp://sources.redhat.com/pub/newlib/index.html">here</a>.</li>
+<li>The tutorial assumes that you're using bash as your shell. If you use
+something else, you might need to adjust some shell-specific commands. </li></ul></p>
+<p>You need some support programs/libraries in order to compile the toolchain. To install them:</p>
+<p><pre><code>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</code></pre></p>
<p>Next, decide where you want to install your toolchain. They
-generally go in /usr/local/, so I'm going to assume
-/usr/local/cross-cortex for this tutorial. To save yourself some
+generally go in <i>/usr/local/</i>, so I'm going to assume
+<i>/usr/local/cross-cortex</i> for this tutorial. To save yourself some
typing, set this path into a shell variable:</p>
+<p><pre><code>$ export TOOLPATH=/usr/local/cross-cortex</code></pre></p>
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ export TOOLPATH=/usr/local/cross-cortex</th>
- </tr>
-</tbody></table>
-
-
-
<h2>Step 1: binutils</h2>
<p>This is the easiest step: unpack, configure, build.</p>
-<p><br></p>
+<p><pre><code>$ tar -xvjf binutils-2.19.50.tar.bz2
+$ cd binutils-2.19.50
+$ mkdir build
+$ cd build
+$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls
+$ make all
+$ sudo make install
+$ export PATH=${TOOLPATH}/bin:$PATH
+$ cd ../..</code></pre></p>
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ tar -xvjf binutils-2.19.tar.bz2</th>
- </tr>
- <tr align="left">
- <th>$ cd binutils-2.19</th>
- </tr>
- <tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
---enable-multilib --with-gnu-as --with-gnu-ld --disable-nls</th>
- </tr>
- <tr align="left">
- <th>$ make all</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
- <tr align="left">
- <th>$ export PATH=${TOOLPATH}/bin:$PATH</th>
- </tr>
-</tbody></table>
-
-
-
<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH. They are fully capable of handling Thumb2.</p>
<h2>Step 2: basic GCC</h2>
<p>In this step we build a "basic" GCC (that is, a GCC without any
support libs, which we'll use in order to build all the libraries for
-our target). But first we need to make a slight modification in the
-configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
-compile properly, giving a very weird "Link tests are not allowed after
-GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
-solution for this:</p>
+our target). Let's compile it (and note that the install step is
+a bit different from Newlib's):</p?
+<p><pre><code>$ tar -xvjf gcc-4.3.3.tar.bz2
+$ cd gcc-4.3.3
+$ mkdir build
+$ cd build
+$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --enable-multilib --enable-languages="c,c++" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld
+$ make all-gcc
+$ sudo -s -H
+# export PATH=/usr/local/cross-cortex/bin:$PATH
+# make install-gcc
+# exit
+$ cd ../..</code></pre></p>
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ tar -xvjf gcc-4.3.1.tar.bz2</th>
- </tr>
- <tr align="left">
- <th>$ cd gcc-4.3.1/libstdc++-v3</th>
- </tr>
- <tr align="left">
- <th>$ joe configure.ac </th>
- </tr>
-</tbody></table>
-
-
-<p> I'm using "joe" here as it's my favourite Linux text mode editor,
-you can use any other text editor. Now find the line which says
-"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it: </p>
-
-
-<code># AC_LIBTOOL_DLOPEN<br></code>
-
-<p>Save the modified file and exit the text editor</p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr>
- <th>$ autoconf</th>
- </tr>
- <tr>
- <th style="text-align: left;">$ cd ..</th>
- </tr>
-</tbody></table>
-
-
-
-
-<p>Great, now we know it will compile, so let's do it:</p>
-
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
---enable-multilib --enable-languages="c,c++" --with-newlib
---without-headers --disable-shared --with-gnu-as --with-gnu-ld</th>
- </tr>
- <tr align="left">
- <th>$ make all-gcc</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install-gcc</th>
- </tr>
-</tbody></table>
-
-
-
-<p>On my system, the last line above (sudo make install-gcc) terminated
-with errors, because it was unable to find our newly compiled binutils.
-If this happens for any kind of "make install" command, this is a quick
-way to solve it:</p>
-
-
-<p><br></p>
-
-<table style="width: 376px; height: 157px;" class="table_cod">
- <tbody><tr>
- <th>$ sudo -s -H</th>
- </tr><tr><td align="undefined" valign="undefined"><code># export PATH=/usr/local/cross-cortex/bin:$PATH</code></td></tr><tr><td align="undefined" valign="undefined"><code># make install-gcc</code></td></tr><tr><td align="undefined" valign="undefined"><code># exit</code></td></tr>
-</tbody></table>
-
-
-<code><br><br><br></code>
-
-
<h2>Step 3: Newlib</h2>
-<p>Again, some modifications are in order before we start compiling.
-Because the CVS version of Newlib doesn't seem to have all the required
-support for Thumb2 yet, we need to tell Newlib to skip some of its
-libraries when compiling:</p>
+<p>Some modifications are in order before we start compiling. Namely, we need to tell Newlib to skip some of its
+libraries when compiling (I'm using <b>vim</b> to edit, feel free to use your editor of choice instead):</p>
+<p><pre><code>$ tar -xvzf newlib-1.17.0.tar.gz
+$ cd newlib-1.17.0
+$ vim configure.ac
-<p><br></p>
+<b>Find this fragment of code:</b>
+ arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )
+ noconfigdirs="$noconfigdirs target-libffi target-qthreads"
+ libgloss_dir=arm
+ ;;
-<table class="table_cod">
- <tbody><tr>
- <th>$ cd [directory where the newlib CVS is located]</th>
- </tr>
- <tr>
- <th style="text-align: left;">$ joe configure.ac</th>
- </tr>
-</tbody></table>
+<b>And add "target-libgloss" to the "noconfigdirs" variable:</b>
+ arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )
+ noconfigdirs="$noconfigdirs target-libffi target-qthreads <b>target-libgloss</b>"
+ libgloss_dir=arm
+ ;;
+<b>Save the modified file and exit the text editor.</b>
+$ autoconf
-<p> Find this fragment of code:</p>
-
-<pre><code> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads"<br> libgloss_dir=arm<br> ;;<br><br> And add "target-libgloss" to the "noconfigdirs" variable:<br><br> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads target-libgloss"<br> libgloss_dir=arm<br> ;;<br><br> Save the modified file and exit the text editor<br> $ autoconf<br></code></pre>
-
-
-<p>On one of the systems I ran the above sequence, it terminated with
+<b>On one of the systems I ran the above sequence, it terminated with
errors, complaining that autoconf 2.59 was not found. I don't know why
that happens. 2.59 seems to be quite ancient, and the build ran equally
well with 2.61 (the version of autoconf on the system that gave the
-error). If this happens to you, first execute autoconf --version to
-find the actual version of your autoconf, then do this:</p>
+error). If this happens to you, first execute <i>autoconf --version</i> to
+find the actual version of your autoconf, then do this:</b>
+<p><pre><code>$ vim config/override.m4
+<b>Look for this line:</b>
+ [m4_define([_GCC_AUTOCONF_VERSION], [2.59])])
-<p><br></p>
+<b>And replace [2.59] with your actual version ([2.61] in my case).
+Save the modified file and exit the text editor.</b>
-<table class="table_cod">
- <tbody><tr>
- <th></th>
- </tr>
-</tbody></table>
+$ autoconf</code></pre></p></code></pre></p>
-<pre><code>$ joe config/override.m4<br><br> Look for this line:<br><br> [m4_define([_GCC_AUTOCONF_VERSION], [2.59])])<br><br> And replace [2.59] with your actual version ([2.61] in my case).<br> $ autoconf<br></code></pre>
-
<p>Once again, now we're ready to actually compile Newlib. But we need
to tell it to compile for Thumb2. As already specified, I'm not a
specialist when it comes to Newlib's build system, so I chosed the
@@ -267,77 +142,44 @@
wanted to keep what's needed from it in the final executable, I added
the "-ffunction-sections -fdata-sections" flags to allow the linker to
perform dead code stripping:</p>
+<p><pre><code>$ mkdir build
+$ cd build
+$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as --disable-shared
+$ make CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections -DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer -mcpu=cortex-m3 -mthumb -D__thumb2__ -D__BUFSIZ__=256" CCASFLAGS="-mcpu=cortex-m3 -mthumb -D__thumb2__"
+$ sudo -s -H
+# export PATH=/usr/local/cross-cortex/bin:$PATH
+# make install
+# exit
+$ cd ../..</code></pre></p>
+<p>Some notes about the flags used in the above sequence:
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ mkdir build</th>
- </tr>
- <tr align="left">
- <th>$ cd build</th>
- </tr>
- <tr align="left">
- <th>$
-../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
---disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as
---disable-shared</th>
- </tr>
- <tr align="left">
- <th>$ make
-CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections
--DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer
--mcpu=cortex-m3 -mthumb -D__thumb2__ -D__BUFSIZ__=256"
-CCASFLAGS="-mcpu=cortex-m3 -mthumb -D__thumb2__"</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
-
-
-
-<p>Some notes about the flags used in the above sequence:</p>
-
-<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-mcpu=cortex-m3 -mthumb:</code> this tells GCC that you want to compile for Cortex. Note that you need both flags.</li><li><code>-D__thumb2__:</code> again, this is Newlib specific, and seems to be required when compiling Newlib for Cortex.</li><li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256:</code>
-again Newlib specific, this is the buffer size allocated by default for
+<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here.
+ For an explanation, see for example <a target="_blank" href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li>
+<li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li>
+<li><code>-mcpu=cortex-m3 -mthumb:</code> this tells GCC that you want to compile for Cortex. Note that you need both flags.</li>
+<li><code>-D__thumb2__:</code> again, this is Newlib specific, and seems to be required when compiling Newlib for Cortex.</li>
+<li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li>
+<li><code>-D__BUFSIZ__=256:</code>again Newlib specific, this is the buffer size allocated by default for
files opened via fopen(). The default is 1024, which I find too much
-for an eLua, so I'm using 256 here. Of course, you can change this
-value.</li></ul>
+for <b>eLua</b>, so I'm using 256 here. Of course, you can change this value.</li></ul></p>
<h2>Step 4: full GCC</h2>
-
<p>Finally, in the last step of our tutorial, we complete the GCC
build. In this stage, a number of compiler support libraries are built
(most notably libgcc.a). Fortunately this is simpler that the Newlib
compilation step, as long as you remember that we want to build our
compiler support libraries for the Cortex architecture:</p>
+<p><pre><code>$ cd gcc-4.3.3/build
+$ make CFLAGS="-mcpu=cortex-m3 -mthumb" CXXFLAGS="-mcpu=cortex-m3 -mthumb" LIBCXXFLAGS="-mcpu=cortex-m3 -mthumb" all
+$ sudo make install
+</code></pre></p>
-
-<p><br></p>
-
-<table class="table_cod">
- <tbody><tr align="left">
- <th>$ cd gcc-4.3.1/build</th>
- </tr>
- <tr align="left">
- <th>$ make CFLAGS="-mcpu=cortex-m3 -mthumb" CXXFLAGS="-mcpu=cortex-m3 -mthumb" LIBCXXFLAGS="-mcpu=cortex-m3 -mthumb" all</th>
- </tr>
- <tr align="left">
- <th>$ sudo make install</th>
- </tr>
-</tbody></table>
-
-
-
-
<h2>All Done!</h2>
<p>Phew! That was quite a disturbing tutorial, with all that confusing
flags lurking in every single shell line :) But at this point you
should have a fully functional Cortex GCC toolchain, which seems to be
something very rare, so enjoy it with pride.
If you need further clarification, or if the above instructions didn't
-work for you, feel free to <a href="http://www.eluaproject.net/en/Contact">contact us</a>.</p><p></p><p></p>
-</div></body></html>
\ No newline at end of file
+work for you, feel free to <a href="overview.html#contacts">contact us</a>.</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/tchainbuild.html
===================================================================
--- branches/eagle_mmc/doc/en/tchainbuild.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tchainbuild.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,9 +1,18 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Toolchain building tutorials</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Toolchain Build</a></h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local"></a>eLua can be compiled and link edited with GCC Toolchains.<br><br>.....................<br><br>
-
- </body></html>
\ No newline at end of file
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Toolchain building tutorials</h3>
+<p>Although not strictly required, you can roll your own toolchain that can be used to build <b>eLua</b>. As explained <a href="toolchains.html">here</a>, <b>eLua</b> can generally be built with
+ready-made toolchains (with the exception of the i386 port), but you might still want to build your own toolchain for various reasons:
+<ul>
+ <li>have a better control over the compilation options of different libraries (most notably libc).</li>
+ <li>use a specific version of gcc/newlib.</li>
+ <li>your toolchain might generate smaller code than a pre-built toolchain.</li>
+ <li>get familiar with the binutils/gcc/newlib build system (not related to <b>eLua</b>, but still a good reason).</li>
+</ul></p>
+<p>Three separate tutorials explain the procedure of building a regular ARM toolchain, a Cortex-M3 toolchain and an i386 toolchain, respectively.</p>
+</body></html>
Added: branches/eagle_mmc/doc/en/toolchains.html
===================================================================
--- branches/eagle_mmc/doc/en/toolchains.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/toolchains.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,175 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Toolchains for eLua</title>
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Toolchains for eLua</h3>
+<p>You need (at least) a toolchain if you decide to build <b>eLua</b> yourself. The toolchain must contain at least a compiler, an assembler, a linker and (most likely) a tool to extract binary
+ data from the compiled image (in order to build the actual firmware). Also, a program that reports the sizes of different sections in the compiled image is often used to give an idea about the
+ resource consumption of <b>eLua</b>. You can use as many toolchains as you want for a given target, as long as the build scripts know to handle them. This
+ section outlines the different toolchain choices available for compiling <b>eLua</b>. Use the links below to navigate directly to your target of interest.
+<ul>
+ <li><a href="#armcortex">Toolchains for ARM and Cortex</a></li>
+ <li><a href="#avr32">Toolchains for AVR32</a></li>
+ <li><a href="#i386">Toolchains for i386</a></li>
+</ul></p>
+<p>If you have a different toolchain, reffer to the <a href="#configuration">toolchain configuration</a> paragraph in this document.</p>
+<a name="armcortex"><h2>Toolcains for ARM and Cortex</h2></a>
+<p>You have multiple options when building <b>eLua</b> for ARM and Cortex CPUs:
+<ul>
+ <li>build your own toolchain. Even if you have a toolchain already available, you might want to do this for maximum flexibility and control (for example to control the libc build flags, or to
+ use specific version of the tools). Check <a href="">##this link</a> for a step by step tutorial on building your own toolchain.</li>
+ <li>use a readily available toolchain. This saves you the hassle of building the toolchain yourself, which makes the process quicker and less error-prone.</li>
+</ul></p>
+<p>Because building a toolchain is already covered in another section of the documentation, we'll focus on installing a pre-compiled toolchain here. ARM is a very popular architecture, and because
+of this there are a lot of toolchains available for download free of charge. One of the most popular ones comes from <a href="http://www.codesourcery.com">CodeSourcery</a>, and we'll cover it here for a number of important reasons:
+<ul>
+ <li>it has support for both "traditional" ARM targets and Cortex-M3 (Thumb2) targets</li>
+ <li>it comes with user-friendly installers for both Linux and Windows</li>
+ <li>it has fairlygood documentation</li>
+ <li><b>eLua</b> supports this toolchain for all its ARM and Cortex targets</li>
+</ul></p>
+<p>Obtaining and installing the toolchain is very easy:
+<ol>
+ <li>go to <a href="http://www.codesourcery.com/sgpp/lite/arm/portal/subscription?@template=lite">the CodeSourcery download location</a> for the toolchain.</li>
+ <li>select from the table the current version in the "EABI" line (the link to the current version is just above the "All versions..." link).</li>
+ <li>download and run the installer.</li>
+</ol></p>
+<p>That's all! Make sure that the location of the toolchain is in your $PATH and build <b>eLua</b> with the <b>toolchain=codesourcery</b> option.</p>
+<a name="avr32"><h2>Toolchains for AVR32</h2></a>
+<p>Currently you have only one option for AVR32: download and install the toolchain from <a href="http://www.atmel.com">Atmel</a>. Unfortuntely they don't provide an installer, just a bunch of
+ Linux packages with some dependencies, so the installation process might be a bit tricky. These are the steps you should follow to install Atmel's AVR32 toolchain:
+<ul>
+ <li>download the correct version for your Linux distribution (in this case Ubuntu) from <a href="http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4118">here</a>.</li>
+ <li>unzip the downloaded archive to a temporary directory, you'll get a bunch of .deb packages</li>
+ <li>install the packages from this command line (the package names are based on version 2.1.4 of the toolchain, change them as needed if you're using a different version):
+ <p><pre><code>$ sudo dpkg -i libavr32ocd1_3.0.9-1_i386.deb libavr32sim_0.2.1-1_i386.deb
+$ sudo dpkg -i libavrtools1_3.0.9-1_i386.deb libelfdwarfparser_2.0.7-1_i386.deb
+$ sudo dpkg -i avr32headers_1.9.11-1_all.deb
+$ sudo dpkg -i avr32parts_1.9.9-1_all.deb
+$ sudo dpkg -i avr32-binutils_2.17.atmel.1.2.6-2_i386
+$ sudo dpkg -i avr32-gcc-newlib_4.2.2-atmel.1.0.8-2_i386.deb
+$ sudo dpkg -i avr32program_3.0.4-1_i386.deb</p></pre></code>
+ If dpkg complains about missing dependencies, install them as required and resume the installation process.
+ </li>
+</ul></p>
+<p>That's it. Your toolchain is already be in $PATH (since it installs itself in /usr/bin) so you should be ready to build <b>eLua</b> for AVR32.</p>
+<a name="i386"><h2>Toolchains for i386</h2></a>
+<p>Currently the only tested procedure for building <b>eLua</b> for i386 is to <a href="">##build an i386 toolchain</a>. Other toolchains might work equally well though, but none was tested so far.
+</p>
+<a name="configuration"><h3>Toolchain configuration in eLua <font color="red">(WIP)</font></h3></a>
+<p>The <b>eLua</b> build system makes provisions for specifying an unlimited number of toolchains for a given target, selectable via the scons <b>toolchain=...</b> option. The default structure
+ of each of the toolchains supported by default is listed in the table below.
+<table class="table_center">
+<tbody>
+<tr>
+ <th>Toolchain</th>
+ <th style="text-align:center;" rowspan="2">Name</th>
+ <th style="text-align:center;" rowspan="2">Compiler</th>
+ <th style="text-align:center;" rowspan="2">Linker</th>
+ <th style="text-align:center;" rowspan="2">Assembler</th>
+ <th style="text-align:center;" rowspan="2">Size tool</th>
+ <th style="text-align:center;" rowspan="2">Image copy tool</th>
+</tr>
+<tr>
+ <td>Platform</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">ARM (ELF)</td>
+ <td style="text-align:center;">arm-gcc</td>
+ <td style="text-align:center;">arm-elf-gcc</td>
+ <td style="text-align:center;">arm-elf-ld</td>
+ <td style="text-align:center;">arm-elf-as</td>
+ <td style="text-align:center;">arm-elf-size</td>
+ <td style="text-align:center;">arm-elf-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">ARM (EABI)</td>
+ <td style="text-align:center;">codesourcery</td>
+ <td style="text-align:center;">arm-none-eabi-gcc</td>
+ <td style="text-align:center;">arm-none-eabi-ld</td>
+ <td style="text-align:center;">arm-none-eabi-as</td>
+ <td style="text-align:center;">arm-none-eabi-size</td>
+ <td style="text-align:center;">arm-none-eabi-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">Cortex (ELF)</td>
+ <td style="text-align:center;">arm-gcc</td>
+ <td style="text-align:center;">arm-elf-gcc</td>
+ <td style="text-align:center;">arm-elf-ld</td>
+ <td style="text-align:center;">arm-elf-as</td>
+ <td style="text-align:center;">arm-elf-size</td>
+ <td style="text-align:center;">arm-elf-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">Cortex (EABI)</td>
+ <td style="text-align:center;">codesourcery</td>
+ <td style="text-align:center;">arm-none-eabi-gcc</td>
+ <td style="text-align:center;">arm-none-eabi-ld</td>
+ <td style="text-align:center;">arm-none-eabi-as</td>
+ <td style="text-align:center;">arm-none-eabi-size</td>
+ <td style="text-align:center;">arm-none-eabi-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">AVR32</td>
+ <td style="text-align:center;">avr32-gcc</td>
+ <td style="text-align:center;">avr32-gcc</td>
+ <td style="text-align:center;">avr32-ld</td>
+ <td style="text-align:center;">avr32-s</td>
+ <td style="text-align:center;">avr32-size</td>
+ <td style="text-align:center;">avr32-objcopy</td>
+</tr>
+<tr>
+ <td style="color: rgb(255, 102, 0);">i386</td>
+ <td style="text-align:center;">i686-gcc</td>
+ <td style="text-align:center;">i686-elf-gcc</td>
+ <td style="text-align:center;">i686-elf-ld</td>
+ <td style="text-align:center;">nasm</td>
+ <td style="text-align:center;">i686-elf-size</td>
+ <td style="text-align:center;">i686-elf-objcopy</td>
+</tr>
+</tbody>
+</table>
+</p>
+<p>If you need to add a new toolchain or modify an existing one, take a look at the scons build script (SConstruct). A toolchain-related fragment of SConstruct is shown below:
+<pre><code># List of toolchains
+toolchain_list = {
+ <b># This defines a toolchain with the name "arm-elf"</b>
+ 'arm-gcc' : {
+ 'compile' : 'arm-elf-gcc',
+ 'link' : 'arm-elf-ld',
+ 'asm' : 'arm-elf-as',
+ 'bin' : 'arm-elf-objcopy',
+ 'size' : 'arm-elf-size'
+ },
+ <b># Another toolchain, this time called "codesourcery"</b>
+ 'codesourcery' : {
+ 'compile' : 'arm-none-eabi-gcc',
+ 'link' : 'arm-none-eabi-ld',
+ 'asm' : 'arm-none-eabi-as',
+ 'bin' : 'arm-none-eabi-objcopy',
+ 'size' : 'arm-none-eabi-size'
+ },
+................
+}
+
+# List of platform/CPU/toolchains combinations
+# The first toolchain in the toolchains list is the default one
+# (the one that will be used if none is specified)
+platform_list = {
+ 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], <b>'toolchains' : [ 'arm-gcc', 'codesourcery' ]</b> },
+ 'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], <b>'toolchains' : [ 'arm-gcc', 'codesourcery' ]</b> },
+ ................
+}</pre></code></p>
+<p>From this fragment it's easy to undertand that there are at most two places in SConstruct that must be taken into account when dealing with toolchain:
+<ul>
+ <li>the definition of <b>toolchain_list</b>. This is a list of all the supported toolchains with all their relevant components (compiler, linker, assembler, image copy tool and size tool).</li>
+ <li>each <b>eLua</b> platform has a list of permitted toolchains (only the toolchains specified in this list can be used to build an <b>eLua</b> image for that target). The first element of
+ this list will be automatically used if a <b>toolchain=...</b> option is not specified on the command line.</li>
+</ul></p>
+<p>Please note that in order to add a new toolchain to <b>eLua</b> it's generally not enough to edit just SConstruct. As different toolchains have different command line options, one should also
+ edit the platform's build configuration file (<i>src/platform/<platform name>/conf.py</i>) and make it aware of the new toolchain. The exact procedure for doing this is highly dependent on
+ the toolchain and it's well beyond the scope of this tutorial.</p>
+</body></html>
+
Modified: branches/eagle_mmc/doc/en/tut_bootpc.html
===================================================================
--- branches/eagle_mmc/doc/en/tut_bootpc.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tut_bootpc.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,13 +1,11 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Booting your PC in eLua</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua" class="local">Booting your PC in eLua</a></h3>
-
- <div class="content">
-
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Booting your PC in eLua</h3>
<p>That's right: after following this tutorial, your PC will boot
directly into Lua! No OS there (this explains why the boot process is
so fast), just you and Lua. You'll be able to use the regular Lua
@@ -16,14 +14,13 @@
<h2>Details</h2>
-<p>Booting Lua involves using the well known <a href="http://www.gnu.org/software/grub/">GRUB</a> that will be used to load a <a href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a>
-compliant ELF file that contains our eLua code. Since the eLua code and
-the build instructions are not available yet, I'll be providing a
-direct link to the ELF file. The code runs in protected mode, so you
+<p>Booting <b>eLua</b> involves using the well known <a target="_blank" href="http://www.gnu.org/software/grub/">GRUB</a> that will be used to load
+a <a target="_blank" href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a>
+compliant ELF file that contains our <b>eLua</b> code. The code runs in protected mode, so you
have access to your whole memory. The code does not access any kind of
storage device (HDD, CDROM, floppy), so if you're worried that it might
brick your system, you can relax now :) I'm only using some very basic
-keyboard and VGA "drivers", so all you're risking is a system freeze
+keyboard and VGA textmode "drivers", so all you're risking is a system freeze
(even this is highly unlikely), nothing a good old RESET can't handle
(be sure to use the hardware reset though, CTRL+ALT+DEL is not handled
by the code). But just in case, see also the next section.</p>
@@ -36,7 +33,7 @@
card registers, so it can't harm it or your monitor. It only implements
a "protected mode keyboard driver" that can't physically damage
anything in your system. In short, I made every effort to make the code
-as harmless as possible. I tested it on 5 different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
+as harmless as possible. I tested it on 5 different computers and in 2 <a target="_blank" href="http://www.virtualbox.org/">VirtualBox</a>
emulators, and nothing bad happened. That said, there are no warranties
of any kind. In the very unlikely event that something bad does happen
to your system, you have my sincere sympathy, but I can't be held
@@ -44,50 +41,61 @@
<h2>Prerequisites</h2>
-<p>To boot your computer in Lua you'll need:</p>
+<p>To boot your computer in Lua you'll need:
-<ul><li>a 386 or better computer running Linux. I actually tested
+<ul>
+<li>a 386 or better computer running Linux. I actually tested
this only on Pentium class computers, but it should run on a 386
-without problems.</li><li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
+without problems.</li>
+<li><a target="_blank" href="http://www.gnu.org/software/grub/">GRUB</a>.
Since you're running Linux, chances are you're already using GRUB as
your bootloader. If not, you must install it. You don't need to install
it on your HDD; a floppy, an USB stick or even a CDROM will work as
well. I won't cover the GRUB installation procedure here, just google
for "install grub on floppy/usb/cdrom" and you'll sure find what you're
-looking for. You can try for example <a href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">here</a>, <a href="http://www.freesoftwaremagazine.com/articles/grub_intro/">here</a> or <a href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">here</a>.</li><li>The eLua ELF file. Download it from <a href="http://elua.berlios.de/surprise">here</a>. OR <a href="http://www.eluaproject.net/en/Downloads">download eLua</a> and compile it for the i386 architecture using a toolchain that you can build by following <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">this tutorial</a>.</li><li>a text editor to edit your GRUB configuration file.</li></ul>
+looking for. You can try for example <a target="_blank" href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">here</a>,
+<a target="_blank" href="http://www.freesoftwaremagazine.com/articles/grub_intro/">here</a> or
+<a target="_blank" href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">here</a>.</li>
+<li>The <b>eLua</b> i386 ELF file, see <a href="downloads.html">here</a> for instructions on how to obtain it. OR <a href="downloads.html">download the eLua source distribution</a> and compile it
+ for the i386 architecture using a toolchain that you can build by following <a href="tc_386.html">this tutorial</a>.</li>
+<li>a text editor to edit your GRUB configuration file.</li>
+</ul></p>
-
<p>The rest of this tutorial assumes that you're using Linux with GRUB,
-and that GRUB is located in /boot/grub, which is true for many Linux
-distributions (I'm using Ubuntu 8.04).</p>
+and that GRUB is located in <i>/boot/grub</i>, which is true for many Linux
+distributions.</p>
<h2>Let's do this</h2>
-<p>First, copy the <a href="http://elua.berlios.de/surprise">eLua ELF file</a> to your "/boot" directory:</p>
-<pre><code>$ sudo cp surprise /boot<br></code></pre>
+<p>First, copy the eLua ELF file to your "/boot" directory:</p>
+<p><pre><code>$ sudo cp surprise /boot<br></code></pre></p>
-<p>Next you need to add another entry to your GRUB menu file (/boot/grub/menu.lst). Edit it and add this entry:</p>
+<p>Next you need to add another entry to your GRUB menu file (<i>/boot/grub/menu.lst</i>). Edit it and add this entry:</p>
-<pre><code> title Surprise!<br> root (hd0,0)<br> kernel /boot/surprise<br> boot<br></code></pre>
+<p><pre><code> title eLua
+ root (hd0,0)
+ kernel /boot/elua_lua_i386.elf <b>(change this if the eLua file name is different)</b>
+ boot</code></pre></p>
-<p>You may need to modify the root (hd0,0) line above to match your
-boot device. The best way to do this is to look in the menu.lst file
+<p>You may need to modify the <i>root (hd0,0)</i> line above to match your
+boot device. The best way to do this is to look in the <i>menu.lst</i> file
for the entry that boots your Linux kernel. It should look similar to
this:</p>
-<pre><code> title Ubuntu, kernel 2.6.20-16-generic<br> root (hd0,2)<br> kernel /boot/vmlinuz-2.6.20-16-generic<br> initrd /boot/initrd.img-2.6.20-16-generic<br> savedefault <br></code></pre>
+<p><pre><code> title Ubuntu, kernel 2.6.20-16-generic
+ <b>root (hd0,2)</b>
+ kernel /boot/vmlinuz-2.6.20-16-generic
+ initrd /boot/initrd.img-2.6.20-16-generic
+ savedefault</code></pre></p>
-<p>After you find it, simply use the root (hdx,y) line from that entry
-(root (hd0,2) in the example above) in your newly created entry instead
-of root (hd0,0).
+<p>After you find it, simply use the <i>root (hdx,y)</i> line from that entry
+(<i>root (hd0,2)</i> in the example above) in your newly created entry instead
+of root (hd0,0).<br>
That's it! Now reboot your computer, and when the GRUB boot menu
-appears, choose "Surprise!" from it. You can even type dofile
-"/rom/bisect.lua" to execute the "bisect.lua" test file. Enjoy!
-As usual, if you need more details, you can <a href="http://www.eluaproject.net/en/Contact">contact us</a>.
-Also, if you want to have you own USB stick that boots Lua, let me
-know. If enough people manifest their interest in this, I'll add
-another tutorial on how to do it (I already have an USB stick that
-boots Lua, of course :) ).</p>
-</div></body></html>
\ No newline at end of file
+appears, choose "eLua" from it. See <a href="using.html">using eLua</a> for
+instructions on how to use your newly installed self-booting programming language :)</p>
+<p>As usual, if you need more details, you can <a href="overview.html#contacts">contact us</a>.
+Also, if you want to go one step ahead and have you own USB stick that boots <b>eLua</b>, check <a href="tut_bootstick.html">this tutorial</a>.</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/tut_bootstick.html
===================================================================
--- branches/eagle_mmc/doc/en/tut_bootstick.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tut_bootstick.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,57 +1,60 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Booting eLua from an USB stick</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick" class="local">Booting eLua from a stick</a></h3>
-
- <div class="content">
-
-<p>This is follow up of <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">this tutorial</a>.
-After completing it you'll be able to boot eLua directly from your USB
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Booting eLua from an USB stick</h3>
+<p>This is follow up of <a href="tut_bootpc.html">this tutorial</a>.
+After completing it you'll be able to boot <b>eLua</b> directly from your USB
stick (provided, of course, that your computer can boot from an USB
stick, which is true for most computers nowadays). You might want to
-check the <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">boot your PC in eLua</a>
+check the <a href="tut_bootpc.html">boot your PC in eLua</a>
tutorial first for more details. If you have an old USB stick that you
don't use anymore, and/or the shear geekness of this idea makes you
feel curious, this tutorial is definitely for you :)</p>
<h2>Disclaimer</h2>
-<p><strong>As mentioned <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">here</a>,
+<p><strong>As mentioned <a href="tut_bootpc.html">here</a>,
the code won't try to access any kind of storage (HDD, CDROM, floppy),
not even for reading, so you don't need to worry about that. Also it
doesn't try to reprogram your video card registers, so it can't harm it
or your monitor. It only implements a "protected mode keyboard driver"
that can't physically damage anything in your system. In short, I made
every effort to make the code as harmless as possible. I tested it on 5
-different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
+different computers and in 2 <a htarget="_blank" ref="http://www.virtualbox.org/">VirtualBox</a>
emulators, and nothing bad happened. That said, there are no warranties
of any kind. In the very unlikely event that something bad does happen
to your system, you have my sincere sympathy, but I can't be held
responsible for that. Also, I can't be held responsible if you mess up
your HDD by failing the GRUB installation procedure (even though, once
again, this shouldn't be possible unless you really insist on messing
-it up). If you're new to computers, this tutorial might not be for you.
+it up). If you're new to computers or Linux, this tutorial might not be for you.
Your call.</strong></p>
<h2>Prerequisites</h2>
-<p>To have your own bootable eLua USB stick you'll need:</p>
+<p>To have your own bootable <b>eLua</b> USB stick you'll need:
<ul><li>an USB stick. I tested this on an 128M USB stick, because
it's the smallest I could find. You should be OK with a 4M stick or
-even a 2M stick</li><li>a computer running Linux. I use Ubuntu, but any other distribution is fine.</li><li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
+even a 2M stick</li>
+<li>a computer running Linux. I use Ubuntu, but any other distribution is fine.</li>
+<li><a target="_blank" href="http://www.gnu.org/software/grub/">GRUB</a>.
Since you're running Linux, chances are you're already using GRUB as
your bootloader. If not, you must install it on your HDD, or at least
know how to install it directly on the USB stick. I won't go into
details here, google it and you'll find lots of good articles about
-GRUB. This tutorial assumes that you're using GRUB as your bootloader.</li><li>The eLua ELF file. Download it from <a href="http://elua.berlios.de/surprise">here</a>. OR <a href="http://www.eluaproject.net/en/Downloads">download eLua</a> and compile it for the i386 architecture using a toolchain that you can build by following <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">this tutorial</a>.</li><li>a text editor to edit your GRUB configuration file.</li></ul>
+GRUB. This tutorial assumes that you're using GRUB as your bootloader.</li>
+<li>The <b>eLua</b> i386 ELF file, see <a href="downloads.html">here</a> for instructions on how to obtain it. OR <a href="downloads.html">download the eLua source distribution</a> and compile it
+ for the i386 architecture using a toolchain that you can build by following <a href="tc_386.html">this tutorial</a>.</li>
+<li>a text editor to edit your GRUB configuration file.</li></ul></p>
<p>The rest of this tutorial assumes that you're using Linux with GRUB,
-and that GRUB is located in /boot/grub, which is true for many Linux
+and that GRUB is located in <i>/boot/grub</i>, which is true for many Linux
distributions.</p>
<h2>Backup your stick</h2>
@@ -65,39 +68,69 @@
chances are you'll need to re-partition and re-format your stick before
installing GRUB on it. The problem is that many sticks have a very
creative, non-standard partition table, and GRUB doesn't like that. I
-looked at the partition table on my eLua USB stick, and it scared me to
+looked at the original partition table of my <b>eLua</b> USB stick and it scared me to
death, so I had to follow this procedure. In short, you'll need to
delete all the partitions from your stick, create a new partition, and
-then format it. For a step by step tutorial check here.</p>
+then format it. For a step by step tutorial check <a target="_blank" href="http://www.4p8.com/eric.brasseur/suse9.1_usb_stick.html">here</a>.</p>
<h2>Install GRUB on your stick</h2>
-<p>First, mount your freshly formatted stick (I'm going to assume that the mount directory is /mnt):</p>
+<p>First, mount your freshly formatted stick (I'm going to assume that the mount directory is <i>/mnt</i>):</p>
-<pre><code> $ sudo mount /dev/sda1 /mnt<br></code></pre>
+<p><pre><code>$ sudo mount /dev/sda1 /mnt<br></code></pre></p>
-
-<p>(of course, you'll need to change /dev/sda1 to reflect the physical location of your USB stick).
+<p>(of course, you'll need to change <i>/dev/sda1</i> to reflect the physical location of your USB stick. You should know the physical location from the previous step).
Then copy the required GRUB files to your stick:</p>
-<pre><code> $ cd /mnt<br> $ mkdir boot<br> $ mkdir boot/grub<br> $ cd /boot/grub<br> $ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub<br></code></pre>
+<p><pre><code>$ cd /mnt
+$ mkdir boot
+$ mkdir boot/grub
+$ cd /boot/grub
+$ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub</code></pre></p>
+<p>Copy the <b>eLua</b> ELF file (<i>elua_lua_i386.elf</i> in this example, change the name if needed) to the GRUB directory as well:</p>
-<p>Copy the <a href="http://elua.berlios.de/surprise">eLua ELF file</a> to the GRUB directory as well:</p>
+<p><pre><code>$ cp elua_lua_i386.elf /mnt/boot/grub</code></pre></p>
-<pre><code> $ cp surprise /mnt/boot/grub<br></code></pre>
+<p>Create a <i>menu.lst</i> file for GRUB with you favorite text editori (I'm using vim):</p>
+<p><pre><code>$ cd /mnt/boot/grub
+$ vim menu.lst
+ title eLua
+ root (hd0,0)
+ kernel /boot/grub/elua_lua_i386.elf
+ boot</code></pre></p>
-<p>Create a menu.lst file for GRUB with you favorite text editor (I'm using joe):</p>
+<p>Now it's time to actually install GRUB on the stick.</p>
-<pre><code> $ cd /mnt/boot/grub<br> $ joe menu.lst<br> title Surprise!<br> root (hd0,0)<br> kernel /boot/grub/surprise<br> boot<br></code></pre>
+<p><pre><code>$ sudo -s -H
+# grub
-<p>Now it's time to actually install GRUB on the stick.</p>
+<b>Now we need to find the GRUB name of our USB stick. We'll use the "find" command from
+GRUB and our eLua ELF file to accomplish this:</b>
-<pre><code> $ sudo -s -H<br> # grub<br> Now we need to find the GRUB name of our USB stick. We'll use the "find" command from<br> GRUB and our "surprise" file to accomplish this:<br><br> grub> find /boot/grub/surprise<br> (hd2,0)<br><br> GRUB should respond with a single line (like (hd2,0) above). If it gives you more <br> than one line, something is wrong. Maybe you also installed eLua on your HDD? If so, <br> delete the /boot/grub/surprise file from your HDD and try again.<br> You might get a different (hdx,y) line. If so, just use it instead of (hd2,0) in the rest of <br> this tutorial.<br><br> grub> root (hd2,0)<br> grub> setup (hd2)<br> Checking if "/boot/grub/stage1" exists... yes<br> Checking if "/boot/grub/stage2" exists... yes<br> Checking if "/boot/grub/fat_stage1_5" exists... yes<br> Running "embed /boot/grub/fat_stage1_5 (hd2)"... 15 sectors are embedded.<br> succeeded<br> Running "install /boot/grub/stage1 (hd2) (hd2)1+15 p (h!
d2,0)/boot/grub/stage2<br> /boot/grub/menu.lst"... succeeded<br> Done. <br> grub> quit<br></code></pre>
+grub> find /boot/grub/elua_lua_i386.elf
+(hd2,0)
+<b>GRUB should respond with a single line (like (hd2,0) above). If it gives you more
+than one line, something is wrong. Maybe you also installed eLua on your HDD? If so,
+delete the /boot/grub/elua_lua_i386.elf file from your HDD and try again.
+You might get a different (hdx,y) line. If so, just use it instead of (hd2,0) in the
+rest of this tutorial</b>.
+grub> root (hd2,0)
+grub> setup (hd2)
+ Checking if "/boot/grub/stage1" exists... yes
+ Checking if "/boot/grub/stage2" exists... yes
+ Checking if "/boot/grub/fat_stage1_5" exists... yes
+ Running "embed /boot/grub/fat_stage1_5 (hd2)"... 15 sectors are embedded.
+ succeeded
+ Running "install /boot/grub/stage1 (hd2) (hd2)1+15 p (hd2,0)/boot/grub/stage2
+ /boot/grub/menu.lst"... succeeded
+ Done.
+grub> quit</code></pre></p>
+
<p>That's it! Now reboot your computer, make sure that your BIOS is set
-to boot from USB, and enjoy! You can even type dofile "/rom/bisect.lua"
-to execute the "bisect.lua" test file.
-As usual, if you need more details, you can <a href="http://www.eluaproject.net/en/Contact">contact us</a>.</p>
-</div></body></html>
\ No newline at end of file
+to boot from USB, and enjoy! See <a href="using.html">using eLua</a> for
+instructions on how to use your new toy :).</p>
+<p>As usual, if you need more details, you can <a href="overview.html#contacts">contact us</a>.</p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/tut_openocd.html
===================================================================
--- branches/eagle_mmc/doc/en/tut_openocd.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tut_openocd.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,28 +1,29 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Using OpenOCD</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Using_OpenOCD" class="local">Using OpenOCD</a></h3>
-
- <div class="content">
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Using OpenOCD</h3>
+<p>This section presents <a target="_blank" href="http://openocd.berlios.de">OpenOCD</a>, a tool used to program <b>eLua</b> on some of its targets.
+If you'd rather skip the long and boring OpenOCD introduction and
+skip directly to the OpenOCD script downloads, use the links below.
-<h2>Quick downloads</h2>
+<ul>
+ <li><a href="#str9files">Configuration files for STR9-comStick</a></li>
+ <li><a href="#lpc2888files">Configuration files for LPC2888</a></li>
+ <li><a href="#str7files">Configuration files for STR7</a></li>
+</ul></p>
-<p>If you'd rather skip the long and boring OpenOCD introduction and
-skip directly to the OpenOCD script downloads, use the links below.</p>
-
-
-<ul><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str9files">Configuration files for STR9-comStick</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#lpc2888files">Configuration files for LPC2888</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str7files">Configuration files for STR7</a></p></li></ul>
-
<h2>About OpenOCD</h2>
-<p><a href="http://elua.berlios.de/tut_openocd.html">OpenOCD</a> is an open source tool that can be used to connect to a CPU's <a href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>
+<p><a target="_blank" href="http://openocd.berlios.de">OpenOCD</a> is an open source tool that can be used to connect to a CPU's
+<a target="_blank" href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>
interface. Using OpenOCD and a physical JTAG connection allows you to
burn the on-chip flash memory of your CPU (or to load your code
directly to RAM), to read the internal CPU memory (Flash/RAM) and to
-use <a href="http://sourceware.org/gdb/">gdb</a> to debug your code.
+use <a target="_blank" href="http://sourceware.org/gdb/">gdb</a> or other debuggers to debug your code.
Needless to say, this is a very handy tool (and especially handy if
your CPU happens to be built around an ARM core, since in this case you
can be almost certain that it has a JTAG interface that you can use).
@@ -34,39 +35,47 @@
docummented. The project's wiki does give a few good pointers about all
the configuration parameters, and there are some good OpenOCD tutorials
out there, but none of them tells the whole story. And the syntax (and
-even some commands) seems to change slightly between releases, which
+even some commands) seems to change between releases, which
makes things even more confusing. This is why I generally choose to use
a different firmware burning tool when available, and resort to OpenOCD
only for targets that lack a proper firmware burning tool. If you need
to debug your code, however, you probably want to use OpenOCD, since
the alternatives aren't cheap.
-To summarize, you can forget about OpenOCD when:</p>
+To summarize, you can forget about OpenOCD when:
-<ul><li><p>your CPU manufacturer provides a special tool for
+<ul>
+ <li>your CPU manufacturer provides a special tool for
firmware burning. This is quite often the case, but more often that not
-the forementioned tools work only in Windows.</p></li><li><p>you
-must debug your code, but you have a good intuition about where the
+the forementioned tools work only in Windows.</li>
+ <li>you must debug your code, but you have a good intuition about where the
problem is located. In this case, simply connecting a LED to a PIO port
and turning it on and off from different parts of your code until you
figure out exactly what's the problem can work wonders. I can't
remember when was the last time I used gdb for debugging, since "LED
-debugging" was all I needed. </p></li></ul>
+debugging" was all I needed. </li>
+</ul></p>
-<p>On the other hand, you should probably use OpenOCD when:</p>
+<p>On the other hand, you should probably use OpenOCD when:
-<ul><li><p>your CPU manufacturer doesn't provide a special tool for firmware burning (or it does, but it's not what you need).</p></li><li><p>you're using Linux, MacOS or another OS that is not supported by the firmware burning tool.</p></li><li><p>you need to do some serious debugging in order to understand what's wrong with your application.</p></li></ul>
+<ul>
+ <li>your CPU manufacturer doesn't provide a special tool for firmware burning (or it does, but it's not what you need).</li>
+ <li>you're using Linux, MacOS or another OS that is not supported by the firmware burning tool.</li>
+ <li>you need to do some serious debugging in order to understand what's wrong with your application.</li>
+</ul></p>
<p>If you decided that you don't need OpenOCD after all, now it's a
good time to navigate away from this page and save yourself from some
possible symptoms of headache. If you need OpenOCD, read on, I'll try
to make this as painless as possible. However, don't expect this to be
a full tutorial on OpenOCD, because it's not; my intention is to give
-you just enough data to use OpenOCD for burning eLua on your board.
+you just enough data to use OpenOCD for burning <b>eLua</b> on your board.
Because of this, I won't be covering debugging with OpenOCD here, just
firmware burning. And, before we begin, please read and understand the
next paragraph.</p>
-<p>DISCLAIMER: using OpenOCD improperly may force your CPU to behave
+<h2>Disclaimer</h2>
+
+<p><b>Using OpenOCD improperly may force your CPU to behave
unexpectedly. While physically damaging your CPU as a result of using
OpenOCD is very hard to accomplish, you might end up with a locked
chip, or you might erase a memory area that was not supposed to be
@@ -75,19 +84,19 @@
I'm going to provide, make sure that you know what you're doing. Also,
I'm not at all an OpenOCD expert, so my configuration scripts might
have errors, even though I tested them. In short, this tutorial comes
-without any guarantees whatsoever.</p>
+without any guarantees whatsoever.</b></p>
<h2>Getting OpenOCD</h2>
-<p>If you're on Windows, the best place to get OpenOCD already compiled and ready to run is to visit the <a href="http://www.yagarto.de/">Yagarto home page</a>.
+<p>If you're on Windows, the best way to get OpenOCD already compiled and ready to run is to
+visit the <a target="_blank" href="http://www.yagarto.de/">Yagarto home page</a>.
They provide a very nice OpenOCD installer, and they seem to keep up
with OpenOCD progress (the versions on the Yagarto site are not
"bleeding edge", but there are quite fresh nevertheless). If you're on
Linux, you can always use apt-get or your distribution-specific package
manager:</p>
-<pre><code>$ sudo apt-get install openocd<br></code></pre>
+<p><pre><code>$ sudo apt-get install openocd<br></code></pre></p>
-
<p>There is a catch here though: the OpenOCD version that I get from
apt-get is dated 2007-09-05, while the Yagarto OpenOCD version is from
2008-06-19. Since I'm using OpenOCD from Windows (because Ubuntu 8.04
@@ -96,8 +105,9 @@
introduction, the meaning and parameters of different commands might
change between OpenOCD version, so if you want to use the Yagarto
version on your non Windows system, you'll have to build it from source
-(see below).
-The main resource on how to build OpenOCD from source is the <a href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a> from the OpenOCD wiki. Also, a very good tutorial can be found <a href="http://forum.sparkfun.com/viewtopic.php?t=11221">here</a>.
+(see below).<br>
+The main resource on how to build OpenOCD from source is the <a target="_blank" href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a>
+from the OpenOCD wiki. Also, a very good tutorial can be found <a target="_blank" href="http://forum.sparkfun.com/viewtopic.php?t=11221">here</a>.
I'm not going to provide step by step build instructions, since the two
links that I mentioned cover this very well, and the build process is
relatively straightforward. However, since both tutorials describe how
@@ -105,69 +115,97 @@
modification do build the Yagarto version instead. The modification is
in the SVN checkout step. Replace this step:</p>
-<pre><code>$ svn checkout svn://svn.berlios.de/openocd/trunk<br></code></pre>
+<p><pre><code>$ svn checkout svn://svn.berlios.de/openocd/trunk<br></code></pre></p>
+<p>with this step ('717' is the SVN revision of the Yagarto OpenOCD build):</p>
-<p>With this step ('717' is the SVN revision of the Yagarto OpenOCD build):</p>
+<p><pre><code>$ svn checkout <b>-r 717</b> svn://svn.berlios.de/openocd/trunk<br></code></pre></p>
-<pre><code>$ svn checkout -r 717 svn://svn.berlios.de/openocd/trunk<br></code></pre>
-
<p>Follow the rest of the build instructions, and in the end you should have a working OpenOCD.</p>
<h2>Supported targets</h2>
-<p>I couldn't find a good page with a list of the targets that are
+<p>I couldn't find a good list of the targets that are
supported by OpenOCD. So, if you want to check if your particular CPU
is supported by OpenOCD, I recommend getting the latest sources (as
described in the previous section) and listing the
trunk/src/target/target directory:</p>
-<pre><code>$ ls trunk/src/target/target<br> at91eb40a.cfg<br> at91r40008.cfg<br> cfi.c<br> ....<br> str9comstick.cfg<br> ....<br></code></pre>
+<p><pre><code>$ ls trunk/src/target/target
+at91eb40a.cfg
+at91r40008.cfg
+....
+str9comstick.cfg
+....
+</code></pre></p>
-<p>If this listing has something that looks like your CPU name, you're
-in luck. OpenOCD has support for LPC from NXP, AT91SAM cfrom Atmel,
-STR7/STR9 from ST, and many others.</p>
+<p>If this listing has something that looks like your CPU name, you're lucky. OpenOCD has support for LPC from NXP, AT91SAM cfrom Atmel, STR7/STR9 from ST, and many others.</p>
+
<h2>Using OpenOCD</h2>
<p>To use OpenOCD, you'll need:</p>
-<ul><li>the OpenOCD executable, as described above</li><li>a board with a JTAG interface</li><li>a JTAG adapter</li></ul>
+<ul>
+ <li>the OpenOCD executable, as described above</li>
+ <li>a board with a JTAG interface</li>
+ <li>a JTAG adapter</li>
+</ul>
-
-<p>In some cases, your CPU board might provide a built in JTAG adapter. For example, my <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a>
+<p>In some cases, your CPU board might provide a built in JTAG adapter. For example,
+my <a target="_blank" href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a>
board provides both an USB-to-JTAG and an USB-to-serial converter built
-on board, switching between them automatically. The same is true for my
-<a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>. On the other hand, my <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> board has only a JTAG connector, I need a separate JTAG adapter to connect to it. I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex, but there are other affordable USB-to-JTAG adapters out there, like the Amontec <a href="http://www.amontec.com/jtagkey-tiny.shtml">JTAGKey-Tiny</a>. Not to mention that you can <a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">build your ownt</a>.
-Although USB is my interface of choice, you'll find JTAG adapters for
+on board, switching between them automagically. The same is true for my
+<a target="_blank" href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.
+On the other hand, my <a target="_blank" href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> board has only a JTAG connector, I need a separate JTAG adapter to connect to it.
+I'm using <a target="_blank" href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex, but there are other affordable USB-to-JTAG adapters out there,
+like the <a target="_blank" href="http://www.amontec.com/jtagkey-tiny.shtml">Amontec JTAGKey-Tiny</a>. Not to mention that you can
+<a target="_blank" href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">build your own</a>. Although USB is my interface of choice, you'll find JTAG adapters for
PC LPT ports too. The good news is that once you buy a JTAG adapter,
chances are that it will work with many boards with different CPUs,
since the JTAG connector layout is standardized and the JTAG adapters
-are generally able to work with different voltages.
-To actually use OpenOCD, you'll need a configuration file. The
+are generally able to work with different voltages.<br>
+To actually use OpenOCD, the next thing you'll need is a configuration file. The
configuration file is the one that lets OpenOCD know about your setup,
-such as:</p>
+such as:
+<ul>
+ <li>the kind of JTAG interface that you're using.</li>
+ <li>the actual hardware platform you're using (ATM7TDMI, ARM966 and so on).</li>
+ <li>the memory configuration of your CPU (flash banks).</li>
+ <li>the script used to program the flash memory.</li>
+</ul></p>
-<pre><code>* the kind of JTAG interface that you're using.<br>* the actual hardware platform you're using (ATM7TDMI, ARM966 and others).<br>* the memory configuration of your CPU (flash banks).<br>* the script used to program the flash memory.<br></code></pre>
-
<p>Presenting a list of all the possible configuration options and
their meaning is way beside the scope of this document, so I'm not
-going to do it, I'll give an example instead. For the example I'm going
-to use parts of my STR-comStick configuration file (comstick.cfg)
+going to do it, I'll give an example instead. I'm going
+to use parts of my STR9-comStick configuration file (comstick.cfg)
adapted from the OpenOCD distribution and from other examples (don't
worry, I'll provide full download links for this file later on). First
we need to tell OpenOCD that we're using a the STR9-comStick
USB-to-JTAG adapter:</p>
-<pre><code>interface ft2232<br>ft2232_device_desc "STR9-comStick A"<br>ft2232_layout comstick<br>ft2232_vid_pid 0x0640 0x002C<br>jtag_speed 4<br>jtag_nsrst_delay 100<br>jtag_ntrst_delay 100<br></code></pre>
+<p><pre><code>interface ft2232
+ft2232_device_desc "STR9-comStick A"
+ft2232_layout comstick
+ft2232_vid_pid 0x0640 0x002C
+jtag_speed 4
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+</code></pre></p>
<p>Also, OpenOCD needs to know what's our target and its memory layout:</p>
-<pre><code>target arm966e little run_and_init 1 arm966e<br>run_and_halt_time 0 50<br><br>working_area 0 0x50000000 32768 nobackup<br><br>flash bank str9x 0x00000000 0x00080000 0 0 0<br>flash bank str9x 0x00080000 0x00008000 0 0 0 <br></code></pre>
+<p><pre><code>target arm966e little run_and_init 1 arm966e
+run_and_halt_time 0 50
+working_area 0 0x50000000 32768 nobackup
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0</code></pre></p>
+
+
<p>This tells OpenOCD that our target is an ARM966-E running in little
endian mode, with two flash memory banks, one that starts at 0x0 and
it's 0x80000 bytes in size, and another one that starts at 0x80000 and
@@ -175,36 +213,50 @@
of our script file (this is the file that is used to pysically program
the CPU memory):</p>
-<pre><code>#Script used for FLASH programming<br>target_script 0 reset str91x_flashprogram.script<br></code></pre>
+<p><pre><code>#Script used for FLASH programming
+target_script 0 reset str91x_flashprogram.script</code></pre></p>
<p>The contents of the str91x_flashprogram.script is very target-dependent:</p>
-<pre><code>wait_halt<br>str9x flash_config 0 4 2 0 0x80000<br>flash protect 0 0 7 off<br>flash erase_sector 0 0 7<br>flash write_bank 0 main.bin 0<br>reset run<br>sleep 10<br>shutdown<br></code></pre>
+<p><pre><code>wait_halt
+str9x flash_config 0 4 2 0 0x80000
+flash protect 0 0 7 off
+flash erase_sector 0 0 7
+flash write_bank 0 main.bin 0
+reset run
+sleep 10
+shutdown</code></pre></p>
<p>I'm not even going to attempt to explain this one :) Basically it
unprotects the flash, erases it, writes the contents of "main.bin" to
flash, and then resets the CPU. If you need to flash a file with a
different name, the only thing you need to modify is the "main.bin" in
-the "flash write_bank" line.
+the "flash write_bank" line.<br>
To use all this, you need to tell OpenOCD to use our configuration file:</p>
-<pre><code>openocd-ftd2xx -f comstick.cfg<br></code></pre>
+<p><pre><code>openocd-ftd2xx -f comstick.cfg<br></code></pre></p>
-<p>(note: under Windows, the OpenOCD executable name is often
+<p>(<b>note</b>: under Windows, the OpenOCD executable name is often
"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
-the actualy name with your executable.)
-That's it for your OpenOCD crash course. I realise that there's much
+the actualy name with your executable).</p>
+<p>That's it for your OpenOCD crash course. I realise that there's much
more to learn, so here's a list of links with much better information
-on the subject:</p>
+on the subject:
-<ul><li><a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">OpenOCD quick reference</a> card. (slightly outdated)</li><li>A very good OpenOCD tutorial.</li><li><a href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">OpenOCD configuration examples</a> from the official OpenOCD wiki.</li><li>An excellent page about using <a href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD with ARM controllers</a>, with lots of real life examples.</li><li>An interesting <a href="http://forum.sparkfun.com/viewtopic.php?p=42079">topic on the SparkFun forum</a> about STR9 and OpenOCD.</li></ul>
+<ul>
+ <li><a target="_blank" href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">OpenOCD quick reference</a> card. (slightly outdated)</li>
+ <li><a target="_blank" href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">OpenOCD configuration examples</a> from the official OpenOCD wiki.</li>
+ <li>An excellent page about using <a target="_blank" href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD with ARM controllers</a>, with lots
+ of real life examples.</li>
+ <li>An interesting <a target="_blank" href="http://forum.sparkfun.com/viewtopic.php?p=42079">topic on the SparkFun forum</a> about STR9 and OpenOCD.</li>
+</ul></p>
<p><a name="str9files"></a></p>
-<h2>Configuration files for STR9-comStick</h2>
+<h2>##Configuration files for STR9-comStick</h2>
<p>Download them below:</p>
@@ -216,46 +268,47 @@
<p><a href="http://elua.berlios.de/other/str91x_reset.script">str91x_reset.script</a></p>
-<p>The comstick.cfg configuration file is for prorgramming the
-STR9-comStick. comrst.cfg is for resetting it. The comStick has a very
+<p>The <b>comstick.cfg</b> configuration file is for prorgramming the
+STR9-comStick. <b>comrst.cfg</b> is for resetting it. The comStick has a very
interesting habit: after you power it (via USB) it does not start
executing the code from the internal flash, you need to execute OpenOCD
-with the comreset.cfg script to start it. This script does exactly what
+with the comreset.cfg script to start it. <b>comrst.cfg</b> does exactly what
it says: executes a CPU reset (since the board doesn't have a RESET
button). This is a very peculiar behaviour, and I'm not sure if it's
generic or it's only relevant to my particular comStick. I suspect that
the CPU RESET line isn't properly handled by the on-board USB-to-JTAG
converter, and the only solution I have for this is to execute this
script everytime you power the board and everytime you need to do a
-RESET.</p>
+RESET.<br>
+Also, be sure to modify <b>str91x_flashprogram.script</b> if your image name is
+not <b>main.bin</b></p>
<p><a name="lpc2888files"></a></p>
-<h2>Configuration files for LPC2888</h2>
+<h2>##Configuration files for LPC2888</h2>
<p>LPC2888 is quite a different animal. I couldn't find any "official"
LPC2888 configuration file for OpenOCD, so I had to learn how to write
my own. It works, but I suspect it can be improved. This time, the
configuration file applies to the latest (SVN) version of OpenOCD, so
-read this tutorial to understand how to get the latest OpenOCD sources
+use this tutorial to understand how to get the latest OpenOCD sources
and how to compile them (this section is based on version 922 of the
OpenOCD repository). Then use the next file to burn your binary image
to the chip:</p>
<p><a href="http://elua.berlios.de/other/lpc2888.cfg">lpc2888.cfg</a></p>
-<p>If your image name is not main.bin edit the file and change the
-corresponding line (flash write_bank 0 main.bin 0), then invoke openocd
+<p>If your image name is not <b>main.bin</b> edit the file and change the
+corresponding line (<i>flash write_bank 0 main.bin 0</i>), then invoke openocd
like this:</p>
-<pre><code>openocd -f lpc2888.cfg<br></code></pre>
+<p><pre><code>openocd -f lpc2888.cfg<br></code></pre></p>
-<p>I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
+<p>I'm using <a target="_blank" href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
from Olimex, but it should be easy to use the script with any other
JTAG adapter (don't forget to change the script to match your adapter).</p>
-<p><a name="str7files"></a></p>
-<h2>Configuration files for STR711FR2 (STR7 from ST)</h2>
+<h2><a name="str7files">##Configuration files for STR711FR2 (STR7 from ST)</a></h2>
<p>Download them below:</p>
@@ -265,24 +318,24 @@
<p><a href="http://elua.berlios.de/other/str7rst.cfg">str7rst.cfg</a></p>
-<p><a href="http://elua.berlios.de/other/str7_reset.script">str7_reset.scrip</a></p>
+<p><a href="http://elua.berlios.de/other/str7_reset.script">str7_reset.script</a></p>
<p>For STR7 I'm using the Yagarto OpenOCD build for Windows (repository
version 717, as described at the beginning of this tutorial). The
-str7prg.cfg configuration file is for prorgramming the STR9-comStick.
-str7rst.cfg is for resetting it. I'm using a STR711FR2 heard board from
-<a href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> to
+<b>str7prg.cfg</b> configuration file is for prorgramming the STR9-comStick.
+<b>str7rst.cfg</b> is for resetting it (you probably won't need this one). I'm using a STR711FR2 heard board from
+<a target="_blank" href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> to
which I attached a few LEDs and a MAX3232 TTL to RS232 converter for
the serial communication. The board comes with its own JTAG adadpter,
but it uses a parallel interface, and since my computer doesn't have
-one, I used the <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex. To use them, invoke the OpenOCD executable like this:</p>
+one, I used the <a target="_blank" href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex. To use them, invoke the OpenOCD executable like this:</p>
-<pre><code>openocd-ftd2xx -f str7prg.cfg<br></code></pre>
+<p><pre><code>openocd-ftd2xx -f str7prg.cfg<br></code></pre></p>
-<p>(note: under Windows, the OpenOCD executable name is often
+<p>(<b>note</b>: under Windows, the OpenOCD executable name is often
"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
-the actualy name with your executable.)
-Also, be sure to modify str7_flashprogram.script if your image name is
-not main.bin.</p><p></p><p></p><p></p><p> </p>
-</div></body></html>
\ No newline at end of file
+the actualy name with your executable).<br>
+Also, be sure to modify <b>str7_flashprogram.script</b> if your image name is
+not <b>main.bin</b></p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/tutorials.html
===================================================================
--- branches/eagle_mmc/doc/en/tutorials.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/tutorials.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,15 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Tutorials</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick"></a><span class="info">eLua Tutorials</span></h3><br></body></html>
\ No newline at end of file
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Tutorials</h3>
+<p>This section contains information about different tools and procedures related to <b>eLua</b>:
+<ul>
+ <li>building toolchains that can be used to build <b>eLua</b> itself.</li>
+ <li>running the standalone <b>eLua</b> (i386) version in different scenarios.</li>
+ <li>using OpenOCD to program <b>eLua</b> to various hardware platforms.</li>
+</ul></p>
+</body></html>
Modified: branches/eagle_mmc/doc/en/using.html
===================================================================
--- branches/eagle_mmc/doc/en/using.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/using.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,102 +1,219 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Using eLua</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
<body style="background-color: rgb(255, 255, 255);">
-<h3>Using eLua</h3><p> So, you already built and installed eLua, but now you don't know
-what to do with it. It's actually quite easy: all you need is your
-board connected to the computer and a terminal emulation program. If
-you're using Windows, I strongly recommend <a href="http://www.ayera.com/teraterm/">TeraTerm</a>.
-It's a freeware, it's very powerful and also easy to use. On Linux,
-you'll probably be stucked with minicom. It's not exactly intuitive,
-and it runs in text mode, but it's still very powerful, and if you
-google for "minicom tutorial" you'll get the hang of it in no time. Or
-you can try any other terminal emulator, as long as you set it up
-properly (and as long as it gives you the option of transferring files
-via XMODEM, which is what eLua uses at the moment). These are the main
+<h3>Using eLua</h3><p> So, you already <a href="building.html">built</a> and <a href="installing.html">installed</a> <b>eLua</b>, and now it is time to (finally) have some fun with it :)
+ You can compile <b>eLua</b> with either console over UART (by far the most popular) and console over TCP/IP (still experimental, but working quite well), so there are two different usage
+ scenarios for this (see <a href="building.html">building eLua</a> for details on how to select serial or TCP/IP console).</p>
+<a name="uart"><h3>Using eLua over serial connections</h3></a>
+<p>All you need to use <b>eLua</b> over a serial connection is your <b>eLua</b>
+board connected to a PC running a terminal emulator program.<br>If
+you're using Windows, I strongly recommend <a target="_blank" href="http://www.ayera.com/teraterm/">TeraTerm</a>.
+It's a freeware, it's very powerful and also easy to use. The native Hyper Terminal progam can do too, but give TeraTerm a chance, it's much better than HyperTerm IMO.<br>On
+Linux,
+you'll probably be stucked with minicom. It is not exactly intuitive
+and it runs in text mode, but it's still very powerful. If you
+google for "minicom tutorial" you'll get the hang of it in no time. You
+can try any other terminal emulator, as long as you set it up
+properly and it gives you the option of transferring files
+via XMODEM, which is what <b>eLua</b> uses at the moment. These are the main
settings you need to look at:</p>
-<ul><li>port setup: 115200 baud (38400 for <a href="http://www.eluaproject.net/en/eLua_on_STR7_CPUs">STR7</a>, 8N1(8 data bits, no parity, one stop bit). </li><li>flow control: none</li><li>newline handling: "CR" on receive, "CR+LF" on send (some terminal programs won't give you a choice here). </li></ul>
+<ul><li>port setup: 115200 baud (38400 for <a href="installing_str7.html">STR7)</a>, 8N1(8 data bits, no parity, one stop bit). </li><li>hardware flow control: none</li><li>newline handling: "CR" on receive, "CR+LF" on send (some terminal programs won't give you a choice here). </li></ul>
<p>Also, depending on the type of your board, you'll need some way to
-connect the board to a serial port on your PC, or to USB if you're
-using an USB to serial converter. For example, as already explained <a href="http://www.eluaproject.net/en/eLua_on_LM3S_CPUs">here</a>,
-the USB port on the LM3S7862 board is dual, so you can use it as an USB
+connect the board to a serial port on your PC or to USB if you're
+using an USB to serial converter. For example, as already explained <a href="installing_lm3s.html">here</a>,
+the USB port on the LM3Sxxxx boards is dual, so you can use it as an USB
to serial converter after downloading your firmware, thus you don't
need any other type of connection. The same is true for the
STR9-comStick board. On the other hand, for the SAM7-EX256 board you'll
need to connect a serial cable to the "RS232" connector, provided that
-the jumpers are already set as explained <a href="http://www.eluaproject.net/en/eLua_on_AT91SAM_CPUs">here</a>.</p>
+the jumpers are already set as explained <a href="installing_at91sam7x.html">here</a> and on the MOD711 you will need to add an RS232 converter chip.
+There's no universal rule here, it all depends on your board.
+</p>
+<a name="tcpip"><h3>Using eLua over TCP/IP connections</h3></a>
+<p>Things are even easier if you decide to enable console over TCP/IP:
+<ul>
+ <li>make sure you know the address of your board. If you enabled static IPs (see <a href="building.html">building</a>) remember what you chose for the static IP; if DHCP is used instead, your
+ DHCP server should've added the address of the <b>eLua</b> board to your DNS. The board name is always "elua", so if you execute "ping elua" from a shell you should see that the board is
+ alive.</li>
+ <li>telnet to the address of the board (or simply "telnet elua" if DHCP is used), and you'll be greeted with the shell prompt (if the shell is enabled, see the next paragraph for details).
+ Note that you can only have an active telnet session to the <b>eLua</b> board at a given time.</li>
+</ul>
+</p>
+<p>If you're under Windows, make sure you're using a proper telnet client, which basically means "just about everything <b>but</b> the build-in telnet client".
+ <a target="_blank" href="http://www.chiark.greenend.org.uk/~sgtatham/putty/">PuTTY</a> is a very good and popular choice.</p>
-<p>After you press the "RESET" button on your board, you should see the
-eLua shell prompt. Up to date documentation of how to use the shell is
-always included in the distribution (docs/the_elua_shell.txt). For your
-convenience, the shell documentation is also provided on this page.</p>
+<a name="pc"><h3>Using standalone eLua on PC</h3></a>
+<p>If you build <b>eLua</b> for the i386 platform, you can boot your PC directly in <b>eLua</b>! No underlying OS, nothing but plain <b>eLua</b>. It won't have any actual peripherals to
+access, but it can use the <b>term</b> module to run <i>hangman.lua</i> and <i>life.lua</i>, as well as other samples, which makes it a nice demo :) Follow <a href="installing_i386.html">
+this link</a> for specific informations about the i386 port. </p>
-<h2>The eLua shell</h2>
+<a name="shell"><h3><a name="shell"></a>The eLua shell</h3></a>
+<p>No matter what's your physical connection (serial, TCP/IP or you PC's monitor after booting <b>eLua</b>), after you setup the PC-<b>eLua</b> board connection (if applicable) and press
+ the "RESET" button on your board or simply press ENTER if you're using the serial connection, you should see the <b>eLua</b> shell prompt (if you enabled the shell in your build, as described <a href="building.html">here</a>). The shell is a simple
+ interactive command interpreter that allows you to:
+<ul>
+ <li>get help on shell usage with the help command</li>
+ <li>run the Lua interpreter in interactive mode just like you'd do on a desktop machine</li>
+ <li>run a Lua program from the eLua File System</li>
+ <li>upload a Lua source file via XMODEM and execute in on board</li>
+ <li>query the eLua version</li>
+ <li>list files on eLua file systems</li>
+</ul></p>
+<p>A detailed description of all the shell commands is given below.</p>
-<p>After you burn eLua to your board and you connect the board to your terminal
-emulator running on the PC, you'll be greeted with the eLua shell prompt, which
-allows you to:</p>
+<h2>help</h2>
+<p>Show a list of all shell commands.</p>
+<h2>ver</h2>
+<p>Print the version of the <b>eLua</b> image installed on the board. Currently, the version only increments for official releases, so if there's inter-release code in the
+development tree, this isn't reflected in the version number.</p>
+<h2>recv</h2>
-<ul><li>run 'lua' as you would run it from the Linux or Windows command prompt</li><li>upload a Lua source file via XMODEM and execute in on board</li><li>query the eLua version</li><li>get help on shell usage</li></ul>
-
-<p>To enable the shell, define BUILD_SHELL in your build.h file, and also
-BUILD_XMODEM if you want to use the "recv" command (see below). See
-docs/elua_components.txt for more details about enabling the shell.</p>
-
-<p>You'll need to configure your terminal emulation program to connect to your eLua
-board. These are the parameters you'll need to set for your serial connection:</p>
-
-<ul><li>speed 115200, 8N1 (8 data bits, no parity, one stop bit)</li><li>no flow control</li><li>newline handling (if available): CR on receive, CR+LF on send</li></ul>
-
-<p>After you setup your terminal program, press the RESET button on the bord.
-When you see the "eLua# " prompt, just enter "help" to see the on-line shell
-help:</p>
-
-<p>eLua# help<br>
-Shell commands:<br>
- help - print this help<br>
- lua [args] - run Lua with the given arguments<br>
- recv - receive a file (XMODEM) and execute it<br>
- ver - print eLua version<br>
- exit - exit from this shelll<br></p>
-
-<p>More details about some of the shell commands are presented below.</p>
-
-<h2>The "recv" command</h2>
-
-<p>To use this, your eLua taret image must be built with support for XMODEM (see
-docs/elua_components.txt for details). Also, your terminal emulation program must
-support sending files via the XMODEM protocol. Both XMODEM with checksum (the
-original version) and XMODEM with CRC are supported, but only XMODEM with 128
+<p>Allows you to receive a Lua file (either source or compiled bytecode) via
+XMODEM and execute it on your board. To use this, your <b>eLua</b> taret image must be built with support for XMODEM
+(see <a href="building.html">building</a> for details).Also, your terminal emulation program must
+support sending files via the XMODEM protocol. Both XMODEM with checksum and XMODEM with CRC are supported, but only XMODEM with 128
byte packets is allowed (XMODEM with 1K packets won't work).
To use this feature, enter "recv" at the shell prompt. eLua will respond with
"Waiting for file ...". At this point you can send the file to the eLua board
via XMODEM. eLua will receive and execute the file. Don't worry when you see 'C'
characters suddenly appearing on your terminal after you enter this command,
-this is how the XMODEM transfer is initiated.</p>
+this is how the XMODEM transfer is initiated.<br>
+Since XMODEM is a protocol that uses serial lines, this command is not available if you're using terminal over TCP/IP.<br>
+If you'd like to send compiled bytecode to <b>eLua</b> instead of source code, please check <a href="using.html#cross">this section</a> first.
+</p>
-<h2>The "lua" command</h2>
+<h2>lua</h2>
-<p>This allows you to start the Lua interpreter with command line parameters, just
-as you would do from a Linux or Windows command prompt. This command has some
+<p>This allows you to start the Lua interpreter, optionally passing command line parameters, just
+as you would do from a desktop machine. The command has some
restrictions:</p>
-<ul><li>the command line can't be longer than 50 chars</li><li>character escaping is not implemented. For example, the next command won't work
- because of the ' escape sequences:</li></ul>
+<ul><li>the command line can't be longer than 50 chars</li>
+<li>character escaping is not implemented. For example, the next command won't work
+ because of the ' (simple quotes) escape sequences:
-<p>eLua# lua -e 'print('Hello, World!')' -i<br>
+<p><pre><code>eLua# lua -e 'print(\'Hello, World!\')' -i<br>
Press CTRL+Z to exit Lua<br>
-lua: (command line):1: unexpected symbol near ''<br></p>
+lua: (command line):1: unexpected symbol near ''</code></pre></p>
-<p>However, if you use both '' and "" for string quoting, it will work:</p>
+<p>However, if you use both '' (simple quotes) and "" (double quotes) for string quotin , it will work:</p>
-<p>eLua# lua -e 'print("Hello, World")' -i<br>
-Press CTRL+Z to exit Lua<br>
+<p><pre><code>eLua# lua -e 'print("Hello, World")' -i
+Press CTRL+Z to exit Lua
Lua 5.1.4 Copyright (C) 1994-2008 Lua.org, PUC-Rio
-Hello,World</p>
-</body></html>
\ No newline at end of file
+Hello,World</code></pre></p></li></ul>
+<p>If you want to execute a file from the <a href="">##ROM file system</a>, remember to prefix it with <i>/rom</i>. For example, to execute <b>hello.lua</b>, do this:</p>
+<p><pre><code>$ lua /rom/hello.lua</code></pre></p>
+<h2>ls or dir</h2>
+<p>Shows a list of all the files in the filesystems used by <b>eLua</b> (currently only the ROM file system), as well as their size and the total size of the given file system.</p>
+<h2>exit</h2>
+<p>Exits the shell. This only makes sense if <b>eLua</b> is compiled with terminal support over TCP/IP , as it closes the telnet session to the <b>eLua</b> board. Otherwise it just
+ terminates the shell and blocks forever until you reset your board.</p>
+<a name="cross"><h3>Cross-compiling your eLua programs</h3></a>
+<p><i>Cross-compilation</i> is the process of compiling a program on one hardware platform for a
+different hardware platform. For example, the process of compiling the <b>eLua</b> binary image on
+a PC for your <b>eLua</b> board is cross-compiling. Lua can be cross-compiled, too. By cross-compiling Lua
+to bytecode on a PC and executing the resulting bytecode directly on your <b>eLua</b>
+board you have some important advantages:
+<ul>
+<li><b>speed</b>: the Lua compiler on the <b>eLua</b> board doesn't have to compile your Lua
+ source code, it just executes the compiled bytecode.</li>
+<li><b>memory</b>: f you're executing bytecode directly, no more
+ memory is "wasted" on the <b>eLua</b> board for compiling the Lua code to bytecode.
+ Many times this could be a "life saver". If you're trying to run Lua code
+ directly on your board and you're getting "not enough memory" errors, you
+ might be able to overcome this by compiling the Lua program on the PC and
+ running the bytecode instead. Also, compiling large Lua programs on your
+ <b>eLua</b> board can lead to stack overflows, which in turn leads to very
+ hard to find errors.</li>
+</ul></p>
+<p>In order to use cross-compilation, the two Lua targets (in this case your desktop PC and your <b>eLua</b> board) must be compatible
+(they should have the same data types, with the same size and the same memory
+representation). This isn't true all the time. For example, some gcc toolchains for ARM targets use a very specific representation for double precision numbers (called FPA
+format) by default, which makes bytecode files generated on the PC with the regular Lua compiler useless on
+ARM boards. Other toolchains don't have this problem. Other targets (like AVR32) are big endian, as opposed to Intel PCs that are little endian.<br>
+To overcome this kind of problems, a "Lua cross-compilation patch" was posted on the
+Lua mailing list a while ago, and it was further modified as part of the <b>eLua</b>
+project to work with ARM targets. This is how to use it (the following
+instructions were tested on Linux, not Windows, but they should work on Windows
+too with little or no tweaking):
+<ul>
+<li>first, make sure that your PC has already a build system intalled (gcc,
+ binutils, libc, headers...). You'll also need scons. The good news is that
+ you should have it already installed, since otherwise you won't be able to
+ build even regular <b>eLua</b> (see <a href="building.html">building</a> for more in-depth instructions).</li>
+<li>from the <b>eLua</b> base directory, issue this command:</li>
+ <p><pre><code>$ scons -f cross-lua.py</code></pre></p></ul>
+<p>You should get a file called <i>luac</i> in the same directory after this. It's almost the same as the regular Lua compiler, but it has a few arguments that deal with differences between
+different targets (shown below in bold):</p>
+<p><pre><code>usage: ./luac [options] [filenames].
+Available options are:
+- process stdin
+-l list
+-o name output to file 'name' (default is "luac.out")
+-p parse only
+-s strip debug information
+-v show version information
+<b>-cci bits cross-compile with given integer size
+-ccn type bits cross-compile with given lua_Number type and size
+-cce endian cross-compile with given endianness ('big' or 'little')</b>
+-- stop handling options</code></pre></p>
+<p>All it's left to do now is to use the table below to figure out what are the right parameters for using the cross-compiler:</p>
+</p><table style="text-align: left;" class="table_center">
+<tbody>
+<tr>
+ <th style="text-align: left;">eLua image type</th>
+ <th style="text-align: center;">Architecture</th>
+ <th style="text-align: center;">Compiler</th>
+ <th style="text-align: center;">Command</th>
+</tr>
+<tr>
+ <td>Floating point (lua)</td>
+ <td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
+ <td><a href="toolchains.html">arm-gcc</a>
+ <td><code>./luac -ccn float_arm 64 -cce little -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Floating point (lua)</td>
+ <td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
+ <td><a href="toolchains.html">codesourcery</a>
+ <td><code>./luac -ccn float 64 -cce little -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Integer (lualong)</td>
+ <td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
+ <td><a href="toolchains.html">arm-gcc<br>codesourcery</a>
+ <td><code>./luac -ccn int 32 -cce little -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Floating point (lua)</td>
+ <td>AVR32</td>
+ <td><a href="toolchains.html">avr32-gcc</a>
+ <td><code>./luac -ccn float 64 -cce big -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Integer (lualong)</td>
+ <td>AVR32</td>
+ <td><a href="toolchains.html">avr32-gcc</a>
+ <td><code>./luac -ccn int 32 -cce big -o <script.luac> -s <script.lua></code></td>
+</tr>
+</tbody>
+</table>
+<p>(note that if for some reason you want to cross-compile <b>eLua</b> for the x86 target you can use the regular Lua compiler).<br>
+You can omit the <i>-s</i> (strip) parameter from compilation, but this will result in larger bytecode files (as the debug information is not stripped if you don't use <i>-s</i>).</p>
+<p>You can use your bytecode file in two ways:</p>
+<ul>
+ <li>write it to <a href="arch_romfs.html">the ROM file system</a> and execute it from there.</li>
+ <li>use the <i>recv</i> command from <a href="using.html#shell">the shell</a> to upload it to the board using a serial connection.</li>
+</ul>
+<p>
+</p>
+</body></html>
+
Modified: branches/eagle_mmc/doc/en/versionhistory.html
===================================================================
--- branches/eagle_mmc/doc/en/versionhistory.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/en/versionhistory.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,9 +1,90 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>eLua version history</title>
<link rel="stylesheet" type="text/css" href="../style.css"></head>
-<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Using_OpenOCD" class="local"></a>eLua Version's History</h3>
-
- <div class="content"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span><br></div></body></html>
\ No newline at end of file
+<body style="background-color: rgb(255, 255, 255);">
+<h3>eLua version history</h3>
+<p>The table below presents the history of all official <b>eLua</b> releases (in reversed order, newest to oldest).</p>
+
+</p><table style="text-align: left" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Version</th>
+<th style="text-align: center;">Release date</th>
+<th style="text-align: center;">Description</th>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.5</td>
+ <td align="center">01.11.2008</td>
+ <td><ul>
+ <li>Added support for STR7 CPUs from ST</li>
+ <li>Added TCP/IP support using the uIP stack</li>
+ <li>Added support for console and shell over TCP/IP besides the previous serial link</li>
+ <li>Added the "net" module (eLua's interface to TCP/IP functions)</li>
+ <li>Added the "cpu" module (eLua's interface to the target CPU)</li>
+ <li>New samples: morse.lua (Morse code encoder), lhttpd.lua (Lua scripting HTTP server)</li>
+ <li>Added support for cross-compiling Lua code (compile on PC, run on target)</li>
+ <li>XMODEM can now receive Lua bytecode in addition to Lua source code</li>
+ <li>The XMODEM buffer is now dynamic (grows as needed) instead of fixed size</li>
+ <li>Project documentation updated</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.4.1</td>
+ <td align="center">10.09.2008</td>
+ <td><ul>
+ <li>changed from Lua version 5.1.3 to Lua version 5.1.4</li>
+ <li>Changed the file system structure; now you can build both Lua versions (floating point and int only) from the same directory</li>
+ <li>Made the math library configurable using the existent 'platform libraries' mechanism</li>
+ <li>The "os" and "package" modules are no longer loaded by Lua, since they can't be used anyway. Because of this, the code size of eLua was reduced.</li>
+ <li>Project documentation updated</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.4</td>
+ <td align="center">02.09.2008</td>
+ <td><ul>
+ <li>Added support for LPC2888 (preliminary)</li>
+ <li>Added PWM module</li>
+ <li>New samples: TV-B-Gone (power off your TV), piano (play piano from your PC keyboard), pwmled (fade led on/off), all based on the new PWM module</li>
+ <li>Added support for multiple memory spaces (this can be used to take advantage of both the internal CPU RAM and external RAM chips on boards that have external RAM)</li>
+ <li>Autorun: if "autorun.lua" is found in the filesystem, it is executed before starting the shell</li>
+ <li>Added "pack" (binary data packing/unpacking) and "bit" (binary operations) modules</li>
+ <li>Build system updated, easier to use, now it knows how to handle "boards" as well as CPUs</li>
+ <li>Modified the existing platform modules to take less RAM and to report an error when an unavailable resource is requested</li>
+ <li>Project documentation updated</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.3</td>
+ <td align="center">09.08.2008</td>
+ <td><ul>
+ <li>Now you can play hangman directly from <b>eLua</b> :), thanks to the new "term" module that handles ANSI escape sequences</li>
+ <li>Added support for ST STR912FAW44</li>
+ <li>Added support for Cortex LM3S6965</li>
+ <li>More intuitive and flexible build system (new syntax, component selection at build time)</li>
+ <li>eLua examples are now part of the repository</li>
+ <li>Project documentation updated</li>
+</ul></td>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.2</td>
+ <td align="center">27.08.2008</td>
+ <td><ul>
+ <li>Added support for Cortex LM3S8962</li>
+ <li>New platform modules (UART, SPI, Timer, platform data)</li>
+ <li>First release of the shell</li>
+ <li>Lua source files can now be sent to target with XMODEM</li>
+ <li>You can download binary file images from the "files" section, so you don't need to compile <b>eLua</b> yourself</li>
+</ul></td>
+</tr>
+</tr>
+<tr>
+ <td align="center" style="color: rgb(255, 102, 0);">0.1</td>
+ <td align="center">11.08.2008</td>
+ <td><ul><li>Initial release, had support for i386 and AT91SAM7X platform</li></ul></td>
+</tr>
+</tbody>
+</table>
+</body></html>
Deleted: branches/eagle_mmc/doc/index_en.html
===================================================================
--- branches/eagle_mmc/doc/index_en.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/index_en.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,28 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
-<title>eLua Doc</title>
-</head>
-
-<frameset rows="80,*" frameborder="0" framespacing="0" bordercolor="#0B6DCE">
- <frame name="wb_title" scrolling="no" noresize="noresize" src="wb_title_en.html"
- frameborder="0" marginheight="0" marginwidth="0" target="wb_cont">
- <frameset cols="200,*" frameborder="1" framespacing="4" bordercolor="#0B6DCE" border="4">
- <frameset rows="27,*" frameborder="0" framespacing="0" bordercolor="#0B6DCE">
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- <frame name="wb_tree" src="wb_tree_en.html" frameborder="1" target="wb_cont">
- </frameset>
- <frame name="wb_cont" src="en/news.html" frameborder="0">
- </frameset>
- <noframes>
- <body>
-
- <p>This page uses frames, but your browser doesn't support them.</p>
-
- </body>
- </noframes>
-</frameset>
-
-</html>
Deleted: branches/eagle_mmc/doc/index_pt.html
===================================================================
--- branches/eagle_mmc/doc/index_pt.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/index_pt.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,28 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
-<title>eLua Doc</title>
-</head>
-
-<frameset rows="80,*" frameborder="0" framespacing="0" bordercolor="#0B6DCE">
- <frame name="wb_title" scrolling="no" noresize="noresize" src="wb_title_pt.html"
- frameborder="0" marginheight="0" marginwidth="0" target="wb_cont">
- <frameset cols="200,*" frameborder="1" framespacing="4" bordercolor="#0B6DCE" border="4">
- <frameset rows="27,*" frameborder="0" framespacing="0" bordercolor="#0B6DCE">
- <frame name="wb_bar" scrolling="no" src="wb_bar_pt.html" frameborder="0" target="wb_cont">
- <frame name="wb_tree" src="wb_tree_pt.html" frameborder="1" target="wb_cont">
- </frameset>
- <frame name="wb_cont" src="pt/news.html" frameborder="0">
- </frameset>
- <noframes>
- <body>
-
- <p>This page uses frames, but your browser doesn't support them.</p>
-
- </body>
- </noframes>
-</frameset>
-
-</html>
Added: branches/eagle_mmc/doc/luadoc/arch_platform_adc.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_adc.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_adc.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,65 @@
+-- eLua platform interface - ADC
+-- Make a full description for each language
+
+data_en =
+{
+ -- Menu name
+ menu_name = "ADC",
+
+ -- Title
+ title = "eLua platform interface - ADC",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the ADC interface(s) of the MCU.",
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_adc_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware ADC specified as argument. Implemented in %src/common.c%, it uses the $NUM_ADC$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_ADC 1 $// The platform has 1 ADC interface$~</p> ]],
+ args = "$id$ - SPI interface ID",
+ ret = "1 if the SPI interface exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_adc_op#( unsigned id, int op, u32 data );",
+ desc = "Executes an operation on an ADC channel",
+ args =
+ {
+ "$id$ - ADC channel ID",
+ [[$op$ - the operation that must be executed. It can take any value from @#adc_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_ADC_GET_MAXVAL$: get the maximum conversion value the channel may supply (based on channel resolution)</li>
+ <li>$PLATFORM_ADC_SET_SMOOTHING$: sets the length of the moving average smoothing filter to $data$ </li>
+ <li>$PLATFORM_ADC_SET_BLOCKING$: sets whether or not sample requests should block, waiting for additional samples</li>
+ <li>$PLATFORM_ADC_IS_DONE$: checks whether sampling has completed</li>
+ <li>$PLATFORM_ADC_OP_SET_TIMER$: selects a timer to control sampling frequency</li>
+ <li>$PLATFORM_ADC_OP_SET_CLOCK$: set the frequency of sample acquisition</li>
+ </ul>]],
+ "$data$ - when used with $op$ == $PLATFORM_ADC_SET_SMOOTHING$, specifies the length of the moving average filter (must be a power of 2). If it is 1, filter is disabled.",
+ "$data$ - when used with $op$ == $PLATFORM_ADC_SET_BLOCKING$, specifies whether or not sample requests block. If 1, requests will block until enough samples are available or sampling has ended. If 0, requests will return immediately with up to the number of samples requested.",
+ "$data$ - when used with $op$ == $PLATFORM_ADC_OP_SET_TIMER$, specifies the timer to use to control sampling frequency.",
+ "$data$ - when used with $op$ == $PLATFORM_ADC_OP_SET_CLOCK$, specifies the frequency of sample collection in Hz (number of samples per second). If 0, timer is not used and samples are acquired as quickly as possible."
+ },
+ ret =
+ {
+ "the maximum possible conversion value when $op$ == $PLATFORM_ADC_GET_MAXVAL$",
+ "whether or not sampling has completed (1: yes, 0: no) when $op$ == $PLATFORM_ADC_IS_DONE$. This will return 1 (yes), if no samples have been requested.",
+ "the actual frequency of acquisition that will be used when $op$ == $PLATFORM_ADC_OP_SET_CLOCK$",
+ "irellevant for other operations"
+ }
+ },
+
+ { sig = "int #platform_adc_check_timer_id#( unsigned id, unsigned timer_id );",
+ desc = "Checks whether a timer may be used with a particular ADC channel",
+ args =
+ {
+ "$id$ - ADC channel ID",
+ "$timer_id$ - Timer ID",
+ },
+ ret = "1 if the timer may be used to trigger the ADC channel, 0 if not",
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_cpu.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_cpu.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_cpu.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,31 @@
+-- eLua platform interface - CPU
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - CPU",
+
+ -- Menu name
+ menu_name = "CPU",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the CPU and its functional modules (interrupt controller, memory controller and others).",
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #platform_cpu_enable_interrupts#();",
+ desc = "Enable global interrupt on the CPU."
+ },
+
+ { sig = "void #platform_cpu_disable_interrupts#();",
+ desc = "Disable global interrupts on the CPU."
+ },
+
+ { sig = "u32 #platform_cpu_get_frequency#();",
+ desc = "Get the CPU frequency.",
+ ret = "the CPU $core$ frequency (in hertz)."
+ },
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_eth.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_eth.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_eth.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,95 @@
+-- eLua platform interface - Ethernet support
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - Ethernet support",
+
+ -- Menu name
+ menu_name = "Ethernet",
+
+ -- Overview
+ overview = [[<font color="red">$NOTE$: TCP/IP support is experimental in eLua. Although functional, it's quite incomplete at the moment.</font></p>
+ <p>This part of the platform interface groups functions related to accessing the Ethernet interface (internal or external) of the CPU. Note that unlike the
+ other parts of the platform interface this one is dedicated for TCP/IP support and thus it does not correspond directly to an eLua module, although
+ the @##@net module@ is implemented with functions that rely on this part of the platform interface. Currently only
+ the ^http://www.sics.se/~~adam/uip/index.php/Main_Page^uIP^ TCP/IP stack is supported by eLua.</p>
+ <p>uIP is implemented in eLua using two hardware interrupts (that should be available on your platform): the Ethernet receive interrupt (to handle
+ incoming packets) and a timer interrupt (timers are used internally by uIP). However, the uIP main loop is only called from the Ethernet interrupt handler
+ in eLua, so in order to acknowledge the timer interrupt (as well as to provide some optimizations) a function that "forces" an Ethernet interrupt
+ must also be provided by the platform interface (see @#platform_eth_force_interrupt at here@ for details).</p>
+ <p>To put everything together, part of the Ethernet platform interface for the $lm3s$ platform is given below:</p>
+ ~u32 platform_eth_get_elapsed_time()
+ {
+ if( eth_timer_fired )
+ {
+ eth_timer_fired = 0;
+ return SYSTICKMS;
+ }
+ else
+ return 0;
+ }
+
+ void SysTickIntHandler()
+ {
+ // Handle virtual timers
+ cmn_virtual_timer_cb();
+
+ // Indicate that a SysTick interrupt has occurred.
+ eth_timer_fired = 1;
+
+ // Generate a fake Ethernet interrupt. This will perform the actual work
+ // of incrementing the timers and taking the appropriate actions.
+ <b>platform_eth_force_interrupt();</b>
+ }
+
+ void EthernetIntHandler()
+ {
+ u32 temp;
+
+ // Read and Clear the interrupt.
+ temp = EthernetIntStatus( ETH_BASE, false );
+ EthernetIntClear( ETH_BASE, temp );
+
+ // Call the UIP main loop
+ <b>elua_uip_mainloop();</b>
+ }~<p>]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #platform_eth_send_packet#( const void* src, u32 size )",
+ desc = "Sends an Ethernet packet to the network",
+ args =
+ {
+ "$src$ - start address of the Ethernet packet",
+ "$size$ - size of the Ethernet packet"
+ },
+ },
+
+ { sig = "u32 #platform_eth_get_packet_nb#( void* buf, u32 maxlen );",
+ desc = "Non-blocking read of an Ethernet packet from the network",
+ args =
+ {
+ "$buf$ - start address of the receive buffer",
+ "$maxlen$ - maximum length of the Ethernet packet",
+ },
+ ret = "the size of the read packet or 0 if no packet is available"
+ },
+
+ { sig = "void #platform_eth_force_interrupt#();",
+ desc = "Force the Ethernet interrupt on the platform (see @#overview at overview@ above for details)",
+ },
+
+ { sig = "u32 #platform_eth_get_elapsed_time#();",
+ desc = [[Get the elapsed time (in ms) since the last invocation of the uIP main loop ($elua_uip_mainloop$, from which this function is called). See @#overview at overview@ for a possible
+ implementation of this function).]],
+ ret =
+ {
+ "0 if the uIP loop was called because of Ethernet activity, not because a timer expired",
+ "the Ethernet timer perios in ms (which indicates timer activity)"
+ },
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_ll.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_ll.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_ll.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,86 @@
+-- eLua platform interface - low level functions
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - low level functions",
+
+ -- Menu title
+ menu_name = "Low-level",
+
+ -- Overview
+ overview = [[
+ This part of the platform interface deals contains a small set of "low level functions" that are used to "couple" the eLua port with the
+ target system. No eLua module exposes these functions, as they are strictly used for porting and do not provide any other functionality.
+ ]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// Error / status codes
+enum
+{
+ PLATFORM_ERR,
+ PLATFORM_OK,
+ PLATFORM_UNDERFLOW = -1
+};]],
+ name = "Status codes",
+ desc = [[
+ This enum defines the possible return values of the @#platform_init at platform_init@ function (although only $PLATFORM_ERR$ and $PLATFORM_OK$ should be
+ returned from $platform_init$).
+ ]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_init#();",
+ desc = [[This is the platform-specific initialization code. It is the first function called from %main()% ($src/main.c$) and it should handle
+ all the platform initialization sequence, included (but not limited to) setting up the proper clocks, initializing the interrupt subsystem,
+ setting up various peripherals and so on. Although platform specific, this function has a common part named %cmn_platform_init% (implemented
+ in $src/common.c$) that initializes terminal support over serial connections, as well as the XMODEM and TERM components
+ (see @building.html at here@ for details). If you need any of these, you need to call %cmn_platform_init% at the end of your
+ %platform_init% function, $after$ initializing all the peripherals (in particular the UART used for the serial connection).<br>
+ An implementation skeleton for this function is given below:</p>
+ ~int platform_init()
+ {
+ ............. // perform all your initializations here
+ cmn_platform_init(); // call the common initialiation code
+ return PLATFORM_OK;
+ }~<p>]],
+ ret =
+ {
+ "$PLATFORM_OK$ for success",
+ [[$PLATFORM_ERR$ if an error occured. If $PLATFORM_ERR$ is returned, %main% will block in an infinite loop right
+ after calling this function, so you should return $PLATFORM_ERR$ only for serious errors]],
+ },
+ },
+
+ { sig = "void* #platform_get_last_free_ram#( unsigned id );",
+ desc = [[Returns the start address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(),
+ a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external
+ RAM chips). Implemented in $src/common.c$, it uses the the $MEM_START_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$
+ file (see @arch_overview.html#platforms at here@ for details). This macro must be defined as an array that contains all the start addresses of
+ free RAM in the system. For internal RAM, this is generally handled by a linker exported symbol (named $end$ in many eLua ports) which
+ points to the firs RAM address after all the constant and non-constant program data. An example is given below:</p>
+ ~#define MEM_START_ADDRESS { ( void* )end }~<p>]],
+ args = "$id$ - the identifier of the RAM area",
+ ret = "the start address of the given memory area",
+ },
+
+ { sig = "void* #platform_get_last_free_ram#( unsigned id );",
+ desc = [[Returns the last address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(),
+ a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external
+ RAM chips). Implemented in $src/common.c$, it uses the the $MEM_END_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$
+ file (see @arch_overview.html#platforms at here@ for details). This macro must be defined as an array that contains all the end addresses of
+ free RAM in the system. For internal RAM, this is generally set as the last RAM memory address minus the size of the system stack(s). An example is
+ given below:</p>
+ ~#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + 0x10000 - STACK_SIZE_TOTAL - 1 ) }~<p>]],
+ args = "$id$ - the identifier of the RAM area",
+ ret = "the end address of the given memory area",
+ },
+
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_pio.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_pio.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_pio.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,107 @@
+-- eLua platform interface - PIO
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - PIO",
+
+ -- Menu name
+ menu_name = "PIO",
+
+ -- OverviewA
+ overview = "This part of the platform interface deals with PIO (Programmable Input Output) operations, thus letting the user access the low level input/output facilities of the host MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[enum
+{
+ // Pin operations
+ PLATFORM_IO_PIN_SET, $// Set the pin to 1$
+ PLATFORM_IO_PIN_CLEAR, $// Clear the pin (set it to 0)$
+ PLATFORM_IO_PIN_GET, $// Get the value of the pin$
+ PLATFORM_IO_PIN_DIR_INPUT, $// Make the pin an input$
+ PLATFORM_IO_PIN_DIR_OUTPUT, $// Make the pin an output$
+ PLATFORM_IO_PIN_PULLUP, $// Activate the pullup on the pin$
+ PLATFORM_IO_PIN_PULLDOWN, $// Activate the pulldown on the pin$
+ PLATFORM_IO_PIN_NOPULL, $// Disable all pullups/pulldowns on the pin$
+ // Port operations
+ PLATFORM_IO_PORT_SET_VALUE, $// Set port value$
+ PLATFORM_IO_PORT_GET_VALUE, $// Get port value$
+ PLATFORM_IO_PORT_DIR_INPUT, $// Set port as input$
+ PLATFORM_IO_PORT_DIR_OUTPUT $// Set port as output$
+}; ]],
+ name = "PIO operations",
+ desc = [[These are the operations that can be executed by the PIO subsystem on both ports and pins. They are given as arguments to the @#platform_pio_op at platform_pio_op@ function
+ shown below. ##TODO: document read in/read out if we keep that]]
+ },
+
+ { text = "typedef u32 pio_type;",
+ name = "PIO data type",
+ desc = [[This is the type used for the actual I/O operations. Currently defined as an unsigned 32-bit type, thus no port can have more than 32 pins. If this happens, it is possible to split
+ it in two or more parts and adding the new parts as "virtual ports" (logical ports that don't have a direct hardware equivalent). The "virtual port" technique is used in the AVR32 backend.]]
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_pio_has_port#( unsigned port );",
+ desc = [[Checks if the platform has the hardware port specified as argument. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_PIO 4 $// The platform has 4 hardware PIO ports$~<p> ]],
+ args = "$port$ - the port ID",
+ ret = "1 if the port exists, 0 otherwise",
+ },
+
+ { sig = "int #platform_pio_has_pin#( unsigned port, unsigned pin );",
+ desc = [[Checks if the platform has the hardware port and pin specified as arguments. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro to check the validity
+ of the port and the $PIO_PINS_PER_PORT$ or $PIO_PIN_ARRAY$ macros to check the validity of the pin. The macros must be defined in the platform's $platform_conf.h$ file
+ (see @arch_overview.html#platforms at here@ for details).
+ <ul>
+ <li>use $PIO_PINS_PER_PORT$ when all the ports of the MCU have the same number of pins. For example:
+ ~#define PIO_PINS_PER_PORT 8 $// Each port has 8 pins$~</li>
+ <li>use $PIO_PIN_ARRAY$ when different ports of the MCU have different number of pins. For example:
+ ~#define PIO_PIN_ARRAY { 4, 4, 2, 6 } $// Port 0 has 4 pins, port 1 has 4 pins, port 2 has 2 pins, port 3 has 6 pins$~</li>
+ </ul>]],
+ args =
+ {
+ "$port$ - the port ID",
+ "$pin$ - the pin number"
+ },
+ ret = "1 if the pin exists, 0 otherwise",
+ },
+
+ { sig = "const char* #platform_pio_get_prefix#( unsigned port );",
+ desc = [[Get the port prefix. Used to establish if the port notation uses numbers (P0, P1, P2...) or letters (PA, PB, PC...). Implemented in %src/common.c%, it uses the
+ $PIO_PREFIX$ macro that must be defined in the platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). The value of this macro can be either '0' (for
+ numeric notation) or 'A' (for letter notation). For example:
+ ~#define PIO_PREFIX 'A' $// Use PA, PB, PC ... for port notation$~<p>]],
+ args = "$port$ - the port ID",
+ ret = "the port prefix (either '0' or 'A')",
+ },
+
+ { sig = "pio_type #platform_pio_op#( unsigned port, pio_type pinmask, int op );",
+ link = "platform_pio_op",
+ desc = "This is the function that does the actual I/O work. It is implemented in the platform's own porting layer (%platform.c%, see @arch_overview.html#ports at here@ for more details).",
+ args =
+ {
+ "$port$ - the port number",
+ [[$pinmask$ - has different meanings:
+ <ul>
+ <li>for $pin operations$ it is the mask of pins in the operation. Each pin on which the function action is executed is encoded with an 1 in the corresponding bit position
+ of the pinmask.</li>
+ <li>for $port operations$ it is only meaningful for $PLATFORM_IO_PORT_SET_VALUE$ and in this case it specifies the new value of the port.</li>
+ </ul>]],
+ "$op$ - specifies the I/O operations, as specified @#pio_operations at here@."
+ },
+ ret =
+ {
+ "an actual value for $PLATFORM_IO_PIN_GET$ (0 or 1) and $PLATFORM_IO_PORT_GET$ (the value of the port).",
+ [[an error flag for all the other operations: 1 if the operation succeeded, 0 otherwise. For example, a platform that doesn't have pulldowns on its ports will always return a 0
+ when caled with the $PLATFORM_IO_PIN_PULLDOWN$ operation.]]
+ }
+ },
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_pwm.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_pwm.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_pwm.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,76 @@
+-- eLua platform interface - PWM
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - PWM",
+
+ -- Menu name
+ menu_name = "PWM",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the PWM channel(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// PWM operations
+enum
+{
+ PLATFORM_PWM_OP_START,
+ PLATFORM_PWM_OP_STOP,
+ PLATFORM_PWM_OP_SET_CLOCK,
+ PLATFORM_PWM_OP_GET_CLOCK
+} ]],
+ name = "PWM operations",
+ desc = "This enum lists all the operations that can be executed on a given PWM channel."
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_pwm_exists#( unsigned id );",
+ desc = [[Checks if the platform has the PWM channel specified as argument. Implemented in %src/common.c%, it uses the $NUM_PWM$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_PWM 4 $// The platform has 4 PWM channels$~<p> ]],
+ args = "$id$ - PWM channel ID",
+ ret = "1 if the specified PWM channel exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_pwm_setup#( unsigned id, u32 frequency, unsigned duty );",
+ desc = "Sets up a PWM channel",
+ args =
+ {
+ "$id$ - PWM channel ID",
+ "$frequency$ - PWM channel frequency (in hertz)",
+ "$duty$ - PWM channel duty cycle, specified as percent (from 0 to 100). Note that some platform don't allow the full 0%-100% duty cycle"
+ },
+ ret = "The actual frequency set on the PWM channel, which might differ from the $frequency$ parameter, depeding on the hardware",
+ },
+
+ { sig = "u32 #platform_pwm_op#( unsigned id, int op, u32 data );",
+ desc = "Executes an operation on a PWM channel",
+ args =
+ {
+ "$id$ - PWM channel ID",
+ [[$op$ - the operation that must be executed. It can take any value from @#pwm_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_PWM_OP_START$: starts PWM generation on the specified channel.</li>
+ <li>$PLATFORM_PWM_OP_STOP$: stops PWM generation on the specified channel.</li>
+ <li>$PLATFORM_PWM_OP_SET_CLOCK$: sets the $base$ clock of the specified PWM channel (which will be used to generate the frequencies requested by
+ @#platform_pwm_setup at platform_pwm_setup@) to $data$ hertz.</li>
+ <li>$PLATFORM_PWM_OP_GET_CLOCK$: get the $base$ clock of the specified PWM channel.</liA>
+ </ul>]],
+ "$data$ - when used with $op$ == $PLATFORM_PWM_OP_SET_CLOCK$ it is used to specify the value of the base clock. Not used with other operations."
+ },
+ ret =
+ {
+ "the actual value of the base clock when $op$ == $PLATFORM_PWM_OP_SET_CLOCK$, which might be different than $data$ depending on the hardware",
+ "the value of the base clock when $op$ == $PLATFORM_PWM_OP_GET_CLOCK$",
+ "irellevant for other operations"
+ }
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_spi.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_spi.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_spi.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,84 @@
+-- eLua platform interface - SPI
+-- Make a full description for each language
+
+data_en =
+{
+ -- Menu name
+ menu_name = "SPI",
+
+ -- Title
+ title = "eLua platform interface - SPI",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the SPI interface(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// SPI mode
+#define PLATFORM_SPI_MASTER 1
+#define PLATFORM_SPI_SLAVE 0 ]],
+ name = "Chip select",
+ desc = "Constants used to select/deselect the SPI SS pin (if applicable)."
+ },
+
+ { text = [[// SS values
+#define PLATFORM_SPI_SELECT_ON 1
+#define PLATFORM_SPI_SELECT_OFF 0]],
+ name = "SPI mode",
+ desc = "Constants used to select/deselect the SPI SS pin (if applicable)."
+ },
+
+ { text = "typedef u32 spi_data_type;",
+ name = "SPI data type",
+ desc = "This is the type of a SPI data word, thus limiting the maximum size of a SPI data work to 32 bits (which should be enough for all practical purposes)."
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_spi_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware SPI specified as argument. Implemented in %src/common.c%, it uses the $NUM_SPI$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_SPI 1 $// The platform has 1 SPI interface$~</p> ]],
+ args = "$id$ - SPI interface ID",
+ ret = "1 if the SPI interface exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_spi_setup#( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits );",
+ desc = [[This function is used to initialize the parameters of the SPI interface. <br><font color="red">$NOTE$</font>: currently, only master SPI mode is implemented in eLua.]],
+ args =
+ {
+ "$id$ - SPI interface ID",
+ "$mode$ - SPI port mode ($PLATFORM_SPI_MASTER$ or $PLATFORM_SPI_SLAVE$, see @#spi_mode at here@.",
+ "$clock$ - clock speed for the SPI interface in master mode.",
+ "$cpol$ - SPI clock polarity",
+ "$cpha$ - SPI clock phase",
+ "$databits$ - length of the SPI data word in bits (usually 8, but configurable on some platforms)."
+ },
+ ret = "the actual clock set for the SPI interface. Depending on the hardware, this may have a different value than the $clock$ argument."
+ },
+
+ { sig = "spi_data_type #platform_spi_send_recv#( unsigned id, spi_data_type data );",
+ desc = "Executes a SPI read/write cycle",
+ args =
+ {
+ "$id$ - SPI interface ID",
+ "$data$ - data to be sent to the SPI interface",
+ },
+ ret = "data read from the SPI interface"
+ },
+
+ { sig = "void #platform_spi_select#( unsigned id, int is_select );",
+ desc = [[For platforms that have a dedicates SS (Slave Select) pin in master SPI mode that can be controlled manually, this function should enable/disable this pin. If this functionality
+ does not exist in hardware this function does nothing.]],
+ args =
+ {
+ "$id$ - SPI interface ID.",
+ "$is_select$ - $PLATFORM_SPI_SELECT_ON$ to select, $PLATFORM_SPI_SELECT_OFF$ to deselect , see @#chip_select at here@."
+ },
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_timers.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_timers.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_timers.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,187 @@
+-- eLua platform interface - timers
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - timers",
+
+ -- Menu name
+ menu_name = "Timers",
+
+ -- Overview
+ overview = [[This part of the platform interface groups functions related to the timers of the MCU. It also makes provisions for using $virtual timers$ on any platform, see @#virtual at this section@
+ for details. Keep in mind that in the following paragraphs a $timer id$ can reffer to both a hardware timer or a virtual timer.]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = "typedef u32 timer_data_type;",
+ name = "Timer data type",
+ desc = "This defines the data type used to specify delays and time intervals (which are always specifide in $microseconds$)."
+ },
+
+ { text = [[// Timer operations
+enum
+{
+ PLATFORM_TIMER_OP_START,
+ PLATFORM_TIMER_OP_READ,
+ PLATFORM_TIMER_OP_SET_CLOCK,
+ PLATFORM_TIMER_OP_GET_CLOCK,
+ PLATFORM_TIMER_OP_GET_MAX_DELAY,
+ PLATFORM_TIMER_OP_GET_MIN_DELAY
+};]],
+ name = "Timer operations",
+ desc = "This enum lists all the operations that can be executed on a given timer."
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_timer_exists#( unsigned id );",
+ desc = [[Checks if the platform has the timer specified as argument. Implemented in %src/common.c%, it uses the $NUM_TIMER$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details) and the virtual timer configuration (@#virtual at here@ for details). For example:</p>
+ ~#define NUM_TIMER 2 $// The platform has 2 hardware timers$~<p>]],
+ args = "$id$ - the timer ID",
+ ret = "1 if the timer exists, 0 otherwise"
+ },
+
+ { sig = "void #platform_timer_delay#( unsigned id, u32 delay_us );",
+ desc = [[Waits on a timer, then returns. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that
+ handles virtual timers) and a platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_delay at platform_s_timer_delay@. This function handles both
+ hardware timer IDs and virtual timer IDs.<br>
+ <font color="red"><a name="limitations">$IMPORTANT NOTE$</font></a>: the real delay after executing this functions depends a number of variables, most notably the base clock of the timer
+ and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay you're requesting is achievable, use
+ @#platform_timer_op at platform_timer_op@ with $PLATFORM_TIMER_OP_GET_MAX_DELAY$ and $PLATFORM_TIMER_OP_GET_MIN_DELAY$ to obtain the maximum and the minimum
+ achievable wait times on your timer, respectively. Even if your delay is within these limits, the $precision$ of this function still varies a lot, mainly as a function of
+ the timer base clock.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$delay_us$ - the delay time (in microseconds)"
+ }
+ },
+
+ { sig = "void #platform_s_timer_delay#( unsigned id, u32 delay_us );",
+ desc = [[This function is identical in functionality to @#platform_timer_delay at platform_timer_delay@, but this is the function that must actually be implemented by a platform port,
+ and it must never handle virtual timer IDs, only hardware timer IDs. It has the same @#limitations at limitations@ as @#platform_timer_delay at platform_timer_delay@.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$delay_us$ - the delay time (in microseconds)"
+ }
+ },
+
+ { sig = "u32 #platform_timer_op#( unsigned id, int op, u32 data );",
+ desc = [[Executes an operation on a timer. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that handles virtual timers) and a
+ platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_op at platform_s_timer_op@. This function handles both hardware timer IDs and virtual
+ timer IDs.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ [[$op$ - the operation. $op$ can take any value from the @#timer_operations at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_TIMER_OP_START$: start the specified timer by setting its counter register to a predefined value.</li>
+ <li>$PLATFORM_TIMER_OP_READ$: get the value of the specified timer's counter register.</li>
+ <li>$PLATFORM_TIMER_SET_CLOCK$: set the clock of the specified timer to $data$ (in hertz). You can never set the clock of a virtual timer, which is set at compile time.</li>
+ <li>$PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.</li>
+ <li>$PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).</li>
+ <li>$PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).</li>
+ </ul>]],
+ "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise",
+ },
+ ret =
+ {
+ "the predefined value used when starting the clock if $op = PLATFORM_TIMER_OP_START$",
+ "the timer's counter register if $op = PLATFORM_TIMER_OP_READ$",
+ "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$",
+ "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$",
+ "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$",
+ "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$"
+ }
+ },
+
+ { sig = "u32 #platform_s_timer_op#( unsigned id, int op, u32 data );",
+ desc = [[This function is identical in functionality to @#platform_timer_op at platform_timer_op@, but this is the function that must actually be implemented by a platform port, and it must
+ never handle virtual timer IDs, only hardware timer IDs.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ [[$op$ - the operation. $op$ can take any value from the @#opval at this enum@, as follows:
+ <ul>
+ <li>$PLATFORM_TIMER_OP_START$: start the specified timer by setting its counter register to a predefined value.</li>
+ <li>$PLATFORM_TIMER_OP_READ$: get the value of the specified timer's counter register.</li>
+ <li>$PLATFORM_TIMER_SET_CLOCK$: set the clock of the specified timer to $data$ (in hertz). You can never set the clock of a virtual timer, which is set at compile time.</li>
+ <li>$PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.</li>
+ <li>$PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).</li>
+ <li>$PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).</li>
+ </ul>]],
+ "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise",
+ },
+ ret =
+ {
+ "the predefined value used when starting the clock if $op = PLATFORM_TIMER_OP_START$",
+ "the timer's counter register if $op = PLATFORM_TIMER_OP_READ$",
+ "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$",
+ "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$",
+ "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$",
+ "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$"
+ }
+ },
+
+ { sig = "u32 #platform_timer_get_diff_us#( unsigned id, timer_data_type end, timer_data_type start );",
+ desc = [[Return the time difference (in us) betweeen two timer values. This function is generic for all platforms, thus it is implemented in %src/common.c%.]],
+ args =
+ {
+ "$id$ - the timer ID",
+ "$end$ - the first timer value",
+ "$start$ - the second timer value",
+ },
+ ret = "the time difference (in microseconds)"
+ }
+ },
+
+ auxdata =
+ {
+ { title = "Virtual timers",
+ desc =
+ [[$Virtual timers$ were added to eLua to overcome some limitations:
+ <ul>
+ <li>there are generally few hardware timers available, some of which might be dedicated (thus not usable directly by eLua).</li>
+ <li>many times it is difficult to share a hardware timer between different parts of an application because of conflicting requirements. Generally it's not possible to have timers that can
+ achieve long delays and high accuracy at the same time (this is especially true for systems that have 16 bit or even smaller timers).</li>
+ </ul></p>
+ <p>In this respect, $virtual timers$ are a set of timers that share a single hardware timer. It is possible, in this way, to have a hardware timer that can implement 4, 8 or more hardware
+ timers. There are a few drawbacks to this approach:
+ <ul>
+ <li>the hardware timer used to implement the virtual timers must generally be dedicated. In fact in cat be still used in "read only mode", which means that the only operations that can
+ be executed on it are $PLATFORM_TIMER_OP_READ$, $PLATFORM_TIMER_GET_CLOCK$, $PLATFORM_TIMER_OP_GET_MAX_DELAY$ and $PLATFORM_TIMER_OP_GET_MIN_DELAY$. However,
+ since the "read only mode" is not enforced by the code, it is advisable to treat this timer as a dedicated resource and thus make it invisible to eLua by not associating it with
+ an ID.</li>
+ <li>the number of virtual timers and their base frequency are fixed at compile time.</li>
+ <li>virtual timers are generally used for large delays with low accuracy, since their base frequency should be fairly low (see below).</li>
+ </ul></p>
+ <p>To $enable$ virtual timers:
+ <ol>
+ <li>edit $platform_conf.h$ (see @arch_overview.html#platforms at here@ for details) and set $VTMR_NUM_TIMERS$ to the number of desired virtual timers and
+ $VTMR_FREQ_HZ$ to the base frequency of the virtual timers (in hertz). For example:
+ ~#define VTMR_NUM_TIMERS 4 // we need 4 virtual timers
+#define VTMR_FREQ_HZ 4 // the base clock for the virtual timers is 4Hz~</li>
+ <li>in your platform port setup a hardware timer to fire an interrupt at $VTMR_FREQ_HZ$ and call the $cmn_virtual_timer_cb$ function (defined in %src/common.c%) in the
+ timer interrupt handler. For example, if the the interrupt handler is called $timer_int_handler$, do this:
+ ~void timer_int_handler( void )
+{
+ // add code to clear the timer interrupt flag here if needed
+ cmn_virtual_timer_cb();
+}~</li>
+ </ol></p>
+ <p>Note that because of step 2 above you are limited by practical constraints on the value of $VTMR_FREQ_HZ$. If set too high, the timer interrupt will fire too often, thus taking too much
+ CPU time. The maximum value depends largely on the hardware and the desired behaviour of the virtual timers, but in practice values larger than 10 might visibly change the behaviour of your
+ system.</p>
+ <p>To $use$ a virtual timer, identify it with the constant $VTMR_FIRST_ID$ (defined in %inc/common.h%) plus an offset. For example, $VTMR_FIRST_ID+0$ (or simply
+ $VTMR_FIRST_ID$) is the ID of the first virtual timer in the system, and $VTMR_FIRST_ID+2$ is the ID of the third virtual timer in the system.</p>
+ ]]
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/arch_platform_uart.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/arch_platform_uart.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/arch_platform_uart.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,126 @@
+-- eLua platform interface - UART
+
+data_en =
+{
+ -- Title
+ title = "eLua platform interface - UART",
+
+ -- Menu name
+ menu_name = "UART",
+
+ -- Overview
+ overview = "This part of the platform interface groups functions related to the UART interface(s) of the MCU.",
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[// Parity
+enum
+{
+ PLATFORM_UART_PARITY_EVEN,
+ PLATFORM_UART_PARITY_ODD,
+ PLATFORM_UART_PARITY_NONE
+};]],
+ name = "UART parity",
+ desc = "Constants used to specify the UART parity mode."
+ },
+
+ { text = [[// Stop bits
+enum
+{
+ PLATFORM_UART_STOPBITS_1,
+ PLATFORM_UART_STOPBITS_1_5,
+ PLATFORM_UART_STOPBITS_2
+};]],
+ name = "UART stop bits",
+ desc = "Constants used to specify the number of UART stop bits.",
+ },
+
+ { text = [[// "Infinite timeout" constant for recv
+#define PLATFORM_UART_INFINITE_TIMEOUT (-1)]],
+ name = "UART timeout",
+ desc = "This constant is used as a special timeout value (infinite timeout) in the UART functions that expect a timeout as argument.",
+ }
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "int #platform_uart_exists#( unsigned id );",
+ desc = [[Checks if the platform has the hardware UART specified as argument. Implemented in %src/common.c%, it uses the $NUM_UART$ macro that must be defined in the
+ platform's $platform_conf.h$ file (see @arch_overview.html#platforms at here@ for details). For example:</p>
+ ~#define NUM_UART 2 $// The platform has 2 UART interfaces$~<p>]],
+ args = "$id$ - UART interface ID",
+ ret = "1 if the specified UART exists, 0 otherwise"
+ },
+
+ { sig = "u32 #platform_uart_setup#( unsigned id, u32 baud, int databits, int parity, int stopbits );",
+ desc = "This function is used to initialize the parameters of the UART interface.",
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$baud$ - baud rate.",
+ "$databits$ - number of databits (maximum 8).",
+ "$parity$ - parity type (can be either $PLATFORM_UART_PARITY_EVEN$, $PLATFORM_UART_PARITY_ODD$ or $PLATFORM_UART_PARITY_NONE$, see @#uart_parity at here@).",
+ [[$stopbits$ - number of stop bits (can be either $PLATFORM_UART_STOPBITS_1$, $PLATFORM_UART_STOPBITS_1_5$ or $PLATFORM_UART_STOPBITS_2$, see
+ @#uart_stop_bits at here@).]],
+ },
+ ret = "the actual baud rate. Depending on the hardware, this may have a different value than the $baud$ argument.",
+ },
+
+ { sig = "void #platform_uart_send#( unsigned id, u8 data );",
+ desc = "Send data to an UART interface.",
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$data$ - data to be sent.",
+ },
+ },
+
+ { sig = "int #platform_uart_recv#( unsigned id, unsigned timer_id, s32 timeout );",
+ link = "platform_uart_recv",
+ desc = [[Receive data from the UART interface (blocking/non blocking with timeout/immediate).<br>
+ This function is "split" in two parts: a platform-independent part that is implemented in %src/common.c%, and a platform-dependent part that must be implemented by each
+ platform in a function named @#platform_s_uart_recv at platform_s_uart_recv@.]],
+ args =
+ {
+ "$id$ - UART interface ID.",
+ "$timer_id$ - the ID of the timer used in this operation (see @arch_platform_timers.html at here@ for details). See also the description of the $timeout$ argument.",
+ [[$timeout$ - specifies a timeout for the receive operation as follows:
+ <ul>
+ <li>$timeout > 0$: the timer with the specified $timer_id$ will be used to timeout the receive operation after $timeout$ microseconds.</li>
+ <li>$timeout = 0$: the function returns immediately regardless of data being available or not. $timer_id$ is ignored.</li>
+ <li>$timeout$ = @#uart_timeout at PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it. In this mode the function doesn't
+ time out, so $timer_id$ is ignored.</li>
+ </ul>]],
+ },
+ ret =
+ {
+ "if $timeout > 0$ and data from the UART is available in $timeout$ microseconds of less it is returned, otherwise -1 is returned",
+ "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned",
+ "if $timeout$ = @#uart_timeout at PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available"
+ }
+ },
+
+ { sig = "int #platform_s_uart_recv#( unsigned id, s32 timeout );",
+ link = "platform_s_uart_recv",
+ desc = [[This is the platform-dependent part of the UART receive function @#platform_uart_recv at platform_uart_recv@, and is in fact a "subset" of the full function
+ (thus being easier to implement by each platform in part). In particular, it never needs to deal with the $timeout > 0$ case, which is handled by @#platform_uart_recv at platform_uart_recv@.]],
+ args =
+ {
+ "$id$ - UART interface ID.",
+ [[$timeout$ - specifies a timeout for the receive operation as follows:
+ <ul>
+ <li>$timeout = 0$: the function returns immediately regardless of data being available or not.</li>
+ <li>$timeout$ = @#uart_timeout at PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it.</li>
+ </ul>]],
+ },
+ ret =
+ {
+ "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned",
+ "if $timeout$ = @#uart_timeout at PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available"
+ }
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/refman_gen_adc.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_adc.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_adc.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,97 @@
+-- eLua reference manual - ADC
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - ADC",
+
+ -- Menu name
+ menu_name = "adc",
+
+ -- Overview
+ overview = [[This module contains functions that access analog to digital converter (ADC) peripherals. ]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#adc.sample#( id, count )",
+ desc = "Request sample conversions.",
+ args =
+ {
+ "$id$ - ADC channel ID. Optionally, this may be a table containing a list of channel IDs (i.e.: {0, 2, 3}), allowing synchronization of acquisition. NOTE: This acceptance of mixed types is only for the sample function.",
+ "$count$ - number of samples to acquire."
+ }
+ },
+ { sig = "sample = #adc.getsample#( id )",
+ desc = "Get converted samples.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$sample$ - numeric value of conversion, or nil if sample was not available."
+ },
+ { sig = "samples = #adc.getsamples#( id, count )",
+ desc = "Get multiple converted samples.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$count$ - optional parameter to indicate number of samples to return. If not included, all available samples are returned."
+ },
+ ret = "$samples$ - table containing integer conversion values. If not enough samples are available, remaining indices will be nil."
+ },
+ { sig = "#adc.insertsamples#( id, table, idx, count )",
+ desc = "Write multiple samples to a table.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$table$ - table to write samples to. Values at $table$[$idx$] to $table$[$idx$ + $count$ -1] will be overwritten with samples (or nil if not enough samples are available).",
+ "$idx$ - first index to use for writing samples",
+ "$count$ - number of samples to return. If not enough samples are available (after blocking, if enabled) remaining values will be nil."
+ }
+ },
+ { sig = "maxval = #adc.maxval#( id )",
+ desc = "Get maximum conversion value.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$maxval$ - maximum conversion value (based on channel resolution)"
+ },
+ { sig = "clock = #adc.setclock#( id, clock, timer_id )",
+ desc = "Set frequency of sample acquisition.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$clock$ - frequency to acquire samples at in Hz (number of samples per second), 0 to acquire as fast as possible.",
+ "$timer_id$ - Timer channel ID to use to control ADC conversion. Note: At this time, a timer selection will apply to all channels on a given ADC peripheral."
+ },
+ ret = "$clock$ - actual acquisition frequency to be used"
+ },
+ { sig = "status = #adc.isdone#( id )",
+ desc = "Check if sampling is done.",
+ args =
+ {
+ "$id$ - ADC channel ID."
+ },
+ ret = "$status$ - 1 if no samples are being acquired, 0 if samples are pending acquisition."
+ },
+ { sig = "#adc.setblocking#( id, mode )",
+ desc = "Set whether or not to block waiting for requested samples.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$mode$ - 1 if requests to get samples should block until requested samples are available or sampling has completed, 0 to return immediately with available samples"
+ },
+ },
+ { sig = "#adc.setsmoothing#( id, length )",
+ desc = "Set length of moving average filter.",
+ args =
+ {
+ "$id$ - ADC channel ID.",
+ "$length$ - number of samples to include in moving average filter (must be a power of 2). If 1, filter is disabled."
+ }
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/refman_gen_bit.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_bit.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_bit.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,139 @@
+-- eLua reference manual - bit module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - bit module",
+
+ -- Menu name
+ menu_name = "bit",
+
+ -- Overview
+ overview = [[Since Lua doesn't have built-in capabilities for bit operations, the $bit$ module was added to eLua to fill this gap. It is based on the ^http://luaforge.net/projects/bitlib^bitlib^
+ library written by Reuben Thomas (slightly adapted to eLua) and provides basic bit operations (like setting and clearing bits) and bitwise operations.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "number = #bit.bit#( position )",
+ desc = "Generate a number with a 1 bit (used for mask generation). Equivalent to %1 <<<< position% in C.",
+ args = "$position$ - position of the bit that will be set to 1.",
+ ret = "$number$ - a number with only one 1 bit at $position$ (the rest are set to 0."
+ },
+
+ { sig = "flag = #bit.isset#( value, position )",
+ desc = "Test if a given bit is set.",
+ args =
+ {
+ "$value$ - the value to test.",
+ "$position$ - bit position to test."
+ },
+ ret = "$flag$ - 1 if the bit at the given position is 1, 0 otherwise."
+ },
+
+ { sig = "flag = #bit.isclear#( value, position )",
+ desc = "Test if a given bit is cleared.",
+ args =
+ {
+ "$value$ - the value to test.",
+ "$position$ - bit position to test."
+ },
+ ret = "$flag$ - 1 if the bit at the given position is 0, 0 othewise."
+ },
+
+ { sig = "number = #bit.set#( value, pos1, pos2, ..., posn )",
+ desc = "Set bits in a number.",
+ args =
+ {
+ "$value$ - the base number.",
+ "$pos1$ - position of the first bit to set.",
+ "$pos2$ - position of the second bit to set.",
+ "$posn$ - position of the nth bit to set."
+ },
+ ret = "$number$ - the number with the bit(s) set in the given position(s)."
+ },
+
+ { sig = "number = #bit.clear#( value, pos1, pos2, ..., posn )",
+ desc = "Clear bits in a number.",
+ args =
+ {
+ "$value$ - the base number.",
+ "$pos1$ - position of the first bit to clear.",
+ "$pos2$ - position of the second bit to clear.",
+ "$posn$ - position of thet nth bit to clear.",
+ },
+ ret = "$number$ - the number with the bit(s) cleared in the given position(s)."
+ },
+
+ { sig = "number = #bit.bnot#( value )",
+ desc = "Bitwise negation, equivalent to %~~value% in C.",
+ args = "$value$ - the number to negate.",
+ ret = "$number$ - the bitwise negated value of the number.",
+ },
+
+ { sig = "number = #bit.band#( val1, val2, ... valn )",
+ desc = "Bitwise AND, equivalent to %val1 & val2 & ... & valn% in C.",
+ args =
+ {
+ "$val1$ - first AND argument.",
+ "$val2$ - second AND argument.",
+ "$valn$ - nth AND argument.",
+ },
+ ret = "$number$ - the bitwise AND of all the arguments."
+ },
+
+ { sig = "number = #bit.bor#( val1, val2, ... valn )",
+ desc = "Bitwise OR, equivalent to %val1 | val2 | ... | valn% in C.",
+ args =
+ {
+ "$val1$ - first OR argument.",
+ "$val2$ - second OR argument.",
+ "$valn$ - nth OR argument."
+ },
+ ret = "$number$ - the bitwise OR of all the arguments."
+ },
+
+ { sig = "number = #bit.bxor#( val1, val2, ... valn )",
+ desc = "Bitwise exclusive OR (XOR), equivalent to %val1 ^^ val2 ^^ ... ^^ valn% in C.",
+ args =
+ {
+ "$val1$ - first XOR argument.",
+ "$val2$ - second XOR argument.",
+ "$valn$ - nth XOR argument."
+ },
+ ret = "$number$ - the bitwise exclusive OR of all the arguments."
+ },
+
+ { sig = "number = #bit.lshift#( value, shift )",
+ desc = "Left-shift a number, equivalent to %value << shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift.",
+ },
+ ret = "$number$ - the number shifted left",
+ },
+
+ { sig = "number = #bit.rshift#( value, shift )",
+ desc = "Logical right shift a number, equivalent to %( unsigned )value >>>> shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift.",
+ },
+ ret = "$number$ - the number shifted right (logically)."
+ },
+
+ { sig = "number = #bit.arshift#( value, shift )",
+ desc = "Arithmetic right shift a number equivalent to %value >>>> shift% in C.",
+ args =
+ {
+ "$value$ - the value to shift.",
+ "$shift$ - positions to shift."
+ },
+ ret = "$number$ - the number shifted right (arithmetically)."
+ }
+ }
+}
+
Added: branches/eagle_mmc/doc/luadoc/refman_gen_cpu.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_cpu.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_cpu.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,100 @@
+-- eLua reference manual - CPU module
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - CPU module",
+
+ -- Menu name
+ menu_name = "cpu",
+
+ -- Overview
+ overview = [[This module deals with low-level access to CPU (and related modules) functionality, such as reading and writing memory, or
+ enabling and disabling interrupts. It also offers access to platform specific CPU-related constants using a special macro defined in the
+ platform's $platform_conf.h$ file, as exaplained @#cpu_constants at here@.]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[cpu.INT_GPIOA
+cpu.INT_GPIOB
+.............
+cpu.INT_UDMA]],
+ name = "CPU constants",
+ desc = [[eLua has a mechanism that lets the user export an unlimited number of constants to the $cpu$ module. Although in theory any kind of constant can be exposed by this module,
+one should only use constants related to the CPU and its subsystems (as shown above, where a number of CPU specific interrupt masks are exposed to Lua using this mechanism). To use this
+mechanism, just declare the $PLATFORM_CPU_CONSTANTS$ macro in your platform's $platform_conf.h$ file and list all your constants as part of this macro, each enclosed in a special macro called
+$_C$. For example, to get the constants listed above declare your $PLATFORM_CPU_CONSTANTS$ macro like this:</p>
+~#define PLATFORM_CPU_CONSTANTS\
+ _C( INT_GPIOA ),\
+ _C( INT_GPIOB ),\
+ .................
+ _C( INT_UDMA )~<p>
+<p>It's worth to note that adding more constants does not increas RAM usage, only Flash usage, so you can expose as much constants as you need without worrying about RAM consumption.]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#cpu.w32#( address, data )",
+ desc = "Writes a 32-bit word to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the 32-bit data to write."
+ },
+ },
+
+ { sig = "data = #cpu.r32#( address )",
+ desc = "Read a 32-bit word from memory.",
+ args = "$address$ - the memory address.",
+ ret = "$data$ - the 32-bit word read from memory."
+ },
+
+ { sig = "#cpu.w16#( address, data )",
+ desc = "Writes a 16-bit word to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the 16-bit data to write."
+ },
+ },
+
+ { sig = "data = #cpu.r16#( address )",
+ desc = "Reads a 16-bit word from memory.",
+ args = "$address$ - the memory address.",
+ ret = "$data$ - the 16-bit word read from memory."
+ },
+
+ { sig = "#cpu.w8#( address, data )",
+ desc = "Writes a byte to memory.",
+ args =
+ {
+ "$address$ - the memory address.",
+ "$data$ - the byte to write."
+ }
+ },
+
+ { sig = "data = #cpu.r8#( address )",
+ desc = "Reads a byte from memory.",
+ args = "$address$ - the memory address",
+ ret = "$data$ - the byte read from memory."
+ },
+
+ { sig = "#cpu.cli#()",
+ desc = "Disable CPU interrupts."
+ },
+
+ { sig = "#cpu.sei#()",
+ desc = "Enable CPU interrupts."
+ },
+
+ { sig = "clock = #cpu.clock#()",
+ desc = "Get the CPU core frequency.",
+ ret = "$clock$ - the CPU clock (in Hertz)."
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/luadoc/refman_gen_pack.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_pack.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_pack.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,135 @@
+-- eLua reference manual - pack
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - pack",
+
+ -- Menu name
+ menu_name = "pack",
+
+ -- Overview
+ overview = [[This module allows for arbitrary packing of data into Lua strings and unpacking data from Lua strings. In this way, a string can be used to store data in a platform-indepdendent
+manner. It is based on the ^http://www.tecgraf.puc-rio.br/~~lhf/ftp/lua/#lpack^lpack^ module from Luiz Henrique de Figueiredo (with some minor tweaks). </p>
+<p>Both methods of this module (@#pack at pack@ and @#unpack at unpack@) use a $format string$ to describe how to pack/unpack the data. The format string contains one or more $data specifiers$, each
+data specifier is applied to a single variable that must be packed/unpacked. The data specifier has the following general format:</p>
+~[endianness]<<format specifier>>[count]~
+<p>where:
+<ul>
+ <li>$endianness$ is an optional endian flags that specifies how the numbers that are to be packed/unpacked are stored in memory. It can be either:
+ <ol>
+ <li>$'<<'$ for little endian.</li>
+ <li>$'>>'$ for big endian.</li>
+ <li>$'='$ for native endian (the platform's endian order, default).</li>
+ </ol></li>
+ <li>$format specifier$ describes what kind of variable will be packed/unpacked. $The format specifier is case-sensitive$. The possible values of this parameter are summarized in the table below:
+ <p><table class="table_center">
+ <tbody>
+ <tr>
+ <th>Format specifier</th>
+ <th>Corresponding variable type</th>
+ </tr>
+ <tr>
+ <td>'z'</td>
+ <td>zero-terminated string</td>
+ </tr>
+ <tr>
+ <td>'p' </td>
+ <td>string preceded by length byte</td>
+ </tr>
+ <tr>
+ <td>'P' </td>
+ <td>string preceded by length word</td>
+ </tr>
+ <tr>
+ <td>'a' </td>
+ <td>string preceded by length size_t</td>
+ </tr>
+ <tr>
+ <td>'A' </td>
+ <td>string</td>
+ </tr>
+ <tr>
+ <td>'f' </td>
+ <td>float</td>
+ </tr>
+ <tr>
+ <td>'d' </td>
+ <td>double</td>
+ </tr>
+ <tr>
+ <td>'n' </td>
+ <td>Lua number</td>
+ </tr>
+ <tr>
+ <td>'c' </td>
+ <td>char</td>
+ </tr>
+ <tr>
+ <td>'b' </td>
+ <td>byte = unsigned char</td>
+ </tr>
+ <tr>
+ <td>'h' </td>
+ <td>short</td>
+ </tr>
+ <tr>
+ <td>'H' </td>
+ <td>unsigned short</td>
+ </tr>
+ <tr>
+ <td>'i' </td>
+ <td>int</td>
+ </tr>
+ <tr>
+ <td>'I' </td>
+ <td>unsigned int</td>
+ </tr>
+ <tr>
+ <td>'l' </td>
+ <td>long</td>
+ </tr>
+ <tr>
+ <td>'L' </td>
+ <td>unsigned long</td>
+ </tr>
+ </table><br></p></li>
+ <li>$count$ is an optional counter for the $format specifier$. For example, $i5$ instructs the code to pack/unpack 5 integer variables, as opposed to $i$ that specifies a
+ single integer variable.</li>
+</ul></p>]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "packed = #pack.pack#( format, val1, val2, ..., valn )",
+ desc = "Packs variables in a string.",
+ args =
+ {
+ "$format$ - format specifier (as described @#overview at here@).",
+ "$val1$ - first variable to pack.",
+ "$val2$ - second variable to pack.",
+ "$valn$ - nth variable to pack.",
+ },
+ ret = "$packed$ - a string containing the packed representation of all variables according to the format."
+ },
+
+ { sig = "nextpos, val1, val2, ..., valn = #pack.unpack#( string, format, [ init ] )",
+ desc = "Unpacks a string",
+ args =
+ {
+ "$string$ - the string to unpack.",
+ "$format$ - format specifier (as described @#overview at here@).",
+ "$init$ - $(optional)$ marks where in $string$ the unpacking should start (1 if not specified)."
+ },
+ ret =
+ {
+ "$nextpos$ - the position in the string after unpacking.",
+ "$val1$ - the first unpacked value.",
+ "$val2$ - the second unpacked value.",
+ "$valn$ - the nth unpacked value."
+ }
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/luadoc/refman_gen_pd.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_pd.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_pd.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,34 @@
+-- eLua reference manual - platform data
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - platform data",
+
+ -- Menu name
+ menu_name = "Platform data (pd)",
+
+ -- Overview
+ overview = [[This module contains functions that access specific platform data. Useful if the code needs to know on which platform it runs.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "platform = #pd.platform#()",
+ desc = "Get platform name.",
+ ret = "$platform$ - the name of the platform on which eLua is running.",
+ },
+
+ { sig = "cpu = #pd.cpu#()",
+ desc = "Get CPU name.",
+ ret = "$cpu$ - the name of the CPU of the platform on which eLua is running.",
+ },
+
+ { sig = "board = #pd.board#()",
+ desc = "Get board name.",
+ ret = "$board$ - the name of the board on which eLua is running.",
+ }
+ },
+}
+
Added: branches/eagle_mmc/doc/luadoc/refman_gen_pwm.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_pwm.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_pwm.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,60 @@
+-- eLua reference manual - platform data
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - PWM",
+
+ -- Menu name
+ menu_name = "pwm",
+
+ -- Overview
+ overview = [[This module contains functions that control pulse-width modulation (PWM) peripherals.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "realfrequency = #pwm.setup#( id, frequency, duty )",
+ desc = "Configure PWM channel.",
+ args =
+ {
+ "$id$ - PWM channel ID.",
+ "$frequency$ - Frequency of PWM channel cycle (in hertz).",
+ "$duty$ - PWM channel duty cycle, specified as percent (from 0 to 100). Note that some platform don't allow the full 0-100 duty cycle"
+ },
+ ret = "$realfrequency$ - actual PWM cycle frequency"
+ },
+ { sig = "#pwm.start#( id )",
+ desc = "Start PWM waveform generation.",
+ args =
+ {
+ "$id$ - PWM channel ID.",
+ }
+ },
+ { sig = "#pwm.stop#( id )",
+ desc = "Stop PWM waveform generation.",
+ args =
+ {
+ "$id$ - PWM channel ID.",
+ }
+ },
+ { sig = "realfrequency = #pwm.setclock#( id, clock )",
+ desc = "Set base PWM clock frequency",
+ args =
+ {
+ "$id$ - PWM channel ID.",
+ "$clock$ - Frequency of base clock.",
+ },
+ ret = "$realfrequency$ - actual base PWM clock."
+ },
+ { sig = "clock = #pwm.getclock#( id )",
+ desc = "Get base PWM clock frequency",
+ args =
+ {
+ "$id$ - PWM channel ID.",
+ },
+ ret = "$clock$ - base PWM clock."
+ },
+ },
+}
\ No newline at end of file
Added: branches/eagle_mmc/doc/luadoc/refman_gen_tmr.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/refman_gen_tmr.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/refman_gen_tmr.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,86 @@
+-- eLua reference manual - platform data
+
+data_en =
+{
+
+ -- Title
+ title = "eLua reference manual - Timer module",
+
+ -- Menu name
+ menu_name = "tmr",
+
+ -- Overview
+ overview = [[This module contains functions that control timer peripherals.]],
+
+ -- Functions
+ funcs =
+ {
+ { sig = "#tmr.delay#( id, period )",
+ desc = "Block for a period of time (in microseconds)",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ "$period$ - the delay time (in microseconds)"
+ },
+ },
+ { sig = "timervalue = #tmr.read#( id )",
+ desc = "Get the value of the specified timer's counter register.",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ },
+ ret = "$timervalue$ - the timer's counter register"
+ },
+ { sig = "timervalue = #tmr.start#( id )",
+ desc = "Start the specified timer by setting its counter register to a predefined value.",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ },
+ ret = "$timervalue$ - the timer's counter register"
+ },
+ { sig = "time_us = #tmr.diff#( id, end, start )",
+ desc = "Return the time difference (in us) betweeen two timer values.",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ "$end$ - the first timer value",
+ "$start$ - the second timer value"
+ },
+ ret = "$time_us$ - the time difference (in microseconds)"
+ },
+ { sig = "mindelay_us = #tmr.mindelay#( id )",
+ desc = "Get the minimum achievable timeout on the specified timer (in us).",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ },
+ ret = "$mindelay_us$ - the minimum achievable delay (in microseconds)"
+ },
+ { sig = "maxdelay_us = #tmr.maxdelay#( id )",
+ desc = "Get the maximum achievable timeout on the specified timer (in us).",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ },
+ ret = "$maxdelay_us$ - the maximum achievable delay (in microseconds)"
+ },
+ { sig = "realclock = #tmr.setclock#( id, clock )",
+ desc = "Set the clock of the specified timer.",
+ args =
+ {
+ "$id$ - Timer channel ID.",
+ "$clock$ - desired clock (in hertz)"
+ },
+ ret = "$realclock$ - actual clock set on the timer"
+ },
+ { sig = "clock = #tmr.getclock#( id )",
+ desc = "Get the clock of the specified timer.",
+ args =
+ {
+ "$id$ - Timer channel ID."
+ },
+ ret = "$clock$ - timer clock"
+ },
+ },
+}
\ No newline at end of file
Added: branches/eagle_mmc/doc/luadoc/template.lua
===================================================================
--- branches/eagle_mmc/doc/luadoc/template.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/luadoc/template.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,52 @@
+-- eLua platform interface - name
+
+data_en =
+{
+
+ -- Title
+ title = "eLua platform interface - name",
+
+ -- Menu name
+ menu_name = "name"
+
+ -- Overview
+ overview = [[
+ ]],
+
+ -- Data structures, constants and types
+ structures =
+ {
+ { text = [[ ]],
+ name = "",
+ desc = [[ ]]
+ },
+ },
+
+ -- Functions
+ funcs =
+ {
+ { sig = "void #functionname#( void )",
+ desc = [[ ]],
+ args =
+ {
+ { name = "", desc = "" },
+ { name = "", desc = "" }
+ },
+ ret =
+ {
+ "",
+ [[ ]],
+ },
+ },
+
+ },
+
+ -- Aux data
+ auxdata =
+ {
+ { title = "",
+ desc = [[]]
+ }
+ }
+}
+
Modified: branches/eagle_mmc/doc/pt/bit_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/bit_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/bit_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,98 +1,98 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over"></a>bit</h3>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bnot"></a>Res = bit.bnot( value ): unary
-negation
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bnot"></a>Res = bit.bnot( value ):
+negação
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="band"></a> Res = bit.band( v1, v2, ... ): <b>bitwise
+<p class="MsoNormal" style="font-family: Verdana;"><a name="band"></a> Res = bit.band( v1, v2, ... ): <b>operação binária
</b>"and"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bor"></a> Res = bit.bor( v1, v2, ... ): <b>bitwise</b><b>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bor"></a> Res = bit.bor( v1, v2, ... ): <b>operação binária</b><b>
</b>"or"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bxor"></a> Res = bit.bxor( v1, v2, ... ): <b>bitwise</b><b>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bxor"></a> Res = bit.bxor( v1, v2, ... ): <b>operação binária</b><b>
</b>"exclusive or"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="lshift"></a> Res = bit.lshift( value, pos ):
-shift "value" left "pos" positions.
+desloca "value" em "pos" posições a esquerda.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="rshift"></a> Res = bit.rshift( value, pos ):
-shift "value" right "pos" positions. The sign is
+desloca "value" em "pos" posições a direita. O sinal não
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- not propagated.
+ é propagado.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="arshift"></a> Res = bit.arshift( value, pos ):
-shift "value" right "pos" positions. The sign
+desloca "value" em "pos" posições a direita. O sinal
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- is propagated ("arithmetic shift").
+ é propagado ("arithmetic shift").
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
-<p class="MsoNormal" style="font-family: Verdana;"><a name="bit"></a> Res = bit.bit( bitno ): a shortcut for
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit"></a> Res = bit.bit( bitno ): um atalho para
bit.lshift( 1, bitno )
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="set"></a> Res1, Res2, ... = bit.set( bitno, v1,
-v2, ... ): set the bit at position "bitno"
+v2, ... ): configura o bit na posição "bitno"
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- in v1, v2, ... to 1.
+ em v1, v2, ... to 1.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="clear"></a> Res1, Res2, ... = bit.clear( bitno,
-v1, v2, ... ): set the bit at position
+v1, v2, ... ): configura o bit na posição
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- "bitno"in v1, v2, ... to 0.
+ "bitno" em v1, v2, ... para 0.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="isset"></a> Res = bit.isset( value, bitno ):
-returns true if bit at position "bitno" in
+retorna verdadeiro se o bit na posição "bitno" em
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- "value" is 1, false otherwise.
+ "value" é igual a 1, caso contrário retorna falso.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="isclear"></a> Res = bit.isclear( value, bitno ):
-returns true if bit at position "bitno" in
+retorna verdadeiro se o bit na posição "bitno" em
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- "value" is 0, false otherwise.
+ "value" é igual a 0, caso contrário retorna falso.
</p>
<br style="font-family: Verdana;">
<br style="font-family: Verdana;">
@@ -129,4 +129,4 @@
<br>
<br>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Copied: branches/eagle_mmc/doc/pt/building.html (from rev 269, branches/eagle_mmc/doc/en/building.html)
===================================================================
--- branches/eagle_mmc/doc/en/building.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/building.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,114 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Building eLua</h3>
+
+Up to date documentation of how to build eLua is always included in the <a href="http://www.eluaproject.net/?p=Downloads">eLua distributions</a>, in the docs directory).<br><p>For your convenience, the building instructions are also provided on this page.</p>
+
+<h2>Prerequisites</h2>
+
+<p>Before you start, you might want to check if the list of platform modules and
+eLua components are set according to your needs. See platform_modules
+and elua_components in the distro doc for details. </p>
+
+<h2>Building eLua</h2>
+
+<p>To build <strong>eLua</strong> you'll need:</p>
+
+<ul><li><p>a GCC/Newlib toolchain for your target. Please note that even if
+ you already have a compiled toolchain, the differences in the Newlib configure
+ flags (mainly the --disable-newlib-supplied-syscalls flags) might prevent
+ eLua for building properly on your machine.</p></li><li><p>Linux. Compiling under windows should be possible, however this isn't tested.
+ I'm using Ubuntu, so I'm also using "apt-get". If you're using a distro with a
+ different package manager you'll need to translate the "apt-get" calls to your
+ specific distribution.</p></li><li><p>python. It should be already installed; if it's not:</p>
+
+ <p>$ sudo apt-get install python</p></li><li><p>scons. eLua uses scons instead of make and makefiles, because I find scons
+ much more "natural" and easier to use than make. To install it:</p>
+
+ <p>$ sudo apt-get install scons</p></li><li><p>your toolchain's "bin" directory (this is generally something like
+ /usr/local/cross-arm/bin, where /usr/local/cross-arm is the directory in which
+ you installed your toolchain) must be in $PATH. </p></li><li><p>if you're building for the i386 platform, you'll also need "nasm":</p>
+
+ <p>$ sudo apt-get install nasm</p></li></ul>
+
+<p>For each platform, eLua assumes a certain name for the compiler/linker/assembler
+executable files, as shown below.</p>
+
+<pre><code>================================================================================<br>| Tool | Compiler | Linker | Assembler | <br>|------------|---------------------|----------------------|--------------------| <br>| Platform | | | |<br>|============|=====================|======================|====================|<br>| ARM (all) | arm-elf-gcc | arm-elf-gcc | arm-elf-gcc |<br>|============|=====================|======================|====================|<br>| i386 | i686-elf-gcc | i686-elf-gcc | nasm |<br>|============|=====================|======================|====================|<br>| Cortex-M3 | arm-elf-gcc | arm-elf-gcc | arm-elf-gcc |<br>|============|=====================|======================|====================|<br></code></pre>
+
+<p>If your toolchain uses different names, you have to modify the "conf.py" file
+from src/platform/[your platform].</p>
+
+<p>To build, go to the directory where you unpacked your eLua distribution and
+invoke scons:</p>
+
+<pre><code>$ scons [target=lua | lualong] <br> [cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962 | <br> lm3s6965 | lpc2888 | str711fr2 ]<br> [board=ek-lm3s8962 | ek-lm3s6965 | str9-comstick | sam7-ex256 | lpc-h2888 | <br> | mod711 | pc]<br> [cpumode=arm | thumb] <br> [allocator = newlib | multiple]<br> [prog]<br></code></pre>
+
+<p>Your build target is specified by two paramters: cpu and board. "cpu" gives the
+name of your CPU, and "board" the name of the board. A board can be associated
+with more than one CPU. This allows the build system to be very flexible. You
+can use these two options together or separately, as shown below:</p>
+
+<ul><li>cpu=name: build for the specified CPU. A board name will be assigned by the
+ build system automatically.</li><li>board=name: build for the specified board. The CPU name will be inferred by
+ the build system automatically.</li><li>cpu=name board=name: build for the specified board and CPU.</li></ul>
+
+<p>For board/CPU assignment look at the beginning of the SConstruct file from the
+base directory, it's self-explanatory.</p>
+
+<p>The other options are as follows:</p>
+
+<ul><li>target=lua | lualong: specify if you want to build full Lua (with floating
+ point support) or integer only Lua (lualong). The default is "lua".</li><li>cpumode=arm | thumb: for ARM target (not Cortex) this specifies the
+ compilation mode. Its default value is 'thumb' for AT91SAM7X targets and
+ 'arm' for STR9 and LPC2888 targets.</li><li>allocator = newlib | multiple: choose between the default newlib allocator
+ (newlib) and the multiple memory spaces allocator (multiple). You should
+ use the 'multiple' allocator only if you need to support multiple memory
+ spaces, as it's larger that the default Newlib allocator (newlib). For more
+ information about this reffer to platform_interface. The default value
+ is 'newlib' for all CPUs except 'lpc2888', since my lpc-h2888 comes with
+ external SDRAM memory and thus it's an ideal target for 'multiple'.</li><li>prog: by default, the above 'scons' command will build only the 'elf' file.
+ Specify "prog" to build also the platform-specific programming file where
+ appropriate (for example, on a AT91SAM7X256 this results in a .bin file that
+ can be programmed in the CPU). </li></ul>
+
+<p>The output will be a file named elua<em>[target]</em>[cpu].elf (and also another
+file with the same name but ending in .bin if "prog" was specified for platforms
+that need .bin files for programming).
+If you want the equivalent of a "make clean", invoke "scons" as shown above,
+but add a "-c" at the end of the command line. "scons -c" is also recommended
+after you change the list of modules/components to build for your target (see
+section "prerequisites" of this document), as scons seems to "overlook" the
+changes to these files on some occasions.</p>
+
+<p>A few examples:</p>
+
+<p>Clear previously built intermediate files.</p>
+
+<pre><code>$ scons cpu=at91sam7x256 -c <br></code></pre>
+
+<p>Build eLua for the AT91SAM7X256 CPU. The board name is detected as sam7-ex256.</p>
+
+<pre><code>$ scons cpu=at91sam7x256<br></code></pre>
+
+<p>Build eLua for the SAM7-EX256 board. The CPU is detected as AT91SAM7X256.</p>
+
+<pre><code>$ scons board=sam7-ex256<br></code></pre>
+
+<p>Build eLua for the SAM7-EX256 board, but "overwrite" the default CPU. This is
+useful when you'd like to see how the specified board would behave with a
+different CPU (in the case of the SAM7-EX256 board it's possible to switch the
+on-board AT91SAM7X256 CPU for an AT91SAM7X512 which has the same pinout but
+comes with more Flash/RAM memory).</p>
+
+<pre><code>$ scons board=sam7-ex256 cpu=at91sam7x512<br></code></pre>
+
+<p>Build eLua for the lpc2888 CPU. The board name is detected as LPC-H2888. Also,
+the bin file required for target programming is generated.</p>
+
+<pre><code>$ scons cpu=lpc2888 prog </code></pre><br><br></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/comunity.html
===================================================================
--- branches/eagle_mmc/doc/pt/comunity.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/comunity.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,55 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<a name="lists"></a><h3>Lista de Discussão</h3>
+<p><strong></strong></p><p style="text-align: left;"><strong>eLua</strong> tem atualmente uma única lista de discussão. Você é bem-vindo em participar de nossa lista em
+<a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.
+É importante observar que essa lista possui um moderador com o objetivo de se evitar o uso de spam, sendo assim necessário, que você faça a sua inscrição, caso decida participar de nossa lista. Mensagens de usuáros não inscritos são raramente aceitas.</p>
+<p style="text-align: left;"></p><p style="text-align: left;">Nosso repositório para desenvolvimento do projeto eLua encontra-se em um subversion server.
+Se você quiser manter-se informado sobre as atividades do nosso servidor SVN, inscreva-se também na nossa <strong>lista de atividades do servidor SVN</strong> em <a target="_top" href="https://lists.berlios.de/mailman/listinfo/elua-svn">https://lists.berlios.de/mailman/listinfo/elua-svn</a>.</p>
+<p></p><p><a href="https://lists.berlios.de/mailman/listinfo/elua-svn"></a></p>
+
+<span style="font-style: italic;"><a name="credits"></a></span><h3>Elua forums</h3>
+<div class="content">
+<p>Ainda não temos um forum dedicado a <strong>eLua</strong>. No entanto, a partir de 22/2/2009, nossa lista de discussão foi copiada e disponibilizada em formato de forum <a target="_top" href="http://n2.nabble.com/eLua-Development-f2368040.html">neste endereço</a> (através do serviço <a target="_top" href="http://nabble.com">Nabble</a>).
+Se você quiser utilizar esta opção, <a target="_top" href="forum.html">clique aqui</a>.
+</p>
+
+
+<span style="font-style: italic;"><a name="credits"></a></span><h3>Créditos</h3>
+<div class="content">
+<p>Os autores de <strong>eLua</strong> agradecem a colaboração da comunidade pela esforço contínuo de desenvolvimento do projeto. Abaixo segue uma lista parcial em ordem alfabética com os nomes de alguns de nossos colaboradores:</p>
+
+<ul>
+<li>Alberto Fabiano</li>
+<li>André Carregal</li>
+<li>Cosmin Filip</li>
+<li>Diego Sueiro</li>
+<li>Everson Denis</li>
+<li>Fabio Pereira</li>
+<li>Fernando Araújo</li>
+<li>Frédéric Thomas</li>
+<li>Ives Cunha,</li>
+<li>James Snyder</li>
+<li>Marcelo Tílio</li>
+<li>Marco Meggiolaro</li>
+<li>Mike Panetta</li>
+<li>Pedro Bittencourt</li>
+<li>Rafael Barmak</li>
+<li>Rafael Sabbagg</li>
+<li>Ralph Hempel</li>
+<li>Raul Nunes</li>
+<li>Ricardo Rosa</li>
+<li>Roberto Ierusalimschy</li>
+<li>Téo Beijamin</li>
+<li>Yuri Takhteyev</li>
+</ul>
+
+... e toda a comunidade de nossa lista de Discussão em <a href="https://lists.berlios.de/mailman/listinfo/elua-dev">https://lists.berlios.de/mailman/listinfo/elua-dev</a>.<strong style="font-weight: normal;"></strong></div>
+<br><br>
+<a name="galery"></a><a name="projects"></a>
+</body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/cpu_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/cpu_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/cpu_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -10,48 +10,48 @@
<p class="MsoNormal" style="font-family: Verdana;"><br>
</p>
<p style="margin-bottom: 0in;"></p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="write32"></a>write32( address, data ) : write
-the 32-bit data at the specified address</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="write32"></a>write32( address, data ) : grava
+dados de 32 bits no endereço especificado</font>
</p>
<p style="margin-bottom: 0in;">
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="write16"></a>write16( address, data ) : write
-the 16-bit data at the specified address</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="write16"></a>write16( address, data ) : grava
+dados de 16 bits no endereço especificado</font>
</p>
<p style="margin-bottom: 0in;">
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="write8"></a>write8( address, data ) : write the
-8-bit data at the specified address</font> <br>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="write8"></a>write8( address, data ) : grava
+dados de 8 bits no endereço especificado</font> <br>
</p>
<p style="margin-bottom: 0in;"><br>
</p>
<br>
-<font face="Bitstream Vera Sans Mono, sans-serif"><a name="read32"></a>Data = read32( address ) :
-reads 32-bit data from the specified address</font>
+<font face="Bitstream Vera Sans Mono, sans-serif"><a name="read32"></a>Data = read32( endereço ) :
+lê dados de 32 bits do endereço especificado</font>
<p style="margin-bottom: 0in;"></p>
<p style="margin-bottom: 0in;">
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="read16"></a>Data = read16( address ) : reads
-16-bit data from the specified address</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="read16"></a>Data = read16( address ) : lê
+dados de 16 bits do endereço especificado</font>
</p>
<p style="margin-bottom: 0in;">
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="read8"></a>Data = read8( address ) : reads 8-bit
-data from the specified address</font></p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="read8"></a>Data = read8( address ) : lê
+dados de 8 bits do endereço especificado</font></p>
<p style="margin-bottom: 0in;"><br>
</p>
<br>
<p style="margin-bottom: 0in;"><a name="disableinterrupts"></a>
-[cpu.disableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">cli(): disable
-CPU interrupts</font>
+[cpu.disableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">cli(): desabilita
+interrupçõs da CPU</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"><a name="enableinterrupts"></a>
-[cpu.enableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">sei(): enable
-CPU interrupts</font>
+[cpu.enableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">sei(): habilita
+interrupçõs da CPU</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
@@ -60,42 +60,42 @@
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
</font></p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="clockfrequency"></a>[cpu.clockfrequency()]
-Clock = clock(): returns the CPU frequency</font>
+Clock = clock(): retorna a frequência da CPU</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Also, you can
-expose as many CPU constants (for example memory mapped registers)</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Além disso, você pode
+expor tantas constantes da CPU (por exemplo memória registradores)</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">as you want to
-this module. You might want to use this feature to access some </font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">quantas você quiser para
+este módulo. Você talvez queira usar este recurso para acessar algumas </font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">CPU memory areas
-(as defined in the CPU header files from the CPU support </font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">áreas de memória usadas pela CPU
+(como está definido nos arquivos de header da CPU do pacote de suporte </font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">package)
-directly from Lua. To do this, you'll need to define the </font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"> da CPU)
+diretamente de Lua. Para realizar isso, você precisará definir a </font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">PLATFORM_CPU_CONSTANTS
-macro in the platform's platform_conf.h file </font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">macro PLATFORM_CPU_CONSTANTS
+no arquivo platform_conf.h da plataforma </font>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">(src/platform/<platform
-name>/platform_conf.h). Include all your constants in a </font>
+name>/platform_conf.h). Inclua todas as constantes na </font>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
-<constant name> ) definition, and then build your project.</font>
+<nome da constante> ) definição, e então faça seu projeto.</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For example,
-let's suppose that your CPU's interrupt controler has 3 memory</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Por exemplo,
+suponhamos que o controlador de interrupções da CPU possua 3 registradores de</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">mapped
-registers: INT_REG_ENABLE, INT_REG_DISABLE and INT_REG_MASK. If you want</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">memória
+mapeada: INT_REG_ENABLE, INT_REG_DISABLE and INT_REG_MASK. Se você quiser</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">to access them
-from Lua, locate the header that defines the values of these</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">acessá-los
+de Lua, localize o header que define os valores para esses</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">registers (I'll
-assume its name is "cpu.h") and add these lines to the</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">registradores (assumirei
+seu nome como sendo "cpu.h") e acrescente essas linhas no arquivo</font>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform_conf.h:</font>
</p>
@@ -119,8 +119,8 @@
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">After this
-you'll be able to access the regs directly from Lua, like this:</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Depois disso
+você poderá acessar os registradores diretamente, como segue:</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
@@ -132,14 +132,14 @@
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For a
-"real-life" example, see the src/platform/lm3s/platform_conf.h file.</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Como
+exemplo prático, veja o arquivo src/platform/lm3s/platform_conf.h.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[uart.sendstring]
-uart.sendstr( id, str1, str2, ... ): this is similar to "uart.send",
-but its parameters are string. </font>
+uart.sendstr( id, str1, str2, ... ): este é semelhante ao "uart.send",
+porém, seus parâmetros são strings. </font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
@@ -181,4 +181,4 @@
<br>
<br>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Modified: branches/eagle_mmc/doc/pt/disp_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/disp_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/disp_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -68,4 +68,4 @@
</span></big> <br>
<br style="font-family: Verdana;">
-</body></html>
\ No newline at end of file
+</body></html>
Added: branches/eagle_mmc/doc/pt/dl_binaries.html
===================================================================
--- branches/eagle_mmc/doc/pt/dl_binaries.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/dl_binaries.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,105 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="sources"></a>Downloading eLua pre-built binary images</span></h3>
+
+If you have an eLua capable hardware, you
+don't need to be a professional developer of the embedded world
+and to understand the details of the eLua building process, to be
+able to have eLua on your nice kits. <br><br>eLua project offers pre-built
+binary images for all the supported platforms.<br><br>All you have to do is to chose the
+corresponding image file from the table below, flash it into your
+board, connect a serial terminal (or Ethernet if you board supports)
+and enjoy eLua.<br><br>
+
+eLua binaries, like the <a href="dl_sources.html">source-code distributions</a>,
+include some example programs in it's file system, so you can run and
+play (yes! we have games too! :) them, following the instructions in
+our <a href="using.html">Using eLua</a> page. The available example programs are described in our <a href="examples.html">Examples</a> page.<br><br>
+
+If you need a customized binary image for an already supported
+platform (ie: with an autorun program, with some code of yours in the
+File System, with your LAN IP settings, .....) and you don't know how to build eLua, feel free to <a href="overview.html#contacts">write us</a> explaining what you need. We may (find some time to :) build one for you and eventually make it available here too.
+
+<br><br>To understand what's in a file name (for example elua_lualong_lm3s8962.bin) check our <a href="building.html">Building eLua</a> page, or at least the last part of it, where the meaning of the file names coming from the build system is explained.<br>
+
+
+<p><br></p><div><br><table class="table_center">
+ <tbody><tr>
+ <th>eLua Version</th>
+ <th>Target MCU</th>
+ <th>Lua Number</th>
+ <th>Memory Usage(KB)</th>
+ <th>Remarks</th>
+ <th>Download File</th>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Atmel ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~189<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x256.bin">elua_lua_at91sam7x256.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Atmel ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~189<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x512g.bin">elua_lua_at91sam7x512g.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Intel x86<br>(for fun :)</td>
+ <td>Float</td>
+ <td> </td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_i386.elf">elua_lua_i386.elf</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Luminary Micro ARM Cortex M3</td>
+ <td>Float</td>
+ <td>ROM: ~202<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s6965.bin">elua_lua_lm3s6965.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Luminary Micro ARM Cortex M3</td>
+ <td>Float</td>
+ <td>ROM: ~202<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s8962.bin">elua_lua_lm3s8962.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>NXP ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~229<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_lpc2888.bin">elua_lua_lpc2888.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>ST Microelectronics ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~189<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_str711fr2g.bin">elua_lua_str711fr2g.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>ST Microelectronics ARM 9</td>
+ <td>Float</td>
+ <td>ROM: ~229<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_str912fw44.bin">elua_lua_str912fw44.bin</a></td>
+ </tr>
+</tbody></table><br></div><p>Notes:</p>
+
+<ul><li>Lua Number refers to the built Lua interpreter number type, float or integer.</li><li>RAM Memory Usage is based on included Lua examples execution.</li></ul></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/dl_old.html
===================================================================
--- branches/eagle_mmc/doc/pt/dl_old.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/dl_old.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="old"></a>Downloading eLua Old Versions</span></h3><br><h2>Source Code</h2>Previous eLua versions, both for source code and binaries, can be downloaded from the <a href="http://developer.berlios.de/project/showfiles.php?group_id=9919">BerliOS files page</a><br><br><br><h2>Binaries</h2><br><p><br></p><div><br><table class="table_center">
+ <tbody><tr>
+ <th>eLua Version</th>
+ <th>Target MCU</th>
+ <th>Lua Number</th>
+ <th>Memory Usage(KB)</th>
+ <th>Remarks</th>
+ <th>Download File</th>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Atmel ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~189<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x256.bin">elua_lua_at91sam7x256.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Atmel ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~189<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_at91sam7x512g.bin">elua_lua_at91sam7x512g.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Intel x86<br>(for fun :)</td>
+ <td>Float</td>
+ <td> </td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_i386.elf">elua_lua_i386.elf</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Luminary Micro ARM Cortex M3</td>
+ <td>Float</td>
+ <td>ROM: ~202<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s6965.bin">elua_lua_lm3s6965.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>Luminary Micro ARM Cortex M3</td>
+ <td>Float</td>
+ <td>ROM: ~202<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_lm3s8962.bin">elua_lua_lm3s8962.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>NXP ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~229<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_lpc2888.bin">elua_lua_lpc2888.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>ST Microelectronics ARM7</td>
+ <td>Float</td>
+ <td>ROM: ~189<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_str711fr2g.bin">elua_lua_str711fr2g.bin</a></td>
+ </tr>
+ <tr>
+ <td>0.5</td>
+ <td>ST Microelectronics ARM 9</td>
+ <td>Float</td>
+ <td>ROM: ~229<br> RAM: 32~64</td>
+ <td>Official eLua release</td>
+ <td><a href="http://prdownload.berlios.de/elua/elua_lua_str912fw44.bin">elua_lua_str912fw44.bin</a></td>
+ </tr>
+</tbody></table><br></div><p>Notes:</p>
+
+<ul><li>Lua Number refers to the built Lua interpreter number type, float or integer.</li><li>RAM Memory Usage is based on included Lua examples execution.</li></ul><br><br><br><br></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/dl_sources.html
===================================================================
--- branches/eagle_mmc/doc/pt/dl_sources.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/dl_sources.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,50 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><br><h3><span class="info"><a name="sources"></a>Baixando código fonte de eLua</span></h3><h2>Versões Oficiais</h2>
+
+<h4>Código Fonte</h4>
+
+<p>A última versão liberada é a v0.6 e está disponível para download aqui:
+####<br>
+O pacote inclui o código fonte completo, documentação, scripts e exemplos de programa em Lua.<br></p>
+
+
+<p>Depois de baixar e descompactar os arquivos para o seu computador, abra o documento index_pt.html na pasta /doc e você terá acesso a documentação. São os arquivos deste site quando da liberação da versão v0.6.
+ Como este site é atualizado frequentemente, verifique sempre a versão online por <a href="news.html">novidades e atualizações de eLua</a>.</p><p>Você encontrará instruções de como compilar eLua na página <a href="building.html">Montando eLua</a>.</p><br><br>
+
+
+<h2><a name="svnpublic"></a>Repositório Público Subversion </h2>
+
+<p>Caso você prefira ter a última versão que ainda está em desenvolvimento ("bleeding edge"), simplesmente baixe-a em nosso repositório Subversion com o seguinte comando:</p>
+
+<pre>$ svn checkout svn://svn.berlios.de/elua/trunk<code><br></code></pre>
+
+
+<p>Para atualizar os seus arquivos use o seguinte comando:</p>
+
+<pre>$ svn update<code><br></code></pre>
+<p><br></p>
+
+<h2>Navegando pelo Repositório Subversion</h2>
+Caso você esteja procurando uma maneira mais fácil de ter acesso ao repositório SVN, use a <a href="http://svn.berlios.de/wsvn/elua">interface WebSVN</a><br><h2></h2>
+
+<h2><a name="svndev"></a>Repositório Subversion para desenvolvedores</h2>
+
+<p>Se você deseja contribuir para o desenvolvimento de eLua e precisa salvar arquivos no repositório, siga os seguintes passos:</p>
+
+<ul><li>se você não tem uma conta no <a href="http://developer.berlios.de/">developer.berlios.de,</a> crie uma antes de passar para o próximo passo.</li><li><a href="../../../../../../websites/elua%20site/www.eluaproject.net/index8603.html?p=Contact">entre em contato</a>, especificando a sua identificação no BerliOS e nós iremos incluí-lo na lista de desenvovedores.</li></ul>
+
+
+<p>Faça o download do repositório:</p>
+
+<pre>$ export SVN_SSH='ssh -l <yourberliosid>'<br style="font-family: Courier New;"><br style="font-family: Courier New;">$ svn checkout svn+ssh://svn.berlios.de/svnroot/repos/elua/trunk<code><br></code></pre>
+
+<p>Para atualizar os seus arquivos use o seguinte comando:</p>
+
+<pre>$ svn update<code><br></code></pre>
+
+<p><br></p><br><br><br><p></p><p></p><p></p><p></p></body></html>
\ No newline at end of file
Copied: branches/eagle_mmc/doc/pt/downloads.html (from rev 269, branches/eagle_mmc/doc/en/downloads.html)
===================================================================
--- branches/eagle_mmc/doc/en/downloads.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/downloads.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,7 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick"></a><span class="info">Downloads</span></h3><br></body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/eluaapi.html
===================================================================
--- branches/eagle_mmc/doc/pt/eluaapi.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/eluaapi.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,15 +1,15 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
<body style="background-color: rgb(255, 255, 255);">
-<h3><a name="over"></a>eLua API</h3>
+<h3><a name="over"></a>API eLua</h3>
<br>
<br>
<br>
<br>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Added: branches/eagle_mmc/doc/pt/examples.html
===================================================================
--- branches/eagle_mmc/doc/pt/examples.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/examples.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,133 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Exemplos de eLua</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Exemplos de código Lua</h3>Distribuições eLua trazem ótimos e interessantes (claro! tem jogos também! :) exemplos de programas em Lua.
+Eles estão incluídos também na distribuição que vem com os códigos fontes, no subdiretório /romfs. <br>Programas Lua para eLua são mostrados e comentados aqui também. <br>Como já foi dito, você pode rodá-los a partir do sistema de arquivos de eLua ou pode usar o shell de eLua e enviá-los através do XMODEM, como or you can use the eLua shell and send them via XMODEM, as
+descrito <a href="using.html#shell">aqui</a>.<br><br>
+
+<h3><a name="hello"></a>hello.lua: o obíquo "Hello, World!"</h3>
+
+<p><strong>Roda em: </strong><br>Todas as arquiteturas</p><p><strong></strong>
+
+<strong>Descrição:<br></strong>Chamar isto de um "programa" é um grande exagero, mas já é uma
+tradição, logo, vamos mantê-la :) Este programa imprime "Hello, World!" em um terminal e
+retorna para o shell. Baixe-o somente se sentir-se muito incomodado em executar o interpretador Lua inserido em eLua e digitá-lo você mesmo :)</p><p><strong>Código fonte comentado:</strong><br></p><p>print("Hello World")</p>
+
+<h2><br></h2><h3><a name="info"></a>info.lua: Obtendo os dados sobre a plataforma</h3>
+
+<p><strong>Roda em: </strong><br>Todas as arquiteturas</p><p><strong>Descrição:<br></strong>
+Este programa não é muito mais complicado do que o "Hello, World!", porém ele mostra um módulo específico de eLua: o módulo "platform data" (pd). Você pode ler
+mais sobre os módulos "platform" na distribuição do código fonte
+(docs/platform_modules.txt). O programa mostrará o nome da plataforma, o nome da CPU, o nome da placa e o clock da CPU e então finaliza e volta para o shell.</p><p><strong>Código fonte comentado:</strong></p><p><span>-- Usa o módulo pd para ter acesso aos dados da plataforma e mostrá-lo no Terminal </span><br><span>print( "Estou usando a platforma " .. pd.platform() ) </span><br><span>print( "A CPU é uma " .. pd.cpu() )</span><br><span><span>print( "A placa é uma " .. pd.board(</span>) )</span><br></p><p></p>
+
+<h3><a name="led"></a>led.lua: o velho LED que pisca, jeito novo de fazer com eLua</h3>
+
+<p><strong>Roda em: </strong><br>Todas as arquiteturas exceto i386</p><p><strong>Descrição:<br></strong><strong></strong>
+Agora temos que fazer algo com "cara" de embarcado: piscar um LED. O código a seguir ilustra alguns recursos interessantes de eLua:</p>
+
+<ul><li><p>código portátil entre plataformas: o código atribue um pino diferente
+para o LED começando pelo nome da placa. Você pode ver como o módulo de dados da plataforma torna a portabilidade do código muito fácil.</p></li><li><p>uart, pio, tmr, pd modules: todas eles são usados aqui.</p></li></ul>
+
+<p>Observe ele piscando, então pressione qualquer tecla para voltar ao shell de eLua.</p><p><strong>Código fonte comentado:</strong></p>
+
+<h3><a name="hangman"></a>hangman.lua: tirando vantagem de seu terminal</h3>
+
+<p><strong>Roda em: </strong><br>Todas as arquiteturas exceto i386</p><strong></strong>
+
+<strong></strong><p><strong>Descrição:<br></strong>Muito longe de ser o melhor exemplo da distribuição eLua (ou poderia ser o morse.lua? :), ele faz uso do
+módulo term (docs/terminal_support.txt) para deixar o usuário jogar como no
+BSD "hangman" diretamente no seu emulador de terminal. Rode o exemplo
+e aproveite. Atualmente existe uma pequena lista de palavras, pois este programa foi escrito principalmente com o propósito de testar a capacidade de eLua, mas é muito fácil
+acrescentar e substituir palavras na lista atual. Uma tela de exemplo pode ser vista <a href="http://elua.berlios.de/other/elua_hangman.png">aqui</a>.</p><p></p>
+
+<h3><a name="pwmled"></a>pwmled.lua: Piscador de LED, classe avançada</h3><p><strong>Roda em: </strong><br>EK-LM3S8962, EK-LM3S6965</p><strong></strong>
+
+<strong></strong><p><strong>Descrição:<br></strong>
+Este programa usa o módulo PWM para acender/apagar a luz do LED gradualmente, indefinidamente. Nada mais a dizer aqui, o código é bem simples, ainda que os
+resultados sejam bem interessantes. Presione qualquer tecla para finalizar o programa e retornar ao shell.</p><p></p>
+
+<h3><a name="tvbgone"></a>tvbgone.lua: yes, eLua can do real time!</h3>
+
+<p><strong>Runs on: </strong><br>EK-LM3S8962, EK-LM3S6965</p><strong></strong>
+
+<strong></strong><p><strong>Description:<br></strong>This is more complex, but also very important for eLua, because it
+proves that real time applications (with relatively strict timing
+requirements) can run from eLua directly. It's the famous TV-B-Gone
+project adapted from <a href="http://www.ladyada.net/make/tvbgone/">LadyAda's kit</a>.
+If you're not familiar with TV-B-Gone, it knows how to do one thing
+very well: power off your TV :) Basically it contains a lot of remote
+control codes (for a lot of TVs) that are continously sent via an IR
+LED. This code uses the PWM module (new in eLua 0.4) and it also does
+file I/O from Lua, since the remote control codes are kept in a
+separate file (which is also part of the ROM file system). To read the
+binary file, the "pack" module (also new in 0.4) is used. To ensure
+that we don't get any unexpected delays, the Lua garbage collector is
+turned off. Take a look at this sample, it's both a very good proof of
+the capabilities of eLua and a good learning resource. To use it on any
+of the Cortex boards (EK-LM3S8962 or EK-LM3S6965) connect an IR LED
+with a resistor between the "PWM2" and "GND" pins of the extension
+connector. Get close to your TV and press the "select" button on your
+board to start sending the IR codes. The on-board LED stays lit while
+the codes are transmitted and shuts off afterwards. Press the "down"
+button on your board to exit the application and return to the shell.</p><p></p>
+
+<h3><a name="piano"></a>piano.lua: because PWM is great</h3><p><strong>Runs on: </strong><br>EK-LM3S8962, EK-LM3S6965, SAM7-EX256</p><strong></strong>
+
+<strong></strong><p><strong>Description:<br></strong>
+Yet another use for the PWM module, this sample can be used to "play"
+notes via the on-board speaker using the PC keyboard. The on-screen
+keyboard shows what keys you must press for different notes, and you
+can set your octave and inter-note delay. Press ESC to end your eLua
+musical session :) A screenshot can be seen <a href="http://elua.berlios.de/other/elua_piano.png">here</a>.</p><p></p>
+
+<h3><a name="bisect"></a>bisect.lua: floating point at its best</h3>
+
+<p><strong>Runs on: </strong><br>All Targets</p><strong></strong>
+
+<strong></strong><p><strong>Description:<br></strong>This is taken directly from the official Lua distribution, and it's
+here to show that eLua can do floating point just like on a desktop
+machine, albeit slower. Run it on your target, then run it again, but
+this time on the PC, and compare the results. Yes, they are identical.</p><p></p>
+
+<h3><a name="morse"></a>morse.lua: because PWM is great, part II</h3>
+
+<p><strong>Runs on: </strong><br>EK-LM3S8962, EK-LM3S6965, SAM7-EX256</p><strong></strong>
+
+<strong></strong><p><strong>Description:<br></strong>This uses the same PWM module for Morse code generation. Just enter a
+text, and listen to it getting Morsed on your board's speaker and on a blinking Led. The
+letters and Morse codes are also shown on the terminal. Use '+' and
+'-'' to change the frequency, up and down arrows to change the speed,
+'s' to mute/unmute, and ESC to exit.</p><p></p>
+
+<h3><a name="lhttpd"></a>lhttpd.lua: only with (e)Lua ...</h3>
+
+<p><strong>Runs on: </strong><br>EK-LM3S8962, EK-LM3S6965<strong></strong>
+
+<strong></strong><br></p><p><strong>Description:<br></strong>This is one of those things that can show the real potential of a
+language (and hopefully the real potential of eLua in this case). As
+you have probably guessed by now, it's a web server written in Lua.
+Except that it is much more than this: it's a scripting web server! That's
+right, you can embed parts of Lua code into your pages, and the server
+will parse them and replace the Lua code with its output. To output
+something from Lua code embedded in a web page, simply use "print" in
+your Lua code. You can also write your pages completely in Lua (again,
+using "print"), the server knows how to handle this too. When is the
+last time you heard about a scripting web server in 256k of Flash/64k
+of RAM? </p><p>The full list of features is given below:</p>
+
+<ul><li>completely written in Lua</li><li>can handle a single connection at a time (for now)</li><li>can serve text and images (so far)</li><li>gets its files from the ROM file system (this will be extended when more filesystems are added)</li><li>can
+execute embedded Lua code and replace it with its output (via "print"
+statements). Embed Lua code in your HTML files between tags, make sure
+your HTML file extension is ".pht", and the server will preprocess it
+and replace the Lua code with its output</li><li>if a file with
+".lua" extension is requested, it doesn't send the file, but executes
+it and sends its output (via "print" statements)</li></ul>
+
+<p>This is still work in progress, but it already works quite well.
+Take a look at romfs/index.pht and romfs/test.lua from the source
+distribution for an example of how to include Lua code in your HTML
+files.</p><p></p><p></p><p></p></body></html>
\ No newline at end of file
Copied: branches/eagle_mmc/doc/pt/faq.html (from rev 269, branches/eagle_mmc/doc/en/faq.html)
===================================================================
--- branches/eagle_mmc/doc/en/faq.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/faq.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,209 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>eLua Frequently Asked Questions</h3><br><p>Welcome to the official eLua FAQ!
+It is assumed that you already know <a>what eLua is</a>, so here's a list of questions you might find useful while exploring eLua.</p>
+
+<ul><li><p><a href="faq.html#learnlua">How can I learn Lua? Is it hard?</a><br></p></li><li><p><a href="faq.html#helpelua">How can I help eLua?</a><br></p></li><li><p><a href="faq.html#comercial">Can I use eLua in my commercial, closed source project?</a><br></p></li><li><p><a href="faq.html#fast">Is eLua fast enough?</a><br></p></li><li><p><a href="faq.html#minimuns">What are the minimum requirements for eLua?</a><br></p></li><li><p><a href="faq.html#portability">Since
+I'm using the Lua platform modules (uart, spi, pwm, tmr...), can I
+trust my peripheral code to run the same on all my platforms?</a><br></p></li><li><p><a href="faq.html#luaversions">What's the deal with floating-point Lua and integer only Lua?</a><br></p></li><li><p><a href="faq.html#windows">All your tutorials give instructions on how to compile eLua under Linux, yet you seem to use a lot of Windows tools. How come?</a><br></p></li><li><p><a href="faq.html#cygwin">Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</a><br></p></li><li><p><a href="faq.html#bytecode">I
+know that Lua can be compiled to bytecode, so I compiled one of the
+eLua examples with luac and tried to run it on my eLua board, but it
+didn't work. Is this a bug in eLua?</a><br></p></li><li><p><a href="faq.html#outofmemory">I get "out of memory" errors when I run my Lua programs, what should I do?</a><br></p></li></ul>
+
+<p><br></p>
+
+<hr>
+
+<p><a name="learnlua"></a>
+<strong>Q: How can I learn Lua? Is it hard?</strong></p>
+
+<p>A: Lua is a minimalistic language (yet very powerful) which is quite
+easy to learn. Once you understand the basic concepts you'll find
+yourself writing Lua programs in notime. The main resource is the <a target="_top" href="http://www.lua.org/">Lua homepage</a>. In the <a target="_top" href="http://www.lua.org/docs.html">documentation page</a>
+you'll find the reference manual and the first version of the excellent
+"Programming in Lua" book. I recommend purchasing the second version of
+this book, since it's likely that this is all you'll ever need to learn
+Lua. Another very good resource is the <a target="_top" href="http://lua-users.org/wiki/">Lua wiki</a>. If you need more help, check the <a target="_top" href="http://www.lua.org/community.html">community page</a>. Lua has a very friendly and active community.</p><p></p><br><p><a name="helpelua"></a>
+<strong>Q: How can I help eLua?</strong></p>
+
+<p>A: OK, so I lied, this is NOT a frequently asked question :)
+However, if you really want to help eLua, keep in mind that we're
+looking for developers. eLua has many ambitious goals, so it would be
+great to have more people working on it. Take a look at the <a href="status.html#roadmap">roadmap page</a>, and if you see something there that you'd like to implement, don't hesitate to <a href="overview.html#contacts">contact us</a>.
+Also, if you'd like to make a donation to the project (money, or maybe
+a development board) rest assured that wwe won't say no :) It also
+helps a lot if you test eLua on your own board and you find a bug or an
+incomplete feature. Or if you just thought about a cool feature that
+you'd like to see in eLua. If so, feel free to <a href="overview.html#contacts">contact us</a>.</p><p></p>
+
+<p><a name="comercial"></a>
+<strong>Q: Can I use eLua in my commercial, closed source project?</strong></p>
+
+<p>A: ### This needs to be updated for the BSD license .........</p><p></p>
+
+<p><a name="fast"></a>
+<strong>Q: Is eLua fast enough?</strong></p>
+
+<p>A: This pretty much depends on what you expect. If you expect your
+Lua code to run as fast as your compiled C code, this won't happen,
+simply because C is a compiled language, while Lua is an interpreted
+language. That said, you'll be happy to know that Lua is one of the
+fastest interpreted languages out there. If you really need both high
+speed and Lua, you can write your speed critical code sections in C and
+export them as a Lua module. This way you get the best of both worlds.
+We don't have any official benchmarks about Lua speed on embedded
+devices, but you might want to check the TV-B-Gone example on the <a href="examples.html">examples page</a>.
+TV-B-Gone is a "software remote control" application coded directly in
+eLua. If you're familiar with the remote control protocols, you'll know
+that this kind of application is quite "real time", and delays in the
+order of milliseconds or even less can make your software remote
+control fail. Yet this sample runs without problems on a 50MHz Cortex
+(Thumb2) CPU. This should give you a fairly intuitive view on the speed
+of eLua.</p><p></p>
+
+<p><a name="minimuns"></a>
+<strong>Q: What are the minimum requirements for eLua?</strong></p>
+
+<p>A: It's hard to give a precise answer to this. As a general rule for
+a 32-bit CPU, we recommend at least 256k of Flash (program memory) and
+at least 64k of RAM. However, this isn't a strict requirement. A
+stripped down, integer-only version of eLua can definetely fit in 128k
+of Flash, and depending on your type of application, 32k of RAM might
+prove just fine. It largely depends on your needs.</p><p></p>
+
+<p><a name="portability"></a>
+<strong>Q: Since I'm using the Lua platform modules (uart, spi, pwm,
+tmr...), can I trust my peripheral code to run the same on all my
+platforms?</strong></p>
+
+<p>A: Unfortunately, no. While eLua makes it possible to have a common
+code on different platforms using the platform interface
+(docs/platform_interface.txt), it can't possibly provide the same
+functionality on all platforms, since all CPUs are not created equal.
+It is very recommended (and many times imperative) to have an
+understanding of the peripherals on your particular CPU before you
+write your code. This, of course, is not particular to eLua, but it's
+especially important since the platform interface might give the
+impression that it offers an uniform functionality over all platforms,
+when in fact the only thing in common is often just the interface
+itself (that is, the methods and variables you can access in a given
+module). eLua tries to help here by giving you an error when you try to
+access a physical resource that is not available (for example a timer,
+a PWM channel, or a PIO pin/port), but it doesn't try to cover all the
+possible platform-related issues, since this would increase the code
+size and complexity too much. These are some caveats that come to mind
+(note that these are only a few examples, the complete list is much
+longer):</p>
+
+
+<ul><li>timers: from all the platforms on which eLua runs, only
+the Luminary Cortex CPUs has rock solid 32-bit timers. You can do
+pretty much everything you need with them. All the other platforms have
+16-bit timers, which imposes some limits on the range of delays you can
+achieve with them. Make sure to use tmr.mindelay(id) and
+tmr.maxdelay(id) to check the actual resolution of your timers, and
+adapt your code accordingly. To 'compensate' for this, it's not
+possible to change the base timer frequency on the Cortex CPUs, but it
+is possible on most other platforms :) So be sure to also check the
+result of tmr.setclock(id)</li><li>also, when using timers,
+remember that if you're using XMODEM and/or the "term" module, TMR0 is
+used by both of them. So, if you change the TMR0 base clock in your
+code, be sure to restore the original setting before returning to the
+shell. You can change this static timer assignment by modifying
+src/main.c. It might also be possible to change it dynamically in the
+future, although I see little use for this.</li><li>PWM: the
+Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5
+respectively share the same base clock setting. So, when you're
+changing the base clock for channel 1, you're also changing the base
+clock for channel 0; if channel 0 was already running, you won't like
+what will happen next. This time no eLua function can save you, you
+simply need you know your CPU architecture.</li><li>GPIO: only
+some platform have internal pullups for the GPIO pins, while Cortex is
+the only platform that also provides pulldowns for its GPIOs. However,
+in this case you're safe, as eLua will signal an error if you try to
+execute a pullup operatin on a platform that does not support it.</li></ul>
+
+<p>The lesson here is clear: understand your platform first!</p><p></p>
+
+
+<p><a name="luaversions"></a>
+<strong>Q: What's the deal with floating-point Lua and integer only Lua?</strong></p>
+
+<p>A: Lua is build around a number type. Every number in Lua will have
+this type. By default, this number type is a double. This means that
+even if your program only does integer operations, they will still be
+treated as doubles. On embedded platforms this is a problem, since the
+floating point operations are generally emulated in software, thus they
+are very slow. This is why eLua gives you "integer only Lua": a Lua
+with the default number type changed to long. The advantages are
+increased speed and smaller code size (since we can force Newlib to
+"cut" the floating point code from printf/scanf and friends, which has
+quite a strong impact on the code size) and increased speed. The
+downside is that you'll loose the ability to do any floating point
+operations.</p><p></p>
+
+
+<p><a name="windows"></a>
+<strong>Q: All your tutorials give instructions on how to compile eLua
+under Linux, yet you seem to use a lot of Windows tools. How come?</strong></p>
+
+<p>A: It's true that we do all the eLua development under Linux, since we
+find Linux an environment much more suited for development. At the same
+time it's true that most of the tools that come with my development
+boards run under Windows. So we choose to use the best of both world: Bogdan runs Linux under an Virtual Machine Manager (<a target="_top" href="http://www.virtualbox.org/">VirtualBox</a>) and do everything else under Windows. Dado does everything on Linux and runs Windows under <a href="http://www.vmware.com" target="_top">VMWare</a>. Both options are nice if you master your environment. To make everything even more flexible, Bogdan keeps his
+VirtualBox Ubuntu image on an external WD passport disk that he can
+carry with him wherever he goes, so he can work on eLua whenever he has a
+bit of spare time :)</p><p></p>
+
+
+<p><a name="cygwin"></a>
+<strong>Q: Will you ever post instructions about how to compile toolchains under Cygwin in Windows?</strong></p>
+
+<p>A: Bogdan: If I ever have way too much spare time on my hands, yes.
+Otherwise, no. There are many reasons for this. As I already mentioned,
+I favour Linux over Windows when it comes to developing applications.
+Also, I noticed that the GNU based toolchains are noticeable slower on
+Cygwin than on Linux, so experimenting with them can prove frustrating.
+Also, compiling under Linux and Cygwin should be quite similar, so try
+starting from my Linux based tutorials, they might work as well on
+Cygwin.</p><p></p>
+
+
+<p><a name="bytecode"></a>
+<strong>Q: I know that Lua can be compiled to bytecode, so I compiled
+one of the eLua examples with luac and tried to run it on my eLua
+board, but it didn't work. Is this a bug in eLua?</strong></p>
+
+<p>A: This is not a bug in eLua, it's a bit more subtle than that. It's
+true that ARM and i386 are very similar when it comes to data types:
+all the fundamental data types have the same length, and they are both
+little endian. So, in theory, if you compile a Lua source file on PC
+you should be able to run the compiled bytecode on your eLua board
+without any modifications. But there's a problem here: the default
+double precision floating point representation is different on ARM and
+PC. So, while the two data types have the same endianess and size, they
+are represented differently in memory. This means that you can't use
+the "regular" luac compiler for this task. However, starting with
+version 0.5, you can cross-compile Lua code on PC to run on target. </p><p></p>
+
+
+<p><a name="outofmemory"></a>
+<strong>Q: I get "out of memory" errors when I run my Lua programs, what should I do?</strong></p>
+
+<p>A: There are a number of things you can try to overcome this:</p>
+
+<ul><li>precompile your source to bytecode: If you use bytecode instead of
+source code Lua won't need to compile your source, so you save some RAM.</li><li>try
+to avoid using too many strings: strings are immutable in Lua. That
+means that a statement like s = s .. "\n" (where s is a string) will
+create a new string each time it's called. If this happens a lot (for
+example in a loop), your memory will quickly run out because of all the
+strings. If you really need to do frequent string operations, put them
+in a table and then use <a href="http://www.lua.org/manual/5.1/manual.html#5.5">table.concat</a> to make a string from your table.</li><li>controll Lua's garbage collection manually: if you're still running out of memory, try
+calling collectgarbage('collect') from your code, which will force a
+garbage collection and thus might free some memory.</li></ul><br><br></body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/gpio_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/gpio_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/gpio_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -12,82 +12,82 @@
</p>
<br>
<p class="MsoNormal" style="font-family: Verdana;"><a name="setpinvalue"></a> [gpio.setpinvalue] pio.setpin(
-value, Pin1, Pin2 ... ): set the value to all the pins in the list
+value, Pin1, Pin2 ... ): atribui "value" (0 ou 1) para todos os pinos
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- to "value" (0 or 1).
+ da lista.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="setpinhigh"></a> [gpio.setpinhigh] pio.set(
-Pin1, Pin2, ... ): set the value of all the pins in the list to 1.
+Pin1, Pin2, ... ): atribui o valor 1 para todos os pinos na lista.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="getpinvalue"></a> [gpio.getpinvalue] Val1, Val2,
-... = pio.get( Pin1, Pin2, ... ): reads one or more pins and returns
+... = pio.get( Pin1, Pin2, ... ): lê um ou mais pinos e retorna
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- their values (0 or 1).
+ seus respectivos valores (0 or 1).
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="setpinlow"></a> [gpio.setpinlow] pio.clear(
-Pin1, Pin2, ... ): set the value of all the pins in the list to 0.
+Pin1, Pin2, ... ): atribui o valor 0 para todos os pinos na lista.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="configpin"></a> [gpio.configpin(gpio.DIR,
-gpio.DIR_INPUT)] pio.input( Pin1, Pin2, ... ): set the specified pin(s)
-as input(s).
+gpio.DIR_INPUT)] pio.input( Pin1, Pin2, ... ): configura o pino(s) especificado(s)
+como entrada(s).
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configpin(gpio.DIR, gpio.DIR_OUTPUT)] pio.output( Pin1, Pin2, ...
-): set the specified pin(s) as output(s).
+): configura o pino(s) especificado(s) como saída(s).
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="setportvalue"></a> [gpio.setportvalue]
-pio.setport( value, Port1, Port2, ... ): set the value of all the ports
-in the
+pio.setport( value, Port1, Port2, ... ): inicializa o valor de todas as portas
+na lista
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- list to "value".
+ para "value".
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="getportvalue"></a> [gpio.getportvalue] Val1,
-Val2, ... = pio.getport( Port1, Port2, ... ): reads one or more ports
-and
+Val2, ... = pio.getport( Port1, Port2, ... ): lê uma ou mais portas
+e
</p>
<p class="MsoNormal" style="font-family: Verdana;">
- returns their values.
+ retorna seus respectivos valores.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="getportname"></a> [gpio.getportname]
-Port = pio.port( code ): return the physical port number associated
-with the given code. For example, "pio.port( pio.P0_20 )" will return
+Port = pio.port( code ): retorna o número físico da porta associada
+com o código passado como argumento da função. Por exemplo, "pio.port( pio.P0_20 )" retornará
0.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;"><a name="getpinnumber"></a> [gpio.getpinnumber] Pin =
-pio.pin( code ): return the physical pin number associated with the
+pio.pin( code ): retorna o número físico do pino associado com
</p>
<p class="MsoNormal" style="font-family: Verdana;">
-given code. For example, "pio.pin( pio.P0_20 )" will return 20.
+o código passado como argumento da função. Por exemplo, "pio.pin( pio.P0_20 )" retornará 20.
</p>
<br>
<a name="togglepin"></a>[gpio.togglepin([Pin1],
@@ -107,48 +107,48 @@
<br>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configport(gpio.DIR, gpio.DIR_INPUT, [Port1], [Port2], ...)]
-pio.port_input( Port1, Port2, ... ): set the specified port(s) as
-input(s).
+pio.port_input( Port1, Port2, ... ): configura a(s) porta(s) especificada(s) como
+entrada(s).
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configport(gpio.DIR, gpio.DIR_OUTPUT, [Port1], [Port2], ...)]
-pio.port_output( Port1, Port2, ... ): set the specified port(s) as
-output(s).
+pio.port_output( Port1, Port2, ... ): configura as porta(s) especificada(s) como
+saída(s).
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configpin(gpio.PULL, gpio.PULL_UP, [Pin1], [Pin2], ...)]
-pio.pullup( Pin1, Pin2, ... ): enable internal pullups on the specified
-pins.Note that some CPUs might not provide this feature.
+pio.pullup( Pin1, Pin2, ... ): habilita "internal pullups" para os pinos
+especificados na lista. É importante observar que algumas CPUs podem não ter este recurso disponível.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configpin(gpio.PULL, gpio.PULL_DOWN, [Pin1], [Pin2], ...)]
-pio.pulldown( Pin1, Pin2, ... ): enable internal pulldowns on the
-specified pins. Note that some CPUs might not provide this feature.
+pio.pulldown( Pin1, Pin2, ... ): habilita "internal pulldowns" para os pinos
+especificados na lista. É importante observar que algumas CPUs podem não ter este recurso disponível.
</p>
<p class="MsoNormal" style="font-family: Verdana;">
</p>
<p class="MsoNormal" style="font-family: Verdana;">
[gpio.configpin(gpio.PULL, gpio.PULL_NO, [Pin1], [Pin2], ...)]
-pio.nopull( Pin1, Pin2, ... ): disable the pullups/pulldowns on the
-specifiedpins. Note that some CPUs might not provide this feature.
+pio.nopull( Pin1, Pin2, ... ): desabilita "internal pullups/pulldowns" para os pinos
+especificados na lista. É importante observar que algumas CPUs podem não ter este recurso disponível.
</p>
<br>
<br>
-What is the real advantage/reason of having a pin "list" on some of
-these functions ? If we cannot build a table with them, there's really
-no great use of this, as we cannot create the list in run time and some
-other proposed functions solve the problem of avoiding more than one
-call for several pins.<br>
-A: It IS usefull and sometimes necessary so it will stay.....<br>
+Qual a real vantagem/razão de usarmos uma "lista" de pinos
+em algumas dessas funções ? Como não podemos criar
+uma tabela com eles, não existe realmente vantagem em usá-la,
+já que não podemos criar a lista em tempo de execução e algumas
+outras funções propostas resolvem o problema de evitar mais de uma chamada para vários pinos.<br>
+A: É útil e as vezes necessária, logo continuará.....<br>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Modified: branches/eagle_mmc/doc/pt/net_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/net_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/net_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,11 +1,11 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
<body style="background-color: rgb(255, 255, 255);">
-<h3><a name="over"></a>net</h3>
+<h3><a name="over"></a>rede</h3>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Added: branches/eagle_mmc/doc/pt/news.html
===================================================================
--- branches/eagle_mmc/doc/pt/news.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/news.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,138 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>eLua Project News</h3><div class="content">
+
+<h2>02 de Fevereiro de 2009</h2>
+<p>Ainda não temos uma versão oficial liberada, no entanto, estamos avançando muito com o projeto. A próxima versão será liberada,
+até o fim deste mês e virá com uma grande quantidade de novos recursos, incluindo suporte para duas novas plataformas, o sistema
+de documentação foi totalmente redesenhado, e algumas surpresas que não mencionarei no momento :) Estamos trabalhando muito para
+tornar <strong>eLua</strong> cada vez melhor para você.</p>
+
+<h2>01 de Novembro de 2008</h2>
+
+<p>A versão 0.5 foi lançada! Dentre outras novidades, essa versão vem com suporte TCP/IP para eLua (!!!!). Segue a lista das atualizações:</p>
+
+<ul>
+<li>Suporte para microcontroladores STR7 da ST Microeletronics</li>
+<li>Suporte TCP/IP usando o stack uIP</li>
+<li>Suporte do console e do *shell* sobre TCP/IP além da conexão serial.</li>
+<li>Módulo "net" (interface **eLua** para as funções TCP/IP)</li>
+<li>Módulo "cpu" (interface **eLua** para o dados do microcontrolador escolhido)</li>
+<li>Novos exemplos: morse.lua (código morse), lhttpd.lua (script Lua para servidor HTTP)</li>
+<li>Cross Compiling Lua (compila no computador, roda na plataforma)</li>
+<li>XMODEM pode agora receber o *bytecode*, além de código fonte Lua</li>
+<li>Um *buffer* dinâmico para o XMODEM (cresce se necessário) ao invés de tamanho fixo</li>
+<li>Documentação atualizada do projeto</li>
+</ul>
+
+<p>Adicionado também um novo tutorial sobre como usar <a href="http://www.eluaproject.net/?p=eLua_on_STR7_CPUs"><strong>eLua</strong> com o microcontrolador STR7</a> da ST. O restante da página do projeto foi atualizada refletindo o Status atual do projeto (isso fica mais evidente nas páginas de <a href="/pt/Faq.html">Perguntas mais frequentes</a>, <a href="/pt//pt/examples.html">Exemplos</a> e <a href="/pt//pt/status.html">Status</a>.</p>
+
+<p><strong>Importante:</strong> não é necessário atualizar o binutils para a versão 2.19 para os microcontroladores Cortex. O tutorial do <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">Cortex GCC para Cortex</a> já foi atualizado com esta informação.</p>
+
+<p>Desfrute dessa nova atualização. A próxima versão será focada na redução das memórias Flash e RAM de <strong>eLua</strong>, além de muitas outras surpresas :)</p>
+
+<h2>16 de Outubro de 2008</h2>
+<p>O <a href="http://www.eluaproject.net/?p=Using_OpenOCD">tutorial OpenOCD</a> foi atualizado com uma nova seção sobre como usar o OpenOCD com CPU's STR7 da ST. Além disso, a <a href="http://www.eluaproject.net/?p=Overview">página sobre</a> foi atualizada com mais informações sobre os autores de eLua. É esperada uma nova versão de Elua para até o fim de Outubro.</p>
+
+<h2>10 de Setembro de 2008</h2>
+<p>Foi liberada a versão 0.4.1! É uma atualização de pouca importância, pois seu propósito principal é se manter atualizada com Lua,
+dessa forma, eLua está agora com a mais recente versão de Lua (5.1.4).
+Provavelmente você não precisa fazer a atualização para esta versão (já que a 5.1.4 corrige alguns poucos e exóticos problemas da 5.1.3), logo,
+ estou disponibilizando somente os fontes, sem nenhum executável. Segue abaixo o log das alterações:</p>
+
+<ul>
+<li>Alterada a estrutura do sistema de arquivos; agora você pode gerar executáveis de ambas as versões de Lua (ponto flutuante e somente inteiro) a partir do mesmo diretório;</li>
+<li>Feita uma biblioteca matemática configurável usando-se o próprio mecanismo de bibliotecas já eistentes na plataforma;</li>
+<li>Os módulos "os" and "package" não são mais carregados por Lua, uma vêz que não podem mais ser utilizados. Devido a isso, o tamanho do código Lua ficou reduzido;</li>
+<li>A documentação do projeto foi atualizada.</li>
+</ul>
+
+
+<h2>02 de Setembro de 2008</h2>
+<p>Foi liberada a versão 0.4! Segue abaixo o log das alterações:</p>
+
+<ul>
+<li>Criado suporte para LPC2888 (preliminarmente);</li>
+<li>Criado o módulo PWM;</li>
+<li>Novos exemplos: TV-B-Gone (desliga a sua TV), piano (toca piano a partir do teclado de seu PC),
+ pwmled (apaga/acende led), todas baseadas no novo módulo PWM;</li>
+<li>Criado suporte para múltiplos espaços de memória (este recurso pode ser usado para obter vantagens tanto de memória RAM interna da CPU quanto de chips externos de memória RAM em placas com memória RAM);</li>
+<li>Autorun: Caso o arquivo "autorun.lua" exista no sistema de arquivos, este é executado antes do inicio do shell;</li>
+<li>Criado os módulos "pack" (compactação/descompactação de dados binários) e "bit" (operações binárias);</li>
+<li>Atualizado o compilador do sistema, que agora está mais fácil de utilizar e sabendo como lidar com "placas", como também CPUs;</li>
+<li>Foram modificados os módulos da plataforma existente para utilizar menos RAM e retornar uma mensagem de erro quando da tentativa de uso de um recurso não disponível no sistema;</li>
+<li>A documentação do projeto foi atualizada.</li>
+</ul>
+
+
+<h2>02 de Setembro de 2008</h2>
+<p>O site eLua foi atualizado antes da liberação da nova versão 0.4, a qual estará em breve disponível (muito breve por sinal). Existe agora uma <a href="http://www.eluaproject.net/?p=Faq">página FAQ</a>. Além disso, as páginas <a href="http://www.eluaproject.net/?p=Status">status e mapa do site</a>, <a href="http://www.eluaproject.net/?p=Building_eLua">compilando eLua</a>, <a href="http://www.eluaproject.net/?p=Example">exemplos de programas</a> e <a href="http://www.eluaproject.net/?p=Using_OpenOCD">usando OpenOCD</a> foram atualizadas. E existe ainda uma outra página chamada <a href="http://www.eluaproject.net/?p=eLua_on_LPC2888_CPUs">Como usar eLua com CPUs LPC2888</a>. Esperada ainda hoje a liberação da versão 0.4.</p>
+
+<h2>09 de Agosto de 2008</h2>
+<p>OK, está levando mais tempo do que esperava :) Está disponível a página sobre como utilizar eLua com CPUs STR9 <a href="http://www.eluaproject.net/?p=eLua_on_STR9_CPUs">aqui</a>.</p>
+
+<h2>09 de Agosto de 2008</h2>
+<p>Foi liberada a versão 0.3! O página do projeto foi atualizada, e mais seções estarão disponíveis em breve, incluindo um tutorial sobre como utilizar eLua com CPUs STR9. Segue abaixo o log das alterações da versão 0.3:</p>
+
+<ul>
+<li>Agora você pode jogar hangman diretamente de eLua :), graças ao novo módulo "term" que é capaz de tratar sequências de "escape" ANSI;</li>
+<li>Criado suporte para o ST STR912FW44</li>
+<li>Criado suporte para o Cortex LM3S6965</li>
+<li>Sistema de compilação mais intuitivo e flexível (nova sintaxe, seleção de componentes em tempo de compilação)</li>
+<li>Examples de eLua esão agora fazendo parte do repositório</li>
+<li>A documentação do projeto foi atualizada.</li>
+</ul>
+
+<h2>06 de Agosto de 2008</h2>
+<p>A página de web foi atualizada com o <a href="http://www.eluaproject.net/?p=Using_OpenOCD">tutorial OpenOCD</a>
+o qual continuará sendo revisado toda vêz que novas plataformas forem adicionadas. Esta atualização é também um anúncio informal da liberação em breve da versão 0.3, a qual (entre outras coisas) traz o suporte para o <a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>.</p>
+
+<h2>29 de Julho de 2008</h2>
+<p>eLua possui um novo repositório no BerliOS. Além do novo menu da página da web, a novidade é que o repositório de código está baseado no SVN (ao contrário do CVS utilizado até o momento).
+Caso você seja um desenvolvedor, provavelmente esta é uma boa notícia. Caso contrário, verifique a página de download para conhecer os novos locais para download.</p>
+
+<h2>28 de Julho de 2008</h2>
+<p>Recebi um relato sobre erros de linker após a execução de <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">minhas intruções</a> durante a compilação de um simples programa C++ para a CPU Cortex com compilador.
+ Verifiquei e descobri que a biblioteca gcc's C++ (libstdc++) não estava gerando código corretamente para Cortex-M3. Minha culpa. Corrigi a página do tutorial. Foi necessário uma única alteração no passo 4,
+onde era preciso fornecer mais parametros para os comandos "make", e não somente o -CFLAGS. Obrigado pelo aviso.</p>
+
+<h2>27 de Julho de 2008</h2>
+<p>Foi liberada a versão 0.2! Além disso, como você já deve ter percebido, a página do projeto foi bastante modificada. Segue abaixo o log das alterações da versão 0.2:</p>
+
+<ul>
+<li>Criado suporte para o Cortex LM3S8962</li>
+<li>Módulos para novas plataformas (UART, SPI, Timer, platform data)</li>
+<li>Primeiro versão do eLua shell</li>
+<li>Arquivos fontes de Lua podem agora serem enviados para processadores com XMODEM</li>
+<li>Pode-se baixar arquivos binários de imagem a partir de seções de "arquivos", logo, você não precisa recompilar eLua</li>
+</ul>
+
+<h2>25 de Julho de 2008</h2>
+<p>A página do projeto fo atualizada para refletir o atual <a href="http://www.eluaproject.net/?p=Status">status e roadmap</a> de eLua.
+Atualmente as páginas de status e de roadmap são separadas. Além disso, a versão 0.2 está sendo liberada em breve, com vários novos recursos, melhoramentos e
+suporte para novas plataformas. Novas documentações estão sendo preparadas.</p>
+
+<h2>15 de Julho de 2008</h2>
+<p>Criado um <a href="http://www.eluaproject.net/?p=Booting_eLua_from_a_stick">tutorial</a> sobre como preparar um pendrive USB de boot com eLua! Acesse-o enquanto está quente! :)</p>
+
+<h2>11 July 2008</h2>
+<p>A versão 0.1 finalmente saiu! Certifique-se de verificar a <a href="http://www.eluaproject.net/?p=Downloads">página de download</a>,
+e também a página do projeto. A instruções de como fazer estão incluídas nos arquivos eLua. Além disso, novos tutoriais (construindo compiladores para o ARM e para o i386) foram criados, e a página <a href="http://www.eluaproject.net/?p=Booting_your_PC_in_eLua">boot em Lua</a> fo atualizada para refletir o fato de que agora você mesmo pode construir um arquivo ELF!</p>
+
+<h2>07 de Julho de 2008</h2>
+<p>Estou ainda "polindo" os códigos fontes e criando mais documentação antes de atualizar a promeira versão par o CVS. Enquanto isso, Preparei uma ótima surpresa para todos voces que se mostraram interessados em eLua (e par voces que não se interessaram também, pois desejo muito que a partir de agora voces fiquem curiosos:) ). Logo, se você sempre quis iniciar seu PC com Lua, dê uma olhada <a href="http://www.eluaproject.net/?p=Booting_your_PC_in_eLua">aqui</a>.
+É isso mesmo: sem OS, simplesmente o GRUB carrega um arquivo de boot tipo ELF!
+O arquivo tipo ELF é construido de acordo com a mesma estrutura em árvore que utilizei para montar dispositivos embarcados em eLua, precisei mudar somente a camada da plataforma
+(mais informações após a próxima atualização dos fontes e inclusão de novas documentações).
+Desejo que tenham gostado, da mesma maneira que eu. Enquanto isso é apenas uma prova de conceitos, não irei abandonar a idéia do "standalone Lua on PC", pois devem ter aplicações interesantes (pense em
+"BIOS scripting with Lua", <a href="http://en.wikipedia.org/wiki/Open_Firmware">Open Firmware</a> com Lua ao invés de Forth, aplicações educacionais e muias outras.)</p>
+
+<h2>05 de Julho de 2008</h2>
+<p>Inaugurada a página na web! Por enquanto você pode ler as <a href="http://www.eluaproject.net/?p=Overview">descrições dos projetos</a>. Além disso, está disponível um tutorial que explica como compilar um toolchain GCC para a arquitetura Cortex <a href="http://www.eluaproject.net/?p=Building_GCC_for_Cortex">aqui</a>.</p>
+</div>
+</body></html>
Copied: branches/eagle_mmc/doc/pt/overview.html (from rev 269, branches/eagle_mmc/doc/en/overview.html)
===================================================================
--- branches/eagle_mmc/doc/en/overview.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/overview.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,98 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<a name="whatis"></a><h3>What is eLua ?</h3>
+<strong>eLua</strong>
+stands for <strong>Embedded Lua</strong> and the project
+aims to offer the full set of features of the <a href="www.lua.org">Lua Programming Language</a> to the embedded world. <span style="font-weight: bold;"><br>eLua</span>
+is not a striped down sub-sub-set of a language, much on the contrary.
+Besides offering different flavors of full Lua implementations
+(ie: integer or fp numbers, ...), <span style="font-weight: bold;">eLua</span>
+extends Lua with some neat types
+for the embedded world (ie: light tables, light functions, ...), to
+allow them to be romable and the aplications to exploit better the
+balance ROM/RAM of the current MCUs.<br><br>
+Lua is the perfect example of a
+minimal, yet fully
+functional language. Although generally advertised as a "scripting
+language" (and used accordingly especially in the game industry), it is
+also fully capable of running stand-alone programs. Its limited
+resource requirements make it suitable to a lot of microcontroller
+families. Lua's incredible portability (Lua code is ANSI C and runs virtually in every known platform) and <span style="font-weight: bold;">eLua</span>'s
+roadmap for supporting the most used MCUs on the market, opens to the
+embedded world a new degree of "portability". Write your program in Lua
+and run it, without or with very few modifications, on every <span style="font-weight: bold;">eLua</span> supported platform, even with different architectures!<br><br>The aim of the project is to have a fully functional Lua development
+environment <strong>on the microcontroller itself</strong>,
+without the need to install a specific development environment on the PC side.
+Initially, a PC will still be needed in order to edit the Lua programs
+for the microcontroller. But as the project evolves this requirement
+will be relaxed, as a basic editor (also residing on the
+microcontroller) will be usable with a variety of input/output devices.<br><br><span style="font-weight: bold;"></span><br>
+<br><br>
+<a name="audience"></a><br><h3>Audience</h3>
+<span style="font-weight: bold;">eLua</span> has a wide and varied audience, from highly skilled developers
+that want to extend their programs with the Lua library facilities and
+portable features, to the newcomer to the embedded world, who wants an
+easy and powerfull environment for prototyping, rapid application
+development, educational or final product quick production.<br><br><span style="font-weight: bold;">eLua</span>
+allows new embedded world programmers to use the simplicity and
+powerfullness of the Lua programming language, to hide low-level
+complexities and platform/architecture-dependent features. A whole new
+class of embedded programmers, with no deep knowledge of the peripheral
+details but with powerfull aplications in mind is now possible. Modern
+designers and multimedia artists are already an example of this "class".<br><br>On
+the other edge of the category, oldtime and skilled embedded developers
+can create complex and abstract modules, offering a degree of portability
+to the final user never dreamed before on the embedded world.<br><br>eLua audience would be among the following categories:<br><ul><li>Embedded developers that are looking for a fast, easy to use and powerful way of coding.</li><li>First-time
+embedded programmers (or simply first time programmers) that are
+looking for an easy way to "dive" into the embedded programming world.
+eLua is a great learning tool.</li><li>People that aren't really
+developers, but want to be able to prototype an embedded system
+fast and painless, without having to learn C for that.</li><li>Embedded
+developers that need powerfull meta-language mecanisms for complex code
+algorithms and data description, not offered by the languages available
+to the embedded development world.</li><li>Field
+engineers that can go their customer site and debug an eLua module on
+site, without any preparation at all, since the whole development
+environment resides on chip already.</li></ul><br><a name="authors"></a>
+<h3>Authors</h3>
+<p><strong>eLua</strong> is a joint project of <strong><a href="#contacts">Bogdan Marinescu</a></strong>,
+a software developer from Bucharest (Romania) and <strong><a href="#contacts">Dado Sutter</a></strong>,
+head of the Led Lab at <a href="http://www.puc-rio.br/">PUC-Rio
+University</a>, in Rio de Janeiro (Brazil). </p>
+<p>Its origins come from the <a href="http://www.circuitcellar.com/renesas2005m16c/winners/1685.htm">ReVaLuaTe</a>
+project also developed by Bogdan Marinescu (as a contest entry for the
+2005 Renesas M16CDesign Contest), and the Volta Project, managed by
+Dado Sutter at PUC-Rio from 2005 to 2007.</p>
+<p><strong>eLua</strong> is an Open Source and
+collaborative project and an always growing list of collaborators can
+be found in our <a href="#credits">Credits
+Page</a></p><p></p>
+<div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><table style="width: 578px; height: 256px; text-align: left; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2"><tbody><tr><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>ReVaLuaTe Project</big></td><td style="text-align: center; font-family: Verdana; font-weight: bold;" valign="undefined"><big>Volta Project</big></td></tr><tr><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 188px;" alt="ReVaLuaTe project picture" src="../wb_img/terminalreneseas.jpg"></td><td style="text-align: center;" valign="undefined"><img style="width: 278px; height: 209px;" alt="Volta project picture" src="../wb_img/volta-small.jpg"></td></tr></tbody></table><div style="text-align: center;"><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"!
></span><br><span style="font-weight: bold;"></span><br><span style="font-weight: bold;"></span></div><br><a name="contacts"></a>
+<h3>Contacts</h3>
+<p><strong>eLua</strong> authors can be contacted at:</p><p><strong>Bogdan Marinescu:</strong> bogdan dot marinescu at gmail dot com</p>
+
+<p><strong>Dado Sutter:</strong> dadosutter at gmail dot com</p> <br> You are also welcome to share your questions and suggestions on our <a href="comunity.html#lists">Mail Discussion List</a>
+<p></p><a name="license"></a>
+<h3>License</h3>
+<div class="content">
+<p><strong>eLua</strong> is Open Source and is freely
+distributed under the GPL (migrating to BSD soon) licence.</p>
+<p>The Lua code (with slight modifications) is included in the
+source
+tree and is, of course, licensed under the same MIT license that Lua
+uses.</p>
+<p>The terms of each of these licences can be viewed on their own
+pages at:</p>
+<p><a target="_top" href="http://en.wikipedia.org/wiki/GNU_General_Public_License">GPL
+Licence</a></p>
+<p><a target="_top" href="http://en.wikipedia.org/wiki/BSD_license#Terms">BSD
+Licence</a></p>
+<p><a target="_top" href="http://en.wikipedia.org/wiki/MIT_License">MIT
+Licence</a></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p></p><p><a href="http://en.wikipedia.org/wiki/MIT_License"></a></p>
+</div>
+</body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/platdependentmodules.html
===================================================================
--- branches/eagle_mmc/doc/pt/platdependentmodules.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/platdependentmodules.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,12 +6,11 @@
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
<body style="background-color: rgb(255, 255, 255);">
-<h3><a name="over"></a>eLua Platform Dependent
-Modules</h3>
+<h3><a name="over"></a>Módulos Dependentes da Plataforma eLua</h3>
<br>
<br>
<br>
<br>
<br>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Copied: branches/eagle_mmc/doc/pt/platdepmodules.html (from rev 269, branches/eagle_mmc/doc/en/platdepmodules.html)
===================================================================
--- branches/eagle_mmc/doc/en/platdepmodules.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/platdepmodules.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,16 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css">
+</head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3><a name="over"></a>Módulos Dependentes da Plataforma eLua</h3>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+</body></html>
Modified: branches/eagle_mmc/doc/pt/pwm_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/pwm_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/pwm_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -10,33 +10,33 @@
<span style="font-weight: bold;"></span><br>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
-use the PWM blocks on the target CPU.</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Permite que Lua use
+os blocos PWM para a CPU em questão.</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><strike><a name="setup"></a>[pwm.setup]</strike>(</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.setup( id,
frequency, Active Cycle ) </font><font face="Bitstream Vera Sans Mono, sans-serif">
-Data = pwm.setup( id, frequency, duty ): sets the PWM block 'id' to
-generate the specified frequency with the specified duty cycle (duty is
-an integer number from 0 to 100, specifying the duty cycle in
-percents). It returns the actual frequency set on the PWM block.</font>
+Data = pwm.setup( id, frequency, duty ): configura o 'id' do bloco PWM para
+gerar a frequência especificada com o ciclo 'duty' especificado (duty é
+um número inteiro entre 0 e 100, indicando o percentual a ser
+utilizado). Ela retorna a frequência real configurada no bloco PWM.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> Here there is a bigger
-change on the proposal.
+<p style="margin-bottom: 0in;"> Aqui existe uma enorme
+mudança na proposta.
</p>
-<p style="margin-bottom: 0in;"> The Timer Clock and the
-PWM "frame" frequency would be set up in the same function (.setup)
+<p style="margin-bottom: 0in;"> O Timer Clock e a frequência
+PWM "frame" seriam configurados na mesma função (.setup)
</p>
-<p style="margin-bottom: 0in;"> The normal control
-function would only set the active cicle (.setcycle)
+<p style="margin-bottom: 0in;"> A função normal de
+controle configuraria somente o ciclo ativo (.setcycle)
</p>
-<p style="margin-bottom: 0in;"> The original .setup
-function would then be replaced by:
+<p style="margin-bottom: 0in;"> A função original .setup
+seria substituída por:
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
@@ -46,39 +46,39 @@
<p style="margin-bottom: 0in;"> <a name="setcycle"></a>[pwm.setcycle(
id, active_cycle )]</p>
<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><a name="start"></a>[pwm.start()]
-pwm.start( id ): start the PWM block 'id'.</font>
+pwm.start( id ): inicia o 'id' do bloco PWM.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="stop"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop()]
</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop(
-id ): stop the PWM block 'id'.</font>
+id ): finaliza o 'id' do bloco PWM.</font>
</p>
<br>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="setclock"></a>Data = pwm.setclock( id, clock ):
-set the base clock of the PWM block 'id' to</font>
+configura o clock base do 'id' do bloco PWM para</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the given clock.
-In returns the actual clock set on the PWM block.</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">o clock informado.
+Retorna o clock corrente do bloco PWM.</font>
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[</font><font face="Bitstream Vera Sans Mono, sans-serif"><strike>pwm.getclock</strike>]
</font><font face="Bitstream Vera Sans Mono, sans-serif">Data
-= pwm.getclock( id ): returns the base clock of the PWM block 'id'.</font>
+= pwm.getclock( id ): retorna o clock base do 'id' do bloco PWM.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> Is it really necessary to
-have
-.getclock ?? The clock is set by the same program, is seldom changed
-during operation, ..........
+<p style="margin-bottom: 0in;"> Realmente é necessário
+existir
+.getclock ?? O clock é configurado pelo mesmo programa, é alterado repentinamente
+durante a operação, ..........
</p>
-<p style="margin-bottom: 0in;"> If really needed, it could
-be something like pwm.gettimerclock(id) or something (must be
-discussed.....)
+<p style="margin-bottom: 0in;"> Caso fosse realmente necessário, poderia ser
+algo como pwm.gettimerclock(id) ou quem sabe (isso deve ser mais
+discutido.....)
</p>
<p style="margin-bottom: 0in;"> <br>
</p>
@@ -132,4 +132,4 @@
</span></big> <br>
<br style="font-family: Verdana;">
-</body></html>
\ No newline at end of file
+</body></html>
Copied: branches/eagle_mmc/doc/pt/refman.html (from rev 269, branches/eagle_mmc/doc/en/refman.html)
===================================================================
--- branches/eagle_mmc/doc/en/refman.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/refman.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,806 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head><meta http-equiv="content-type" content="text/html; charset=ISO-8859-1"><meta http-equiv="Content-Language" content="en-us"><title>Product</title><link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>eLua Modules Reference Manual
+</h3>
+<h2><a name="genericmodules"></a>eLua Generic
+Modules</h2>A Generic eLua Module is a module that can be used by a Lua program running on any of the <a href="status.html#platforms">supported eLua platforms</a>.<br>Write your code once and it is already automatically ported to the main platforms of the embedded world.<br><br><br><br><br><br><br><br><br><br><h3><a name="bitmodule"></a>bit</h3>
+Bitwise operations in eLua is implemented thru
+the BitLib library, from Reuben Thomas.<br>
+BitLib project is hosted at LuaForge on
+<a href="http://luaforge.net/projects/bitlib" target="_top">http://luaforge.net/projects/bitlib</a><br>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bnot"></a>Res = bit.bnot( value )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+unary negation
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_band"></a> Res = bit.band( v1, v2, ... )</p>
+<p class="MsoNormal" style="font-family: Verdana;"><b>bitwise
+</b>"and"
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bor"></a> Res = bit.bor( v1, v2, ... )</p>
+<p class="MsoNormal" style="font-family: Verdana;"><span style="font-weight: bold;"> </span><b class="info" style="font-weight: bold;">bitwise</b><b class="info" style="font-weight: bold;">
+</b><span class="info" style="font-weight: bold;">"or"</span>
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bxor"></a> Res = bit.bxor( v1, v2, ... )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+<b>bitwise</b><b> </b>"exclusive or"
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_lshift"></a> Res = bit.lshift( value, pos )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+shift "value" left "pos" positions.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_rshift"></a> Res = bit.rshift( value, pos )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+shift "value" right "pos" positions. The sign is not propagated.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_arshift"></a> Res = bit.arshift( value, pos )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+shift "value" right "pos" positions. The sign is propagated
+("arithmetic shift").
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_bit"></a> Res = bit.bit( bitno )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+a shortcut for bit.lshift( 1, bitno )
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_set"></a> Res1, Res2, ... = bit.set( bitno, v1,
+v2, ... )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+set the bit at position "bitno" in v1, v2, ... to 1.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_clear"></a> Res1, Res2, ... = bit.clear( bitno,
+v1, v2, ... )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+set the bit at position "bitno"in v1, v2, ... to 0.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_isset"></a> Res = bit.isset( value, bitno )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+returns true if bit at position "bitno" in "value" is 1, false
+otherwise.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="bit_isclear"></a> Res = bit.isclear( value, bitno )</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+returns true if bit at position "bitno" in "value" is 0, false
+otherwise.
+</p>
+<br style="font-family: Verdana;">
+<br style="font-family: Verdana;">
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<h3><a name="cpumodule"></a>cpu</h3>
+<p class="MsoNormal" style="font-family: Verdana;"><br>
+</p>
+<p style="margin-bottom: 0in;"> </p>
+<font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write32"></a>write32( address, data ) : write
+the 32-bit data at the specified address</font>
+<p style="margin-bottom: 0in;"></p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write16"></a>write16( address, data ) : write
+the 16-bit data at the specified address</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_write8"></a>write8( address, data ) : write the
+8-bit data at the specified address</font> <br>
+</p>
+<p style="margin-bottom: 0in;"><br>
+</p>
+<br>
+<font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read32"></a>Data = read32( address ) :
+reads 32-bit data from the specified address</font>
+<p style="margin-bottom: 0in;"></p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read16"></a>Data = read16( address ) : reads
+16-bit data from the specified address</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_read8"></a>Data = read8( address ) : reads 8-bit
+data from the specified address</font></p>
+<p style="margin-bottom: 0in;"><br>
+</p>
+<br>
+<p style="margin-bottom: 0in;"><a name="cpu_disableinterrupts"></a>
+[cpu.disableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">cli(): disable
+CPU interrupts</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"><a name="cpu_enableinterrupts"></a>
+[cpu.enableinterrupts()] <font face="Bitstream Vera Sans Mono, sans-serif">sei(): enable
+CPU interrupts</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
+</font></p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu_clockfrequency"></a>[cpu.clockfrequency()]
+Clock = clock(): returns the CPU frequency</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">Also, you can
+expose as many CPU constants (for example memory mapped registers)</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">as you want to
+this module. You might want to use this feature to access some </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">CPU memory areas
+(as defined in the CPU header files from the CPU support </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">package)
+directly from Lua. To do this, you'll need to define the </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">PLATFORM_CPU_CONSTANTS
+macro in the platform's platform_conf.h file </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">(src/platform/<platform
+name>/platform_conf.h). Include all your constants in a </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
+<constant name> ) definition, and then build your project.</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For example,
+let's suppose that your CPU's interrupt controler has 3 memory</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">mapped
+registers: INT_REG_ENABLE, INT_REG_DISABLE and INT_REG_MASK. If you want</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">to access them
+from Lua, locate the header that defines the values of these</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">registers (I'll
+assume its name is "cpu.h") and add these lines to the</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform_conf.h:</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#include "cpu.h"</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#define
+PLATFORM_CPU_CONSTANTS\</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
+INT_REG_ENABLE ),\</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C(
+INT_REG_DISABLE ),\</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">_C( INT_REG_MASK
+)</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">After this
+you'll be able to access the regs directly from Lua, like this:</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">data = cpu.r32(
+cpu.INT_REG_ENABLE )</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">cpu.w32(
+cpu.INT_REG_ENABLE, data )</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">For a
+"real-life" example, see the src/platform/lm3s/platform_conf.h file.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[uart.sendstring]
+uart.sendstr( id, str1, str2, ... ): this is similar to "uart.send",
+but its parameters are string. </font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> </p>
+<h3><a name="gpiomodule">pio</a></h3>
+<p class="MsoNormal" style="font-family: Verdana;">
+<b>pio</b></p><p class="MsoNormal" style="font-family: Verdana;">Programable Input Output Module</p><p class="MsoNormal" style="font-family: Verdana;">Some notes on PIO:</p><ul><li>pio: only
+some platform have internal pullups for the pio pins, while Cortex is
+the only platform that also provides pulldowns for its pios. However,
+in this case you're safe, as eLua will signal an error if you try to
+execute a pullup operatin on a platform that does not support it.</li></ul><p class="MsoNormal" style="font-family: Verdana;">
+</p>
+<br>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinvalue"></a> [pio.setpinvalue] pio.setpin(
+value, Pin1, Pin2 ... ): set the value to all the pins in the list
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+ to "value" (0 or 1).
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinhigh"></a> [pio.setpinhigh] pio.set(
+Pin1, Pin2, ... ): set the value of all the pins in the list to 1.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getpinvalue"></a> [pio.getpinvalue] Val1, Val2,
+... = pio.get( Pin1, Pin2, ... ): reads one or more pins and returns
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+ their values (0 or 1).
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setpinlow"></a> [pio.setpinlow] pio.clear(
+Pin1, Pin2, ... ): set the value of all the pins in the list to 0.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_configpin"></a> [pio.configpin(pio.DIR, pio.DIR_INPUT)] pio.input( Pin1, Pin2, ... ): set the specified pin(s)
+as input(s).
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+[pio.configpin(pio.DIR, pio.DIR_OUTPUT)] pio.output( Pin1, Pin2, ...
+): set the specified pin(s) as output(s).
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_setportvalue"></a> [pio.setportvalue]
+pio.setport( value, Port1, Port2, ... ): set the value of all the ports
+in the
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+ list to "value".
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getportvalue"></a> [pio.getportvalue] Val1,
+Val2, ... = pio.getport( Port1, Port2, ... ): reads one or more ports
+and
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+ returns their values.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getportname"></a> [pio.getportname]
+Port = pio.port( code ): return the physical port number associated
+with the given code. For example, "pio.port( pio.P0_20 )" will return
+0.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;"><a name="gpio_getpinnumber"></a> [pio.getpinnumber] Pin =
+pio.pin( code ): return the physical pin number associated with the
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+given code. For example, "pio.pin( pio.P0_20 )" will return 20.
+</p>
+<br>
+<a name="gpio_togglepin"></a>[pio.togglepin([Pin1],
+[Pin2], ...)]<br>
+<br>
+<a name="gpio_toogleport"></a>[pio.toggleport([Port1],
+[Port2], ...)]<br style="font-family: Verdana;">
+<br>
+Another idea (can be added to the above ?)<br>
+[pio.configport(pio.[FUNCTION], pio.MASK, [MASK])]<br>
+Ex:<br>
+ pio.configpin(pio.DIR, pio.DIR_INPUT) (.DIR_OUTPUT)<br>
+ pio.configpin(pio.PULL, pio.PULL_UP) (.PULL_DOWN,
+PULL_NO)<br style="font-family: Verdana;">
+<br>
+<p class="MsoNormal" style="font-family: Verdana;">
+[pio.configport(pio.DIR, pio.DIR_INPUT, [Port1], [Port2], ...)]
+pio.port_input( Port1, Port2, ... ): set the specified port(s) as
+input(s).
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+[pio.configport(pio.DIR, pio.DIR_OUTPUT, [Port1], [Port2], ...)]
+pio.port_output( Port1, Port2, ... ): set the specified port(s) as
+output(s).
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+[pio.configpin(pio.PULL, pio.PULL_UP, [Pin1], [Pin2], ...)]
+pio.pullup( Pin1, Pin2, ... ): enable internal pullups on the specified
+pins.Note that some CPUs might not provide this feature.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+[pio.configpin(pio.PULL, pio.PULL_DOWN, [Pin1], [Pin2], ...)]
+pio.pulldown( Pin1, Pin2, ... ): enable internal pulldowns on the
+specified pins. Note that some CPUs might not provide this feature.
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+
+</p>
+<p class="MsoNormal" style="font-family: Verdana;">
+[pio.configpin(pio.PULL, pio.PULL_NO, [Pin1], [Pin2], ...)]
+pio.nopull( Pin1, Pin2, ... ): disable the pullups/pulldowns on the
+specifiedpins. Note that some CPUs might not provide this feature.
+</p>
+<br>
+<h3><a name="netmodule"></a>net</h3>
+<br>
+<h3><a name="pwmmodule"></a>pwm</h3>
+<span style="font-weight: bold;"></span><br>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
+use the PWM blocks on the target CPU.</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><strike><a name="pwm_setup"></a>[pwm.setup]</strike>(</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.setup( id,
+frequency, Active Cycle ) </font><font face="Bitstream Vera Sans Mono, sans-serif">
+Data = pwm.setup( id, frequency, duty ): sets the PWM block 'id' to
+generate the specified frequency with the specified duty cycle (duty is
+an integer number from 0 to 100, specifying the duty cycle in
+percents). It returns the actual frequency set on the PWM block.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> Here there is a bigger
+change on the proposal.
+</p>
+<p style="margin-bottom: 0in;"> The Timer Clock and the
+PWM "frame" frequency would be set up in the same function (.setup)
+</p>
+<p style="margin-bottom: 0in;"> The normal control
+function would only set the active cicle (.setcycle)
+</p>
+<p style="margin-bottom: 0in;"> The original .setup
+function would then be replaced by:
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[pwm.setup( id,
+tmrclock, pwm_frequency )</font> ]<br>
+</p>
+<p style="margin-bottom: 0in;"> <a name="pwm_setcycle"></a>[pwm.setcycle(
+id, active_cycle )]</p>
+<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_start"></a>[pwm.start()]
+pwm.start( id ): start the PWM block 'id'.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_stop"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop()]
+</font><font face="Bitstream Vera Sans Mono, sans-serif">pwm.stop(
+id ): stop the PWM block 'id'.</font>
+</p>
+<br>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="pwm_setclock"></a>Data = pwm.setclock( id, clock ):
+set the base clock of the PWM block 'id' to</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the given clock.
+In returns the actual clock set on the PWM block.</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">[</font><font face="Bitstream Vera Sans Mono, sans-serif"><strike>pwm.getclock</strike>]
+</font><font face="Bitstream Vera Sans Mono, sans-serif">Data
+= pwm.getclock( id ): returns the base clock of the PWM block 'id'.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<h3><a name="spimodule"></a>spi</h3>
+<span style="font-weight: bold;"></span><br>
+<big><span style="font-family: Helvetica,Arial,sans-serif;"></span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_setup"></a>Actual_clock = spi.setup( id,
+spi.MASTER | spi.SLAVE, clock, cpol, cpha,</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>databits):
+set the SPI interface with the given parameters, returns the clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>that
+was set for the interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<span style="font-family: Helvetica,Arial,sans-serif;">
+
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_select"></a>spi.select(
+</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>
+): sets the selected spi as active (sets the SS line of the given
+interface).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_unselect"></a>spi.unselect(
+id ): clears the SS line of the given interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_send"></a>spi.send(
+id, Data1, Data2, ... ): sends all the data to the specified SPI</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<span style="font-family: Helvetica,Arial,sans-serif;">
+
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="spi_sendrecv"></a>[</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>spi.sendrecv(</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id,
+Out1, Out2, ...</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>)]
+</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>In1,
+In2, ... = spi.send_recv( id, Out1, Out2, ... ): sends all the "out"
+bytes</big></font><span style="font-family: Helvetica,Arial,sans-serif;"> </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>to
+the specified SPI interface and returts the data read after each sent
+byte.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Returning
+several values in this blocking way would not complicate some queued
+send implementations ? (ok, this could be another function :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+</span><br style="font-family: Helvetica,Arial,sans-serif;">
+<br style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Sending multiple data/chars in a single
+call and not in
+a table argument does not allow the data to be built in run time
+(without some string massage, of course :)</big></font><br>
+<br>
+<br>
+<br>
+</big>
+<h3><a name="sysmodule"></a>sys</h3>
+<br>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_platform"></a>[sys.platform()]
+pd.platform(): returns the platform name (f.e. LM3S)</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_mcu"></a>[sys.mcu()]
+pd.cpu(): returns the CPU name (f.e. LM3S8962)</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="sys_cpu"></a>[sys.cpu()]
+would return ARM Cortex M3 in this case.....</font></p>
+<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><br>
+</font></p>
+<font face="Bitstream Vera Sans Mono, sans-serif"> <a name="sys_board"></a>[sys.board()]</font><font face="Bitstream Vera Sans Mono, sans-serif">
+pd.board(): returns the CPU board (f.e. EK-LM3S8962)</font>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<h3><a name="term_termmodule">term</a></h3>
+ Terminal support
+<p> <a name="term_clear"></a>[term.clear]
+term.clrscr(): clear the screen </p>
+<p> <br>
+<a name="term_cleareol"></a>[term.cleareol]
+term.clreol(): clear from the current cursor position to the end of the
+line </p>
+<p> </p>
+<p><a name="term_moveto"></a> [term.moveto]
+term.gotoxy( x, y ): position the cursor at the given coordinates<br>
+</p>
+<br>
+<p><a name="term_moveup"></a> [term.moveup]
+term.up( delta ): move the cursor up "delta" lines </p>
+<p> </p>
+<p><a name="term_movedown"></a> [term.movedown]
+term.down( delta ): move the cursor down "delta" lines </p>
+<p> </p>
+<p><a name="term_moveleft"></a> [term.moveleft]
+term.left( delta ): move the cursor left "delta" lines </p>
+<p> <br>
+<a name="term_moveright"></a>[term.moveright] term.right(
+delta ): move the cursor right "delta" lines </p>
+<p> </p>
+<p><a name="term_getlinecount"></a>
+[term.getlinecount] Lines = term.lines(): returns the number of lines </p>
+<p> </p>
+<p><a name="term_getcolcount"></a>
+[term.getcolcount] Cols = term.cols(): returns the number of columns </p>
+<p> </p>
+<br>
+<p><a name="term_printstr"></a> [term.printstr]
+term.putstr( s1, s2, ... ): writes the specified string(s) to the
+terminal<br>
+</p>
+<p> </p>
+<p> [term.printchar] term.put( c1, c2, ... ): writes the
+specified character(s) to the terminal </p>
+<p> </p>
+<p><a name="term_getx"></a> [term.getx] Cx =
+term.cursorx(): return the cursor X position </p>
+<p> </p>
+<p> <a name="term_gety"></a>[term.gety] Cy =
+term.cursory(): return the cursor Y position </p>
+<p> </p>
+<p> <font size="2"><a name="term_inputchar"></a>[term.inputchar]
+c = term.getch( term.WAIT | term.NOWAIT ): returns a char read from the
+</font> </p>
+<font size="2"> terminal.</font>
+<br style="font-family: Verdana;">
+<br>
+<br>
+<h3><a name="tmr_tmrmodule"></a>tmr</h3>
+<span style="font-weight: bold;"></span><big><br>
+</big>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">It allows Lua to
+execute timer specific operations (delay, read timer value,</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">start timer, get
+time difference).</font></p><p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif">Some notes on timers:</font></p><ul><li>timers: from all the platforms on which eLua runs, only
+the Luminary Cortex CPUs has rock solid 32-bit timers. You can do
+pretty much everything you need with them. All the other platforms have
+16-bit timers, which imposes some limits on the range of delays you can
+achieve with them. Make sure to use tmr.mindelay(id) and
+tmr.maxdelay(id) to check the actual resolution of your timers, and
+adapt your code accordingly. To 'compensate' for this, it's not
+possible to change the base timer frequency on the Cortex CPUs, but it
+is possible on most other platforms :) So be sure to also check the
+result of tmr.setclock(id)</li><li>also, when using timers,
+remember that if you're using XMODEM and/or the "term" module, TMR0 is
+used by both of them. So, if you change the TMR0 base clock in your
+code, be sure to restore the original setting before returning to the
+shell. You can change this static timer assignment by modifying
+src/main.c. It might also be possible to change it dynamically in the
+future, although I see little use for this.</li><li>PWM: the
+Cortex CPUs have 6 PWM channels, but channels 0/1, 2/3 and 4/5
+respectively share the same base clock setting. So, when you're
+changing the base clock for channel 1, you're also changing the base
+clock for channel 0; if channel 0 was already running, you won't like
+what will happen next. This time no eLua function can save you, you
+simply need you know your CPU architecture.</li></ul><p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_delay"></a>tmr.delay( id, delay ): uses timer
+'id' to wait for 'delay' us.</font>
+</p>
+<p style="margin-bottom: 0in;"> <br>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-style: italic;"><a name="tmr_read"></a></span>Data
+= tmr.read( id ): reads the value of timer 'id'. The returned value is </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform
+dependent.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-style: italic;"><a name="tmr_start"></a></span>Data
+= tmr.start( id ): start the timer 'id', and also returns its value at</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the moment of
+start. The returned value is platform dependent.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_diff"></a>diff
+= tmr.diff( id, end, start ): returns the time difference (in us)
+between</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">the timer values
+'end' and 'start' (obtained from calling tmr.start or</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">tmr.read). The
+order of end/start is irrelevant. </font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_mindelay"></a>Data = tmr.mindelay( id ): returns
+the minimum delay (in us ) that can be </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">achieved by
+calling the tmr.delay function. If the return value is 0, the </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">platform layer
+is capable of executing sub-microsecond delays.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_maxdelay"></a>Data = tmr.maxdelay( id ): returns
+the maximum delay (in us) that can be</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">achieved by
+calling the tmr.delay function.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_setclock"></a>Data = tmr.setclock( id, clock ):
+sets the clock of the given timer. Returns the</font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">actual clock set
+for the timer.</font>
+</p>
+<p style="margin-bottom: 0in;">
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="tmr_getclock"></a>Data = tmr.getclock( id ): return
+the clock of the given timer.</font>
+</p>
+<br>
+<br>
+<br>
+<br>
+<br>
+<h3><a name="uartmodule"></a>uart</h3>
+
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_setup"></a><span style="font-weight: bold;">uart.setup(</span></font><font style="font-weight: bold;" face="Bitstream Vera Sans Mono, sans-serif"> id, baud,
+databits, </font>
+</p><p style="margin-bottom: 0in; font-weight: bold;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.PARITY_EVEN
+| uart.</font><font face="Bitstream Vera Sans Mono, sans-serif">PARITY</font><font face="Bitstream Vera Sans Mono, sans-serif">_ODD | uart.</font><font face="Bitstream Vera Sans Mono, sans-serif">PARITY</font><font face="Bitstream Vera Sans Mono, sans-serif">_NONE, </font>
+</p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;">uart.STOPBITS_1
+| uart.STOPBITS_1_5 | uart.STOPBITS_2
+)</span></font></p>
+<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;"></span> Set the UART interface with the given
+parameters.</font></p><p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"> Returns the actual baud rate that was set for the UART.</font>
+</p>
+
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
+</font></p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_send"></a></font><font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;">uart.send( id,
+Data1, Data2, ... )</span></font></p><p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><span style="font-weight: bold;"></span> Send all the data to the specified UART interface.</font>
+</p>
+
+
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
+</font></p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="uart_recv"></a></font><font face="Bitstream Vera Sans Mono, sans-serif">uart.recv(</font><font face="Bitstream Vera Sans Mono, sans-serif"> id,
+uart.TIMEOUT_NO | <strike>uart.TIMEOUT_INFINITE</strike> |
+timeout )</font><font face="Bitstream Vera Sans Mono, sans-serif">
+ </font><font face="Bitstream Vera Sans Mono, sans-serif">Data =
+uart.recv( id, uart.NO_TIMEOUT | uart.INF_TIMEOUT | timeout )</font></p>
+<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"> Reads a byte from the
+specified UART interface.</font></p>
+<p style="margin-bottom: 0in;"></p>
+<p style="margin-bottom: 0in;">
+</p>
+<h2><a name="platdepmodules"></a>eLua Platform
+Dependent
+Modules</h2>A Platform Dependent eLua Module is a module that runs only on one or on a few <a href="status.html#platforms">supported eLua platforms</a>.<br>These
+modules make use of specifical devices and features offered by some
+kits and allow eLua aplications to make the best use of the external
+hardware on your platforms.<br><h3><a name="adcmodule"></a>adc - Analog to Digital Conversion Module</h3><span style="font-weight: bold;">Currently runs on:</span> LM3Sxxxx<br><br> The ADC module handles the Analog to Digital Conversion Peripherals.<br><br><br><a name="adc_sample"></a><span style="font-weight: bold;">adc.sample(channel_id)</span><br> Generate one processed sample.<br><br><br><a name="adc_getsamples"></a><span style="font-weight: bold;">adc.getsamples(channel_id,
+[count])</span><br> Request <span style="font-style: italic;">count</span> samples from the buffer.<br> if singular, an
+integer is returned. if multiple, a table of integers is returned. If
+<span style="font-style: italic;">count</span> is either zero or omitted, all available samples are returned.<br><br><br><a name="adc_maxval"></a><span style="font-weight: bold;">adc.maxval(channel_id)</span><br> Returns the largest integer one can expect fromr this channel on a given platform (based on bit depth).<br><br><br><a name="adc_samplesready"></a><span style="font-weight: bold;">adc.samplesready(channel_id)<br></span> Returns the number of samples waiting in the buffer.<br><br><br><a name="adc_dataready"></a><span style="font-weight: bold;">adc.dataready(channel_id)<br></span> If running in non-blocking mode, this will indicate if all of the
+samples requested from the last sample or <br>burst have been acquired and
+are waiting in the buffer.<br><br><br><a name="adc_setmode"></a><span style="font-weight: bold;">adc.setmode(channel_id,
+mode)<br></span> <span style="font-style: italic;">mode</span> 0 sets blocking mode. adc.getsamples will wait for
+requested samples to be captured before returning.<br> <span style="font-style: italic;">mode</span> 1 sets non-blocking mode<br><br><br><a name="adc_setsmoothing"></a><span style="font-weight: bold;">adc.setsmoothing(channel_id, length)<br></span> Set the length of the smoothing filter.<br> This must be a power of 2 (maximum = 128)<br><br><br><a name="adc_getsmoothing"></a><span style="font-weight: bold;">adc.getsmoothing(channel_id)<br></span> Get the current smoothing length in use.<br><br><br><a name="adc_burst"></a><span style="font-weight: bold;">adc.burst(
+channel_id, count, timer_id, frequency)<br></span> Request that <span style="font-style: italic;">count</span> samples be converted from <span style="font-style: italic;">channel_id</span>, using <span style="font-style: italic;">timer_id</span> at <span style="font-style: italic;">frequency.<br></span> <span style="font-style: italic;">count </span>must be greater than zero and a power of 2<br><br><br>
+<h3><a name="dispmodule"></a>disp</h3>
+<span style="font-weight: bold;">Currently runs on:</span> LM3Sxxxx<br><br> The disp module handles the RIT OLED display usage on Luminary Micro Cortex-M3 boards<br>
+<p class="MsoNormal"></p><p class="MsoNormal"><a name="disp_init"></a><span style="font-weight: bold;">
+disp.init( freq )</span></p><p class="MsoNormal">freq specifies the SSI Clock Frequency to be used.<br><br>This function initializes the SSI interface to the OLED display and configures the SSD1329 controller on the panel.<br></p><br><p class="MsoNormal"><a name="disp_enable"></a>
+<span style="font-weight: bold;">disp.enable()</span> </p>
+<p class="MsoNormal">Enable the SSI component of the OLED display driver.<br></p><p class="MsoNormal">freq specifies the SSI Clock Frequency to be used.<br>This function initializes the SSI interface to the OLED display.</p><p class="MsoNormal">
+</p>
+<p class="MsoNormal"><a name="disp_disable"></a>
+<span style="font-weight: bold;">disp.disable()</span> </p>
+<p class="MsoNormal"> <br>
+</p>
+<p class="MsoNormal"> <a name="disp_on"></a><span style="font-weight: bold;">disp.on()</span>
+</p>
+<p class="MsoNormal"> Turns on the OLED display.<br> This function will turn on the OLED display, causing it to display the contents of its internal frame buffer.<br><br>
+</p>
+<p class="MsoNormal"><a name="disp_off"></a>
+<span style="font-weight: bold;">disp.off</span>()</p><p class="MsoNormal">Turns off the OLED display<br>This
+function will turn off the OLED display. This will stop the
+scanning of the panel and turn off the on-chip DC-DC converter,
+preventing damage to the panel due to burn-in (it has similar
+characters to a CRT in this respect).<br><br></p>
+<p class="MsoNormal"><a name="disp_clear"></a>
+<span style="font-weight: bold;">disp.clear()</span></p><p class="MsoNormal">Clears the OLED display.<br>This function will clear the display RAM. All pixels in the display will be turned off.<br></p>
+ <a name="disp_print"></a><span style="font-weight: bold;">disp.print( str, x, y, gray )</span><br><br>Displays a string on the OLED display.<br><br>Calling Arguments:<br>str is a string to be displayed.<br>x is the horizontal position to display the string, specified in columns from the left edge of the display.<br>y is the vertical position to display the string, specified in rows from the top edge of the display.<br>gray is the 4-bit gray scale (intensity) value to be used for displayed text. <br><br>This
+function will draw a string on the display. Only the ASCII
+characters between 32 (space) and 126 (tilde) are supported;
+other characters will result in random data being draw on the
+display (based on whatever appears before/after the font in
+memory). The font is mono-spaced, so characters such as ``i'' and
+``l'' have more white space around them than characters such as ``m''
+or ``w''.<br>If the drawing of the string reaches the right edge of the
+display, no more characters will be drawn. Therefore, special
+care is not required to avoid supplying a string that is ``too long''
+to display.<br><br>Because the OLED display packs 2 pixels of data in a single byte, the<br>parameter \e ulX must be an even column number (for example, 0, 2, 4, and<br>so on).<br><br>
+<br>
+<p class="MsoNormal"><a name="disp_draw"></a>
+<span style="font-weight: bold;">disp.draw( img, x, y, withd, height, gray )</span></p><p class="MsoNormal">Displays an image on the OLED display.<br><br>img a pointer to the string data representing a rit format image to display.<br>x is the horizontal position to display the string, specified in columns from the left edge of the display.<br>y is the vertical position to display the string, specified in rows from the top edge of the display.<br>width is the width of the image, specified in columns.<br>height is the height of the image, specified in rows.<br><br>This
+function will display a bitmap graphic on the display. Because of
+the format of the display RAM, the starting column x and the number of
+columns y must be an integer multiple of two.<br>The image data is
+organized with the first row of image data appearing left to
+right, followed immediately by the second row of image data. Each
+byte contains the data for two columns in the current row, with
+the leftmost column being contained in bits 7:4 and the rightmost
+column being contained in bits 3:0.<br>For example, an image six
+columns wide and seven scan lines tall would be arranged as
+follows (showing how the twenty one bytes of the image would appear on
+the display):<br><br>Because the OLED display packs 2 pixels of data in
+a single byte, the parameter x must be an even column number (for
+example, 0, 2, 4, and so on).<span style="font-weight: bold;"></span></p><p class="MsoNormal"><span style="font-family: Courier New;"> +-------------------+-------------------+-------------------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte
+0 |
+Byte 1
+| Byte
+2 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte
+3 |
+Byte 4
+| Byte
+5 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte
+6 |
+Byte 7
+| Byte
+8 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte
+9 |
+Byte 10 |
+Byte 11 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte 12
+| Byte 13
+| Byte 14 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte 15
+| Byte 16
+| Byte 17 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;">
+| Byte 18
+| Byte 19
+| Byte 20 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |</span><br style="font-family: Courier New;"><span style="font-family: Courier New;"> +---------+---------+---------+---------+---------+---------+</span><span style="font-weight: bold;"></span></p><p class="MsoNormal"><span style="font-weight: bold;"></span></p><p class="MsoNormal"><span style="font-weight: bold;"></span> </p>
+</body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/spi_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/spi_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/spi_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -13,32 +13,31 @@
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
</span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>databits):
-set the SPI interface with the given parameters, returns the clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+configura a interface SPI com os parâmetros fornecidos, retorna o clock</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>that
-was set for the interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>que
+foi configurado para a interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="select"></a>spi.select(
</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>
-): sets the selected spi as active (sets the SS line of the given
-interface).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+): configura a SPI selecionada como ativa (configura a linha SS da interface em questão).</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="unselect"></a>spi.unselect(
-id ): clears the SS line of the given interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+id ): inicializa a linha SS da interface em questão.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big> </big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="send"></a>spi.send(
-id, Data1, Data2, ... ): sends all the data to the specified SPI</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+id, Data1, Data2, ... ): envia todos os dados para a interface SPI especificada.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
- </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>interface.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+ </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<span style="font-family: Helvetica,Arial,sans-serif;">
@@ -46,21 +45,19 @@
<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big><a name="sendrecv"></a>[</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>spi.sendrecv(</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>id,
Out1, Out2, ...</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>)]
</big></font><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>In1,
-In2, ... = spi.send_recv( id, Out1, Out2, ... ): sends all the "out"
-bytes</big></font><span style="font-family: Helvetica,Arial,sans-serif;"> </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>to
-the specified SPI interface and returts the data read after each sent
-byte.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+In2, ... = spi.send_recv( id, Out1, Out2, ... ): envia todos os "out"
+bytes</big></font><span style="font-family: Helvetica,Arial,sans-serif;"> </span><font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>para
+a interface SPI especificada e retorna o dado lido a cada byte enviado.</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Returning
-several values in this blocking way would not complicate some queued
-send implementations ? (ok, this could be another function :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Retornando
+diversos valôres dessa forma, facilitaria algumas futuras implementações ? (ok, isso poderia ser uma outra função :)</big></font><span style="font-family: Helvetica,Arial,sans-serif;">
</span><br style="font-family: Helvetica,Arial,sans-serif;">
<br style="font-family: Helvetica,Arial,sans-serif;">
-<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Sending multiple data/chars in a single
-call and not in
-a table argument does not allow the data to be built in run time
-(without some string massage, of course :)</big></font><br>
+<font style="font-family: Helvetica,Arial,sans-serif;" size="2"><big>Enviando múltiplos data/chars em uma única
+chamada e não usando
+uma tabela como argumento, evita que os dados sejam montados em tempo de execução
+(claro que sem menhum string de mensagem :)</big></font><br>
<br>
<br>
<br>
@@ -97,4 +94,4 @@
</span></big> <br>
<br style="font-family: Verdana;">
-</body></html>
\ No newline at end of file
+</body></html>
Added: branches/eagle_mmc/doc/pt/status.html
===================================================================
--- branches/eagle_mmc/doc/pt/status.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/status.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,418 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css">
+</head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Current Status of Platforms and Modules Supported</h3>
+<p>As already stated, eLua allows you to run Lua completely on
+the
+microcontroller. A fast-growing set of complementary modules is also
+provided, for Lua programming eLua's generic (portable) peripherals. </p>
+<p>The following features are ready or being implemented:</p>
+<ul>
+<li>a (mostly) platform independent peripheral library (PIO,
+UART, PWM, SPI, TMR, ADC, NET, I2C...)</li>
+<li>a very low footprint embedded rom file system, easy to port
+to different types of memory chips and other storage devices</li>
+<li>a small FAT rw file system layer for SD cards.</li>
+<li>an embedded editor, to edit Lua programs directly via a
+serial connection or other input devices</li>
+<li>a minimal "shell" (for file operations, environment
+configuration and other facilities)</li>
+<li>network support</li>
+<li>an embedded http server</li>
+<li>Terminal / Console over Ethernet</li>
+</ul>
+<p>Porting eLua to another compatible platform should be as easy
+and
+painless as possible. Currently this is restricted to platforms for
+which the gcc+newlib combo is available. This might change in the
+future, but please not that this is not a priority of the project at
+this point.</p>
+<p>Also, the Lua "core" comes in two flavors: "regular Lua"
+(using
+floating point as the number type) and "integer Lua" (using integers).
+We'll add more about this in a future tutorial
+about Lua. For now, it's enough to say that "regular Lua" will be able
+to perform floating point operations (but will be slower because the
+floating point operations will be emulated in software on the MCU),
+while "integer Lua" will only be able to perform operations with
+integer numbers (but support for fixed and even floating point can be
+added with separate modules) and thus will be faster.</p>
+<p></p>
+<h3>Symbol Legends</h3>
+
+<table style="width: 325px; height: 169px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: center;">Symbol</th>
+<th style="text-align: center;">Meaning</th>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: left;">Implemented and tested</td>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: left;">Implemented, not tested</td>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: left;">Not yet implemented</td>
+</tr>
+<tr>
+<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: left;">Not applicable</td>
+</tr>
+</tbody>
+</table><br><br>
+<h3>Platforms x Modules Supported</h3>The following table shows the status of <span style="font-weight: bold;">eLua</span>'s modules implementation by
+platform.<br><br>
+<table style="text-align: left;">
+<tbody>
+<tr>
+<th>Module</th>
+<th rowspan="2">PIO</th>
+<th rowspan="2">SPI</th>
+<th rowspan="2">UART</th>
+<th rowspan="2">TMR</th>
+<th rowspan="2">PWM</th>
+<th rowspan="2">NET</th>
+<th rowspan="2">CPU</th>
+<th rowspan="2">ADC</th>
+</tr>
+<tr><td style="color: rgb(255, 102, 0);">MCU</td>
+</tr><tr>
+<td style="color: rgb(255, 102, 0);">LM3S8962</td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Implemented" src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img style="width: 16px; height: 16px;" alt="Not Tested" src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"> </td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">LM3S6965</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">i386</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/agt_action_fail1.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">AT91SAM7X256</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">AT91SAM7X512</td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">STR912FW44</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">LPC2888</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">STR711FR2</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"> <img style="height: 16px; width: 16px;" alt="Not Implemented" src="../wb_img/agt_action_fail1.png"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">AVR32</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><br>
+</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"> <br>
+</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><br>
+</td>
+</tr>
+<tr>
+<td style="color: rgb(255, 102, 0);">STM32</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+<td style="text-align: center;"><br>
+</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+<td style="text-align: center;"></td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"> </td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+</tbody>
+</table>
+<br>
+<br>
+<br>
+<br>
+<br>
+<h3><a name="roadmap"></a>Status of features
+& roadmap</h3>
+<p>The following table shows the status of some existent and
+planned eLua
+features. </p>
+<p><br>
+</p>
+<table style="text-align: left; width: 672px; height: 691px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">eLua Features</th>
+<th style="text-align: center;">Status</th>
+</tr>
+<tr>
+<td style="text-align: left;">Full Lua interpreter
+running on targets</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td>Various Lua scripts examples running properly</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Choose floating point
+or integer Lua</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">XMODEM transfer over
+UART</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Embedded ROM (Flash)
+file
+system</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Terminal / Console
+over UART or Ethernet</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua command shell</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua complete
+interrupt support</td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua "memory limiting"
+mode</td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">FAT File System layer
+for mmc/sd cards</td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Embedded R/W file
+system</td>
+<td style="text-align: center;">Partially
+implemented and tested</td>
+</tr>
+<tr>
+<td style="text-align: left;">eLua FP module (for
+integer Lua)</td>
+<td style="color: rgb(255, 102, 0); text-align: center;"><img src="../wb_img/ksame.png">
+</td>
+</tr>
+<tr>
+<td style="text-align: left;">Embedded text editor</td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">Lua debugging on target</td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">GUI/IDE interface for
+eLua</td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">GUI eLua build
+configuration tool<br>
+</td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png">
+</td>
+</tr><tr><td align="undefined" valign="undefined">Embedded http web server</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/agt_action_success.png"></td></tr>
+</tbody>
+</table>
+<br>
+<br>
+<br>
+<table style="text-align: left; width: 677px; height: 403px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Generic Multi-Platform
+Peripheral Modules</th>
+<th style="text-align: center;">Status</th>
+</tr>
+<tr>
+<td style="text-align: left;">PIO - Programable
+Input / Output</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td>TMR - Timers</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">PWM - Pulse Width
+Modulation</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">UART - Universal
+Assincronous Rx Tx</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">SPI - Serial
+Programable Interface</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">CMP - Analog
+Comparator</td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">I2C </td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">CNT - Event Counter
+</td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">CAN</td>
+<td style="text-align: center;"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td style="text-align: left;">NET -
+Ethernet module</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+</tbody>
+</table>
+<br>
+<br>
+<br>
+<table style="width: 681px; height: 68px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Platform-Dependent
+Peripheral Modules</th>
+<th>Status</th>
+</tr>
+<tr>
+<td style="text-align: left;">DISP - RIT
+OLED Display Support for LM3Sxxxx</td>
+<td style="text-align: center;"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+<tr>
+<td align="undefined" valign="undefined">LM3S
+- Luminary Micro kits onboard devices support (Leds, Buttons, ...)</td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/agt_action_success.png"></td>
+</tr>
+</tbody>
+</table>
+<br>
+<br>
+<br>
+<table style="width: 680px; height: 389px;" class="table_center">
+<tbody>
+<tr>
+<th style="text-align: left;">Functional Abstraction
+Auxiliary Modules</th>
+<th>Status</th>
+</tr>
+<tr>
+<td style="text-align: left;">GPS - NMEA0183
+Sentences parsing and command handling</td>
+<td style="text-align: center;"><img src="../wb_img/yellowled.png"></td>
+</tr>
+<tr>
+<td align="undefined" valign="undefined">PID
+- Proportional, Integrative & Derivative Control</td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td align="undefined" valign="undefined">LCD
+- Liquid Crystal Display support</td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+</tr>
+<tr>
+<td align="undefined" valign="undefined">ROT
+- Rotary Switch & Encoder support</td>
+<td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td>
+</tr><tr><td align="undefined" valign="undefined">CHDK - Interfacing with Canon cameras also running Lua under <a href="http://chdk.wikia.com/" target="_top">CHKD</a></td><td style="text-align: center;" valign="undefined"><img src="../wb_img/yellowled.png"></td></tr><tr><td align="undefined" valign="undefined">DISP - External text & graphics displays</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">FUZZ - Fuzzy Logic Control</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">HUM - Humity Sensors over SPI, UART, I2C, PIO, ....</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">TMP - Temperature Sensors over SPI, UART, I2C, PIO, ....</td><td style="text-align: center;" valign="undefined"><img src="../wb_i!
mg/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">BAR - Pressure Sensors over SPI, UART, I2C, PIO, ....</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">X10 - X10 Protocol support for X10 Devices Mapping & Control</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">MCP - Magnetic Compass abstraction</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr><tr><td align="undefined" valign="undefined">PS2 - Play Station 2 Joystick interfacing support</td><td style="text-align: center;" valign="undefined"><img src="../wb_img/ksame.png"></td></tr>
+</tbody>
+</table><br><br>If you need a module for a specific device support or logic & modeling abstraction, don't hesitate to suggest it in our <a href="https://lists.berlios.de/mailman/listinfo/elua-dev" target="_top">eLua User's and Developers List</a>. You may have one ready before you would imagine :)<br><br><br><br>
+</body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/sys_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/sys_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/sys_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -9,26 +9,26 @@
<h3><a name="over"></a>sys</h3>
<br>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="platform"></a>[sys.platform()]
-pd.platform(): returns the platform name (f.e. LM3S)</font>
+pd.platform(): retorna o nome da plataforma (f.e. LM3S)</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="mcu"></a>[sys.mcu()]
-pd.cpu(): returns the CPU name (f.e. LM3S8962)</font>
+pd.cpu(): retorna o nome da CPU (f.e. LM3S8962)</font>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="cpu"></a>[sys.cpu()]
-would return ARM Cortex M3 in this case.....</font></p>
+neste caso retornaria ARM Cortex M3.....</font></p>
<p style="margin-bottom: 0in;"><font face="Bitstream Vera Sans Mono, sans-serif"><br>
</font></p>
<font face="Bitstream Vera Sans Mono, sans-serif"> <a name="board"></a>[sys.board()]</font><font face="Bitstream Vera Sans Mono, sans-serif">
-pd.board(): returns the CPU board (f.e. EK-LM3S8962)</font>
+pd.board(): retorna o nome da placa da CPU (f.e. EK-LM3S8962)</font>
<p style="margin-bottom: 0in;"> <br>
</p>
-<p style="margin-bottom: 0in;"> Could also be <b>elua.</b><br>
+<p style="margin-bottom: 0in;"> Poderia ser também <b>elua.</b><br>
</p>
-<p style="margin-bottom: 0in;"> Many other miscelania
-functions will need a place to live and sys or elua is more generic
-than pd for it.<br>
+<p style="margin-bottom: 0in;"> Muitas outras funções
+ainda serão necessárias e neste caso sys ou eLua são mais abrangentes
+para isso do que pd.<br>
</p>
<font style="color: rgb(0, 0, 255);" color="#ff0000">
</font><br>
@@ -66,4 +66,4 @@
<br>
<br>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Copied: branches/eagle_mmc/doc/pt/tc_386.html (from rev 269, branches/eagle_mmc/doc/en/tc_386.html)
===================================================================
--- branches/eagle_mmc/doc/en/tc_386.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tc_386.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,281 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Building GCC for i386</a></h3>
+
+ <div class="content">
+
+<p>At first, the idea of an i386 "cross" compiler under Linux seems
+strange. After all, you're already running Linux on a i386 compatible
+architecture. But the compiler is sometimes tied in misterious ways
+with the operating system it's running on (see for example <a href="http://wiki.osdev.org/GCC_Cross-Compiler">this page</a>
+for some possible symptoms). And after all, you want to use Newlib, not
+libc, and to customize your development environment as much as
+possible. This tutorial will show you how to do that.</p>
+
+<p><strong>DISCLAIMER: I'm by no means a specialist in the
+GCC/newlib/binutils compilation process. I'm sure that there are better
+ways to accomplish what I'm describing here, however I just wanted a
+quick and dirty way to build a toolchain, I have no intention in
+becoming too intimate with the build process. If you think that what I
+did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Contact">contact me</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+
+<h2>› Prerequisites</h2>
+<p>To build your toolchain you'll need:</p>
+
+<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
+will do as long as you know how to find the equivalent of "apt-get" for
+your distribution. I won't be going into details about this, google it
+and you'll sure find what you need. It is also assumed that the Linux
+system already has a "basic" native toolchain installed (gcc/make and
+related). This is true for Ubuntu after installation. Again, you might
+need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+At the moment of writing this, the latest versions is 2.18, which for
+some weird reason refuses to compile on my system, so I'm using 2.17
+instead.</li><li>GCC: version 4.3.0 or newer is recommended. As
+I'm writing this, the latest GCC version is 4.3.1 which I'll be using
+for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib: as I'm writing this, the latest official Newlib version is 1.16.0. Download it from the <a href="ftp://sources.redhat.com/pub/newlib/index.html">Newlib FTP directory</a>.</li><li>Also,
+the tutorial assumes that you're using bash as your shell. If you use
+something else, you might need to adjust some shell-specific commands. </li></ul>
+
+
+<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo</th>
+ </tr>
+</tbody></table>
+
+
+<p>Next, decide where you want to install your toolchain. They
+generally go in /usr/local/, so I'm going to assume
+/usr/local/cross-i686 for this tutorial. To save yourself some typing,
+set this path into a shell variable:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ export TOOLPATH=/usr/local/cross-i686</th>
+ </tr>
+</tbody></table>
+
+
+<h2>› Step 1: binutils</h2>
+
+<p>This is the easiest step: unpack, configure, build.</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th style="text-align: left;">$ tar -xvjf binutils-2.17.tar.bz2</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd binutils-2.17</th>
+ </tr>
+ <tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$ ../configure --target=i686-elf --prefix=$TOOLPATH --with-gnu-as --with-gnu-ld --disable-nls</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+ <tr align="left">
+ <th>$ export PATH=${TOOLPATH}/bin:$PATH</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<p>Now you have your i386 "binutils" (assembler, linker, disassembler ...) in your PATH.</p>
+<h2>› Step 2: basic GCC</h2>
+
+<p>In this step we build a "basic" GCC (that is, a GCC without any
+support libs, which we'll use in order to build all the libraries for
+our target). But first we need to make a slight modification in the
+configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
+compile properly, giving a very weird "Link tests are not allowed after
+GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
+solution for this:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ tar -xvjf gcc-4.3.1.tar.bz2</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd gcc-4.3.1/libstdc++-v3</th>
+ </tr>
+ <tr align="left">
+ <th>$ joe configure.ac</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<p>I'm using "joe" here as it's my favourite Linux text mode editor,
+you can use any other text editor. Now find the line which says
+"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it: </p>
+
+<pre><code> # AC_LIBTOOL_DLOPEN<br></code></pre>
+
+<p>Save the modified file and exit the text editor</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ autoconf</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd ..</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Great, now we know it will compile, so let's do it:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=i686-elf --prefix=$TOOLPATH
+--enable-languages="c,c++" --with-newlib --without-headers
+--disable-shared --with-gnu-as --with-gnu-ld
+</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all-gcc</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install-gcc</th>
+ </tr>
+</tbody></table>
+
+
+<p>On my system, the last line above (sudo make install-gcc) terminated
+with errors, because it was unable to find our newly compiled binutils.
+If this happens for any kind of "make install" command, this is a quick
+way to solve it:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ sudo -s -H</th>
+ </tr>
+</tbody></table>
+
+
+<pre><code> # export PATH=/usr/local/cross-i686/bin:$PATH<br> # make install-gcc<br> # exit<br></code></pre>
+
+
+<h2>› Step 3: Newlib</h2>
+
+<p>Once again, Newlib is as easy as unpack, configure, build. But I
+wanted my library to be as small as possible (as opposed to as fast as
+possible) and I only wanted to keep what's needed from it in the final
+executable, so I added the "-ffunction-sections -fdata-sections" flags
+to allow the linker to perform dead code stripping:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ tar xvfz newlib-1.16.0.tar.gz</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd newlib-1.16.0</th>
+ </tr>
+ <tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=i686-elf --prefix=$TOOLPATH
+--disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as
+--disable-shared</th>
+ </tr>
+ <tr align="left">
+ <th>$ make
+CFLAGS_FOR_TARGET="-ffunction-sections
+-fdata-sections -D__PREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os
+-fomit-frame-pointer -D__BUFSIZ__=256"</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Some notes about the flags used in the above sequence:</p>
+
+<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li><li><code>-D__PREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256:</code>
+again Newlib specific, this is the buffer size allocated by default for
+files opened via fopen(). The default is 1024, which I find too much
+for an eLua, so I'm using 256 here. Of course, you can change this
+value.</li></ul>
+
+
+<h2>› Step 4: full GCC</h2>
+
+<p>Finally, in the last step of our tutorial, we complete the GCC
+build. In this stage, a number of compiler support libraries are built
+(most notably libgcc.a). Fortunately this is simpler that the Newlib
+compilation step:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ cd gcc-4.3.1/build</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<h2>› Step 5: all done!</h2>
+
+<p>Now you can finally enjoy your i386 toolchain, and compile eLua with
+it :) After you do, you'll be able to boot eLua directly on your PC, as
+described <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Booting_your_PC_in_eLua">here</a>, but you won't need to download the ELF file from the eLua project page, since you just generated it using your own toolchain!
+If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="http://www.giga.puc-rio.br/cgi-bin/elua.cgi?p=Contact">contact me</a>.</p>
+</div></body></html>
\ No newline at end of file
Copied: branches/eagle_mmc/doc/pt/tc_arm.html (from rev 269, branches/eagle_mmc/doc/en/tc_arm.html)
===================================================================
--- branches/eagle_mmc/doc/en/tc_arm.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tc_arm.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,310 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_ARM" class="local">Building GCC for ARM</a></h3>
+
+ <div class="content">
+
+<p> This tutorial explains how you can create a GCC+Newlib toolchain
+that can be used to compile programs for the ARM architecture, thus
+making it possible to compile programs for the large number of ARM CPUs
+out there. You'll need such a toolchain if you want to compile eLua for
+ARM CPUs. This tutorial is similar to many others you'll find on the
+Internet (particulary the one from <a href="http://www.gnuarm.com/">gnuarm</a>, on which it's based), but it's a bit more detailed and shows some "tricks" you can use when compiling Newlib.</p>
+
+<p><strong>DISCLAIMER: I'm by no means a specialist in the
+GCC/newlib/binutils compilation process. I'm sure that there are better
+ways to accomplish what I'm describing here, however I just wanted a
+quick and dirty way to build a toolchain, I have no intention in
+becoming too intimate with the build process. If you think that what I
+did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.eluaproject.net/en/Contact">contact me</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+
+<h2>Prerequisites</h2>
+<p>To build your toolchain you'll need:</p>
+
+<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
+will do as long as you know how to find the equivalent of "apt-get" for
+your distribution. I won't be going into details about this, google it
+and you'll sure find what you need. It is also assumed that the Linux
+system already has a "basic" native toolchain installed (gcc/make and
+related).This is true for Ubuntu after installation. Again, you might
+need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+At the moment of writing this, the latest versions is 2.18, which for
+some weird reason refuses to compile on my system, so I'm using 2.17
+instead.</li><li>GCC: version 4.3.0 or newer is recommended. As
+I'm writing this, the latest GCC version is 4.3.1 which I'll be using
+for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib: as I'm writing this, the latest official Newlib version is 1.16.0. Download it from the <a href="ftp://sources.redhat.com/pub/newlib/index.html">Newlib FTP directory</a>.</li><li>Also,
+the tutorial assumes that you're using bash as your shell. If you use
+something else, you might need to adjust some shell-specific commands. </li></ul>
+
+
+<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo</th>
+ </tr>
+</tbody></table>
+
+
+<p>Next, decide where you want to install your toolchain. They
+generally go in /usr/local/, so I'm going to assume
+/usr/local/cross-arm for this tutorial. To save yourself some typing,
+set this path into a shell variable:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ export TOOLPATH=/usr/local/cross-arm</th>
+ </tr>
+</tbody></table>
+
+
+<h2>› Step 1: binutils</h2>
+<p>This is the easiest step: unpack, configure, build.</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ tar -xvjf binutils-2.17.tar.bz2</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ cd binutils-2.17</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ mkdir build</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ cd build</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th style="text-align: left;">$ ../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork --enable-multilib--with-gnu-as --with-gnu-ld --disable-nls</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ make all</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ export PATH=${TOOLPATH}/bin:$PATH</th>
+ </tr>
+</tbody></table>
+
+
+<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH.</p>
+
+<h2>Step 2: basic GCC</h2>
+
+<p>In this step we build a "basic" GCC (that is, a GCC without any
+support libs, which we'll use in order to build all the libraries for
+our target). But first we need to make a slight modification in the
+configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
+compile properly, giving a very weird "Link tests are not allowed after
+GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
+solution for this:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ tar -xvjf gcc-4.3.1.tar.bz2</th>
+ </tr>
+ <tr>
+ <th>$ cd gcc-4.3.1/libstdc++-v3</th>
+ </tr>
+ <tr>
+ <th style="text-align: left;">$ joe configure.ac</th>
+ </tr>
+</tbody></table>
+
+
+<p> I'm using "joe" here as it's my favourite Linux text mode editor,
+you can use any other text editor. Now find the line which says
+"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it:</p>
+
+<p><code># AC_LIBTOOL_DLOPEN</code></p>
+
+<p>Save the modified file and exit the text editor</p>
+
+<p><br> </p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ autoconf</th>
+ </tr>
+ <tr>
+ <th style="text-align: left;">$ cd ..</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Great, now we know it will compile, so let's do it:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
+--enable-multilib --enable-languages="c,c++" --with-newlib
+--without-headers --disable-shared--with-gnu-as --with-gnu-ld</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all-gcc</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install-gcc</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<p>On my system, the last line above (sudo make install-gcc) terminated
+with errors, because it was unable to find our newly compiled binutils.
+If this happens for any kind of "make install" command, this is a quick
+way to solve it:</p>
+
+<p style="text-align: left;"><br></p><div style="text-align: left;">
+
+</div><table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ sudo -s -H</th>
+ </tr>
+ <tr align="left">
+ <th># export PATH=/usr/local/cross-arm/bin:$PATH</th>
+ </tr>
+ <tr align="left">
+ <th># make install-gcc</th>
+ </tr>
+ <tr>
+ <th style="text-align: left;"># exit</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<h2>Step 3: Newlib</h2>
+
+<p>Once again, Newlib is as easy as unpack, configure, build. But I
+wanted my library to be as small as possible (as opposed to as fast as
+possible) and I only wanted to keep what's needed from it in the final
+executable, so I added the "-ffunction-sections -fdata-sections" flags
+to allow the linker to perform dead code stripping:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ tar xvfz newlib-1.16.0.tar.gz</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd newlib-1.16.0</th>
+ </tr>
+ <tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
+--disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as
+--disable-shared</th>
+ </tr>
+ <tr align="left">
+ <th>$ make
+CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections
+-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer
+-D__BUFSIZ__=256"</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Some notes about the flags used in the above sequence:</p>
+
+<ul><li><code>--disable-newlib-supplied-syscalls</code>: this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a></li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__</code>: compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-Os -fomit-frame-pointer</code>: tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256</code>:
+again Newlib specific, this is the buffer size allocated by default for
+files opened via fopen(). The default is 1024, which I find too much
+for an eLua, so I'm using 256 here. Of course, you can change this
+value.</li></ul>
+
+
+<h2>Step 4: full GCC</h2>
+
+<p>Finally, in the last step of our tutorial, we complete the GCC
+build. In this stage, a number of compiler support libraries are built
+(most notably libgcc.a). Fortunately this is simpler that the Newlib
+compilation step:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ cd gcc-4.3.1/build</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all</th>
+ </tr> <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<h2>Step 5: all done!</h2>
+
+<p>Now you can finally enjoy your ARM toolchain, and compile eLua with it :)
+If you need further clarification, or if the above instructions didn't work for you, feel free to <a href="http://www.eluaproject.net/en/Contact">contact me</a>.</p>
+</div></body></html>
\ No newline at end of file
Copied: branches/eagle_mmc/doc/pt/tc_cortex.html (from rev 269, branches/eagle_mmc/doc/en/tc_cortex.html)
===================================================================
--- branches/eagle_mmc/doc/en/tc_cortex.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tc_cortex.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,343 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><div class="content">
+
+<h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_Cortex" class="local">Building GCC for Cortex</a></h3><p>This tutorial explains how you can create a GCC+Newlib toolchain
+that can be used to compile programs for the Cortex (Thumb2)
+architecture, thus making it possible to use GCC to compile programs
+for the increasingly number of Cortex CPUs out there (<a href="http://www.luminarymicro.com/">Luminary Micro</a>, <a href="http://www.st.com/mcu/inchtml-pages-stm32.html">ST</a>,
+with new Cortex CPUs being announced by Atmel and other companies). I
+am writing this tutorial because I needed to work on a Cortex CPU for
+the eLua project and I couldn't find anywhere a complete set of
+instructions for building GCC for this architecture. You'll need such a
+toolchain if you want to compile eLua for Cortex-M3 CPUs.</p>
+
+<p><strong>DISCLAIMER: I'm by no means a specialist in the
+GCC/newlib/binutils compilation process. I'm sure that there are better
+ways to accomplish what I'm describing here, however I just wanted a
+quick and dirty way to build a toolchain, I have no intention in
+becoming too intimate with the build process. If you think that what I
+did is wrong, innacurate, or simply outrageously ugly, feel free to <a href="http://www.eluaproject.net/en/Contact">contact us</a> and I'll make the necessary corrections. And of course, this tutorial comes without any guarantees whatsoever.</strong></p>
+
+<h2>Prerequisites</h2>
+<p>To build your toolchain you'll need:</p>
+
+<ul><li>a computer running Linux: I use Ubuntu 8.04, but any Linux
+will do as long as you know how to find the equivalent of "apt-get" for
+your distribution. I won't be going into details about this, google it
+and you'll sure find what you need. It is also assumed that the Linux
+system already has a "basic" native toolchain installed (gcc/make and
+related). This is true for Ubuntu after installation. Again, you might
+need to check your specific distribution.</li><li>GNU binutils: get it from <a href="http://ftp.gnu.org/gnu/binutils/">here</a>.
+At the moment of writing this, the latest versions is 2.18, which for
+some weird reason refuses to compile on my system, so I'm using 2.17
+instead. <strong>UPDATE</strong>: you MUST use the new binutils 2.19
+distribution for the Cortex toolchain, since it fixes some assembler
+issues. You won't be able to compile eLua 0.5 or higher if you don't
+use binutils 2.19.</li><li>GCC: since support for Cortex (Thumb2)
+was only introduced staring with version 4.3.0, you'll need to download
+version 4.3.0 or newer. As I'm writing this, the latest GCC version is
+4.3.1, which I'll be using for this tutorial. Download it from <a href="http://gcc.gnu.org/mirrors.html">here</a> after choosing a suitable mirror.</li><li>Newlib:
+as I'm writing this, the latest official Newlib version is 1.16.0.
+However, the CVS version contains some fixes for the Thumb2
+architecture, some of them in very important functions (like
+setjmp/longjmp), so you'll need to fetch the sources from CVS (this
+will most likely change when a new official Newlib version is
+released). So go to <a href="http://sourceware.org/newlib/download.html">http://sourceware.org/newlib/download.html</a> and follow the instructions there in order to get the latest sources from CVS.</li><li>Also,
+the tutorial assumes that you're using bash as your shell. If you use
+something else, you might need to adjust some shell-specific commands. </li></ul>
+
+
+<p>Also, you need some support programs/libraries in order to compile the toolchain. To install them:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ sudo apt-get install flex bison libgmp3-dev libmpfr-dev autoconf texinfo build-essential</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Next, decide where you want to install your toolchain. They
+generally go in /usr/local/, so I'm going to assume
+/usr/local/cross-cortex for this tutorial. To save yourself some
+typing, set this path into a shell variable:</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ export TOOLPATH=/usr/local/cross-cortex</th>
+ </tr>
+</tbody></table>
+
+
+
+<h2>Step 1: binutils</h2>
+
+<p>This is the easiest step: unpack, configure, build.</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ tar -xvjf binutils-2.19.tar.bz2</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd binutils-2.19</th>
+ </tr>
+ <tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
+--enable-multilib --with-gnu-as --with-gnu-ld --disable-nls</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+ <tr align="left">
+ <th>$ export PATH=${TOOLPATH}/bin:$PATH</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Now you have your ARM "binutils" (assembler, linker, disassembler ...) in your PATH. They are fully capable of handling Thumb2.</p>
+
+<h2>Step 2: basic GCC</h2>
+
+<p>In this step we build a "basic" GCC (that is, a GCC without any
+support libs, which we'll use in order to build all the libraries for
+our target). But first we need to make a slight modification in the
+configuration files. Out of the box, the GCC 4.3.1/newlib combo won't
+compile properly, giving a very weird "Link tests are not allowed after
+GCC_NO_EXECUTABLES" error. After a bit of googling, I found the
+solution for this:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ tar -xvjf gcc-4.3.1.tar.bz2</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd gcc-4.3.1/libstdc++-v3</th>
+ </tr>
+ <tr align="left">
+ <th>$ joe configure.ac </th>
+ </tr>
+</tbody></table>
+
+
+<p> I'm using "joe" here as it's my favourite Linux text mode editor,
+you can use any other text editor. Now find the line which says
+"AC_LIBTOOL_DLOPEN" and comment it out by adding a "#" before it: </p>
+
+
+<code># AC_LIBTOOL_DLOPEN<br></code>
+
+<p>Save the modified file and exit the text editor</p>
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ autoconf</th>
+ </tr>
+ <tr>
+ <th style="text-align: left;">$ cd ..</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<p>Great, now we know it will compile, so let's do it:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
+--enable-multilib --enable-languages="c,c++" --with-newlib
+--without-headers --disable-shared --with-gnu-as --with-gnu-ld</th>
+ </tr>
+ <tr align="left">
+ <th>$ make all-gcc</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install-gcc</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>On my system, the last line above (sudo make install-gcc) terminated
+with errors, because it was unable to find our newly compiled binutils.
+If this happens for any kind of "make install" command, this is a quick
+way to solve it:</p>
+
+
+<p><br></p>
+
+<table style="width: 376px; height: 157px;" class="table_cod">
+ <tbody><tr>
+ <th>$ sudo -s -H</th>
+ </tr><tr><td align="undefined" valign="undefined"><code># export PATH=/usr/local/cross-cortex/bin:$PATH</code></td></tr><tr><td align="undefined" valign="undefined"><code># make install-gcc</code></td></tr><tr><td align="undefined" valign="undefined"><code># exit</code></td></tr>
+</tbody></table>
+
+
+<code><br><br><br></code>
+
+
+<h2>Step 3: Newlib</h2>
+
+<p>Again, some modifications are in order before we start compiling.
+Because the CVS version of Newlib doesn't seem to have all the required
+support for Thumb2 yet, we need to tell Newlib to skip some of its
+libraries when compiling:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th>$ cd [directory where the newlib CVS is located]</th>
+ </tr>
+ <tr>
+ <th style="text-align: left;">$ joe configure.ac</th>
+ </tr>
+</tbody></table>
+
+
+
+<p> Find this fragment of code:</p>
+
+<pre><code> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads"<br> libgloss_dir=arm<br> ;;<br><br> And add "target-libgloss" to the "noconfigdirs" variable:<br><br> arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )<br> noconfigdirs="$noconfigdirs target-libffi target-qthreads target-libgloss"<br> libgloss_dir=arm<br> ;;<br><br> Save the modified file and exit the text editor<br> $ autoconf<br></code></pre>
+
+
+<p>On one of the systems I ran the above sequence, it terminated with
+errors, complaining that autoconf 2.59 was not found. I don't know why
+that happens. 2.59 seems to be quite ancient, and the build ran equally
+well with 2.61 (the version of autoconf on the system that gave the
+error). If this happens to you, first execute autoconf --version to
+find the actual version of your autoconf, then do this:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr>
+ <th></th>
+ </tr>
+</tbody></table>
+
+<pre><code>$ joe config/override.m4<br><br> Look for this line:<br><br> [m4_define([_GCC_AUTOCONF_VERSION], [2.59])])<br><br> And replace [2.59] with your actual version ([2.61] in my case).<br> $ autoconf<br></code></pre>
+
+
+<p>Once again, now we're ready to actually compile Newlib. But we need
+to tell it to compile for Thumb2. As already specified, I'm not a
+specialist when it comes to Newlib's build system, so I chosed the
+quick, dirty and not so elegant solution of providing the compilation
+flags directly from the command line. Also, as I wanted my library to
+be as small as possible (as opposed to as fast as possible) and I only
+wanted to keep what's needed from it in the final executable, I added
+the "-ffunction-sections -fdata-sections" flags to allow the linker to
+perform dead code stripping:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ mkdir build</th>
+ </tr>
+ <tr align="left">
+ <th>$ cd build</th>
+ </tr>
+ <tr align="left">
+ <th>$
+../configure --target=arm-elf --prefix=$TOOLPATH --enable-interwork
+--disable-newlib-supplied-syscalls --with-gnu-ld --with-gnu-as
+--disable-shared</th>
+ </tr>
+ <tr align="left">
+ <th>$ make
+CFLAGS_FOR_TARGET="-ffunction-sections -fdata-sections
+-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__ -Os -fomit-frame-pointer
+-mcpu=cortex-m3 -mthumb -D__thumb2__ -D__BUFSIZ__=256"
+CCASFLAGS="-mcpu=cortex-m3 -mthumb -D__thumb2__"</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+
+<p>Some notes about the flags used in the above sequence:</p>
+
+<ul><li><code>--disable-newlib-supplied-syscalls:</code> this deserves a page of its own, but I won't cover it here. For an explanation, see for example <a href="http://openhardware.net/Embedded_ARM/NewLib_Stubs/">this page</a>.</li><li><code>-DPREFER_SIZE_OVER_SPEED -D__OPTIMIZE_SIZE__:</code> compile Newlib for size, not for speed (these are Newlib specific).</li><li><code>-mcpu=cortex-m3 -mthumb:</code> this tells GCC that you want to compile for Cortex. Note that you need both flags.</li><li><code>-D__thumb2__:</code> again, this is Newlib specific, and seems to be required when compiling Newlib for Cortex.</li><li><code>-Os -fomit-frame-pointer:</code> tell GCC to optimize for size, not for speed.</li><li><code>-D__BUFSIZ__=256:</code>
+again Newlib specific, this is the buffer size allocated by default for
+files opened via fopen(). The default is 1024, which I find too much
+for an eLua, so I'm using 256 here. Of course, you can change this
+value.</li></ul>
+
+
+<h2>Step 4: full GCC</h2>
+
+<p>Finally, in the last step of our tutorial, we complete the GCC
+build. In this stage, a number of compiler support libraries are built
+(most notably libgcc.a). Fortunately this is simpler that the Newlib
+compilation step, as long as you remember that we want to build our
+compiler support libraries for the Cortex architecture:</p>
+
+
+<p><br></p>
+
+<table class="table_cod">
+ <tbody><tr align="left">
+ <th>$ cd gcc-4.3.1/build</th>
+ </tr>
+ <tr align="left">
+ <th>$ make CFLAGS="-mcpu=cortex-m3 -mthumb" CXXFLAGS="-mcpu=cortex-m3 -mthumb" LIBCXXFLAGS="-mcpu=cortex-m3 -mthumb" all</th>
+ </tr>
+ <tr align="left">
+ <th>$ sudo make install</th>
+ </tr>
+</tbody></table>
+
+
+
+
+<h2>All Done!</h2>
+<p>Phew! That was quite a disturbing tutorial, with all that confusing
+flags lurking in every single shell line :) But at this point you
+should have a fully functional Cortex GCC toolchain, which seems to be
+something very rare, so enjoy it with pride.
+If you need further clarification, or if the above instructions didn't
+work for you, feel free to <a href="http://www.eluaproject.net/en/Contact">contact us</a>.</p><p></p><p></p>
+</div></body></html>
\ No newline at end of file
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===================================================================
--- branches/eagle_mmc/doc/en/tchainbuild.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tchainbuild.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,9 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local">Toolchain Build</a></h3><a name="title" href="http://www.eluaproject.net/en/Building_GCC_for_i386" class="local"></a>eLua can be compiled and link edited with GCC Toolchains.<br><br>.....................<br><br>
+
+ </body></html>
\ No newline at end of file
Modified: branches/eagle_mmc/doc/pt/term_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/term_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/term_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,60 +1,59 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
<body style="background-color: rgb(255, 255, 255);">
<h3><a name="over">term</a></h3>
- Terminal support
+ Suporte de Terminal
<p> <a name="clear"></a>[term.clear]
-term.clrscr(): clear the screen </p>
+term.clrscr(): apaga a tela </p>
<p> <br>
<a name="cleareol"></a>[term.cleareol]
-term.clreol(): clear from the current cursor position to the end of the
-line </p>
+term.clreol(): apaga a partir da posição corrente do cursor até o fim da
+linha </p>
<p> </p>
<p><a name="moveto"></a> [term.moveto]
-term.gotoxy( x, y ): position the cursor at the given coordinates<br>
+term.gotoxy( x, y ): posiciona o cursor em uma coordenada especÃfica<br>
</p>
<br>
<p><a name="moveup"></a> [term.moveup]
-term.up( delta ): move the cursor up "delta" lines </p>
+term.up( delta ): move o cursor para cima "delta" linhas </p>
<p> </p>
<p><a name="movedown"></a> [term.movedown]
-term.down( delta ): move the cursor down "delta" lines </p>
+term.down( delta ): move o cursor para baixo "delta" linhas </p>
<p> </p>
<p><a name="moveleft"></a> [term.moveleft]
-term.left( delta ): move the cursor left "delta" lines </p>
+term.left( delta ): move o cursor para esquerda "delta" caracteres </p>
<p> <br>
<a name="moveright"></a>[term.moveright] term.right(
-delta ): move the cursor right "delta" lines </p>
+delta ): move o cursor para direita "delta" caracteres </p>
<p> </p>
<p><a name="getlinecount"></a>
-[term.getlinecount] Lines = term.lines(): returns the number of lines </p>
+[term.getlinecount] Lines = term.lines(): retorna o número de linhas </p>
<p> </p>
<p><a name="getcolcount"></a>
-[term.getcolcount] Cols = term.cols(): returns the number of columns </p>
+[term.getcolcount] Cols = term.cols(): retorna o número de colunas </p>
<p> </p>
<br>
<p><a name="printstr"></a> [term.printstr]
-term.putstr( s1, s2, ... ): writes the specified string(s) to the
-terminal<br>
+term.putstr( s1, s2, ... ): imprime um string especificado no terminal<br>
</p>
<p> </p>
<p> [term.printchar] term.put( c1, c2, ... ): writes the
-specified character(s) to the terminal </p>
+imprime um carater especÃfico no terminal </p>
<p> </p>
<p><a name="getx"></a> [term.getx] Cx =
-term.cursorx(): return the cursor X position </p>
+term.cursorx(): retorna a posição X do cursor </p>
<p> </p>
<p> <a name="gety"></a>[term.gety] Cy =
-term.cursory(): return the cursor Y position </p>
+term.cursory(): retorna a posição Y do cursor </p>
<p> </p>
<p> <font size="2"><a name="inputchar"></a>[term.inputchar]
-c = term.getch( term.WAIT | term.NOWAIT ): returns a char read from the
-</font> </p>
-<font size="2"> terminal.</font>
+c = term.getch( term.WAIT | term.NOWAIT ): retorna um caracter lido do
+</font> terminal</p>
+<font size="2"> .</font>
<br style="font-family: Verdana;">
-</body></html>
\ No newline at end of file
+</body></html>
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===================================================================
--- branches/eagle_mmc/doc/en/tut_bootpc.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tut_bootpc.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua" class="local">Booting your PC in eLua</a></h3>
+
+ <div class="content">
+
+<p>That's right: after following this tutorial, your PC will boot
+directly into Lua! No OS there (this explains why the boot process is
+so fast), just you and Lua. You'll be able to use the regular Lua
+interpreter to write your programs and even use "dofile" to execute Lua
+code.</p>
+
+<h2>Details</h2>
+
+<p>Booting Lua involves using the well known <a href="http://www.gnu.org/software/grub/">GRUB</a> that will be used to load a <a href="http://www.gnu.org/software/grub/manual/multiboot/">multiboot</a>
+compliant ELF file that contains our eLua code. Since the eLua code and
+the build instructions are not available yet, I'll be providing a
+direct link to the ELF file. The code runs in protected mode, so you
+have access to your whole memory. The code does not access any kind of
+storage device (HDD, CDROM, floppy), so if you're worried that it might
+brick your system, you can relax now :) I'm only using some very basic
+keyboard and VGA "drivers", so all you're risking is a system freeze
+(even this is highly unlikely), nothing a good old RESET can't handle
+(be sure to use the hardware reset though, CTRL+ALT+DEL is not handled
+by the code). But just in case, see also the next section.</p>
+
+<h2>Disclaimer</h2>
+
+<p><strong>As already mentioned, the code won't try to access any kind
+of storage (HDD, CDROM, floppy), not even for reading, so you don't
+need to worry about that. Also it doesn't try to reprogram your video
+card registers, so it can't harm it or your monitor. It only implements
+a "protected mode keyboard driver" that can't physically damage
+anything in your system. In short, I made every effort to make the code
+as harmless as possible. I tested it on 5 different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
+emulators, and nothing bad happened. That said, there are no warranties
+of any kind. In the very unlikely event that something bad does happen
+to your system, you have my sincere sympathy, but I can't be held
+responsible for that.</strong></p>
+
+<h2>Prerequisites</h2>
+
+<p>To boot your computer in Lua you'll need:</p>
+
+<ul><li>a 386 or better computer running Linux. I actually tested
+this only on Pentium class computers, but it should run on a 386
+without problems.</li><li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
+Since you're running Linux, chances are you're already using GRUB as
+your bootloader. If not, you must install it. You don't need to install
+it on your HDD; a floppy, an USB stick or even a CDROM will work as
+well. I won't cover the GRUB installation procedure here, just google
+for "install grub on floppy/usb/cdrom" and you'll sure find what you're
+looking for. You can try for example <a href="http://orgs.man.ac.uk/documentation/grub/grub_3.html">here</a>, <a href="http://www.freesoftwaremagazine.com/articles/grub_intro/">here</a> or <a href="http://www.mayrhofer.eu.org/Default.aspx?pageindex=6&pageid=45">here</a>.</li><li>The eLua ELF file. Download it from <a href="http://elua.berlios.de/surprise">here</a>. OR <a href="http://www.eluaproject.net/en/Downloads">download eLua</a> and compile it for the i386 architecture using a toolchain that you can build by following <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">this tutorial</a>.</li><li>a text editor to edit your GRUB configuration file.</li></ul>
+
+
+<p>The rest of this tutorial assumes that you're using Linux with GRUB,
+and that GRUB is located in /boot/grub, which is true for many Linux
+distributions (I'm using Ubuntu 8.04).</p>
+
+<h2>Let's do this</h2>
+
+<p>First, copy the <a href="http://elua.berlios.de/surprise">eLua ELF file</a> to your "/boot" directory:</p>
+<pre><code>$ sudo cp surprise /boot<br></code></pre>
+
+<p>Next you need to add another entry to your GRUB menu file (/boot/grub/menu.lst). Edit it and add this entry:</p>
+
+<pre><code> title Surprise!<br> root (hd0,0)<br> kernel /boot/surprise<br> boot<br></code></pre>
+
+
+<p>You may need to modify the root (hd0,0) line above to match your
+boot device. The best way to do this is to look in the menu.lst file
+for the entry that boots your Linux kernel. It should look similar to
+this:</p>
+
+<pre><code> title Ubuntu, kernel 2.6.20-16-generic<br> root (hd0,2)<br> kernel /boot/vmlinuz-2.6.20-16-generic<br> initrd /boot/initrd.img-2.6.20-16-generic<br> savedefault <br></code></pre>
+
+
+<p>After you find it, simply use the root (hdx,y) line from that entry
+(root (hd0,2) in the example above) in your newly created entry instead
+of root (hd0,0).
+That's it! Now reboot your computer, and when the GRUB boot menu
+appears, choose "Surprise!" from it. You can even type dofile
+"/rom/bisect.lua" to execute the "bisect.lua" test file. Enjoy!
+As usual, if you need more details, you can <a href="http://www.eluaproject.net/en/Contact">contact us</a>.
+Also, if you want to have you own USB stick that boots Lua, let me
+know. If enough people manifest their interest in this, I'll add
+another tutorial on how to do it (I already have an USB stick that
+boots Lua, of course :) ).</p>
+</div></body></html>
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===================================================================
--- branches/eagle_mmc/doc/en/tut_bootstick.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tut_bootstick.html 2009-07-30 18:10:13 UTC (rev 371)
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Booting_eLua_from_a_stick" class="local">Booting eLua from a stick</a></h3>
+
+ <div class="content">
+
+<p>This is follow up of <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">this tutorial</a>.
+After completing it you'll be able to boot eLua directly from your USB
+stick (provided, of course, that your computer can boot from an USB
+stick, which is true for most computers nowadays). You might want to
+check the <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">boot your PC in eLua</a>
+tutorial first for more details. If you have an old USB stick that you
+don't use anymore, and/or the shear geekness of this idea makes you
+feel curious, this tutorial is definitely for you :)</p>
+
+<h2>Disclaimer</h2>
+
+<p><strong>As mentioned <a href="http://www.eluaproject.net/en/Booting_your_PC_in_eLua">here</a>,
+the code won't try to access any kind of storage (HDD, CDROM, floppy),
+not even for reading, so you don't need to worry about that. Also it
+doesn't try to reprogram your video card registers, so it can't harm it
+or your monitor. It only implements a "protected mode keyboard driver"
+that can't physically damage anything in your system. In short, I made
+every effort to make the code as harmless as possible. I tested it on 5
+different computers and in 2 <a href="http://www.virtualbox.org/">VirtualBox</a>
+emulators, and nothing bad happened. That said, there are no warranties
+of any kind. In the very unlikely event that something bad does happen
+to your system, you have my sincere sympathy, but I can't be held
+responsible for that. Also, I can't be held responsible if you mess up
+your HDD by failing the GRUB installation procedure (even though, once
+again, this shouldn't be possible unless you really insist on messing
+it up). If you're new to computers, this tutorial might not be for you.
+Your call.</strong></p>
+
+<h2>Prerequisites</h2>
+
+<p>To have your own bootable eLua USB stick you'll need:</p>
+
+<ul><li>an USB stick. I tested this on an 128M USB stick, because
+it's the smallest I could find. You should be OK with a 4M stick or
+even a 2M stick</li><li>a computer running Linux. I use Ubuntu, but any other distribution is fine.</li><li><a href="http://www.gnu.org/software/grub/">GRUB</a>.
+Since you're running Linux, chances are you're already using GRUB as
+your bootloader. If not, you must install it on your HDD, or at least
+know how to install it directly on the USB stick. I won't go into
+details here, google it and you'll find lots of good articles about
+GRUB. This tutorial assumes that you're using GRUB as your bootloader.</li><li>The eLua ELF file. Download it from <a href="http://elua.berlios.de/surprise">here</a>. OR <a href="http://www.eluaproject.net/en/Downloads">download eLua</a> and compile it for the i386 architecture using a toolchain that you can build by following <a href="http://www.eluaproject.net/en/Building_GCC_for_i386">this tutorial</a>.</li><li>a text editor to edit your GRUB configuration file.</li></ul>
+
+
+<p>The rest of this tutorial assumes that you're using Linux with GRUB,
+and that GRUB is located in /boot/grub, which is true for many Linux
+distributions.</p>
+<h2>Backup your stick</h2>
+
+<p>Since the stick is going to be formatted, make sure to backup the
+data from your stick first (you can copy it back after finishing the
+tutorial).</p>
+
+<h2>Partition and format your stick</h2>
+
+<p>Depending on your stick, this step might not be required, but
+chances are you'll need to re-partition and re-format your stick before
+installing GRUB on it. The problem is that many sticks have a very
+creative, non-standard partition table, and GRUB doesn't like that. I
+looked at the partition table on my eLua USB stick, and it scared me to
+death, so I had to follow this procedure. In short, you'll need to
+delete all the partitions from your stick, create a new partition, and
+then format it. For a step by step tutorial check here.</p>
+<h2>Install GRUB on your stick</h2>
+
+<p>First, mount your freshly formatted stick (I'm going to assume that the mount directory is /mnt):</p>
+
+<pre><code> $ sudo mount /dev/sda1 /mnt<br></code></pre>
+
+
+<p>(of course, you'll need to change /dev/sda1 to reflect the physical location of your USB stick).
+Then copy the required GRUB files to your stick:</p>
+
+<pre><code> $ cd /mnt<br> $ mkdir boot<br> $ mkdir boot/grub<br> $ cd /boot/grub<br> $ cp stage1 fat_stage1_5 stage2 /mnt/boot/grub<br></code></pre>
+
+
+<p>Copy the <a href="http://elua.berlios.de/surprise">eLua ELF file</a> to the GRUB directory as well:</p>
+
+<pre><code> $ cp surprise /mnt/boot/grub<br></code></pre>
+
+
+<p>Create a menu.lst file for GRUB with you favorite text editor (I'm using joe):</p>
+
+<pre><code> $ cd /mnt/boot/grub<br> $ joe menu.lst<br> title Surprise!<br> root (hd0,0)<br> kernel /boot/grub/surprise<br> boot<br></code></pre>
+
+<p>Now it's time to actually install GRUB on the stick.</p>
+
+<pre><code> $ sudo -s -H<br> # grub<br> Now we need to find the GRUB name of our USB stick. We'll use the "find" command from<br> GRUB and our "surprise" file to accomplish this:<br><br> grub> find /boot/grub/surprise<br> (hd2,0)<br><br> GRUB should respond with a single line (like (hd2,0) above). If it gives you more <br> than one line, something is wrong. Maybe you also installed eLua on your HDD? If so, <br> delete the /boot/grub/surprise file from your HDD and try again.<br> You might get a different (hdx,y) line. If so, just use it instead of (hd2,0) in the rest of <br> this tutorial.<br><br> grub> root (hd2,0)<br> grub> setup (hd2)<br> Checking if "/boot/grub/stage1" exists... yes<br> Checking if "/boot/grub/stage2" exists... yes<br> Checking if "/boot/grub/fat_stage1_5" exists... yes<br> Running "embed /boot/grub/fat_stage1_5 (hd2)"... 15 sectors are embedded.<br> succeeded<br> Running "install /boot/grub/stage1 (hd2) (hd2)1+15 p (h!
d2,0)/boot/grub/stage2<br> /boot/grub/menu.lst"... succeeded<br> Done. <br> grub> quit<br></code></pre>
+
+
+<p>That's it! Now reboot your computer, make sure that your BIOS is set
+to boot from USB, and enjoy! You can even type dofile "/rom/bisect.lua"
+to execute the "bisect.lua" test file.
+As usual, if you need more details, you can <a href="http://www.eluaproject.net/en/Contact">contact us</a>.</p>
+</div></body></html>
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===================================================================
--- branches/eagle_mmc/doc/en/tut_openocd.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/tut_openocd.html 2009-07-30 18:10:13 UTC (rev 371)
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Using_OpenOCD" class="local">Using OpenOCD</a></h3>
+
+ <div class="content">
+
+<h2>Quick downloads</h2>
+
+<p>If you'd rather skip the long and boring OpenOCD introduction and
+skip directly to the OpenOCD script downloads, use the links below.</p>
+
+
+<ul><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str9files">Configuration files for STR9-comStick</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#lpc2888files">Configuration files for LPC2888</a></p></li><li><p><a href="http://www.eluaproject.net/en/Using_OpenOCD?p=Using_OpenOCD#str7files">Configuration files for STR7</a></p></li></ul>
+
+<h2>About OpenOCD</h2>
+
+<p><a href="http://elua.berlios.de/tut_openocd.html">OpenOCD</a> is an open source tool that can be used to connect to a CPU's <a href="http://en.wikipedia.org/wiki/JTAG">JTAG</a>
+interface. Using OpenOCD and a physical JTAG connection allows you to
+burn the on-chip flash memory of your CPU (or to load your code
+directly to RAM), to read the internal CPU memory (Flash/RAM) and to
+use <a href="http://sourceware.org/gdb/">gdb</a> to debug your code.
+Needless to say, this is a very handy tool (and especially handy if
+your CPU happens to be built around an ARM core, since in this case you
+can be almost certain that it has a JTAG interface that you can use).
+That said, if your only goal is to burn your firmware, my personal
+suggestion is to avoid using OpenOCD if possible. It has quite a steep
+learning curve, because it is a command line tool that uses
+configuration files with lots of different parameters, and this takes a
+while to get used to. Worse, I feel that it is not very well
+docummented. The project's wiki does give a few good pointers about all
+the configuration parameters, and there are some good OpenOCD tutorials
+out there, but none of them tells the whole story. And the syntax (and
+even some commands) seems to change slightly between releases, which
+makes things even more confusing. This is why I generally choose to use
+a different firmware burning tool when available, and resort to OpenOCD
+only for targets that lack a proper firmware burning tool. If you need
+to debug your code, however, you probably want to use OpenOCD, since
+the alternatives aren't cheap.
+To summarize, you can forget about OpenOCD when:</p>
+
+<ul><li><p>your CPU manufacturer provides a special tool for
+firmware burning. This is quite often the case, but more often that not
+the forementioned tools work only in Windows.</p></li><li><p>you
+must debug your code, but you have a good intuition about where the
+problem is located. In this case, simply connecting a LED to a PIO port
+and turning it on and off from different parts of your code until you
+figure out exactly what's the problem can work wonders. I can't
+remember when was the last time I used gdb for debugging, since "LED
+debugging" was all I needed. </p></li></ul>
+
+<p>On the other hand, you should probably use OpenOCD when:</p>
+
+<ul><li><p>your CPU manufacturer doesn't provide a special tool for firmware burning (or it does, but it's not what you need).</p></li><li><p>you're using Linux, MacOS or another OS that is not supported by the firmware burning tool.</p></li><li><p>you need to do some serious debugging in order to understand what's wrong with your application.</p></li></ul>
+
+<p>If you decided that you don't need OpenOCD after all, now it's a
+good time to navigate away from this page and save yourself from some
+possible symptoms of headache. If you need OpenOCD, read on, I'll try
+to make this as painless as possible. However, don't expect this to be
+a full tutorial on OpenOCD, because it's not; my intention is to give
+you just enough data to use OpenOCD for burning eLua on your board.
+Because of this, I won't be covering debugging with OpenOCD here, just
+firmware burning. And, before we begin, please read and understand the
+next paragraph.</p>
+
+<p>DISCLAIMER: using OpenOCD improperly may force your CPU to behave
+unexpectedly. While physically damaging your CPU as a result of using
+OpenOCD is very hard to accomplish, you might end up with a locked
+chip, or you might erase a memory area that was not supposed to be
+erased, you might even disable the JTAG interface on your chip (thus
+rendering it unusable). If you modify the configuration scripts that
+I'm going to provide, make sure that you know what you're doing. Also,
+I'm not at all an OpenOCD expert, so my configuration scripts might
+have errors, even though I tested them. In short, this tutorial comes
+without any guarantees whatsoever.</p>
+<h2>Getting OpenOCD</h2>
+
+<p>If you're on Windows, the best place to get OpenOCD already compiled and ready to run is to visit the <a href="http://www.yagarto.de/">Yagarto home page</a>.
+They provide a very nice OpenOCD installer, and they seem to keep up
+with OpenOCD progress (the versions on the Yagarto site are not
+"bleeding edge", but there are quite fresh nevertheless). If you're on
+Linux, you can always use apt-get or your distribution-specific package
+manager:</p>
+
+<pre><code>$ sudo apt-get install openocd<br></code></pre>
+
+
+<p>There is a catch here though: the OpenOCD version that I get from
+apt-get is dated 2007-09-05, while the Yagarto OpenOCD version is from
+2008-06-19. Since I'm using OpenOCD from Windows (because Ubuntu 8.04
+doesn't seem to handle my USB-to-JTAG adapters very well), my
+instructions are relevant to the Yagarto version. As mentioned in the
+introduction, the meaning and parameters of different commands might
+change between OpenOCD version, so if you want to use the Yagarto
+version on your non Windows system, you'll have to build it from source
+(see below).
+The main resource on how to build OpenOCD from source is the <a href="http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD">OpenOCD build page</a> from the OpenOCD wiki. Also, a very good tutorial can be found <a href="http://forum.sparkfun.com/viewtopic.php?t=11221">here</a>.
+I'm not going to provide step by step build instructions, since the two
+links that I mentioned cover this very well, and the build process is
+relatively straightforward. However, since both tutorials describe how
+to build the bleeding edge version of OpenOCD, you'll need a slight
+modification do build the Yagarto version instead. The modification is
+in the SVN checkout step. Replace this step:</p>
+
+<pre><code>$ svn checkout svn://svn.berlios.de/openocd/trunk<br></code></pre>
+
+
+<p>With this step ('717' is the SVN revision of the Yagarto OpenOCD build):</p>
+
+<pre><code>$ svn checkout -r 717 svn://svn.berlios.de/openocd/trunk<br></code></pre>
+
+
+<p>Follow the rest of the build instructions, and in the end you should have a working OpenOCD.</p>
+<h2>Supported targets</h2>
+
+<p>I couldn't find a good page with a list of the targets that are
+supported by OpenOCD. So, if you want to check if your particular CPU
+is supported by OpenOCD, I recommend getting the latest sources (as
+described in the previous section) and listing the
+trunk/src/target/target directory:</p>
+
+<pre><code>$ ls trunk/src/target/target<br> at91eb40a.cfg<br> at91r40008.cfg<br> cfi.c<br> ....<br> str9comstick.cfg<br> ....<br></code></pre>
+
+
+<p>If this listing has something that looks like your CPU name, you're
+in luck. OpenOCD has support for LPC from NXP, AT91SAM cfrom Atmel,
+STR7/STR9 from ST, and many others.</p>
+<h2>Using OpenOCD</h2>
+
+<p>To use OpenOCD, you'll need:</p>
+
+<ul><li>the OpenOCD executable, as described above</li><li>a board with a JTAG interface</li><li>a JTAG adapter</li></ul>
+
+
+<p>In some cases, your CPU board might provide a built in JTAG adapter. For example, my <a href="http://www.luminarymicro.com/products/lm3s8962_can_ethernet_evaluation_kit.html">LM3S8962</a>
+board provides both an USB-to-JTAG and an USB-to-serial converter built
+on board, switching between them automatically. The same is true for my
+<a href="http://www.hitex.com/index.php?id=383">STR9-comStick</a>. On the other hand, my <a href="http://www.olimex.com/dev/sam7-ex256.html">SAM7-EX256</a> board has only a JTAG connector, I need a separate JTAG adapter to connect to it. I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex, but there are other affordable USB-to-JTAG adapters out there, like the Amontec <a href="http://www.amontec.com/jtagkey-tiny.shtml">JTAGKey-Tiny</a>. Not to mention that you can <a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/usbjtag/usbjtag.html">build your ownt</a>.
+Although USB is my interface of choice, you'll find JTAG adapters for
+PC LPT ports too. The good news is that once you buy a JTAG adapter,
+chances are that it will work with many boards with different CPUs,
+since the JTAG connector layout is standardized and the JTAG adapters
+are generally able to work with different voltages.
+To actually use OpenOCD, you'll need a configuration file. The
+configuration file is the one that lets OpenOCD know about your setup,
+such as:</p>
+
+<pre><code>* the kind of JTAG interface that you're using.<br>* the actual hardware platform you're using (ATM7TDMI, ARM966 and others).<br>* the memory configuration of your CPU (flash banks).<br>* the script used to program the flash memory.<br></code></pre>
+
+
+<p>Presenting a list of all the possible configuration options and
+their meaning is way beside the scope of this document, so I'm not
+going to do it, I'll give an example instead. For the example I'm going
+to use parts of my STR-comStick configuration file (comstick.cfg)
+adapted from the OpenOCD distribution and from other examples (don't
+worry, I'll provide full download links for this file later on). First
+we need to tell OpenOCD that we're using a the STR9-comStick
+USB-to-JTAG adapter:</p>
+
+<pre><code>interface ft2232<br>ft2232_device_desc "STR9-comStick A"<br>ft2232_layout comstick<br>ft2232_vid_pid 0x0640 0x002C<br>jtag_speed 4<br>jtag_nsrst_delay 100<br>jtag_ntrst_delay 100<br></code></pre>
+
+
+<p>Also, OpenOCD needs to know what's our target and its memory layout:</p>
+
+<pre><code>target arm966e little run_and_init 1 arm966e<br>run_and_halt_time 0 50<br><br>working_area 0 0x50000000 32768 nobackup<br><br>flash bank str9x 0x00000000 0x00080000 0 0 0<br>flash bank str9x 0x00080000 0x00008000 0 0 0 <br></code></pre>
+
+
+<p>This tells OpenOCD that our target is an ARM966-E running in little
+endian mode, with two flash memory banks, one that starts at 0x0 and
+it's 0x80000 bytes in size, and another one that starts at 0x80000 and
+it's 0x8000 bytes in size. Finally, OpenOCD must know what's the name
+of our script file (this is the file that is used to pysically program
+the CPU memory):</p>
+
+<pre><code>#Script used for FLASH programming<br>target_script 0 reset str91x_flashprogram.script<br></code></pre>
+
+
+<p>The contents of the str91x_flashprogram.script is very target-dependent:</p>
+
+<pre><code>wait_halt<br>str9x flash_config 0 4 2 0 0x80000<br>flash protect 0 0 7 off<br>flash erase_sector 0 0 7<br>flash write_bank 0 main.bin 0<br>reset run<br>sleep 10<br>shutdown<br></code></pre>
+
+
+<p>I'm not even going to attempt to explain this one :) Basically it
+unprotects the flash, erases it, writes the contents of "main.bin" to
+flash, and then resets the CPU. If you need to flash a file with a
+different name, the only thing you need to modify is the "main.bin" in
+the "flash write_bank" line.
+To use all this, you need to tell OpenOCD to use our configuration file:</p>
+
+<pre><code>openocd-ftd2xx -f comstick.cfg<br></code></pre>
+
+
+<p>(note: under Windows, the OpenOCD executable name is often
+"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
+the actualy name with your executable.)
+That's it for your OpenOCD crash course. I realise that there's much
+more to learn, so here's a list of links with much better information
+on the subject:</p>
+
+<ul><li><a href="http://www.hs-augsburg.de/%7Ehhoegl/proj/openocd/oocd-quickref.pdf">OpenOCD quick reference</a> card. (slightly outdated)</li><li>A very good OpenOCD tutorial.</li><li><a href="http://openfacts.berlios.de/index-en.phtml?title=OpenOCD_scripts">OpenOCD configuration examples</a> from the official OpenOCD wiki.</li><li>An excellent page about using <a href="http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html">OpenOCD with ARM controllers</a>, with lots of real life examples.</li><li>An interesting <a href="http://forum.sparkfun.com/viewtopic.php?p=42079">topic on the SparkFun forum</a> about STR9 and OpenOCD.</li></ul>
+
+
+<p><a name="str9files"></a></p>
+<h2>Configuration files for STR9-comStick</h2>
+
+<p>Download them below:</p>
+
+<p><a href="http://elua.berlios.de/other/comstick.cfg">comstick.cfg</a></p>
+
+<p><a href="http://elua.berlios.de/other/str91x_flashprogram.script">str91x_flashprogram.script</a></p>
+
+<p><a href="http://elua.berlios.de/other/comrst.cfg">comrst.cfg</a></p>
+
+<p><a href="http://elua.berlios.de/other/str91x_reset.script">str91x_reset.script</a></p>
+
+<p>The comstick.cfg configuration file is for prorgramming the
+STR9-comStick. comrst.cfg is for resetting it. The comStick has a very
+interesting habit: after you power it (via USB) it does not start
+executing the code from the internal flash, you need to execute OpenOCD
+with the comreset.cfg script to start it. This script does exactly what
+it says: executes a CPU reset (since the board doesn't have a RESET
+button). This is a very peculiar behaviour, and I'm not sure if it's
+generic or it's only relevant to my particular comStick. I suspect that
+the CPU RESET line isn't properly handled by the on-board USB-to-JTAG
+converter, and the only solution I have for this is to execute this
+script everytime you power the board and everytime you need to do a
+RESET.</p>
+
+<p><a name="lpc2888files"></a></p>
+<h2>Configuration files for LPC2888</h2>
+
+<p>LPC2888 is quite a different animal. I couldn't find any "official"
+LPC2888 configuration file for OpenOCD, so I had to learn how to write
+my own. It works, but I suspect it can be improved. This time, the
+configuration file applies to the latest (SVN) version of OpenOCD, so
+read this tutorial to understand how to get the latest OpenOCD sources
+and how to compile them (this section is based on version 922 of the
+OpenOCD repository). Then use the next file to burn your binary image
+to the chip:</p>
+
+<p><a href="http://elua.berlios.de/other/lpc2888.cfg">lpc2888.cfg</a></p>
+
+<p>If your image name is not main.bin edit the file and change the
+corresponding line (flash write_bank 0 main.bin 0), then invoke openocd
+like this:</p>
+
+<pre><code>openocd -f lpc2888.cfg<br></code></pre>
+
+
+<p>I'm using <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a>
+from Olimex, but it should be easy to use the script with any other
+JTAG adapter (don't forget to change the script to match your adapter).</p>
+
+<p><a name="str7files"></a></p>
+<h2>Configuration files for STR711FR2 (STR7 from ST)</h2>
+
+<p>Download them below:</p>
+
+<p><a href="http://elua.berlios.de/other/str7prg.cfg">str7prg.cfg</a></p>
+
+<p><a href="http://elua.berlios.de/other/str7_flashprogram.script">str7_flashprogram.script</a></p>
+
+<p><a href="http://elua.berlios.de/other/str7rst.cfg">str7rst.cfg</a></p>
+
+<p><a href="http://elua.berlios.de/other/str7_reset.script">str7_reset.scrip</a></p>
+
+<p>For STR7 I'm using the Yagarto OpenOCD build for Windows (repository
+version 717, as described at the beginning of this tutorial). The
+str7prg.cfg configuration file is for prorgramming the STR9-comStick.
+str7rst.cfg is for resetting it. I'm using a STR711FR2 heard board from
+<a href="http://www.sctec.com.br/content/view/101/30/">ScTec</a> to
+which I attached a few LEDs and a MAX3232 TTL to RS232 converter for
+the serial communication. The board comes with its own JTAG adadpter,
+but it uses a parallel interface, and since my computer doesn't have
+one, I used the <a href="http://www.olimex.com/dev/arm-usb-tiny.html">ARM-USB-TINY</a> from Olimex. To use them, invoke the OpenOCD executable like this:</p>
+
+<pre><code>openocd-ftd2xx -f str7prg.cfg<br></code></pre>
+
+
+<p>(note: under Windows, the OpenOCD executable name is often
+"openocd-ftd2xx". Under Linux it's simply "openocd". Replace it with
+the actualy name with your executable.)
+Also, be sure to modify str7_flashprogram.script if your image name is
+not main.bin.</p><p></p><p></p><p></p><p> </p>
+</div></body></html>
\ No newline at end of file
Added: branches/eagle_mmc/doc/pt/tutorials.html
===================================================================
--- branches/eagle_mmc/doc/pt/tutorials.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/tutorials.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,15 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Tutoriais</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Tutoriais</h3>
+<p>Esta sessão contêm informação sobre diferentes ferramentas e procedimentos relacionados com <b>eLua</b>:
+<ul>
+ <li>construindo toolchains que podem ser utilizados para construir o próprio <b>eLua</b>.</li>
+ <li>rodando <b>eLua</b> (i386) na versão standalone utilizando diferentes cenários.</li>
+ <li>usando OpenOCD para programar em <b>eLua</b> em diferentes plataformas.</li>
+</ul></p>
+</body></html>
Modified: branches/eagle_mmc/doc/pt/uart_ref.html
===================================================================
--- branches/eagle_mmc/doc/pt/uart_ref.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/uart_ref.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
<html><head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
-<meta http-equiv="Content-Language" content="en-us"><title>Product</title>
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
<link rel="stylesheet" type="text/css" href="../style.css">
</head>
@@ -22,19 +22,19 @@
|uart.PAR_ODD | uart.PAR_NONE, </font>
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">uart.STOP_1 |
-uart.STOP_1_5 | uart.STOP_2 ): set the UART interface with the</font>
+uart.STOP_1_5 | uart.STOP_2 ): configura a interface UART com os</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">given
-parameters, returns the baud rate that was set for the UART.</font>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">parametros
+passados, retorna o "baud rate" definido para a UART.</font>
</p>
<p style="margin-bottom: 0in;">
</p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><br>
</font></p>
<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif"><a name="send"></a>[</font><font face="Bitstream Vera Sans Mono, sans-serif">uart.send] </font><font face="Bitstream Vera Sans Mono, sans-serif">uart.send( id,
-Data1, Data2, ... ): send all the data to the specified UART interface.</font>
+Data1, Data2, ... ): envia todos os dados para a UART especificada.</font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#### Data 1 only
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">#### Data 1 somente
!?!!<br>
</font></p>
<p style="margin-bottom: 0in;">
@@ -45,10 +45,10 @@
uart.TIMEOUT_NO | <strike>uart.TIMEOUT_INFINITE</strike> |
timeout )</font><font face="Bitstream Vera Sans Mono, sans-serif">
</font><font face="Bitstream Vera Sans Mono, sans-serif">Data =
-uart.recv( id, uart.NO_TIMEOUT | uart.INF_TIMEOUT | timeout ): reads a </font>
+uart.recv( id, uart.NO_TIMEOUT | uart.INF_TIMEOUT | timeout ): lê um </font>
</p>
-<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">byte from the
-specified UART interface.</font></p>
+<p style="margin-bottom: 0in;"> <font face="Bitstream Vera Sans Mono, sans-serif">byte da
+interface UART especificada.</font></p>
<p style="margin-bottom: 0in;"></p>
<p style="margin-bottom: 0in;"></p>
<p style="margin-bottom: 0in;"></p>
@@ -72,4 +72,4 @@
<p style="margin-bottom: 0in;"></p>
<p style="margin-bottom: 0in;"></p>
<br>
-</body></html>
\ No newline at end of file
+</body></html>
Added: branches/eagle_mmc/doc/pt/using.html
===================================================================
--- branches/eagle_mmc/doc/pt/using.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/pt/using.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,193 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Usando eLua</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);">
+<h3>Usando eLua</h3><p> Bem, você já <a href="building.html">construiu</a> e <a href="installing.html">instalou</a> <b>eLua</b>, e agora está na hora (finalmente) da curtir eLua :)
+ Você pode compilar <b>eLua</b> utilizando tanto uma conexão serial (UART, longe de ser a mais comum) como uma conexão TCP/IP (neste caso, ainda em testes, mas funcionando muito bem), logo existem dois cenários para esta situação (veja também <a href="building.html">building eLua</a> para mais detalhes de como escolher entre console serial ou TCP/IP).</p>
+<a name="uart"><h3>Usando eLua com uma conexão serial</h3></a>
+<p>Tudo o que você precisa para usar <b>eLua</b> com uma conexão serial é de sua placa <b>eLua</b> conectada a um PC rodando um programa emulador de terminal.<br>Se
+você está usando o Windows, recomendo o <a target="_blank" href="http://www.ayera.com/teraterm/">TeraTerm</a>.
+É gratuito, possui muitos recursos e é fácil de usar. O pré-instalado Hyper Terminal também pode ser usado, porém dê uma chance ao TeraTerm, pois ele é muito melhor do que o HyperTerm IMO.<br>Se você usa o
+Linux,
+irá provavelmente se deparar com o minicom a qualque momento. Ele não é muito intuitivo e roda em modo texto, mas possui bastante recursos. Se você
+pesquisar no google por "minicom tutorial", poderá aprender rapidamente como instalá-lo e utilizá-lo. Você
+pode tentar outros emuladores, desde que configure-o
+adequadamente e que ele permite que você faça transferência de arquivos
+via XMODEM, que no momento é o processo que <b>eLua</b> utiliza. Estes sáo os principais
+parâmetros a serem configurados:</p>
+
+<ul><li>configuraçáo da porta: 115200 baud (38400 para o <a href="installing_str7.html">STR7)</a>, 8N1(8 bits de dados, sem paridade, um stop bit). </li><li>controle de fluxo do hardware: nenhum</li><li>como interpretar uma nova linha: "CR" na recepção, "CR+LF" no envio (alguns emuladores não permitem essa opção). </li></ul>
+
+
+<p>Além disso, dependendo do tipo da sua placa, você irá precisar conectá-la a uma porta serial do seu PC ou a uma porta USB, caso esteja usando um conversor USB/Serial. Por exemplo, como já foi explicado <a href="installing_lm3s.html">aqui</a>,
+a porta USB nas placas LM3Sxxxx possui duas conexões, portanto você pode usá-la como um conversor de USB para serial depois de atualizar o firmware, sendo assim, você não precisa de nenhum outro tipo de conexão. O mesmo acontece com a placa STR9-comStick. Entretanto, para a placa SAM7-EX256 você precisará conectar um cabo serial ao conector "RS232", desde que
+os jumpers já estejam configurados como explicado <a href="installing_at91sam7x.html">aqui</a> e para a placa MOD711 você precisará acrescentar um chip conversor RS232.
+Não existe uma única regra, tudo depende do modêlo da sua placa.
+</p>
+<a name="tcpip"><h3>Usando eLua com uma conexão TCP/IP</h3></a>
+<p>As coisas ficam bem mais fáceis se você decidir usar uma conexão TCP/IP:
+<ul>
+ <li>certifique-se que você conhece o endereço de sua placa. Se você habilitou IP estático (veja <a href="building.html">construindo</a>). lembre-se qual o IP escolhido; caso esteja usando DHCP, seu servidor DHCP deve ter incluído o endereço de sua placa <b>eLua</b> como seu DNS. O nome da placa sempre é "elua", logo caso você execute um "ping elua" a partir do shell poderá verificar se a placa está ativa.</li>
+ <li>um telnet para o endereço da placa (ou simplesmente "telnet elua" com DHCP ativo), e você será recebido pelo shell prompt da placa (se o shell estiver ativo, leia o próximo parágrafo para mais detalhes).
+ É importante salientar, que a placa <b>eLua</b> só poderá estar conectada a uma sessão telnet ativa a cada instante.</li>
+</ul>
+</p>
+<p>Se você está rodando Windows, certifique-se que esteja utilizando um telnet adequado, o que significa na prática "tudo menos o telnet nativo".
+ <a target="_blank" href="http://www.chiark.greenend.org.uk/~sgtatham/putty/">PuTTY</a> é muito popular e uma boa opção.</p>
+
+<a name="pc"><h3>Usando eLua "standalone" em seu PC</h3></a>
+<p>Se você construiu <b>eLua</b> para a plataforma i386, poderá dar boot direto pela placa <b>eLua</b>! Sem sistema operacional controlando o seu computador, somente <b>eLua</b> puro. Não haverá nenhum periférico para ter acesso, mas podemos usar o módulo term para executar o <i>hangman.lua</i> e o <i>life.lua</i>, bem como outros exemplos, o que o torna uma boa demonstração :) Siga <a href="installing_i386.html">
+este link</a> para obter informações específicas sobre a plataforma i386. </p>
+
+<a name="shell"><h3><a name="shell"></a>O shell eLua</h3></a>
+<p>Não importa como você está conectado fisicamente (serial, TCP/IP ou pelo seu monitor de vídeo do PC após o boot com <b>eLua</b>), depois que você configurar a conexão PC-placa <b>elua</b> (se aplicável) e pressionar o botão "RESET" de sua placa ou simplesmente pressionar ENTER se você estiver usando uma conexão serial, você deve ver o shell prompt de <b>eLua</b> (se na construção de eLua, o shell prompt foi habilitado como descrito <a href="building.html">aqui</a>). O shell é um simples interpretador de comandos interativo que permite:
+<ul>
+ <li>fornece uma ajuda para o uso do interpretador com o comando help</li>
+ <li>roda o interpretador Lua no modo interativo da mesma forma que fazemos em nosso computador</li>
+ <li>roda programas Lua a partir do sistema de arquivo eLua</li>
+ <li>transfere arquivo fonte via XMODEM e execute-o</li>
+ <li>mostra a versão de eLua</li>
+ <li>lista arquivos eLua</li>
+</ul></p>
+<p>Segue abaixo uma descrição detalhada de todos os comandos.</p>
+
+<h2>help</h2>
+<p>Mostra uma lista de todos os comandos disponíveis.</p>
+<h2>ver</h2>
+<p>Mostra a versão da imagem de <b>eLua</b> instalada na placa. Atualmente, a versão é somente incrementada por atualizações oficiais, logo se é liberada uma versão intermediária, esta não interfere no número da versão.</p>
+<h2>recv</h2>
+
+<p>Permite que você receba um arquivo eLua (tanto arquivos fontes quanto compilados) via
+XMODEM e execute-o em sua placa. Para usar este comando, é necessário que a imagem do seu <b>eLua</b> tenha sido configurada para suportar XMODEM
+(veja <a href="building.html">construindo</a> para mais detalhes). Além disso, o seu programa emulador de terminal deve suportar o envio de arquivos via protocolo XMODEM. Ambos XMODEM com checksum e XMODEM com CRC são suportados, no entanto só é aceito o XMODEM com pacotes de 128
+bytes (XMODEM com pacotes de 1K não funciona).
+Para usar esse recurso, digite "recv" no prompt do shell. eLua responderá com
+"Waiting for file ...". Neste momento, você poderá enviar o arquivo para a placa eLua
+via XMODEM. eLua receberá e executará o arquivo. Não se preocupe quando ver o
+caracter 'C' aparecendo em seu terminal depois de entrar como esse comando,
+pois essa é a forma como o XMODEM é inicializado.<br>
+Como o XMODEM é um protocolo que se utiliza de comunicação serial, este comando não está disponível caso você esteja usando uma conexão TCP/IP.<br>
+Caso você esteja querendo enviar arquivos binários já compilados ao invés de código fonte para <b>eLua</b>, veja antes <a href="using.html#cross">essa sessão</a>.
+</p>
+
+<h2>lua</h2>
+
+<p>Esse comando inicia a interpretador Lua, aceitando opcionalmente parâmetros na linha de comando, exatamente
+como se você estivesse em seu computador. O comando possui algumas restrições:</p>
+
+<ul><li>No máximo 50 caracteres para o tamanho da linha de comando</li>
+<li>a sequência 'ESC` não foi implemantada. Por exemplo, o seguinte comando não funcionará
+ devido a sequência 'ESC' com ' ('aspas simples') somente:
+
+<p><pre><code>eLua# lua -e 'print(\'Hello, World!\')' -i<br>
+Press CTRL+Z to exit Lua<br>
+lua: (command line):1: unexpected symbol near ''</code></pre></p>
+
+<p>Entretanto, se você usar ambas ' ('aspas simples') e " ("aspas duplas"), então funcionará:</p>
+
+<p><pre><code>eLua# lua -e 'print("Hello, World")' -i
+Press CTRL+Z to exit Lua
+Lua 5.1.4 Copyright (C) 1994-2008 Lua.org, PUC-Rio
+Hello,World</code></pre></p></li></ul>
+<p>Caso você queira executar um arquivo a partir do <a href="">##ROM file system</a>, não se esqueça de colocar antes do nome do arquivo o prefixo <i>/rom</i>. Por exemplo, para executar o arquivo <b>hello.lua</b>, digite o seguinte:</p>
+<p><pre><code>$ lua /rom/hello.lua</code></pre></p>
+<h2>ls or dir</h2>
+<p>Lista todos os arquivos do sistema de arquivos utilizado por <b>eLua</b> (atualmente armazenado em ROM), bem como o total ocupado e o espaço total do sistema de arquivos.</p>
+<h2>exit</h2>
+<p>Sai do shell. Esse comando só faz sentido, caso você tenha compilado <b>eLua</b> para conexão sobre TCP/IP, já que a sessão telnet é encerrada com a placa <b>eLua</b>. Caso contrário o comando simplesmente encerra
+ o shell e trava até você resetar sua placa.</p>
+<a name="cross"><h3>Cross-compilation: compilando seus programas eLua para uma plataforma diferente</h3></a>
+<p><i>Cross-compilation</i> é o processo de compilação de um programa em uma platforma com obejtivo de ser
+utilzado em uma outra plataforma. Por exemplo, o processo de compilação para gerar uma imagem binária de <b>eLua</b> em
+seu PC para uso na sua placa <b>eLua</b> é o que chamamos de "cross-compiling". Lua pode ser compilada dessa forma também. Ao compilar Lua usando esse procedimento
+ você tem algumas vantagens importantes:
+<ul>
+<li><b>volocidade</b>: o compilador Lua na placa <b>eLua</b> não precisa compilar o código fonte Lua
+ , simplesmente executa o código binário.</li>
+<li><b>memória</b>: caso você esteja executando diretamente um código binário, nenhuma memória a mais
+ é "gasta" em placa <b>eLua</b> para compilação do código Lua para bytecode.
+ Muitas vezes isso é a "salvação". Caso você esteja tentando executar código Lua direto de sua placa e recebendo a mensagem de erro "not enough memory",
+ pode mudar esse resultado compilando o programa Lua em seu PC e depois
+ executando o arquivo gerado. Alé disso, compilar programas Lua muito grandes em sua placa
+ <b>eLua</b> pode acarretar estouro de pilha, o que normalmente nos leva a erros difíceis de serem encontrados.</li>
+</ul></p>
+<p>Para usar "cross-compilation", as duas plataformas Lua (neste caso seu PC e sua placa <b>eLua</b>) devem ser compatíveis
+(devem ter os mesmos tipos de dados, com os mesmos tamanhos e a mesma representação de memória).
+ Isto não é verdadeiro sempre. Por exemplo, alguns toolchains gcc para arquitetura ARM usam como padrão uma representação muito específica para números com dupla precisão (conhecida como formato FPA), tornando dessa forma, os arquivos bytecode gerados no PC com um compilador Lua inúteis para as placas ARM. Outros toolchains não possuem esse problema. Outras arquiteturas (como a AVR32) são "big endian", ao contrário da plataforma Intel para PCs que é "little endian".<br>
+Para resolver esses tipos de problemas, um patch para "Lua cross-compilation" foi enviado para a lista de e-mails de Lua
+a pouco tempo atrás, e foi bastante modificado como parte do projeto <b>eLua</b>
+ para funcionar com a arquitetura ARM. Aqui está como usá-lo (as instruções abaixo foram testadas em Linux, não em Windows, mesmo assim, elas devem funcionar também no Windows com pouco ou quase nenhum esforço):
+<ul>
+<li>primeiro, certifique-se que seu PC já esteja com todos os arquivos necessários para a construção de um <b>eLua</b> (gcc,
+ binutils, libc, headers...). Você precisará também do scons. A boa notícia é que você já deve ter o scon instalado em seu sistema,
+já que, caso contrá você não seria capaz nem mesmo de construir <b>eLua</b> (veja <a href="building.html">construindo</a> para instruções mais detalhadas).</li>
+<li>a partir do diretório base de <b>eLua</b>, digite o seguinte comando:</li>
+ <p><pre><code>$ scons -f cross-lua.py</code></pre></p></ul>
+<p>Esse comando gera um arquivo chamado <i>luac</i> no mesmo. É quase a mesma coisa que no compilador comum, mas possui alguns poucos argumentos para lidar com as diferenças entre as diversas arquiteturas (mostradas abaixo em negrito):</p>
+<p><pre><code>usage: ./luac [options] [filenames].
+Available options are:
+- process stdin
+-l list
+-o name output to file 'name' (default is "luac.out")
+-p parse only
+-s strip debug information
+-v show version information
+<b>-cci bits cross-compile with given integer size
+-ccn type bits cross-compile with given lua_Number type and size
+-cce endian cross-compile with given endianness ('big' or 'little')</b>
+-- stop handling options</code></pre></p>
+<p>Tudo que deve ser feito agora é usar a tabela abaixo para identificar qual os parâmetros certos para serem utilizados no cross-compiler:</p>
+</p><table style="text-align: left;" class="table_center">
+<tbody>
+<tr>
+ <th style="text-align: left;">tipo da imagem de eLua</th>
+ <th style="text-align: center;">Arquitetura</th>
+ <th style="text-align: center;">Compilador</th>
+ <th style="text-align: center;">Comando</th>
+</tr>
+<tr>
+ <td>Ponto Flutuante (lua)</td>
+ <td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
+ <td><a href="toolchains.html">arm-gcc</a>
+ <td><code>./luac -ccn float_arm 64 -cce little -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Ponto Flutuante (lua)</td>
+ <td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
+ <td><a href="toolchains.html">codesourcery</a>
+ <td><code>./luac -ccn float 64 -cce little -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Inteiro (lualong)</td>
+ <td>ARM7TDMI<br>Cortex-M3<br>ARM966E-S</td>
+ <td><a href="toolchains.html">arm-gcc<br>codesourcery</a>
+ <td><code>./luac -ccn int 32 -cce little -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Ponto Flutuante (lua)</td>
+ <td>AVR32</td>
+ <td><a href="toolchains.html">avr32-gcc</a>
+ <td><code>./luac -ccn float 64 -cce big -o <script.luac> -s <script.lua></code></td>
+</tr>
+<tr>
+ <td>Inteiro (lualong)</td>
+ <td>AVR32</td>
+ <td><a href="toolchains.html">avr32-gcc</a>
+ <td><code>./luac -ccn int 32 -cce big -o <script.luac> -s <script.lua></code></td>
+</tr>
+</tbody>
+</table>
+<p>(observe que se por alguma razão você precisa de um cross-compile <b>eLua</b> para x86, poderá usar o próprio compilador Lua).<br>
+Você pode omitir o parâmetro <i>-s</i> (de strip) da compilação, mas isso resultará em arquivos binários maiores (quando não se usa o parâmetro <i>-s</i>, a informação de debug não é removida do arquivo gerado).</p>
+<p>Você pode usar o arquivo gerado de duas formas:</p>
+<ul>
+ <li>gravá-lo em uma <a href="arch_romfs.html">ROM do sistema de sua placa</a> e executá-lo a partir daí.</li>
+ <li>usar o comando <i>recv</i> a partir <a href="using.html#shell">do shell</a> para enviá-lo para a placa usando uma conexão serial.</li>
+</ul>
+<p>
+</p>
+</body></html>
+
Copied: branches/eagle_mmc/doc/pt/versionhistory.html (from rev 269, branches/eagle_mmc/doc/en/versionhistory.html)
===================================================================
--- branches/eagle_mmc/doc/en/versionhistory.html 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/doc/pt/versionhistory.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,9 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
+<html><head>
+<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
+<meta http-equiv="Content-Language" content="en-us"><title>Produto</title>
+
+<link rel="stylesheet" type="text/css" href="../style.css"></head>
+<body style="background-color: rgb(255, 255, 255);"><h3><a name="title" href="http://www.eluaproject.net/en/Using_OpenOCD" class="local"></a>Histórico das versões de eLua</h3>
+
+ <div class="content"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span><br></div></body></html>
Modified: branches/eagle_mmc/doc/readme.txt
===================================================================
--- branches/eagle_mmc/doc/readme.txt 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/readme.txt 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,17 +1,13 @@
This document describes the eLua documentation structure, formats and the
tools used to maintain it.
-## Temporary note:
-## - This is the new doc structure proposed for eLua, still
-## under evaluation but probably replacing soon the single manual format.
-## - The /doc directory will soon replace the current /docs
-
eLua documentation is created and maintained offline, in HTML format and
integrated with the same version control system used for eLua Source Code.
This allows the same content to be deployed both online, published on the
site, and offline, included in our releases.
All the content pages are created and edited offline, using any HTML
editor. We're currently using KompoZer and opened to new sugestions :)
+
The "doc site" structure is created by a help doc generator tool called
WebBook, created at Tecgraf/PUC-Rio. WebBook is Open Source and Free
Software, 100% written in Lua and it's usage is described in
Deleted: branches/eagle_mmc/doc/ssSearch.class
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/doc/ssSearchThread.class
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/doc/ssSearch_en.html
===================================================================
--- branches/eagle_mmc/doc/ssSearch_en.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/ssSearch_en.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,25 +0,0 @@
-<html>
-<head>
-<title>ssSearch</title>
-<link rel="stylesheet" type="text/css" href="style.css">
-</head>
-<body>
-<h3>Simple Search</h3>
-<blockquote>
-<center>
- <applet code="ssSearch.class" width="640" height="480">
- <param name="BGCOLOR" value="0B6DCE">
- <param name="LISTAREACOLOR" value="ffffff">
- <!-- Use "_self", "_blank", "_parent", "_top" or any other user-defined name -->
- <param name="TARGETFRAME" value="_self">
- <param name="DATAFILE" value="wb_search_en.txt">
- <!-- The APPLETHOME param is just an acknowledgement -->
- <!-- Do not edit the value of APPLETHOME param -->
- <param name="APPLETHOME" value="http://www.geocities.com/SiliconValley/Lakes/5365/index.html">
- </applet>
-</center>
-</blockquote>
-<p>Powered by <a href="http://us.geocities.com/nsenthil/ssSearch.html">ssSearch</a>
-from Nalla
-Senthilnathan.</p>
-</body></html>
Deleted: branches/eagle_mmc/doc/ssSearch_pt.html
===================================================================
--- branches/eagle_mmc/doc/ssSearch_pt.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/ssSearch_pt.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,25 +0,0 @@
-<html>
-<head>
-<title>ssSearch</title>
-<link rel="stylesheet" type="text/css" href="style.css">
-</head>
-<body>
-<h3>Busca Simples</h3>
-<blockquote>
-<center>
- <applet code="ssSearch.class" width="640" height="480">
- <param name="BGCOLOR" value="0B6DCE">
- <param name="LISTAREACOLOR" value="ffffff">
- <!-- Use "_self", "_blank", "_parent", "_top" or any other user-defined name -->
- <param name="TARGETFRAME" value="_self">
- <param name="DATAFILE" value="wb_search_pt.txt">
- <!-- The APPLETHOME param is just an acknowledgement -->
- <!-- Do not edit the value of APPLETHOME param -->
- <param name="APPLETHOME" value="http://www.geocities.com/SiliconValley/Lakes/5365/index.html">
- </applet>
-</center>
-</blockquote>
-<p>Powered by <a href="http://us.geocities.com/nsenthil/ssSearch.html">ssSearch</a>
-from Nalla
-Senthilnathan.</p>
-</body></html>
Modified: branches/eagle_mmc/doc/style.css
===================================================================
--- branches/eagle_mmc/doc/style.css 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/style.css 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,125 +1,134 @@
- body {
- margin-left: 1em;
- margin-right: 1em;
- font-family: tahoma, verdana, arial, helvetica, geneva, sans-serif;
- background-color:#ffffff;
- }
- p {
- margin-left: 1em;
- line-height: 130%;
- }
- h2 {
- color: #3366CC;
- }
- h3 {
- padding: 4px;
- background-color: #E1E1E1;
- border: 1px solid #808080;
- color: #5C5C5C;
- }
- pre {
- background-color: #CEE7FF;
- border: 1px solid #62A0FF;
- padding: 10px;
- font-family: 'Monotype.com', "Courier New", Courier, monospace;
- font-size: 90%;
- line-height: 125%;
- margin-left: 3em;
- margin-right: 3em;
- }
- p.info {
- margin-left: 3em;
- }
- ul {
- margin-left: 2em;
- }
- h4 {
- background-color: #E1E1E1;
- padding: 3px;
- margin-right: 2em;
- margin-left: 2em;
- }
- h1 {
- text-align: center;
- }
- table {
- border-collapse: collapse;
- }
- td {
- padding: 5px;
- border: 1px solid #808080;
- }
- th {
- padding: 5px;
- border: 2px solid #808080;
- background-color: #C0C0C0;
- }
- .homeTitle {
- font-family: Arial, Helvetica, sans-serif;
- font-size: 36pt;
- font-weight: bold;
- color: #003399;
- text-align: center;
- }
- .homeDescription {
- font-family: Arial, Helvetica, sans-serif;
- font-size: 20pt;
- color: #003399;
- text-align: center;
- }
- .homeVersion {
- margin: 10px;
- font-family: Arial, Helvetica, sans-serif;
- font-size: 16pt;
- color: #003399;
- text-align: center;
- }
+/* Generated by KompoZer */
+body {
+ margin-left: 1em;
+ margin-right: 1em;
+ font-family: tahoma,verdana,arial,helvetica,geneva,sans-serif;
+ background-color: #ffffff;
+}
+p {
+ margin-left: 1em;
+ line-height: 130%;
+}
+h2 {
+ border: 1px solid #808080;
+ padding: 4px;
+ background-color: #aaffcc;
+ font-size: 99%;
+ margin-left: 1em;
+}
+h3 {
+ border: 1px solid #808080;
+ padding: 6px;
+ background-color: #cee7ff;
+ color: #5c5c5c;
+}
+table {
+ margin-left: 1em;
+}
+pre {
+ border: 1px dashed #62a0ff;
+ padding: 4px;
+ background-color: #cee7ff;
+ font-family: 'Monotype.com',"Courier New",Courier,monospace;
+ font-size: 90%;
+ line-height: 125%;
+ margin-left: 1em;
+ margin-right: 1em;
+ overflow: auto;
+}
+p.info {
+ margin-left: 3em;
+}
+ul {
+ margin-left: 2em;
+}
+ol {
+ margin-left: 2em;
+}
+h4 {
+ margin-left: 2em;
+}
+h1 {
+ text-align: center;
+}
+table {
+ border-collapse: collapse;
+}
+td {
+ border: 1px solid #808080;
+ padding: 5px;
+}
+th {
+ border: 2px solid #808080;
+ padding: 5px;
+ background-color: #c0c0c0;
+}
+.homeTitle {
+ font-family: Arial,Helvetica,sans-serif;
+ font-size: 36pt;
+ font-weight: bold;
+ color: #003399;
+ text-align: center;
+}
+.homeDescription {
+ font-family: Arial,Helvetica,sans-serif;
+ font-size: 20pt;
+ color: #003399;
+ text-align: center;
+}
+.homeVersion {
+ margin: 10px;
+ font-family: Arial,Helvetica,sans-serif;
+ font-size: 16pt;
+ color: #003399;
+ text-align: center;
+}
.bg_winxp {
- text-align: center;
- background-color: #ECE9D8;
+ text-align: center;
+ background-color: #ece9d8;
}
.bg_vista {
- text-align: center;
- background-color: #F0F0F0;
+ text-align: center;
+ background-color: #f0f0f0;
}
.bg_gtk {
- text-align: center;
- background-color: #EFEBE7;
+ text-align: center;
+ background-color: #efebe7;
}
.bg_mot {
- text-align: center;
- background-color: #ADB1C2;
+ text-align: center;
+ background-color: #adb1c2;
}
.bg_win2k {
- text-align: center;
- background-color: #D4D0C8;
+ text-align: center;
+ background-color: #d4d0c8;
}
- #navigation {
- position: fixed;
- top: 0;
- right: 0;
- background-color: #E1E1E1;
- }
- #navigation ul {
- list-style-type: none;
- margin: 0;
- padding: 0;
- }
- #navigation li {
- float: left;
- }
- #navigation a {
- color: #5C5C5C;
- text-decoration: none;
- display: block;
- padding: 3px;
- border: 1px solid #808080;
- background-color: #E1E1E1;
- font-size: small;
- }
- #navigation a:hover {
- color: #E1E100;
- text-decoration: none;
- border: 1px solid #808080;
- background-color: #5C5C5C;
- }
+#navigation {
+ position: fixed;
+ top: 0;
+ right: 0;
+ background-color: #e1e1e1;
+}
+#navigation ul {
+ margin: 0;
+ padding: 0;
+ list-style-type: none;
+}
+#navigation li {
+ float: left;
+}
+#navigation a {
+ border: 1px solid #808080;
+ padding: 3px;
+ color: #5c5c5c;
+ text-decoration: none;
+ display: block;
+ background-color: #e1e1e1;
+ font-size: small;
+}
+#navigation a:hover {
+ border: 1px solid #808080;
+ color: #e1e100;
+ text-decoration: none;
+ background-color: #5c5c5c;
+}
Deleted: branches/eagle_mmc/doc/template_ssSearch.html
===================================================================
--- branches/eagle_mmc/doc/template_ssSearch.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/template_ssSearch.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,22 +0,0 @@
-<html>
-<head>
-<title>ssSearch</title>
-<link rel="stylesheet" type="text/css" href="style.css">
-</head>
-<body>
-<h3>WB_SEARCH</h3>
-<blockquote>
-<center>
- <applet code="ssSearch.class" width="640" height="480">
- <param name="BGCOLOR" value="0B6DCE">
- <param name="LISTAREACOLOR" value="ffffff">
- <!-- Use "_self", "_blank", "_parent", "_top" or any other user-defined name -->
- <param name="TARGETFRAME" value="_self">
- <param name="DATAFILE" value="wb_searchWB_LNG.txt">
- <!-- The APPLETHOME param is just an acknowledgement -->
- <!-- Do not edit the value of APPLETHOME param -->
- <param name="APPLETHOME" value="http://www.geocities.com/SiliconValley/Lakes/5365/index.html">
- </applet>
-</center>
-</blockquote>
-</body></html>
Modified: branches/eagle_mmc/doc/wb/wb_build.lua
===================================================================
--- branches/eagle_mmc/doc/wb/wb_build.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb/wb_build.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -76,7 +76,7 @@
local wb_title = readFile("template_wb_title.html")
if(wb_usr.logo_image_file ~= nil and wb_usr.logo_image_file ~= "")then
- wb_title = string.gsub(wb_title, "WB_LOGO", [[<img src="wb_img/]]..wb_usr.logo_image_file..[[" border="0">]])
+ wb_title = string.gsub(wb_title, "WB_LOGO", [[<A href="]]..wb_usr.logo_onclick_link..[[" target="blank"><img src="wb_img/]]..wb_usr.logo_image_file..[[" border="0"></A>]])
else
wb_title = string.gsub(wb_title, "WB_LOGO","")
end
@@ -245,6 +245,9 @@
-- Write Footer
file:write(" </div>\n")
+ if wb_usr.tree.footer then
+ file:write(wb_usr.tree.footer)
+ end
file:write("</body>\n")
file:write("</html>\n")
Deleted: branches/eagle_mmc/doc/wb/wb_usr.lua
===================================================================
--- branches/eagle_mmc/doc/wb/wb_usr.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb/wb_usr.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,713 +0,0 @@
--------------------------------------------------------------------------------
--- eLua Documentation Structure Definition
---
--- This is the configuration file for the WebBook html help generator.
--- It is used to generate the menu tree and it's links to the content pages.
--- More info about WebBook can be found @ http://www.tecgraf.puc-rio.br/webbook
---
--------------------------------------------------------------------------------
-
-
--- General config parameters
-wb_usr = {
- langs = {"en","pt" },
- start_size = "200",
- title_bar_height = 80,
- enable_search = true,
- --search_label = "Search:",
- search_link = "http://www.eluaproject.net",
- --contact = "dadosutter at eluaproject.net",
- --copyright_name = "eLua Team",
- --copyright_link = "http://www.eluaproject.net",
-
- title_bgcolor = "midnightblue",
- file_title = "wb",
- start_open = "1",
- logo_image_file = "eLua-logo-80x80.png"
-}
-
-
-
--- Page and Bar Titles
-wb_usr.messages =
-{
- en =
- {
- title = "eLua Doc",
- bar_title = "eLua - Embedded Lua"
- },
- pt =
- {
- title = "eLua Doc",
- bar_title = "eLua - Embedded Lua"
- }
-}
-
-
-
--- Menu Tree Definition
-wb_usr.tree =
-{
- name = { nl = "eLua" },
- link = "news.html",
- folder =
- {
- { name = {en = "Overview", pt = "Apresentação" },
- link = "overview.html",
- folder =
- {
- { name = { en = "What is", pt = "O que é eLua ?" },
- link = "overview.html#whatis",
- },
- { name = { en = "Audience", pt = "Público alvo" },
- link = "overview.html#audience",
- },
---[[
- { name = { en = "Uses", pt = "Aplicações" },
- link = "overview.html#uses",
- },
---]]
- { name = { en = "Authors", pt = "Autores" },
- link = "overview.html#authors",
- },
- { name = { en = "Contacts", pt = "Contatos" },
- link = "overview.html#contacts",
- },
- { name = { en = "Licence", pt = "Licença" },
- link = "overview.html#license",
- },
- },
- },
- {
- name = {en = "Community", pt = "Comunidade" },
- link = "comunity.html",
- folder =
- {
- { name = { en = "Lists", pt = "Listas" },
- link = "comunity.html#lists",
- },
- { name = { en = "Credits", pt = "Créditos" },
- link = "comunity.html#credits",
- },
---[[
- { name = { en = "Galery", pt = "Galeria" },
- link = "comunity.html#galery",
- },
- { name = { en = "Projects", pt = "Projetos" },
- link = "comunity.html#projects",
- },
---]]
- },
- },
- {
- name = {en = "Status", pt = "Status" },
- link = "status.html",
- folder =
- {
- { name = { en = "News", pt = "NotÃcias" },
- link = "news.html",
- },
- { name = { en = "Platforms Supported", pt = "Plataformas Suportadas" },
- link = "status.html#platforms",
- },
- { name = { en = "Roadmap", pt = "Futuro" },
- link = "status.html#roadmap",
- },
- },
- },
- {
- name = { en = "Documentation", pt = "Documentação" },
- link = "using.html",
- folder =
- {
- {
- name = { en = "FAQ", pt = "FAQ" },
- link = "faq.html",
- },
- {
- name = { en = "Using", pt = "Usando" },
- link = "using.html",
- },
- {
- name = { en = "Building", pt = "Building" },
- link = "building.html",
- },
- {
- name = { en = "Examples", pt = "Exemplos" },
- link = "examples.html",
- folder =
- {
- { name = { en = "hello.lua", pt = "hello.lua" },
- link = "examples.html#hello",
- },
- { name = { en = "info.lua", pt = "info.lua" },
- link = "examples.html#info",
- },
- { name = { en = "led.lua", pt = "led.lua" },
- link = "examples.html#led",
- },
- { name = { en = "hangman.lua", pt = "hangman.lua" },
- link = "examples.html#hangman",
- },
- { name = { en = "pwmled.lua", pt = "pwmled.lua" },
- link = "examples.html#pwmled",
- },
- { name = { en = "tvbgone.lua", pt = "tvbgone.lua" },
- link = "examples.html#tvbgone",
- },
- { name = { en = "piano.lua", pt = "piano.lua" },
- link = "examples.html#piano",
- },
- { name = { en = "bisect.lua", pt = "bisect.lua" },
- link = "examples.html#bisect",
- },
- { name = { en = "morse.lua", pt = "morse.lua" },
- link = "examples.html#morse",
- },
- { name = { en = "lhttpd.lua", pt = "lhttpd.lua" },
- link = "examples.html#lhttpd",
- },
- },
- },
- {
- name = { en = "Tutorials", pt = "Tutoriais" },
- link = "tutorials.html",
- folder =
- {
- { name = { en = "Booting on a PC", pt = "Booting on a PC" },
- link = "tut_bootpc.html",
- },
- { name = { en = "Booting from a Pendrive", pt = "Booting from a Pendriv" },
- link = "tut_bootstick.html",
- },
- { name = { en = "Toolchain Building", pt = "Toolchain Building" },
- link = "tchainbuild.html",
- folder =
- {
- { name = { en = "ARM7 & ARM9 Toolchains", pt = "ARM 7 & ARM9 Toolchains" },
- link = "tc_arm.html",
- },
- { name = { en = "ARM Cortex-M3", pt = "ARM Cortex-M3" },
- link = "tc_cortex.html",
- },
- { name = { en = "i386", pt = "i386" },
- link = "tc_386.html",
- },
- },
- },
- { name = { en = "Using OpenOCD", pt = "Using OpenOC" },
- link = "tut_openocd.html",
- },
- },
- },
- {
- name = {en = "Version History", pt = "Histórico de Versões" },
- link = "versionhistory.html",
- folder =
- {
- { name = { en = "v 0.4", pt = "v 0.4" },
- link = "versionhistory.html#04",
- },
- { name = { en = "v 0.5", pt = "v 0.5" },
- link = "versionhistory.html#05",
- },
- { name = { en = "v 0.6", pt = "v 0.6" },
- link = "versionhistory.html#06",
- },
- },
- },
- },
- },
- {
- name = { en = "Reference Manual", pt = "Manual de Referência" },
- link = "refman.html#genericmodules",
- folder =
- {
- {
- name = { en = "Generic Modules", pt = "Módulos Genéricos" },
- link = "refman.html#genericmodules",
- folder =
- {
- {
- name = { en = "bit", pt = "bit" },
- link = "refman.html#bitmodule",
- folder =
- {
- {
- name ={ en = "bnot", pt = "bnot" },
- link = "refman.html#bit_bnot"
- },
- {
- name ={ en = "band", pt = "band" },
- link = "refman.html#bit_band"
- },
- {
- name ={ en = "bor", pt = "bor" },
- link = "refman.html#bit_bor"
- },
- {
- name ={ en = "bxor", pt = "bxor" },
- link = "refman.html#bit_bxor"
- },
- {
- name ={ en = "lshift", pt = "lshift" },
- link = "refman.html#bit_lshift"
- },
- {
- name ={ en = "rshift", pt = "rshift" },
- link = "refman.html#bit_rshift"
- },
- {
- name ={ en = "bit", pt = "bit" },
- link = "refman.html#bit_bit"
- },
- {
- name ={ en = "set", pt = "set" },
- link = "refman.html#bit_set"
- },
- {
- name ={ en = "clear", pt = "clear" },
- link = "refman.html#bit_clear"
- },
- {
- name ={ en = "isset", pt = "isset" },
- link = "refman.html#bit_isset"
- },
- {
- name ={ en = "isclear", pt = "isclear" },
- link = "refman.html#bit_isclear"
- },
- },
- },
- {
- name = { en = "cpu", pt = "cpu" },
- link = "refman.html#cpumodule",
- folder =
- {
- {
- name ={ en = "write32", pt = "write32" },
- link = "refman.html#cpu_write32"
- },
- {
- name ={ en = "write16", pt = "write16" },
- link = "refman.html#cpu_write16"
- },
- {
- name ={ en = "write8", pt = "write8" },
- link = "refman.html#cpu_write8"
- },
- {
- name ={ en = "reat32", pt = "read32" },
- link = "refman.html#cpu_read32"
- },
- {
- name ={ en = "read16", pt = "read16" },
- link = "refman.html#cpu_read16"
- },
- {
- name ={ en = "read8", pt = "read8" },
- link = "refman.html#cpu_read8"
- },
- {
- name ={ en = "disableinterrupts", pt = "disableinterrupts" },
- link = "refman.html#cpu_disableinterrupts"
- },
- {
- name ={ en = "enableinterrupts", pt = "enableinterrupts" },
- link = "refman.html#cpu_enableinterrupts"
- },
- {
- name ={ en = "clockfrequency", pt = "clockfrequency" },
- link = "refman.html#cpu_clockfrequency"
- },
- },
- },
- {
- name = { en = "gpio", pt = "gpio" },
- link = "refman.html#gpiomodule",
- folder =
- {
- {
- name ={ en = "configpin", pt = "configpin" },
- link = "refman.html#gpio_configpin"
- },
- {
- name ={ en = "setpinvalue", pt = "setpinvalue" },
- link = "refman.html#gpio_setpinvalue"
- },
- {
- name ={ en = "getpinvalue", pt = "getpinvalue" },
- link = "refman.html#gpio_getpinvalue"
- },
- {
- name ={ en = "setpinhigh", pt = "setpinhigh" },
- link = "refman.html#gpio_setpinhigh"
- },
- {
- name ={ en = "setpinlow", pt = "setpinlow" },
- link = "refman.html#gpio_setpinlow"
- },
- },
- },
- {
- name = {en = "net", pt = "net" },
- link = "refman.html#netmodule",
- folder =
- {
- {
- name ={ en = "to be added ...", pt = "setup" },
- link = "net_ref.html#net_setup"
- },
- },
- },
- {
- name = { en = "pwm", pt = "pwm" },
- link = "refman.html#pwmmodule",
- folder =
- {
- {
- name ={ en = "setup", pt = "setup" },
- link = "refman.html#pwm_setup"
- },
- {
- name ={ en = "setcycle", pt = "setcycle" },
- link = "refman.html#pwm_setcycle"
- },
- {
- name ={ en = "start", pt = "start" },
- link = "refman.html#pwm_start"
- },
- {
- name ={ en = "stop", pt = "stop" },
- link = "refman.html#pwm_stop"
- },
- {
- name ={ en = "setclock", pt = "setclock" },
- link = "refman.html#pwm_setclock"
- },
- {
- name ={ en = "getclock", pt = "getclock" },
- link = "refman.html#pwm_getclock"
- },
- },
- },
- {
- name = { en = "spi", pt = "spi" },
- link = "refman.html#spimodules",
- folder =
- {
- {
- name ={ en = "setup", pt = "setup" },
- link = "refman.html#spi_setup"
- },
- {
- name ={ en = "select", pt = "select" },
- link = "refman.html#spi_select"
- },
- {
- name ={ en = "unselect", pt = "unselect" },
- link = "refman.html#spi_unselect"
- },
- {
- name ={ en = "send", pt = "send" },
- link = "refman.html#spi_send"
- },
- {
- name ={ en = "sendrecv", pt = "sendrecv" },
- link = "refman.html#spi_sendrecv"
- },
- },
- },
- {
- name = { en = "sys", pt = "sys" },
- link = "refman.html#sysmodule",
- folder =
- {
- {
- name ={ en = "platform", pt = "platform" },
- link = "refman.html#sys_platforms"
- },
- {
- name ={ en = "mcu", pt = "mcu" },
- link = "refman.html#sys_mcu"
- },
- {
- name ={ en = "cpu", pt = "cpu" },
- link = "refman.html#sys_cpu"
- },
- {
- name ={ en = "board", pt = "board" },
- link = "refman.html#sys_board"
- },
- },
- },
- {
- name = {en = "term", pt = "term" },
- link = "refman.html#termmodule",
- folder =
- {
- {
- name ={ en = "clear", pt = "clear" },
- link = "refman.html#term_clear"
- },
- {
- name ={ en = "cleareol", pt = "cleareol" },
- link = "refman.html#term_cleareol"
- },
- {
- name ={ en = "moveto", pt = "moveto" },
- link = "refman.html#term_moveto"
- },
- {
- name ={ en = "moveup", pt = "moveup" },
- link = "refman.html#term_moveup"
- },
- {
- name ={ en = "movedown", pt = "movedown" },
- link = "refman.html#term_movedown"
- },
- {
- name ={ en = "moveleft", pt = "moveleft" },
- link = "refman.html#term_moveleft"
- },
- {
- name ={ en = "moveright", pt = "moveright" },
- link = "refman.html#term_moveright"
- },
- {
- name ={ en = "getlinecount", pt = "getlinecount" },
- link = "refman.html#term_getlinecount"
- },
- {
- name ={ en = "getcolcount", pt = "getcolcount" },
- link = "refman.html#term_getcolcount"
- },
- {
- name ={ en = "printstr", pt = "printstr" },
- link = "refman.html#term_printstr"
- },
- {
- name ={ en = "getx", pt = "getx" },
- link = "refman.html#term_getx"
- },
- {
- name ={ en = "gety", pt = "gety" },
- link = "refman.html#term_gety"
- },
- {
- name ={ en = "inputchar", pt = "inputchar" },
- link = "refman.html#term_inputchar"
- },
- },
- },
- {
- name = { en = "tmr", pt = "tmr" },
- link = "refman.html#tmrmodule",
- folder =
- {
- {
- name ={ en = "delay", pt = "delay" },
- link = "refman.html#tmr_delay"
- },
- {
- name ={ en = "read", pt = "read" },
- link = "refman.html#tmr_read"
- },
- {
- name ={ en = "start", pt = "start" },
- link = "refman.html#tmr_start"
- },
- {
- name ={ en = "diff", pt = "diff" },
- link = "refman.html#tmr_diff"
- },
- {
- name ={ en = "mindelay", pt = "mindelay" },
- link = "refman.html#tmr_mindelay"
- },
- {
- name ={ en = "maxdelay", pt = "maxdelay" },
- link = "refman.html#tmr_maxdelay"
- },
- {
- name ={ en = "setclock", pt = "setclock" },
- link = "refman.html#tmr_setclock"
- },
- },
- },
- {
- name = {en = "uart", pt = "uart" },
- link = "refman.html#uartmodule",
- folder =
- {
- {
- name ={ en = "setup", pt = "setup" },
- link = "refman.html#uart_setup"
- },
- {
- name ={ en = "send", pt = "send" },
- link = "refman.html#uart_send"
- },
- {
- name ={ en = "recv", pt = "recv" },
- link = "refman.html#uart_recv"
- },
- },
- },
- },
- },
- {
- name = {en = "Platform Dependent Modules", pt = "Dependentes de Plataforma" },
- link = "platdepmodules.html",
- folder =
- {
- { name = { en = "adc", pt = "adc" },
- link = "refman.html#adcmodule",
- folder =
- {
- {
- name ={ en = "sample", pt = "sample" },
- link = "refman.html#adc_sample"
- },
- {
- name ={ en = "getsamples", pt = "getsamples" },
- link = "refman.html#adc_getsamples"
- },
- {
- name = { en = "maxval", pt = "maxval" },
- link = "refman.html#adc_maxval"
- },
- {
- name = { en = "samplesready", pt = "samplesready" },
- link = "refman.html#adc_samplesready"
- },
- {
- name = { en = "dataready", pt = "dataready" },
- link = "refman.html#adc_dataready"
- },
- {
- name = { en = "setmode", pt = "setmode" },
- link = "refman.html#adc_setmode"
- },
- {
- name = { en = "setsmoothing", pt = "setsmoothing" },
- link = "refman.html#adc_setsmoothing"
- },
- {
- name = { en = "getsmoothing", pt = "getsmoothing" },
- link = "refman.html#adc_getsmoothing"
- },
- {
- name = { en = "burst", pt = "burst" },
- link = "refman.html#adc_burst"
- },
- },
- },
- { name = { en = "disp", pt = "disp" },
- link = "refman.html#dispmodule",
- folder =
- {
- {
- name ={ en = "init", pt = "init" },
- link = "refman.html#disp_init"
- },
- {
- name = { en = "enable", pt = "enable" },
- link = "refman.html#disp_enable"
- },
- {
- name = { en = "disable", pt = "disable" },
- link = "refman.html#disp_disable"
- },
- {
- name = { en = "on", pt = "on" },
- link = "refman.html#disp_on"
- },
- {
- name = { en = "off", pt = "off" },
- link = "refman.html#disp_off"
- },
- {
- name = { en = "print", pt = "print" },
- link = "refman.html#disp_print"
- },
- {
- name = { en = "draw", pt = "draw" },
- link = "refman.html#disp_draw"
- },
- },
- },
- },
- },
- },
- },
- {
- name = { en = "Downloads", pt = "Downloads" },
- link = "downloads.html",
- folder =
- {
- {
- name = { en = "Binaries", pt = "Binaries" },
- link = "dl_binaries.html",
- folder =
- {
- {
- name = { en = "Atmel", pt = "Atmel" },
- link = "lm_bin.html",
- },
- {
- name = { en = "Luminary Micro", pt = "Luminary Micro" },
- link = "lm_bin.html",
- },
- {
- name = { en = "PC i386", pt = "PC i386" },
- link = "lm_bin.html",
- },
- {
- name = { en = "Phillips", pt = "Phillips" },
- link = "lm_bin.html",
- },
- {
- name = { en = "ST Micro", pt = "ST Micro" },
- link = "lm_bin.html",
- },
- },
- },
- {
- name = { en = "Source Code", pt = "Fontes" },
- link = "sources.html",
- folder =
- {
- {
- name = { en = "v0.6", pt = "v0.6" },
- link = "sources.html#06"
- },
- {
- name = { en = "trunk", pt = "trunk" },
- link = "sources.html#trunk"
- },
- {
- name = { en = "old versions", pt = "anteriores" },
- link = "oldversions.html",
- folder =
- {
- {
- name = { en = "v0.5", pt = "v0.5" },
- link = "oldversions.html#05"
- },
- {
- name = { en = "v0.4", pt = "v0.4" },
- link = "sources.html#04"
- },
- },
- },
- },
- },
- {
- name = { en = "Developers", pt = "Desenvolvedores" },
- link = "developers.html"
- },
- },
- },
- },
-}
Added: branches/eagle_mmc/doc/wb/wb_usr_template.lua
===================================================================
--- branches/eagle_mmc/doc/wb/wb_usr_template.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb/wb_usr_template.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,458 @@
+-------------------------------------------------------------------------------
+-- eLua Documentation Structure Definition
+--
+-- This is the configuration file for the WebBook html help generator.
+-- It is used to generate the menu tree and it's links to the content pages.
+-- More info about WebBook can be found @ http://www.tecgraf.puc-rio.br/webbook
+--
+-------------------------------------------------------------------------------
+
+
+-- General config parameters
+wb_usr = {
+ langs = {"en","pt" },
+ start_size = "200", -- Menu tree initial width
+ title_bar_height = 80, -- Title bar initial height
+ title_bgcolor = "midnightblue",
+ enable_search = true,
+ search_link = "http://www.eluaproject.net",
+-- search_label = "Search: ",
+-- contact = "eluateam at eluaproject.net",
+-- copyright_name = "eLua Team",
+-- copyright_link = "http://www.eluaproject.net",
+ file_title = "wb",
+ start_open = "1",
+ logo_image_file = "eLuaLogo.png",
+ logo_onclick_link = ""
+}
+
+
+
+-- Page and Bar Titles
+wb_usr.messages =
+{
+ en =
+ {
+ title = "eLua Doc",
+ bar_title = "eLua - Embedded Lua"
+ },
+ pt =
+ {
+ title = "eLua Doc",
+ bar_title = "eLua - Embedded Lua"
+ }
+}
+
+
+
+-- Menu Tree Definition
+wb_usr.tree =
+{
+ name = { nl = "eLua" },
+ link = "news.html",
+ footer = [[
+ <p style="margin-left: 5px;"><a href="http://www.pax.com/free-counters.html"><img src="http://counter.pax.com/counter/image?counter=ctr-zsg80nnmqt" alt="Free Hit Counter" border="0" /></a></p>
+ ]],
+ folder =
+ {
+ { name = {en = "Overview", pt = "Apresentação" },
+ link = "overview.html",
+ folder =
+ {
+ { name = { en = "What is", pt = "O que é eLua ?" },
+ link = "overview.html#whatis",
+ },
+ {
+ name = { en = "Features", pt = "CaracterÃsticas" },
+ link = "overview.html#features",
+ },
+ { name = { en = "Audience", pt = "Público alvo" },
+ link = "overview.html#audience",
+ },
+--[[
+ { name = { en = "Uses", pt = "Aplicações" },
+ link = "overview.html#uses",
+ },
+--]]
+ { name = { en = "Authors", pt = "Autores" },
+ link = "overview.html#authors",
+ },
+ { name = { en = "Contacts", pt = "Contatos" },
+ link = "overview.html#contacts",
+ },
+ { name = { en = "License", pt = "Licença" },
+ link = "overview.html#license",
+ },
+ },
+ },
+
+ {
+ name = { en = "Downloads", pt = "Downloads" },
+ link = "downloads.html",
+ folder =
+ {
+ {
+ name = { en = "Binaries", pt = "Binaries" },
+ link = "downloads.html#binaries",
+ },
+ {
+ name = { en = "Source Code", pt = "Fontes" },
+ link = "downloads.html#source",
+ folder =
+ {
+ {
+ name = { en = "Official Releases", pt = "Versões Oficiais[B" },
+ link = "downloads.html#official"
+ },
+ {
+ name = { en = "SVN Public", pt = "SVN Público" },
+ link = "downloads.html#svnpublic"
+ },
+ {
+ name = { en = "Developers", pt = "Desenvolvedores" },
+ link = "downloads.html#svndev"
+ },
+ },
+ },
+ {
+ name = { en = "Old Versions", pt = "Versões Anteriores" },
+ link = "dl_old.html",
+ folder =
+ {
+ { name = { en = "0.4.1", pt = "0.4.1" },
+ link = "dl_old.html#v041"
+ },
+ { name = { en = "0.4", pt = "0.4" },
+ link = "dl_old.html#v04"
+ },
+ { name = { en = "0.3", pt = "0.3" },
+ link = "dl_old.html#v03"
+ },
+ { name = { en = "0.2", pt = "0.2" },
+ link = "dl_old.html#v02"
+ },
+ { name = { en = "0.1", pt = "0.1" },
+ link = "dl_old.html#v01"
+ },
+ },
+ },
+ },
+ },
+
+ {
+ name = {en = "Community", pt = "Comunidade" },
+ link = "comunity.html",
+ folder =
+ {
+ { name = { en = "Lists", pt = "Listas" },
+ link = "comunity.html#lists",
+ },
+ { name = { en = "Forums", pt = "Fórums" },
+ link = "comunity.html#forums",
+ },
+ { name = { en = "Credits", pt = "Créditos" },
+ link = "comunity.html#credits",
+ },
+--[[
+ { name = { en = "Galery", pt = "Galeria" },
+ link = "comunity.html#galery",
+ },
+ { name = { en = "Projects", pt = "Projetos" },
+ link = "comunity.html#projects",
+ },
+--]]
+ },
+ },
+ {
+ name = { en = "News", pt = "NotÃcias" },
+ link = "news.html",
+ },
+ {
+ name = {en = "Status", pt = "Status" },
+ link = "status.html",
+ folder =
+ {
+ { name = { en = "Platforms Supported", pt = "Plataformas Suportadas" },
+ link = "status.html#platforms",
+ },
+ { name = { en = "Roadmap", pt = "Futuro" },
+ link = "status.html#roadmap",
+ },
+ },
+ },
+
+ {
+ name = {en = "Version History", pt = "Histórico de Versões" },
+ link = "versionhistory.html",
+ },
+
+ {
+ name = { en = "", pt = "" }, -- Horizontal Separator
+ link = ""
+ },
+ {
+ name = { en = "Documentation", pt = "Documentação" },
+ link = "doc.html",
+ folder =
+ {
+ {
+ name = { en = "Building", pt = "Building" },
+ link = "building.html",
+ folder =
+ {
+ { name = { en = "Toolchains", pt = "Toolchains" },
+ link = "toolchains.html",
+ },
+ },
+ },
+ {
+ name = { en = "Installing", pt = "Instalando" },
+ link = "installing.html",
+ folder =
+ {
+ { name = { en = "AT91SAM7X", pt = "AT91SAM7X" },
+ link = "installing_at91sam7x.html",
+ },
+ { name = { en = "LM3S", pt = "LM3S" },
+ link = "installing_lm3s.html",
+ },
+ { name = { en = "AVR32", pt = "AVR32" },
+ link = "installing_avr32.html",
+ },
+ { name = { en = "LPC288x", pt = "LPC288x" },
+ link = "installing_lpc2888.html",
+ },
+ { name = { en = "STR7", pt = "STR7" },
+ link = "installing_str7.html",
+ },
+ { name = { en = "STR9", pt = "STR9" },
+ link = "installing_str9.html",
+ },
+ { name = { en = "STM32", pt = "STM32" },
+ link = "installing_stm32.html",
+ },
+ { name = { en = "i386", pt = "i386" },
+ link = "installing_i386.html"
+ },
+ },
+ },
+ {
+ name = { en = "Using", pt = "Usando" },
+ link = "using.html",
+ folder =
+ {
+ { name = { en = "Over UART", pt = "UART" },
+ link = "using.html#uart",
+ },
+ { name = { en = "Over TCP/IP", pt = "TCP/IP" },
+ link = "using.html#tcpip",
+ },
+ { name = { en = "On PC", pt = "no PC" },
+ link = "using.html#pc",
+ },
+ { name = { en = "The shell", pt = "O Shell" },
+ link = "using.html#shell",
+ },
+ { name = { en = "Cross-compiling", pt = "Cross Compiling" },
+ link = "using.html#cross",
+ },
+ },
+ },
+ {
+ name = { en = "FAQ", pt = "FAQ" },
+ link = "faq.html",
+ },
+ { name = { en = "Architecture", pt = "Arquitetura" },
+ link = "arch.html",
+ folder =
+ {
+ { name = { en = "Overview", pt = "Visão Geral" },
+ link = "arch_overview.html",
+ folder =
+ {
+ { name = { en = "Structure", pt = "Estrutura" },
+ link = "arch_overview.html#structure",
+ },
+ { name = { en = "Common code", pt = "Código base" },
+ link = "arch_overview.html#common",
+ },
+ { name = { en = "Platform interface", pt = "Plataformas" },
+ link = "arch_overview.html#platform",
+ },
+ { name = { en = "Platforms/ports", pt = "Plataformas" },
+ link = "arch_overview.html#platforms",
+ },
+ { name = { en = "Booting eLua", pt = "Bootando eLua" },
+ link = "arch_overview.html#boot",
+ },
+ },
+ },
+ { name = { en = "Platform interface", pt = "Módulos" },
+ link = "arch_platform.html",
+ folder = {
+ $$ARCH_PLATFORM$$
+ }
+ },
+ { name = { en = "ROM file system", pt = "ROM File System" },
+ link = "arch_romfs.html",
+ },
+ { name = { en = "Adding a new port", pt = "Adicionando um novo Port" },
+ link = "arch_newport.html",
+ },
+ { name = { en = "Modules and LTR", pt = "Módulos e LTR" },
+ link = "arch_ltr.html",
+ },
+ { name = { en = "Consoles and terminals", pt = "Consoles e Terminais"},
+ link = "arch_con_term.html",
+ },
+ { name = { en = "TCP/IP in eLua", pt = "TCP/IP em eLua" },
+ link = "arch_tcpip.html",
+ },
+ { name = { en = "eLua coding style", pt = "Estilo de Código" },
+ link = "arch_coding.html",
+ },
+ }
+ },
+ {
+ name = { en = "Examples", pt = "Exemplos" },
+ link = "examples.html",
+ },
+ },
+ },
+
+ {
+ name = { en = "Tutorials", pt = "Tutoriais" },
+ link = "tutorials.html",
+ folder =
+ {
+ { name = { en = "Booting on a PC", pt = "Booting on a PC" },
+ link = "tut_bootpc.html",
+ },
+ { name = { en = "Booting from a Pendrive", pt = "Booting from a Pendriv" },
+ link = "tut_bootstick.html",
+ },
+ { name = { en = "Toolchain Building", pt = "Toolchain Building" },
+ link = "tchainbuild.html",
+ folder =
+ {
+ { name = { en = "ARM7 & ARM9 Toolchains", pt = "ARM 7 & ARM9 Toolchains" },
+ link = "tc_arm.html",
+ },
+ { name = { en = "ARM Cortex-M3", pt = "ARM Cortex-M3" },
+ link = "tc_cortex.html",
+ },
+ { name = { en = "i386", pt = "i386" },
+ link = "tc_386.html",
+ },
+ },
+ },
+ { name = { en = "Using OpenOCD", pt = "Using OpenOC" },
+ link = "tut_openocd.html",
+ },
+ },
+ },
+
+
+ {
+ name = { en = "Reference Manual", pt = "Manual de Referência" },
+ link = "refman.html",
+ folder =
+ {
+ {
+ name = { en = "Generic Modules", pt = "Módulos Genéricos" },
+ link = "refman_gen.html",
+ folder = {
+ $$REFMAN_GEN$$
+ },
+ },
+ {
+ name = {en = "Platform Dependent Modules", pt = "Dependentes de Plataforma" },
+ link = "refman.html#platdepmodules",
+ folder =
+ {
+ { name = { en = "adc", pt = "adc" },
+ link = "refman.html#adcmodule",
+ folder =
+ {
+ {
+ name ={ en = "sample", pt = "sample" },
+ link = "refman.html#adc_sample"
+ },
+ {
+ name ={ en = "getsamples", pt = "getsamples" },
+ link = "refman.html#adc_getsamples"
+ },
+ {
+ name = { en = "maxval", pt = "maxval" },
+ link = "refman.html#adc_maxval"
+ },
+ {
+ name = { en = "samplesready", pt = "samplesready" },
+ link = "refman.html#adc_samplesready"
+ },
+ {
+ name = { en = "dataready", pt = "dataready" },
+ link = "refman.html#adc_dataready"
+ },
+ {
+ name = { en = "setmode", pt = "setmode" },
+ link = "refman.html#adc_setmode"
+ },
+ {
+ name = { en = "setsmoothing", pt = "setsmoothing" },
+ link = "refman.html#adc_setsmoothing"
+ },
+ {
+ name = { en = "getsmoothing", pt = "getsmoothing" },
+ link = "refman.html#adc_getsmoothing"
+ },
+ {
+ name = { en = "burst", pt = "burst" },
+ link = "refman.html#adc_burst"
+ },
+ },
+ },
+ { name = { en = "disp", pt = "disp" },
+ link = "refman.html#dispmodule",
+ folder =
+ {
+ {
+ name ={ en = "init", pt = "init" },
+ link = "refman.html#disp_init"
+ },
+ {
+ name = { en = "enable", pt = "enable" },
+ link = "refman.html#disp_enable"
+ },
+ {
+ name = { en = "disable", pt = "disable" },
+ link = "refman.html#disp_disable"
+ },
+ {
+ name = { en = "on", pt = "on" },
+ link = "refman.html#disp_on"
+ },
+ {
+ name = { en = "off", pt = "off" },
+ link = "refman.html#disp_off"
+ },
+ {
+ name = { en = "clear", pt = "clear" },
+ link = "refman.html#disp_clear"
+ },
+ {
+ name = { en = "print", pt = "print" },
+ link = "refman.html#disp_print"
+ },
+ {
+ name = { en = "draw", pt = "draw" },
+ link = "refman.html#disp_draw"
+ },
+ },
+ },
+ },
+ },
+ },
+ },
+ },
+}
Property changes on: branches/eagle_mmc/doc/wb/wb_usr_template.lua
___________________________________________________________________
Name: svn:executable
+ *
Deleted: branches/eagle_mmc/doc/wb_bar_en.html
===================================================================
--- branches/eagle_mmc/doc/wb_bar_en.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_bar_en.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,29 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
- <title>Bar</title>
- <base target="wb_cont">
- <style type="text/css">
- .navigation{
- padding: 0;
- margin: 0;
- white-space: nowrap;
- border: 1px solid #7F93C7;
- background-color: #FFFFFF;
- line-height: 19px;
- }
- .navigation p { margin: 1px; white-space: nowrap; }
- .navigation img { vertical-align: middle; }
- </style>
-</head>
-
-<body style="margin: 2px; background-color: #F1F1F1">
- <div class="navigation">
- <p><a target="_blank" href="http://www.eluaproject.net"><img src="wb_img/logo.png" style="border-width: 0px"></a>
- <img src="wb_img/barlineleft.png"><img alt="Expand All Nodes" src="wb_img/showall.png" onclick="parent.wb_tree.showAllFolders()" onmouseover="this.src='wb_img/showall_over.png'" onmouseout="this.src='wb_img/showall.png'"><img alt="Contract All Nodes" src="wb_img/hideall.png" onclick="parent.wb_tree.hideAllFolders()" onmouseover="this.src='wb_img/hideall_over.png'" onmouseout="this.src='wb_img/hideall.png'"><img alt="Sync Tree with Contents" src="wb_img/sync.png" onclick="parent.wb_tree.syncContents()" onmouseover="this.src='wb_img/sync_over.png'" onmouseout="this.src='wb_img/sync.png'"><img alt="Next Link" src="wb_img/next.png" onclick="parent.wb_tree.nextContents()" onmouseover="this.src='wb_img/next_over.png'" onmouseout="this.src='wb_img/next.png'"><img alt="Previous Link" src="wb_img/previous.png" onclick="parent.wb_tree.prevContents()" onmouseover="this.src='wb_img/previous_over.png'" onmouseout="this.src='wb_img/previous.png'"><img src="wb_img/barlineright.png"><a t!
arget="_top" href="index_pt.html"><img alt="Switch Language" src="wb_img/lng_en.png" onmouseover="this.src='wb_img/lng_en_over.png'" onmouseout="this.src='wb_img/lng_en.png'" style="border-width: 0px"></a>
-
- </p>
- </div>
-</body>
-</html>
Deleted: branches/eagle_mmc/doc/wb_bar_pt.html
===================================================================
--- branches/eagle_mmc/doc/wb_bar_pt.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_bar_pt.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,29 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Strict//EN">
-<html>
-<head>
-<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
- <title>Bar</title>
- <base target="wb_cont">
- <style type="text/css">
- .navigation{
- padding: 0;
- margin: 0;
- white-space: nowrap;
- border: 1px solid #7F93C7;
- background-color: #FFFFFF;
- line-height: 19px;
- }
- .navigation p { margin: 1px; white-space: nowrap; }
- .navigation img { vertical-align: middle; }
- </style>
-</head>
-
-<body style="margin: 2px; background-color: #F1F1F1">
- <div class="navigation">
- <p><a target="_blank" href="http://www.eluaproject.net"><img src="wb_img/logo.png" style="border-width: 0px"></a>
- <img src="wb_img/barlineleft.png"><img alt="Expande Todos os Nós" src="wb_img/showall.png" onclick="parent.wb_tree.showAllFolders()" onmouseover="this.src='wb_img/showall_over.png'" onmouseout="this.src='wb_img/showall.png'"><img alt="Contrai Todos os Nós" src="wb_img/hideall.png" onclick="parent.wb_tree.hideAllFolders()" onmouseover="this.src='wb_img/hideall_over.png'" onmouseout="this.src='wb_img/hideall.png'"><img alt="Sincroniza Ãrvore com Conteúdo" src="wb_img/sync.png" onclick="parent.wb_tree.syncContents()" onmouseover="this.src='wb_img/sync_over.png'" onmouseout="this.src='wb_img/sync.png'"><img alt="Próximo Link" src="wb_img/next.png" onclick="parent.wb_tree.nextContents()" onmouseover="this.src='wb_img/next_over.png'" onmouseout="this.src='wb_img/next.png'"><img alt="Link Anterior" src="wb_img/previous.png" onclick="parent.wb_tree.prevContents()" onmouseover="this.src='wb_img/previous_over.png'" onmouseout="this.src='wb_img/previous.png'"><img src="wb_img/b!
arlineright.png"><a target="_top" href="index_en.html"><img alt="Troca Idioma" src="wb_img/lng_pt.png" onmouseover="this.src='wb_img/lng_pt_over.png'" onmouseout="this.src='wb_img/lng_pt.png'" style="border-width: 0px"></a>
-
- </p>
- </div>
-</body>
-</html>
Deleted: branches/eagle_mmc/doc/wb_img/Thumbs.db
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/doc/wb_img/eLua-logo-80x80.png
===================================================================
(Binary files differ)
Added: branches/eagle_mmc/doc/wb_img/eLuaLogo.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/eLuaLogo.png 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_img/eLuaLogo.png 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,37 @@
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Added: branches/eagle_mmc/doc/wb_img/elua_arch.png
===================================================================
--- branches/eagle_mmc/doc/wb_img/elua_arch.png 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_img/elua_arch.png 2009-07-30 18:10:13 UTC (rev 371)
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Added: branches/eagle_mmc/doc/wb_img/stat_ok.png
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--- branches/eagle_mmc/doc/wb_search_en.txt 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_search_en.txt 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,26 +0,0 @@
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Deleted: branches/eagle_mmc/doc/wb_search_pt.txt
===================================================================
--- branches/eagle_mmc/doc/wb_search_pt.txt 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_search_pt.txt 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,26 +0,0 @@
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Deleted: branches/eagle_mmc/doc/wb_title_en.html
===================================================================
--- branches/eagle_mmc/doc/wb_title_en.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_title_en.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,69 +0,0 @@
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===================================================================
--- branches/eagle_mmc/doc/wb_title_pt.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_title_pt.html 2009-07-30 18:10:13 UTC (rev 371)
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Deleted: branches/eagle_mmc/doc/wb_tree_en.html
===================================================================
--- branches/eagle_mmc/doc/wb_tree_en.html 2009-07-30 13:04:10 UTC (rev 370)
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link21folder.4.1" href="en/examples.html#led">led.lua</a></p>
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- <div id="folder.4.2.1">
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link51folder.5.1.1" href="en/refman.html#bit_set">set</a></p>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link64folder.5.1.2" href="en/refman.html#cpu_clockfrequency">clockfrequency</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.3" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.3')"><a name="link65folder.5.1.3" class="el" href="en/refman.html#gpiomodule">gpio</a></p>
- <div id="folder.5.1.3">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link66folder.5.1.3" href="en/refman.html#gpio_configpin">configpin</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link67folder.5.1.3" href="en/refman.html#gpio_setpinvalue">setpinvalue</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link68folder.5.1.3" href="en/refman.html#gpio_getpinvalue">getpinvalue</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link69folder.5.1.3" href="en/refman.html#gpio_setpinhigh">setpinhigh</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link70folder.5.1.3" href="en/refman.html#gpio_setpinlow">setpinlow</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.4" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.4')"><a name="link71folder.5.1.4" class="el" href="en/refman.html#netmodule">net</a></p>
- <div id="folder.5.1.4">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link72folder.5.1.4" href="en/net_ref.html#net_setup">to be added ...</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.5" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.5')"><a name="link73folder.5.1.5" class="el" href="en/refman.html#pwmmodule">pwm</a></p>
- <div id="folder.5.1.5">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link74folder.5.1.5" href="en/refman.html#pwm_setup">setup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link75folder.5.1.5" href="en/refman.html#pwm_setcycle">setcycle</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link76folder.5.1.5" href="en/refman.html#pwm_start">start</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link77folder.5.1.5" href="en/refman.html#pwm_stop">stop</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link78folder.5.1.5" href="en/refman.html#pwm_setclock">setclock</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link79folder.5.1.5" href="en/refman.html#pwm_getclock">getclock</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.6" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.6')"><a name="link80folder.5.1.6" class="el" href="en/refman.html#spimodules">spi</a></p>
- <div id="folder.5.1.6">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link81folder.5.1.6" href="en/refman.html#spi_setup">setup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link82folder.5.1.6" href="en/refman.html#spi_select">select</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link83folder.5.1.6" href="en/refman.html#spi_unselect">unselect</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link84folder.5.1.6" href="en/refman.html#spi_send">send</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link85folder.5.1.6" href="en/refman.html#spi_sendrecv">sendrecv</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.7" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.7')"><a name="link86folder.5.1.7" class="el" href="en/refman.html#sysmodule">sys</a></p>
- <div id="folder.5.1.7">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link87folder.5.1.7" href="en/refman.html#sys_platforms">platform</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link88folder.5.1.7" href="en/refman.html#sys_mcu">mcu</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link89folder.5.1.7" href="en/refman.html#sys_cpu">cpu</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link90folder.5.1.7" href="en/refman.html#sys_board">board</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.8" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.8')"><a name="link91folder.5.1.8" class="el" href="en/refman.html#termmodule">term</a></p>
- <div id="folder.5.1.8">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link92folder.5.1.8" href="en/refman.html#term_clear">clear</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link93folder.5.1.8" href="en/refman.html#term_cleareol">cleareol</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link94folder.5.1.8" href="en/refman.html#term_moveto">moveto</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link95folder.5.1.8" href="en/refman.html#term_moveup">moveup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link96folder.5.1.8" href="en/refman.html#term_movedown">movedown</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link97folder.5.1.8" href="en/refman.html#term_moveleft">moveleft</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link98folder.5.1.8" href="en/refman.html#term_moveright">moveright</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link99folder.5.1.8" href="en/refman.html#term_getlinecount">getlinecount</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link100folder.5.1.8" href="en/refman.html#term_getcolcount">getcolcount</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link101folder.5.1.8" href="en/refman.html#term_printstr">printstr</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link102folder.5.1.8" href="en/refman.html#term_getx">getx</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link103folder.5.1.8" href="en/refman.html#term_gety">gety</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link104folder.5.1.8" href="en/refman.html#term_inputchar">inputchar</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.9" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.9')"><a name="link105folder.5.1.9" class="el" href="en/refman.html#tmrmodule">tmr</a></p>
- <div id="folder.5.1.9">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link106folder.5.1.9" href="en/refman.html#tmr_delay">delay</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link107folder.5.1.9" href="en/refman.html#tmr_read">read</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link108folder.5.1.9" href="en/refman.html#tmr_start">start</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link109folder.5.1.9" href="en/refman.html#tmr_diff">diff</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link110folder.5.1.9" href="en/refman.html#tmr_mindelay">mindelay</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link111folder.5.1.9" href="en/refman.html#tmr_maxdelay">maxdelay</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link112folder.5.1.9" href="en/refman.html#tmr_setclock">setclock</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.10" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.5.1.10')"><a name="link113folder.5.1.10" class="el" href="en/refman.html#uartmodule">uart</a></p>
- <div id="folder.5.1.10">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link114folder.5.1.10" href="en/refman.html#uart_setup">setup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link115folder.5.1.10" href="en/refman.html#uart_send">send</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link116folder.5.1.10" href="en/refman.html#uart_recv">recv</a></p>
- </div>
- </div>
- <p><img src="wb_img/vertline.png"><img name="imgfolder.5.2" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.5.2')"><a name="link117folder.5.2" class="el" href="en/platdepmodules.html">Platform Dependent Modules</a></p>
- <div id="folder.5.2">
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img name="imgfolder.5.2.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.2.1')"><a name="link118folder.5.2.1" class="el" href="en/refman.html#adcmodule">adc</a></p>
- <div id="folder.5.2.1">
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link119folder.5.2.1" href="en/refman.html#adc_sample">sample</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link120folder.5.2.1" href="en/refman.html#adc_getsamples">getsamples</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link121folder.5.2.1" href="en/refman.html#adc_maxval">maxval</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link122folder.5.2.1" href="en/refman.html#adc_samplesready">samplesready</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link123folder.5.2.1" href="en/refman.html#adc_dataready">dataready</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link124folder.5.2.1" href="en/refman.html#adc_setmode">setmode</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link125folder.5.2.1" href="en/refman.html#adc_setsmoothing">setsmoothing</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link126folder.5.2.1" href="en/refman.html#adc_getsmoothing">getsmoothing</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link127folder.5.2.1" href="en/refman.html#adc_burst">burst</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img name="imgfolder.5.2.2" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.5.2.2')"><a name="link128folder.5.2.2" class="el" href="en/refman.html#dispmodule">disp</a></p>
- <div id="folder.5.2.2">
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link129folder.5.2.2" href="en/refman.html#disp_init">init</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link130folder.5.2.2" href="en/refman.html#disp_enable">enable</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link131folder.5.2.2" href="en/refman.html#disp_disable">disable</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link132folder.5.2.2" href="en/refman.html#disp_on">on</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link133folder.5.2.2" href="en/refman.html#disp_off">off</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link134folder.5.2.2" href="en/refman.html#disp_print">print</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link135folder.5.2.2" href="en/refman.html#disp_draw">draw</a></p>
- </div>
- </div>
- </div>
- <p><img name="imgfolder.6" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.6')"><a name="link136folder.6" class="el" href="en/downloads.html">Downloads</a></p>
- <div id="folder.6">
- <p><img src="wb_img/blank.png"><img name="imgfolder.6.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.6.1')"><a name="link137folder.6.1" class="el" href="en/dl_binaries.html">Binaries</a></p>
- <div id="folder.6.1">
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link138folder.6.1" href="en/lm_bin.html">Atmel</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link139folder.6.1" href="en/lm_bin.html">Luminary Micro</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link140folder.6.1" href="en/lm_bin.html">PC i386</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link141folder.6.1" href="en/lm_bin.html">Phillips</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link142folder.6.1" href="en/lm_bin.html">ST Micro</a></p>
- </div>
- <p><img src="wb_img/blank.png"><img name="imgfolder.6.2" src="wb_img/plusnode.png" onclick="toggleFolder('folder.6.2')"><a name="link143folder.6.2" class="el" href="en/sources.html">Source Code</a></p>
- <div id="folder.6.2">
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link144folder.6.2" href="en/sources.html#06">v0.6</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link145folder.6.2" href="en/sources.html#trunk">trunk</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img name="imgfolder.6.2.1" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.6.2.1')"><a name="link146folder.6.2.1" class="el" href="en/oldversions.html">old versions</a></p>
- <div id="folder.6.2.1">
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link147folder.6.2.1" href="en/oldversions.html#05">v0.5</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link148folder.6.2.1" href="en/sources.html#04">v0.4</a></p>
- </div>
- </div>
- <p><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link149folder.6" href="en/developers.html">Developers</a></p>
- </div>
- </div>
-</body>
-</html>
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--- branches/eagle_mmc/doc/wb_tree_pt.html 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/doc/wb_tree_pt.html 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,427 +0,0 @@
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- <h3><a name="link0folder.0" class="el" href="pt/news.html">eLua</a></h3>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link164folder.4" href="pt/faq.html">FAQ</a></p>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link166folder.4" href="pt/building.html">Building</a></p>
- <p><img src="wb_img/vertline.png"><img name="imgfolder.4.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.4.1')"><a name="link167folder.4.1" class="el" href="pt/examples.html">Exemplos</a></p>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link168folder.4.1" href="pt/examples.html#hello">hello.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link169folder.4.1" href="pt/examples.html#info">info.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link170folder.4.1" href="pt/examples.html#led">led.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link171folder.4.1" href="pt/examples.html#hangman">hangman.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link172folder.4.1" href="pt/examples.html#pwmled">pwmled.lua</a></p>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link174folder.4.1" href="pt/examples.html#piano">piano.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link175folder.4.1" href="pt/examples.html#bisect">bisect.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link176folder.4.1" href="pt/examples.html#morse">morse.lua</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link177folder.4.1" href="pt/examples.html#lhttpd">lhttpd.lua</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img name="imgfolder.4.2" src="wb_img/plusnode.png" onclick="toggleFolder('folder.4.2')"><a name="link178folder.4.2" class="el" href="pt/tutorials.html">Tutoriais</a></p>
- <div id="folder.4.2">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link179folder.4.2" href="pt/tut_bootpc.html">Booting on a PC</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link180folder.4.2" href="pt/tut_bootstick.html">Booting from a Pendriv</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.4.2.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.4.2.1')"><a name="link181folder.4.2.1" class="el" href="pt/tchainbuild.html">Toolchain Building</a></p>
- <div id="folder.4.2.1">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link182folder.4.2.1" href="pt/tc_arm.html">ARM 7 & ARM9 Toolchains</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link183folder.4.2.1" href="pt/tc_cortex.html">ARM Cortex-M3</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link184folder.4.2.1" href="pt/tc_386.html">i386</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link185folder.4.2" href="pt/tut_openocd.html">Using OpenOC</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img name="imgfolder.4.3" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.4.3')"><a name="link186folder.4.3" class="el" href="pt/versionhistory.html">Histórico de Versões</a></p>
- <div id="folder.4.3">
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- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link188folder.4.3" href="pt/versionhistory.html#05">v 0.5</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link189folder.4.3" href="pt/versionhistory.html#06">v 0.6</a></p>
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- <p><img name="imgfolder.5" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5')"><a name="link190folder.5" class="el" href="pt/refman.html#genericmodules">Manual de Referência</a></p>
- <div id="folder.5">
- <p><img src="wb_img/vertline.png"><img name="imgfolder.5.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1')"><a name="link191folder.5.1" class="el" href="pt/refman.html#genericmodules">Módulos Genéricos</a></p>
- <div id="folder.5.1">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.1')"><a name="link192folder.5.1.1" class="el" href="pt/refman.html#bitmodule">bit</a></p>
- <div id="folder.5.1.1">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link193folder.5.1.1" href="pt/refman.html#bit_bnot">bnot</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link194folder.5.1.1" href="pt/refman.html#bit_band">band</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link195folder.5.1.1" href="pt/refman.html#bit_bor">bor</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link196folder.5.1.1" href="pt/refman.html#bit_bxor">bxor</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link197folder.5.1.1" href="pt/refman.html#bit_lshift">lshift</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link198folder.5.1.1" href="pt/refman.html#bit_rshift">rshift</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link199folder.5.1.1" href="pt/refman.html#bit_bit">bit</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link200folder.5.1.1" href="pt/refman.html#bit_set">set</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link201folder.5.1.1" href="pt/refman.html#bit_clear">clear</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link202folder.5.1.1" href="pt/refman.html#bit_isset">isset</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link203folder.5.1.1" href="pt/refman.html#bit_isclear">isclear</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.2" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.2')"><a name="link204folder.5.1.2" class="el" href="pt/refman.html#cpumodule">cpu</a></p>
- <div id="folder.5.1.2">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link205folder.5.1.2" href="pt/refman.html#cpu_write32">write32</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link206folder.5.1.2" href="pt/refman.html#cpu_write16">write16</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link207folder.5.1.2" href="pt/refman.html#cpu_write8">write8</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link208folder.5.1.2" href="pt/refman.html#cpu_read32">read32</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link209folder.5.1.2" href="pt/refman.html#cpu_read16">read16</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link210folder.5.1.2" href="pt/refman.html#cpu_read8">read8</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link211folder.5.1.2" href="pt/refman.html#cpu_disableinterrupts">disableinterrupts</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link212folder.5.1.2" href="pt/refman.html#cpu_enableinterrupts">enableinterrupts</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link213folder.5.1.2" href="pt/refman.html#cpu_clockfrequency">clockfrequency</a></p>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.3" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.3')"><a name="link214folder.5.1.3" class="el" href="pt/refman.html#gpiomodule">gpio</a></p>
- <div id="folder.5.1.3">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link215folder.5.1.3" href="pt/refman.html#gpio_configpin">configpin</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link216folder.5.1.3" href="pt/refman.html#gpio_setpinvalue">setpinvalue</a></p>
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- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link218folder.5.1.3" href="pt/refman.html#gpio_setpinhigh">setpinhigh</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link219folder.5.1.3" href="pt/refman.html#gpio_setpinlow">setpinlow</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.4" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.4')"><a name="link220folder.5.1.4" class="el" href="pt/refman.html#netmodule">net</a></p>
- <div id="folder.5.1.4">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link221folder.5.1.4" href="pt/net_ref.html#net_setup">setup</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.5" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.5')"><a name="link222folder.5.1.5" class="el" href="pt/refman.html#pwmmodule">pwm</a></p>
- <div id="folder.5.1.5">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link223folder.5.1.5" href="pt/refman.html#pwm_setup">setup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link224folder.5.1.5" href="pt/refman.html#pwm_setcycle">setcycle</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link225folder.5.1.5" href="pt/refman.html#pwm_start">start</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link226folder.5.1.5" href="pt/refman.html#pwm_stop">stop</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link227folder.5.1.5" href="pt/refman.html#pwm_setclock">setclock</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link228folder.5.1.5" href="pt/refman.html#pwm_getclock">getclock</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.6" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.6')"><a name="link229folder.5.1.6" class="el" href="pt/refman.html#spimodules">spi</a></p>
- <div id="folder.5.1.6">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link230folder.5.1.6" href="pt/refman.html#spi_setup">setup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link231folder.5.1.6" href="pt/refman.html#spi_select">select</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link232folder.5.1.6" href="pt/refman.html#spi_unselect">unselect</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link233folder.5.1.6" href="pt/refman.html#spi_send">send</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link234folder.5.1.6" href="pt/refman.html#spi_sendrecv">sendrecv</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.7" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.7')"><a name="link235folder.5.1.7" class="el" href="pt/refman.html#sysmodule">sys</a></p>
- <div id="folder.5.1.7">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link236folder.5.1.7" href="pt/refman.html#sys_platforms">platform</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link237folder.5.1.7" href="pt/refman.html#sys_mcu">mcu</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link238folder.5.1.7" href="pt/refman.html#sys_cpu">cpu</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link239folder.5.1.7" href="pt/refman.html#sys_board">board</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.8" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.8')"><a name="link240folder.5.1.8" class="el" href="pt/refman.html#termmodule">term</a></p>
- <div id="folder.5.1.8">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link241folder.5.1.8" href="pt/refman.html#term_clear">clear</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link242folder.5.1.8" href="pt/refman.html#term_cleareol">cleareol</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link243folder.5.1.8" href="pt/refman.html#term_moveto">moveto</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link244folder.5.1.8" href="pt/refman.html#term_moveup">moveup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link245folder.5.1.8" href="pt/refman.html#term_movedown">movedown</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link246folder.5.1.8" href="pt/refman.html#term_moveleft">moveleft</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link247folder.5.1.8" href="pt/refman.html#term_moveright">moveright</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link248folder.5.1.8" href="pt/refman.html#term_getlinecount">getlinecount</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link249folder.5.1.8" href="pt/refman.html#term_getcolcount">getcolcount</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link250folder.5.1.8" href="pt/refman.html#term_printstr">printstr</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link251folder.5.1.8" href="pt/refman.html#term_getx">getx</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link252folder.5.1.8" href="pt/refman.html#term_gety">gety</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link253folder.5.1.8" href="pt/refman.html#term_inputchar">inputchar</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.9" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.1.9')"><a name="link254folder.5.1.9" class="el" href="pt/refman.html#tmrmodule">tmr</a></p>
- <div id="folder.5.1.9">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link255folder.5.1.9" href="pt/refman.html#tmr_delay">delay</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link256folder.5.1.9" href="pt/refman.html#tmr_read">read</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link257folder.5.1.9" href="pt/refman.html#tmr_start">start</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link258folder.5.1.9" href="pt/refman.html#tmr_diff">diff</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link259folder.5.1.9" href="pt/refman.html#tmr_mindelay">mindelay</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link260folder.5.1.9" href="pt/refman.html#tmr_maxdelay">maxdelay</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link261folder.5.1.9" href="pt/refman.html#tmr_setclock">setclock</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img name="imgfolder.5.1.10" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.5.1.10')"><a name="link262folder.5.1.10" class="el" href="pt/refman.html#uartmodule">uart</a></p>
- <div id="folder.5.1.10">
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link263folder.5.1.10" href="pt/refman.html#uart_setup">setup</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link264folder.5.1.10" href="pt/refman.html#uart_send">send</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link265folder.5.1.10" href="pt/refman.html#uart_recv">recv</a></p>
- </div>
- </div>
- <p><img src="wb_img/vertline.png"><img name="imgfolder.5.2" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.5.2')"><a name="link266folder.5.2" class="el" href="pt/platdepmodules.html">Dependentes de Plataforma</a></p>
- <div id="folder.5.2">
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img name="imgfolder.5.2.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.5.2.1')"><a name="link267folder.5.2.1" class="el" href="pt/refman.html#adcmodule">adc</a></p>
- <div id="folder.5.2.1">
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link268folder.5.2.1" href="pt/refman.html#adc_sample">sample</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link269folder.5.2.1" href="pt/refman.html#adc_getsamples">getsamples</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link270folder.5.2.1" href="pt/refman.html#adc_maxval">maxval</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link271folder.5.2.1" href="pt/refman.html#adc_samplesready">samplesready</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link272folder.5.2.1" href="pt/refman.html#adc_dataready">dataready</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link273folder.5.2.1" href="pt/refman.html#adc_setmode">setmode</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link274folder.5.2.1" href="pt/refman.html#adc_setsmoothing">setsmoothing</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link275folder.5.2.1" href="pt/refman.html#adc_getsmoothing">getsmoothing</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link276folder.5.2.1" href="pt/refman.html#adc_burst">burst</a></p>
- </div>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img name="imgfolder.5.2.2" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.5.2.2')"><a name="link277folder.5.2.2" class="el" href="pt/refman.html#dispmodule">disp</a></p>
- <div id="folder.5.2.2">
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link278folder.5.2.2" href="pt/refman.html#disp_init">init</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link279folder.5.2.2" href="pt/refman.html#disp_enable">enable</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link280folder.5.2.2" href="pt/refman.html#disp_disable">disable</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link281folder.5.2.2" href="pt/refman.html#disp_on">on</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link282folder.5.2.2" href="pt/refman.html#disp_off">off</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link283folder.5.2.2" href="pt/refman.html#disp_print">print</a></p>
- <p><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link284folder.5.2.2" href="pt/refman.html#disp_draw">draw</a></p>
- </div>
- </div>
- </div>
- <p><img name="imgfolder.6" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.6')"><a name="link285folder.6" class="el" href="pt/downloads.html">Downloads</a></p>
- <div id="folder.6">
- <p><img src="wb_img/blank.png"><img name="imgfolder.6.1" src="wb_img/plusnode.png" onclick="toggleFolder('folder.6.1')"><a name="link286folder.6.1" class="el" href="pt/dl_binaries.html">Binaries</a></p>
- <div id="folder.6.1">
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link287folder.6.1" href="pt/lm_bin.html">Atmel</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link288folder.6.1" href="pt/lm_bin.html">Luminary Micro</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link289folder.6.1" href="pt/lm_bin.html">PC i386</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link290folder.6.1" href="pt/lm_bin.html">Phillips</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/nodelast.png"><a class="el" name="link291folder.6.1" href="pt/lm_bin.html">ST Micro</a></p>
- </div>
- <p><img src="wb_img/blank.png"><img name="imgfolder.6.2" src="wb_img/plusnode.png" onclick="toggleFolder('folder.6.2')"><a name="link292folder.6.2" class="el" href="pt/sources.html">Fontes</a></p>
- <div id="folder.6.2">
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link293folder.6.2" href="pt/sources.html#06">v0.6</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/node.png"><a class="el" name="link294folder.6.2" href="pt/sources.html#trunk">trunk</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img name="imgfolder.6.2.1" src="wb_img/plusnodelast.png" onclick="toggleFolder('folder.6.2.1')"><a name="link295folder.6.2.1" class="el" href="pt/oldversions.html">anteriores</a></p>
- <div id="folder.6.2.1">
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/node.png"><a class="el" name="link296folder.6.2.1" href="pt/oldversions.html#05">v0.5</a></p>
- <p><img src="wb_img/blank.png"><img src="wb_img/vertline.png"><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link297folder.6.2.1" href="pt/sources.html#04">v0.4</a></p>
- </div>
- </div>
- <p><img src="wb_img/blank.png"><img src="wb_img/nodelast.png"><a class="el" name="link298folder.6" href="pt/developers.html">Desenvolvedores</a></p>
- </div>
- </div>
-</body>
-</html>
Deleted: branches/eagle_mmc/docs/eLua_Manual.odt
===================================================================
(Binary files differ)
Deleted: branches/eagle_mmc/docs/eLua_Manual.pdf
===================================================================
(Binary files differ)
Added: branches/eagle_mmc/inc/cexcept.h
===================================================================
--- branches/eagle_mmc/inc/cexcept.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/cexcept.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,248 @@
+/*===
+cexcept.h 2.0.1 (2008-Jul-19-Sat)
+http://www.nicemice.net/cexcept/
+Adam M. Costello
+http://www.nicemice.net/amc/
+
+An interface for exception-handling in ANSI C (C89 and subsequent ISO
+standards), developed jointly with Cosmin Truta.
+
+ Copyright (c) 2000-2008 Adam M. Costello and Cosmin Truta.
+ This software may be modified only if its author and version
+ information is updated accurately, and may be redistributed
+ only if accompanied by this unaltered notice. Subject to those
+ restrictions, permission is granted to anyone to do anything
+ with this software. The copyright holders make no guarantees
+ regarding this software, and are not responsible for any damage
+ resulting from its use.
+
+The cexcept interface is not compatible with and cannot interact
+with system exceptions (like division by zero or memory segmentation
+violation), compiler-generated exceptions (like C++ exceptions), or
+other exception-handling interfaces.
+
+When using this interface across multiple .c files, do not include
+this header file directly. Instead, create a wrapper header file that
+includes this header file and then invokes the define_exception_type
+macro (see below). The .c files should then include that header file.
+
+The interface consists of one type, one well-known name, and six macros.
+
+
+define_exception_type(type_name);
+
+ This macro is used like an external declaration. It specifies
+ the type of object that gets copied from the exception thrower to
+ the exception catcher. The type_name can be any type that can be
+ assigned to, that is, a non-constant arithmetic type, struct, union,
+ or pointer. Examples:
+
+ define_exception_type(int);
+
+ enum exception { out_of_memory, bad_arguments, disk_full };
+ define_exception_type(enum exception);
+
+ struct exception { int code; const char *msg; };
+ define_exception_type(struct exception);
+
+ Because throwing an exception causes the object to be copied (not
+ just once, but twice), programmers may wish to consider size when
+ choosing the exception type.
+
+
+struct exception_context;
+
+ This type may be used after the define_exception_type() macro has
+ been invoked. A struct exception_context must be known to both
+ the thrower and the catcher. It is expected that there be one
+ context for each thread that uses exceptions. It would certainly
+ be dangerous for multiple threads to access the same context.
+ One thread can use multiple contexts, but that is likely to be
+ confusing and not typically useful. The application can allocate
+ this structure in any way it pleases--automatic, static, or dynamic.
+ The application programmer should pretend not to know the structure
+ members, which are subject to change.
+
+
+struct exception_context *the_exception_context;
+
+ The Try/Catch and Throw statements (described below) implicitly
+ refer to a context, using the name the_exception_context. It is
+ the application's responsibility to make sure that this name yields
+ the address of a mutable (non-constant) struct exception_context
+ wherever those statements are used. Subject to that constraint, the
+ application may declare a variable of this name anywhere it likes
+ (inside a function, in a parameter list, or externally), and may
+ use whatever storage class specifiers (static, extern, etc) or type
+ qualifiers (const, volatile, etc) it likes. Examples:
+
+ static struct exception_context
+ * const the_exception_context = &foo;
+
+ { struct exception_context *the_exception_context = bar; ... }
+
+ int blah(struct exception_context *the_exception_context, ...);
+
+ extern struct exception_context the_exception_context[1];
+
+ The last example illustrates a trick that avoids creating a pointer
+ object separate from the structure object.
+
+ The name could even be a macro, for example:
+
+ struct exception_context ec_array[numthreads];
+ #define the_exception_context (ec_array + thread_id)
+
+ Be aware that the_exception_context is used several times by the
+ Try/Catch/Throw macros, so it shouldn't be expensive or have side
+ effects. The expansion must be a drop-in replacement for an
+ identifier, so it's safest to put parentheses around it.
+
+
+void init_exception_context(struct exception_context *ec);
+
+ For context structures allocated statically (by an external
+ definition or using the "static" keyword), the implicit
+ initialization to all zeros is sufficient, but contexts allocated
+ by other means must be initialized using this macro before they
+ are used by a Try/Catch statement. It does no harm to initialize
+ a context more than once (by using this macro on a statically
+ allocated context, or using this macro twice on the same context),
+ but a context must not be re-initialized after it has been used by a
+ Try/Catch statement.
+
+
+Try statement
+Catch (expression) statement
+
+ The Try/Catch/Throw macros are capitalized in order to avoid
+ confusion with the C++ keywords, which have subtly different
+ semantics.
+
+ A Try/Catch statement has a syntax similar to an if/else statement,
+ except that the parenthesized expression goes after the second
+ keyword rather than the first. As with if/else, there are two
+ clauses, each of which may be a simple statement ending with a
+ semicolon or a brace-enclosed compound statement. But whereas
+ the else clause is optional, the Catch clause is required. The
+ expression must be a modifiable lvalue (something capable of being
+ assigned to) of the same type (disregarding type qualifiers) that
+ was passed to define_exception_type().
+
+ If a Throw that uses the same exception context as the Try/Catch is
+ executed within the Try clause (typically within a function called
+ by the Try clause), and the exception is not caught by a nested
+ Try/Catch statement, then a copy of the exception will be assigned
+ to the expression, and control will jump to the Catch clause. If no
+ such Throw is executed, then the assignment is not performed, and
+ the Catch clause is not executed.
+
+ The expression is not evaluated unless and until the exception is
+ caught, which is significant if it has side effects, for example:
+
+ Try foo();
+ Catch (p[++i].e) { ... }
+
+ IMPORTANT: Jumping into or out of a Try clause (for example via
+ return, break, continue, goto, longjmp) is forbidden--the compiler
+ will not complain, but bad things will happen at run-time. Jumping
+ into or out of a Catch clause is okay, and so is jumping around
+ inside a Try clause. In many cases where one is tempted to return
+ from a Try clause, it will suffice to use Throw, and then return
+ from the Catch clause. Another option is to set a flag variable and
+ use goto to jump to the end of the Try clause, then check the flag
+ after the Try/Catch statement.
+
+ IMPORTANT: The values of any non-volatile automatic variables
+ changed within the Try clause are undefined after an exception is
+ caught. Therefore, variables modified inside the Try block whose
+ values are needed later outside the Try block must either use static
+ storage or be declared with the "volatile" type qualifier.
+
+
+Throw expression;
+
+ A Throw statement is very much like a return statement, except that
+ the expression is required. Whereas return jumps back to the place
+ where the current function was called, Throw jumps back to the Catch
+ clause of the innermost enclosing Try clause. The expression must
+ be compatible with the type passed to define_exception_type(). The
+ exception must be caught, otherwise the program may crash.
+
+ Slight limitation: If the expression is a comma-expression, it must
+ be enclosed in parentheses.
+
+
+Try statement
+Catch_anonymous statement
+
+ When the value of the exception is not needed, a Try/Catch statement
+ can use Catch_anonymous instead of Catch (expression).
+
+
+Everything below this point is for the benefit of the compiler. The
+application programmer should pretend not to know any of it, because it
+is subject to change.
+
+===*/
+
+
+#ifndef CEXCEPT_H
+#define CEXCEPT_H
+
+
+#include <setjmp.h>
+
+#define define_exception_type(etype) \
+struct exception_context { \
+ jmp_buf *penv; \
+ int caught; \
+ volatile struct { etype etmp; } v; \
+}
+
+/* etmp must be volatile because the application might use automatic */
+/* storage for the_exception_context, and etmp is modified between */
+/* the calls to setjmp() and longjmp(). A wrapper struct is used to */
+/* avoid warnings about a duplicate volatile qualifier in case etype */
+/* already includes it. */
+
+#define init_exception_context(ec) ((void)((ec)->penv = 0))
+
+#define Try \
+ { \
+ jmp_buf *exception__prev, exception__env; \
+ exception__prev = the_exception_context->penv; \
+ the_exception_context->penv = &exception__env; \
+ if (setjmp(exception__env) == 0) { \
+ do
+
+#define exception__catch(action) \
+ while (the_exception_context->caught = 0, \
+ the_exception_context->caught); \
+ } \
+ else { \
+ the_exception_context->caught = 1; \
+ } \
+ the_exception_context->penv = exception__prev; \
+ } \
+ if (!the_exception_context->caught || action) { } \
+ else
+
+#define Catch(e) exception__catch(((e) = the_exception_context->v.etmp, 0))
+#define Catch_anonymous exception__catch(0)
+
+/* Try ends with do, and Catch begins with while(0) and ends with */
+/* else, to ensure that Try/Catch syntax is similar to if/else */
+/* syntax. */
+/* */
+/* The 0 in while(0) is expressed as x=0,x in order to appease */
+/* compilers that warn about constant expressions inside while(). */
+/* Most compilers should still recognize that the condition is always */
+/* false and avoid generating code for it. */
+
+#define Throw \
+ for (;; longjmp(*the_exception_context->penv, 1)) \
+ the_exception_context->v.etmp =
+
+
+#endif /* CEXCEPT_H */
Modified: branches/eagle_mmc/inc/elua_adc.h
===================================================================
--- branches/eagle_mmc/inc/elua_adc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/elua_adc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -2,16 +2,19 @@
#define __ELUA_ADC_H__
#include "type.h"
+#include "platform_conf.h"
+
typedef struct
{
// Status Bit Flags
volatile u8 op_pending: 1, // Is there a pending conversion?
- nonblocking: 1, // Are we in blocking or non-blocking mode? (0 - blocking, 1 - nonblocking)
- burst: 1, // Acquiring in burst mode
- smooth_ready: 1; // Has smoothing filter warmed up (i.e. smoothlen samples collected)
+ blocking: 1, // Are we in blocking or non-blocking mode? (0 - blocking, 1 - nonblocking)
+ freerunning: 1, // If true, we don't stop when we've acquired the requested number of samples
+ smooth_ready: 1, // Has smoothing filter warmed up (i.e. smoothlen samples collected)
+ value_fresh: 1; // Whether the value pointed to by value_ptr is fresh
- unsigned id, timer_id;
+ unsigned id;
u8 logsmoothlen;
volatile u16 smoothidx;
@@ -19,17 +22,41 @@
u16 *smoothbuf;
volatile u16 reqsamples;
-} elua_adc_state;
+ volatile u16 *value_ptr;
+} elua_adc_ch_state;
+typedef struct
+{
+ elua_adc_ch_state *ch_state[ NUM_ADC ];
+ volatile u16 sample_buf[ NUM_ADC ];
+ volatile u8 clocked: 1,
+ force_reseq: 1,
+ skip_cycle: 1,
+ running: 1; // Whether or not sequence is running
+ volatile u32 ch_active; // bits represent whether channel should be converted on this device
+ volatile u32 last_ch_active; // keep copy of old configuration
+ unsigned timer_id, seq_id; // Timer bound to device, sequencer device id
+ volatile u8 seq_ctr, seq_len;
+} elua_adc_dev_state;
+// Channel Management
+#define ACTIVATE_CHANNEL( d, id ) ( d->ch_active |= ( ( u32 )1 << ( id ) ) )
+#define INACTIVATE_CHANNEL( d, id ) ( d->ch_active &= ~( ( u32 )1 << ( id ) ) )
+#define INCR_SEQCTR( d ) ( d->seq_ctr++ )
+
+int adc_setup_channel( unsigned id, u8 logcount );
+void adc_update_dev_sequence( unsigned dev_id );
+void adc_init_dev_state( unsigned dev_id );
+elua_adc_dev_state *adc_get_dev_state( unsigned dev_id );
void adc_smooth_data( unsigned id );
-elua_adc_state *adc_get_ch_state( unsigned id );
+elua_adc_ch_state *adc_get_ch_state( unsigned id );
u16 adc_get_processed_sample( unsigned id );
-void adc_init_state( unsigned id );
+void adc_init_ch_state( unsigned id );
int adc_update_smoothing( unsigned id, u8 loglen );
void adc_flush_smoothing( unsigned id );
u16 adc_samples_requested( unsigned id );
u16 adc_samples_available( unsigned id );
-void adc_wait_pending( unsigned id );
+u16 adc_wait_samples( unsigned id, unsigned samples );
-#endif
\ No newline at end of file
+#endif
+
Added: branches/eagle_mmc/inc/luarpc_rpc.h
===================================================================
--- branches/eagle_mmc/inc/luarpc_rpc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/luarpc_rpc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,194 @@
+#include "cexcept.h"
+#include <stdint.h>
+
+#ifdef LUA_REMOTE
+/* signed and unsigned 8, 16 and 32 bit types */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+
+#define LUARPC_ENABLE_SERIAL
+#define BUILD_LUARPC
+#endif
+
+/****************************************************************************/
+/* handle the differences between winsock and unix */
+
+#ifdef WIN32 /* BEGIN WIN32 SOCKET SETUP */
+
+#define close closesocket
+#define read(fd,buf,len) recv ((fd),(buf),(len),0)
+#define write(fd,buf,len) send ((fd),(buf),(len),0)
+#define SOCKTYPE SOCKET
+#define sock_errno (WSAGetLastError())
+
+#else
+
+#define SOCKTYPE int
+#define net_startup() ;
+#define sock_errno errno
+#define transport_strerror strerror
+
+#endif
+
+/****************************************************************************/
+/* parameters */
+
+#define MAXCON 10 /* maximum number of waiting server connections */
+
+/* a kind of silly way to get the maximum int, but oh well ... */
+#define MAXINT ((int)((((unsigned int)(-1)) << 1) >> 1))
+
+/****************************************************************************/
+/* error handling */
+
+/* allow special handling for GCC compiler */
+#ifdef __GNUC__
+#define DOGCC(x) x
+#else
+#define DOGCC(x) /* */
+#endif
+
+
+/* assertions */
+
+#ifndef NDEBUG
+#ifdef __GNUC__
+#define MYASSERT(a) if (!(a)) rpcdebug ( \
+ "assertion \"" #a "\" failed in %s() [%s]",__FUNCTION__,__FILE__);
+#else
+#define MYASSERT(a) if (!(a)) rpcdebug ( \
+ "assertion \"" #a "\" failed in %s:%d",__FILE__,__LINE__);
+#endif
+#else
+#define MYASSERT(a) ;
+#endif
+
+/****************************************************************************/
+/* more error handling */
+
+/* error numbers passed around are normal system "errno" error numbers
+ * (normally generated by transport operations), except when they have the
+ * following values:
+ */
+
+enum {
+ ERR_EOF = MAXINT - 100, /* reached end of file on transport */
+ ERR_CLOSED = MAXINT - 101, /* attempted operation on closed transport */
+ ERR_PROTOCOL = MAXINT - 102, /* some error in the received protocol */
+ ERR_NODATA = MAXINT - 103,
+ ERR_BADFNAME = MAXINT - 104,
+ ERR_DATALINK = MAXINT - 105,
+ ERR_COMMAND = MAXINT - 106,
+ ERR_HEADER = MAXINT - 107
+};
+
+enum exception_type { done, nonfatal, fatal };
+
+struct exception {
+ enum exception_type type;
+ int errnum;
+};
+
+define_exception_type(struct exception);
+
+extern struct exception_context the_exception_context[ 1 ];
+
+#define NUM_FUNCNAME_CHARS 20
+
+/* Transport Connection Structure */
+
+/* FIXME: should be cleaner */
+typedef struct _Transport Transport;
+struct _Transport
+{
+ int fd; /* INVALID_TRANSPORT if socket is closed */
+ u8 loc_little: 1, // Local is little endian?
+ loc_armflt: 1, // local float representation is arm float?
+ loc_intnum: 1, // Local is integer only?
+ net_little: 1, // Network is little endian?
+ net_intnum: 1; // Network is integer only?
+ u8 lnum_bytes;
+};
+
+#define LUARPC_MODE "elua"
+
+typedef struct _Handle Handle;
+struct _Handle
+{
+ Transport tpt; /* the handle socket */
+ int error_handler; /* function reference */
+ int async; /* nonzero if async mode being used */
+ int read_reply_count; /* number of async call return values to read */
+};
+
+
+typedef struct _Helper Helper;
+struct _Helper {
+ Handle *handle; /* pointer to handle object */
+ Helper *parent; /* parent helper */
+ u8 nparents; /* number of parents */
+ char funcname[NUM_FUNCNAME_CHARS]; /* name of the function */
+};
+
+
+typedef struct _ServerHandle ServerHandle;
+struct _ServerHandle {
+ Transport ltpt; /* listening socket, always valid if no error */
+ Transport atpt; /* accepting socket, valid if connection established */
+ int link_errs;
+};
+
+/* Maximum number of framing errors before connection reset */
+#define MAX_LINK_ERRS ( 2 )
+
+#define INVALID_TRANSPORT (-1)
+
+#define HEAD_BYTE (0x7e)
+
+#define TAIL_BYTE (0x7f)
+
+#define TRANSPORT_VERIFY_OPEN \
+ if (tpt->fd == INVALID_TRANSPORT) \
+ { \
+ e.errnum = ERR_CLOSED; \
+ e.type = fatal; \
+ Throw( e ); \
+ }
+
+/* Arg & Error Checking Provided to Transport Mechanisms */
+int check_num_args (lua_State *L, int desired_n);
+void deal_with_error (lua_State *L, Handle *h, const char *error_string);
+void my_lua_error( lua_State *L, const char *errmsg );
+
+/* TRANSPORT API */
+
+/* Setup Transport */
+void transport_init (Transport *tpt);
+
+/* Open Listener / Server */
+void transport_open_listener(lua_State *L, ServerHandle *handle);
+
+/* Open Connection / Client */
+int transport_open_connection(lua_State *L, Handle *handle);
+
+/* Accept Connection */
+void transport_accept (Transport *tpt, Transport *atpt);
+
+/* Read & Write to Transport */
+void transport_read_buffer (Transport *tpt, u8 *buffer, int length);
+void transport_write_buffer (Transport *tpt, const u8 *buffer, int length);
+
+/* Check if data is available on connection without reading:
+ - 1 = data available, 0 = no data available */
+int transport_readable (Transport *tpt);
+
+/* Check if transport is open:
+ - 1 = connection open, 0 = connection closed */
+int transport_is_open (Transport *tpt);
+
+/* Shut down connection */
+void transport_close (Transport *tpt);
\ No newline at end of file
Modified: branches/eagle_mmc/inc/newlib/genstd.h
===================================================================
--- branches/eagle_mmc/inc/newlib/genstd.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/newlib/genstd.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -5,13 +5,17 @@
#include "type.h"
#include "devman.h"
+#include "platform.h"
// STD device name (for devman)
#define STD_DEV_NAME "/std"
+#define STD_INFINITE_TIMEOUT PLATFORM_UART_INFINITE_TIMEOUT
+#define STD_INTER_CHAR_TIMEOUT 10000
+
// Send/receive function types
typedef void ( *p_std_send_char )( int fd, char c );
-typedef int ( *p_std_get_char )();
+typedef int ( *p_std_get_char )( s32 to );
// STD functions
void std_set_send_func( p_std_send_char pfunc );
@@ -19,3 +23,4 @@
DM_DEVICE* std_get_desc();
#endif
+
Modified: branches/eagle_mmc/inc/platform.h
===================================================================
--- branches/eagle_mmc/inc/platform.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/platform.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -67,6 +67,17 @@
pio_type platform_pio_op( unsigned port, pio_type pinmask, int op );
// *****************************************************************************
+// CAN subsection
+
+// Maximum length for any CAN message
+#define PLATFORM_CAN_MAXLEN 8
+
+int platform_can_exists( unsigned id );
+u32 platform_can_setup( unsigned id, u32 clock );
+void platform_can_send( unsigned id, u32 canid, u8 idtype, u8 len, const u8 *data );
+void platform_can_recv( unsigned id, u32 *canid, u8 *idtype, u8 *len, u8 *data );
+
+// *****************************************************************************
// SPI subsection
// There are 4 "virtual" SPI ports (SPI0...SPI3).
@@ -184,19 +195,23 @@
enum
{
PLATFORM_ADC_GET_MAXVAL,
- PLATFORM_ADC_GET_SMOOTHING,
PLATFORM_ADC_SET_SMOOTHING,
- PLATFORM_ADC_SET_NONBLOCKING,
- PLATFORM_ADC_FLUSH,
+ PLATFORM_ADC_SET_BLOCKING,
+ PLATFORM_ADC_SET_FREERUNNING,
+ PLATFORM_ADC_IS_DONE,
+ PLATFORM_ADC_OP_SET_TIMER,
+ PLATFORM_ADC_OP_SET_CLOCK,
};
// Functions requiring platform-specific implementation
-int platform_adc_sample( unsigned id );
-int platform_adc_burst( unsigned id, u8 logcount, unsigned timer_id, u32 frequency );
+int platform_adc_update_sequence( );
+int platform_adc_start_sequence( );
void platform_adc_stop( unsigned id );
+u32 platform_adc_setclock( unsigned id, u32 frequency);
// ADC Common Functions
int platform_adc_exists( unsigned id );
+int platform_adc_check_timer_id( unsigned id, unsigned timer_id );
u32 platform_adc_op( unsigned id, int op, u32 data );
// *****************************************************************************
@@ -213,10 +228,4 @@
void* platform_get_first_free_ram( unsigned id );
void* platform_get_last_free_ram( unsigned id );
-// *****************************************************************************
-// Misc support
-
-unsigned int intlog2( unsigned int v );
-u32 rndpow2( u32 v);
-
#endif
Added: branches/eagle_mmc/inc/salloc.h
===================================================================
--- branches/eagle_mmc/inc/salloc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/salloc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,14 @@
+// A very simple, quite inneficient, yet very small memory allocator
+
+#ifndef __SALLOC_H__
+#define __SALLOC_H__
+
+#include <stddef.h>
+
+void* smalloc( size_t size );
+void sfree( void* ptr );
+void* scalloc( size_t nmemb, size_t size );
+void* srealloc( void* ptr, size_t size );
+
+#endif // #ifndef __SALLOC_H__
+
Modified: branches/eagle_mmc/inc/term.h
===================================================================
--- branches/eagle_mmc/inc/term.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/term.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -13,7 +13,7 @@
// Terminal input function
typedef int ( *p_term_in )( int );
// Terminal translate input function
-typedef int ( *p_term_translate )( u8 );
+typedef int ( *p_term_translate )( int );
// Terminal input mode (parameter of p_term_in and term_getch())
#define TERM_INPUT_DONT_WAIT 0
Modified: branches/eagle_mmc/inc/utils.h
===================================================================
--- branches/eagle_mmc/inc/utils.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/utils.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -8,6 +8,28 @@
#define UMAX( x, y ) ( ( x ) >= ( y ) ? ( x ) : ( y ) )
#define UABS( x ) ( ( x ) >= 0 ? ( x ) : -( x ) )
+
+// Macro version of Duff's device found in
+// "A Reusable Duff Device" by Ralf Holly
+// Dr Dobb's Journal, August 1, 2005
+
+#define DUFF_DEVICE_8(count, action) \
+ do { \
+ int _count = ( count ); \
+ int _times = ( _count + 7 ) >> 3; \
+ switch ( _count & 7 ){ \
+ case 0: do { action; \
+ case 7: action; \
+ case 6: action; \
+ case 5: action; \
+ case 4: action; \
+ case 3: action; \
+ case 2: action; \
+ case 1: action; \
+ } while (--_times > 0); \
+ } \
+ } while (0)
+
#define STD_CTRLZ_CODE 26
#endif
Modified: branches/eagle_mmc/inc/validate.h
===================================================================
--- branches/eagle_mmc/inc/validate.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/inc/validate.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -10,13 +10,13 @@
// Can't define more than one console devices
#if defined( BUILD_CON_TCP ) && defined( BUILD_CON_GENERIC )
-#error "Can't have two console devices (don't enable BUILD_CON_TCP and BUILD_CON_GENERIC in build.h at the same time)"
+#error "Can't have two console devices (don't enable BUILD_CON_TCP and BUILD_CON_GENERIC in platform_conf.h at the same time)"
#endif // #if defined( BUILD_CON_TCP ) && defined( BUILD_CON_GENERIC )
// For TCP console we need to enable TCP support
#ifdef BUILD_CON_TCP
#ifndef BUILD_UIP
- #error "BUILD_CON_TCP requires BUILD_UIP to be defined in build.h"
+ #error "BUILD_CON_TCP requires BUILD_UIP to be defined in platform_conf.h"
#endif // #ifndef BUILD_UIP
#endif // #ifdef BUILD_CON_TCP
@@ -24,18 +24,25 @@
// (they can still function separately over UART, but this doesn't make sense)
#ifdef BUILD_CON_TCP
#ifdef BUILD_XMODEM
- #error "XMODEM doesn't work with TCP console. Disable BUILD_XMODEM in build.h"
+ #error "XMODEM doesn't work with TCP console. Disable BUILD_XMODEM in platform_conf.h"
#endif // #ifdef BUILD_XMODME
#ifdef BUILD_TERM
- #error "ANSI terminal support doesn't work (yet) with TCP console. Disable BUILD_TERM in build.h"
+ #error "ANSI terminal support doesn't work (yet) with TCP console. Disable BUILD_TERM in platform_conf.h"
#endif // #ifdef BUILD_TERM
#endif // #ifdef BUILD_CON_TCP
// For DHCP we need to have TCP/IP support
#ifdef BUILD_DHCPC
#ifndef BUILD_UIP
- #error "DHCP client requires TCP/IP support (enable BUILD_UIP in build.h)"
+ #error "DHCP client requires TCP/IP support (enable BUILD_UIP in platform_conf.h)"
#endif // #ifndef BUILD_UIP
#endif // #ifdef BUILD_DHCPC
+// For DNS we need to have TCP/IP support
+#ifdef BUILD_DNS
+ #ifndef BUILD_UIP
+ #error "DNS resolver requires TCP/IP support (enable BUILD_UIP in platform_conf.h)"
+ #endif // #ifndef BUILD_UIP
+#endif // #ifdef BUILD_DNS
+
#endif // #ifndef __VALIDATE_H__
Copied: branches/eagle_mmc/remote-lua.py (from rev 269, branches/eagle_mmc/cross-lua.py)
===================================================================
--- branches/eagle_mmc/cross-lua.py 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/remote-lua.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,23 @@
+import os, sys
+
+output = 'lua'
+cdefs = '-DLUA_CROSS_COMPILER -DLUA_REMOTE -DLUA_USE_READLINE'
+
+# Lua source files and include path
+lua_files = """lapi.c lcode.c ldebug.c ldo.c ldump.c lfunc.c lgc.c llex.c lmem.c lobject.c lopcodes.c
+ lparser.c lstate.c lstring.c ltable.c ltm.c lundump.c lvm.c lzio.c lauxlib.c lbaselib.c
+ ldblib.c liolib.c lmathlib.c loslib.c ltablib.c lstrlib.c loadlib.c linit.c lua.c print.c lrotable.c"""
+lua_full_files = " " + " ".join( [ "src/lua/%s" % name for name in lua_files.split() ] )
+lua_full_files += " src/modules/luarpc.c src/luarpc_posix_serial.c "
+local_include = "-Isrc/lua -Iinc -Isrc/modules"
+
+# Compiler/linker options
+cccom = "gcc -g %s -Wall %s -c $SOURCE -o $TARGET" % ( local_include, cdefs )
+linkcom = "gcc -o $TARGET $SOURCES -lm -lreadline"
+
+# Env for building the program
+comp = Environment( CCCOM = cccom,
+ LINKCOM = linkcom,
+ ENV = os.environ )
+Decider( 'MD5' )
+Default( comp.Program( output, Split( lua_full_files ) ) )
Modified: branches/eagle_mmc/romfs/LM3S.lua
===================================================================
--- branches/eagle_mmc/romfs/LM3S.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/LM3S.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,19 +1,20 @@
-local gpio = gpio
+local pio = pio
module(...)
-BTN_UP = "PE_0"
-BTN_DOWN = "PE_1"
-BTN_LEFT = "PE_2"
-BTN_RIGHT = "PE_3"
-BTN_SELECT = "PF_1"
+BTN_UP = pio.PE_0
+BTN_DOWN = pio.PE_1
+BTN_LEFT = pio.PE_2
+BTN_RIGHT = pio.PE_3
+BTN_SELECT = pio.PF_1
+
btnpressed = function( button )
- return ( gpio[ button ] == 0 )
+ return pio.pin.getval( button ) == 0
end
-LED_1 = "PF_0"
+LED_1 = pio.PF_0
-gpio.PE_0_3_DIR, gpio.PF_1_DIR = gpio.INPUT, gpio.INPUT
-gpio.PE_0_3_PULL, gpio.PF_1_PULL = gpio.PULLUP, gpio.PULLUP
-gpio.PF_0_DIR = gpio.OUTPUT
+pio.pin.setdir( pio.INPUT, pio.PE_0, pio.PE_1, pio.PE_2, pio.PE_3, pio.PF_1 )
+pio.pin.setpull( pio.PULLUP, pio.PE_0, pio.PE_1, pio.PE_2, pio.PE_3, pio.PF_1 )
+pio.pin.setdir( pio.OUTPUT, pio.PF_0 )
Added: branches/eagle_mmc/romfs/adcpoll.lua
===================================================================
--- branches/eagle_mmc/romfs/adcpoll.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/adcpoll.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,49 @@
+-- Acquire ADC samples using a timer with polling for available samples
+
+if pd.board() == "ET-STM32" then
+ timer = 2
+ adcchannels = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
+ adcsmoothing = {4, 4, 4, 4, 16, 16, 16, 16, 32, 32, 32, 32, 64, 128, 64, 128}
+else
+ timer = 0
+ adcchannels = {0,1,2,3}
+ adcsmoothing = {4, 64, 32, 16}
+end
+
+-- Setup ADC and start sampling
+for i, v in ipairs(adcchannels) do
+ adc.setblocking(v,0) -- no blocking on any channels
+ adc.setsmoothing(v,adcsmoothing[i]) -- set smoothing from adcsmoothing table
+ adc.setclock(v, 4 ,timer) -- get 4 samples per second, per channel
+end
+
+-- Draw static text on terminal
+term.clrscr()
+term.print(1,1,"ADC Status:")
+term.print(1,3," CH SLEN RES")
+term.print(1,#adcchannels+5,"Press ESC to exit.")
+
+-- start sampling on all channels at the same time
+adc.sample(adcchannels,128)
+
+while true do
+ for i, v in ipairs(adcchannels) do
+ -- If samples are not being collected, start
+ if adc.isdone(v) == 1 then adc.sample(v,128) end
+
+ -- Try and get a sample
+ tsample = adc.getsample(v)
+
+ -- If we have a new sample, then update display
+ if not (tsample == nil) then
+ term.print(1,i+3,string.format("ADC%02d (%03d): %04d\n", v, adcsmoothing[i], tsample))
+ end
+ end
+
+ -- Exit if user hits Escape
+ key = term.getchar( term.NOWAIT )
+ if key == term.KC_ESC then break end
+end
+
+term.clrscr()
+term.moveto(1, 1)
Property changes on: branches/eagle_mmc/romfs/adcpoll.lua
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/romfs/adcscope.lua
===================================================================
--- branches/eagle_mmc/romfs/adcscope.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/adcscope.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,52 +1,62 @@
+-- Acquire ADC samples as quickly as possible, without the use of a timer
+-- provides statistics on time and memory usage while running
-adcchannels = {0, 1, 2, 3}
-adcsmoothing = {4, 16, 32, 64}
+if pd.board() == "ET-STM32" then
+ adcchannels = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
+ adcsmoothing = {4, 4, 4, 4, 16, 16, 16, 16, 32, 32, 32, 32, 64, 128, 64, 128}
+ numiter = 50
+else
+ adcchannels = {0,1,2,3}
+ adcsmoothing = {4, 16, 64, 128}
+ numiter = 200
+end
+-- Setup ADC
for i, v in ipairs(adcchannels) do
- adc.setmode(v,0)
- adc.setsmoothing(v,adcsmoothing[i])
+ adc.setblocking(v,1) -- block, waiting for samples when an adc.get* function is used
+ adc.setclock(v,0) -- set clock to zero: no timer, acquire samples as fast as possible
+ adc.setsmoothing(v,adcsmoothing[i]) -- apply moving average filter using lengths from adcsmoothing
end
+-- Draw static text on terminal
term.clrscr()
+term.print(1,1,"ADC Status:")
+term.print(1,3," CH SLEN RES")
+term.print(1,#adcchannels+7,"Press ESC to exit.")
-term.gotoxy(1,1)
-term.putstr("ADC Status:")
-term.gotoxy(1,3)
-term.putstr(" CH SLEN RES")
-term.gotoxy(1,#adcchannels+6)
-term.putstr("Press ESC to exit.")
-
+-- Use some locals for speed
local adcvals = {}
-local ctr = 0
+local key, stime, etime, dtime, i, v
+local sample = adc.sample
+local insertsamples = adc.insertsamples
+local tread = tmr.read
+local tstart = tmr.start
while true do
- local key, stime, etime, dtime
- local sample = adc.sample
- local getsamples = adc.getsamples
- ctr = ctr + 1
+ stime = tstart(0) -- start timer
+ for j=1,numiter do -- acuire numiter samples
+ sample(adcchannels, 1)
+ for i, v in ipairs(adcchannels) do
+ insertsamples(v,adcvals,i,1) -- for each iteration j, get samples and put them in adcvals
+ end
+ end
+ etime = tread(0) -- get cycle end time
+ dtime = tmr.diff(0,etime,stime)/numiter -- compute average acquisition time per cycle
- stime = tmr.start(0)
+ -- draw last acquired samples on the console
+ term.moveto(1,4)
for i, v in ipairs(adcchannels) do
- sample(v)
- adcvals[i] = getsamples(v,1)
+ term.print(string.format("ADC%02d (%03d): %04d\n", v, adcsmoothing[i],adcvals[i]))
+ term.moveto(1,i+4)
end
- etime = tmr.read(0)
- dtime = tmr.diff(0,etime,stime)
- if ( ctr == 100 ) then
- ctr = 0
- term.gotoxy(1,4)
- for i, v in ipairs(adcchannels) do
- term.putstr(string.format("ADC%d (%03d): %04d\n",v,adcsmoothing[i],adcvals[i]))
- term.gotoxy(1,i+4)
- end
- term.putstr(string.format("Tcyc: %06d (us)\n",dtime))
-
- key = term.getch( term.NOWAIT )
- if key == term.KC_ESC then break end
- end
- if key == term.KC_ESC then break end
+ -- draw acquisition statistics
+ term.print(string.format("Tcyc: %06d (us)\n",dtime))
+ term.print(1,#adcchannels+5,string.format("Mem: %03.2f (kB)\n",collectgarbage("count")))
+
+ key = term.getchar( term.NOWAIT )
+ if key == term.KC_ESC then break end -- exit if user hits Escape
end
term.clrscr()
-term.gotoxy( 1 , 1 )
\ No newline at end of file
+term.moveto( 1 , 1 )
Modified: branches/eagle_mmc/romfs/dualpwm.lua
===================================================================
--- branches/eagle_mmc/romfs/dualpwm.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/dualpwm.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,20 +1,26 @@
-- Control LED intensity with PWM on two channels
-local pwmid1, pwmid2, tmrid = 0, 1, 3
+local pwmid1, pwmid2, tmrid
-if pd.board() ~= "MOD711" then
- print "Unsopported board"
+if pd.board() == 'MOD711' or pd.board() == 'ET-STM32' then
+ pwmid1, pwmid2, tmrid = 0, 1, 3
+else
+ print( pd.board() .. " not supported by this example" )
return
end
print "Control LED with PWM (fade up/down)"
print "Press any key to exit"
local crtduty, incr = 10, 5
+tmr.start( tmrid )
+
pwm.setup( pwmid1, 50000, crtduty )
pwm.setup( pwmid2, 50000, 100 - crtduty )
+
pwm.start( pwmid1 )
pwm.start( pwmid2 )
-while uart.recv( 1, 0, 0 ) < 0 do
+
+while uart.getchar( 1, 0 ) == "" do
if crtduty == 95 or crtduty == 5 then
incr = -incr
end
Modified: branches/eagle_mmc/romfs/hangman.lua
===================================================================
--- branches/eagle_mmc/romfs/hangman.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/hangman.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -8,7 +8,7 @@
return
end
-local h, w = term.lines(), term.cols()
+local h, w = term.getlines(), term.getcols()
local tries = 0
-- "Database" with our words
@@ -19,41 +19,30 @@
function hang()
if tries == 0 then
-- Build the basic structure
- term.gotoxy( 5, 1 )
- term.putstr( string.rep( '_', 6 ) )
- term.gotoxy( 5, 2 )
- term.putstr( '| |')
- local i
+ term.print( 5, 1, string.rep( '_', 6 ) )
+ term.print( 5, 2, '| |')
for i = 3, 6 do
- term.gotoxy( 5, i )
- term.putstr( '|' )
+ term.print( 5, i, '|' )
end
- term.gotoxy( 3, 7 )
- term.putstr( '__|_____')
- term.gotoxy( 3, 8 )
- term.putstr( '| |___')
- term.gotoxy( 3, 9 )
- term.putstr( '|__________|')
+ term.print( 3, 7, '__|_____')
+ term.print( 3, 8, '| |___')
+ term.print( 3, 9, '|__________|')
elseif tries == 1 then
-- Draw the head
- term.gotoxy( 10, 3 )
- term.putstr( "O" )
+ term.print( 10, 3, "O" )
elseif tries == 2 or tries == 3 then
-- First or second part of body
- term.gotoxy( 10, tries + 2 )
- term.putstr( "|" )
+ term.print( 10, tries + 2, "|" )
elseif tries == 4 or tries == 5 then
-- First leg / first hand
- term.gotoxy( 9, tries == 4 and 6 or 4 )
- term.putstr( "/" )
+ term.print( 9, tries == 4 and 6 or 4, "/" )
elseif tries == 6 or tries == 7 then
-- Second hand / second leg
- term.gotoxy( 11, tries == 7 and 6 or 4 )
- term.putstr( "\\" )
+ term.print( 11, tries == 7 and 6 or 4, "\\" )
end
end
@@ -61,18 +50,14 @@
-- Show the game statistics
function stats()
- term.gotoxy( w - 20, 5 )
- term.putstr( "Total words: ", tostring( total ) )
- term.gotoxy( w - 20, 6 )
- term.putstr( "Guessed words: ", tostring( guessed ) )
+ term.print( w - 20, 5, "Total words: ", tostring( total ) )
+ term.print( w - 20, 6, "Guessed words: ", tostring( guessed ) )
end
while true do
term.clrscr()
- term.gotoxy( 3, 12 )
- term.putstr( "eLua hangman" )
- term.gotoxy( 3, 13 )
- term.putstr( "ESC to exit" )
+ term.print( 3, 12, "eLua hangman" )
+ term.print( 3, 13, "ESC to exit" )
stats()
-- Draw the hanging site
@@ -80,29 +65,27 @@
hang()
-- Then write the "Guess" line
- term.gotoxy( 2, h - 3 )
- term.putstr( "Word: " )
+ term.print( 2, h - 3, "Word: " )
local lword = words[ math.random( #words ) ]:lower()
- term.putstr( string.rep( "-", #lword ) )
- term.gotoxy( 2, h - 2 )
- term.putstr( "Guess: " )
+ term.print( string.rep( "-", #lword ) )
+ term.print( 2, h - 2, "Guess: " )
local nguess = 0
local tried = {}
local key
while tries < 7 and nguess < #lword do
- key = term.getch( term.WAIT )
+ key = term.getchar()
if key == term.KC_ESC then break end
if key > 0 and key < 255 then
key = string.char( key ):lower()
- term.gotoxy( 2, h - 1 )
+ term.moveto( 2, h - 1 )
term.clreol()
if not key:find( '%l' ) then
- term.putstr( "Invalid character" )
+ term.print( "Invalid character" )
else
key = key:byte()
if tried[ key ] ~= nil then
- term.putstr( "Already tried this key" )
+ term.print( "Already tried this key" )
else
tried[ key ] = true
local i
@@ -110,8 +93,7 @@
for i = 1, #lword do
if key == lword:byte( i ) then
ok = true
- term.gotoxy( 7 + i, h - 3 )
- term.put( key )
+ term.print( 7 + i, h - 3, string.char( key ) )
nguess = nguess + 1
end
end
@@ -121,28 +103,26 @@
end
end
end
- term.gotoxy( 9, h - 2 )
+ term.moveto( 9, h - 2 )
end
end
if key == term.KC_ESC then break end
- term.gotoxy( 2, h - 1 )
+ term.moveto( 2, h - 1 )
total = total + 1
if nguess == #lword then
- term.putstr( "Congratulations! Another game? (y/n)" )
+ term.print( "Congratulations! Another game? (y/n)" )
guessed = guessed + 1
else
- term.gotoxy( 8, h - 3 )
- term.putstr( lword )
- term.gotoxy( 2, h - 1 )
- term.putstr( "Game over. Another game? (y/n)" )
+ term.print( 8, h - 3, lword )
+ term.print( 2, h - 1, "Game over. Another game? (y/n)" )
end
-- Show statistics again
stats()
repeat
- key = string.char( term.getch( term.WAIT ) ):lower()
+ key = string.char( term.getchar() ):lower()
until key == 'y' or key == 'n'
if key == 'n' then
@@ -152,5 +132,5 @@
end
term.clrscr()
-term.gotoxy( 1 , 1 )
+term.moveto( 1 , 1 )
Modified: branches/eagle_mmc/romfs/index.pht
===================================================================
--- branches/eagle_mmc/romfs/index.pht 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/index.pht 2009-07-30 18:10:13 UTC (rev 371)
@@ -30,12 +30,12 @@
</table>
</form>
<?lua
- pio.PF_0_DIR = pio.OUTPUT
+ pio.pin.setdir( pio.OUTPUT, pio.PF_0 )
if reqdata['ledon'] then
- pio.PF_0 = 1
+ pio.pin.sethigh( pio.PF_0 )
print '<br><font color="blue"><b>The LED is now ON</b></font><br>'
elseif reqdata['ledoff'] then
- pio.PF_0 = 0
+ pio.pin.setlow( pio.PF_0 )
print '<br><font color="blue"><b>The LED is now OFF</b></font><br>'
elseif next(reqdata) ~= nil then
print '<br><font color="red"><b>Invalid CGI request!</b></font><br>'
Modified: branches/eagle_mmc/romfs/led.lua
===================================================================
--- branches/eagle_mmc/romfs/led.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/led.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -2,20 +2,20 @@
local uartid, invert, ledpin = 0, false
if pd.board() == "SAM7-EX256" then
- ledpin = "PB_20"
+ ledpin = pio.PB_20
elseif pd.board() == "EK-LM3S8962" or pd.board() == "EK-LM3S6965" then
- ledpin = "PF_0"
+ ledpin = pio.PF_0
elseif pd.board() == "EAGLE-100" then
- ledpin = "PE_1"
+ ledpin = pio.PE_1
elseif pd.board() == "STR9-COMSTICK" then
- ledpin = "P9_0"
+ ledpin = pio.P9_0
elseif pd.board() == "LPC-H2888" then
- ledpin = "P2_1"
+ ledpin = pio.P2_1
elseif pd.board() == "MOD711" then
- ledpin = "P1_7"
+ ledpin = pio.P1_7
uartid = 1
elseif pd.board() == "ATEVK1100" then
- ledpin = "PB_27"
+ ledpin = pio.PB_27
invert = true
else
print( "\nError: Unknown board " .. pd.board() .. " !" )
@@ -23,18 +23,18 @@
end
function cycle()
- if not invert then gpio[ ledpin ] = 1 else gpio[ ledpin ] = 0 end
+ if not invert then pio.pin.sethigh( ledpin ) else pio.pin.setlow( ledpin ) end
tmr.delay( 0, 500000 )
- if not invert then gpio[ ledpin ] = 0 else gpio[ ledpin ] = 1 end
+ if not invert then pio.pin.setlow( ledpin ) else pio.pin.sethigh( ledpin ) end
tmr.delay( 0, 500000 )
end
-gpio.dir[ ledpin ] = gpio.OUTPUT
+pio.pin.setdir( pio.OUTPUT, ledpin )
print( "Hello from eLua on " .. pd.cpu() )
print "Watch your LED blinking :)"
print "Press any key to end this demo.\n"
-while uart.recv( uartid, 0, 0 ) < 0 do
+while uart.getchar( uartid, 0 ) == "" do
cycle()
end
Modified: branches/eagle_mmc/romfs/lhttpd.lua
===================================================================
--- branches/eagle_mmc/romfs/lhttpd.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/lhttpd.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,122 +1,122 @@
--- Check platform
+-- Check platform
if pd.board() ~= 'EK-LM3S8962' and pd.board() ~= 'EK-LM3S6965' and pd.board() ~= 'EAGLE-100' then
print( pd.board() .. " not supported by this example" )
return
-end
-
--- Mapping between file extension (and request) and HTTP response
-local extmap = {
- txt = "text/plain",
- htm = "text/html",
- pht = "text/html",
- gif = "image/gif",
- jpg = "imge/jpeg",
- png = "image/png",
- lua = "text/html"
-}
-
-local basedir = "/rom/"
-reqdata = {}
-
--- Auxiliary function: execute the given code with a substituted "print"
--- that prints everything to a string, return the code output
-local function docode(thecode)
- local strbuf = {}
- local oldprint, newprint = print, function(...)
- local total, idx = select('#', ...)
- for idx = 1, total do
- strbuf[#strbuf + 1] = tostring(select(idx, ...)) .. (idx == total and '\n' or '\t')
- end
- end
- print = newprint
- local f = loadstring(thecode)
- if f then
- f()
- else
- print ">>> Invalid Lua code <<<"
- end
- print = oldprint
- collectgarbage('collect')
- return table.concat(strbuf)
-end
-
-function process(header)
- -- look for first line
- local s, e = header:find("[^\n]+\n")
- local reqstr = header:sub(s, e)
- local respheader, respdata = '', ''
-
- reqdata = {}
- -- check if the request is valid, also keep the actual request
- local i, valid, req = 0, false
- for w in reqstr:gmatch("%S+") do
- valid = ( i == 0 and w == "GET" ) or valid
- req = ( i == 1 and w ) or req
- i = i + 1
- end
-
- -- valid is true if the request is valid, req has the request string
- if valid then
- -- now look for all parameters in this request (if any)
- local fname = ""
- if req:find("%?") then
- local rest
- _, _, fname, rest = req:find("(.*)%?(.*)")
- -- small trick: end "rest" with a "&" for easier processing
- -- now look for "var=value" pairs in the request (GET encoding)
- rest = rest .. "&"
- for crtpair in rest:gmatch("[^&]+") do
- local _, __, k, v = crtpair:find("(.*)=(.*)")
- -- replace all "%xx" characters with their actual value
- v = v:gsub("(%%%x%x)", function(s) return string.char(tonumber(s:sub(2, -1), 16)) end)
- reqdata[k] = v
- end
- else
- fname = req
- end
- fname = ( fname == "/" ) and "index.pht" or fname:sub(2, -1)
- s, e = fname:find("%.[%a%d]+$")
- local ftype = fname:sub(s+1, e):lower()
- ftype = (#ftype > 0 and ftype) or "txt"
- fname = basedir .. fname
-
- -- now "fname" has the name of the requested file, and "reqdata" the actual request data
- -- also "ftype" holds the file type (actually its extension)
- local tf = io.open(fname, "r")
- if tf then
- respheader = "HTTP/1.1 200 OK\r\nConnection: close\r\nServer: eLua-miniweb\r\nContent-Type: " .. extmap[ftype or "txt"] .. "\r\n\r\n"
- -- Preprocess "lua" and "pht" files: run the Lua ones, parse the .htm ones for "<?lua ... ?>" sequences
- if ftype == "pht" or ftype == "lua" then
- local fdata = tf:read("*a")
- if ftype == "lua" then
- respdata = docode(fdata)
- else
- -- Look for <?lua ... lua> patterns and execute them accordingly
- respdata = fdata:gsub("<%?lua(.-)%?>", docode)
- end
- else
- respdata = tf:read("*a")
- end
- tf:close()
- else
- respheader = "HTTP/1.1 404 Not Found\r\nConnection: close\r\nServer: eLua-miniweb\r\nContent-Type: text/html\r\n\r\nPage not found"
- end
- end
- return respheader .. respdata
-end
-
-while true do
- local sock, remoteip, err = net.accept( 80 )
- print( "Got connection on socket", sock )
- print( "Remote ip: " .. net.unpackip( remoteip, "*s" ) )
- local response, err2 = net.recv( sock, 1024 )
- print "Got request"
- local httpdata = process( response )
- if #httpdata > 0 then
- print "Sending response"
- net.send( sock, httpdata )
- end
- net.close( sock )
- reqdata = {}
- collectgarbage('collect')
-end
+end
+
+-- Mapping between file extension (and request) and HTTP response
+local extmap = {
+ txt = "text/plain",
+ htm = "text/html",
+ pht = "text/html",
+ gif = "image/gif",
+ jpg = "imge/jpeg",
+ png = "image/png",
+ lua = "text/html"
+}
+
+local basedir = "/rom/"
+reqdata = {}
+
+-- Auxiliary function: execute the given code with a substituted "print"
+-- that prints everything to a string, return the code output
+local function docode(thecode)
+ local strbuf = {}
+ local oldprint, newprint = print, function(...)
+ local total, idx = select('#', ...)
+ for idx = 1, total do
+ strbuf[#strbuf + 1] = tostring(select(idx, ...)) .. (idx == total and '\n' or '\t')
+ end
+ end
+ print = newprint
+ local f = loadstring(thecode)
+ if f then
+ f()
+ else
+ print ">>> Invalid Lua code <<<"
+ end
+ print = oldprint
+ collectgarbage('collect')
+ return table.concat(strbuf)
+end
+
+function process(header)
+ -- look for first line
+ local s, e = header:find("[^\n]+\n")
+ local reqstr = header:sub(s, e)
+ local respheader, respdata = '', ''
+
+ reqdata = {}
+ -- check if the request is valid, also keep the actual request
+ local i, valid, req = 0, false
+ for w in reqstr:gmatch("%S+") do
+ valid = ( i == 0 and w == "GET" ) or valid
+ req = ( i == 1 and w ) or req
+ i = i + 1
+ end
+
+ -- valid is true if the request is valid, req has the request string
+ if valid then
+ -- now look for all parameters in this request (if any)
+ local fname = ""
+ if req:find("%?") then
+ local rest
+ _, _, fname, rest = req:find("(.*)%?(.*)")
+ -- small trick: end "rest" with a "&" for easier processing
+ -- now look for "var=value" pairs in the request (GET encoding)
+ rest = rest .. "&"
+ for crtpair in rest:gmatch("[^&]+") do
+ local _, __, k, v = crtpair:find("(.*)=(.*)")
+ -- replace all "%xx" characters with their actual value
+ v = v:gsub("(%%%x%x)", function(s) return string.char(tonumber(s:sub(2, -1), 16)) end)
+ reqdata[k] = v
+ end
+ else
+ fname = req
+ end
+ fname = ( fname == "/" ) and "index.pht" or fname:sub(2, -1)
+ s, e = fname:find("%.[%a%d]+$")
+ local ftype = fname:sub(s+1, e):lower()
+ ftype = (#ftype > 0 and ftype) or "txt"
+ fname = basedir .. fname
+
+ -- now "fname" has the name of the requested file, and "reqdata" the actual request data
+ -- also "ftype" holds the file type (actually its extension)
+ local tf = io.open(fname, "r")
+ if tf then
+ respheader = "HTTP/1.1 200 OK\r\nConnection: close\r\nServer: eLua-miniweb\r\nContent-Type: " .. extmap[ftype or "txt"] .. "\r\n\r\n"
+ -- Preprocess "lua" and "pht" files: run the Lua ones, parse the .htm ones for "<?lua ... ?>" sequences
+ if ftype == "pht" or ftype == "lua" then
+ local fdata = tf:read("*a")
+ if ftype == "lua" then
+ respdata = docode(fdata)
+ else
+ -- Look for <?lua ... lua> patterns and execute them accordingly
+ respdata = fdata:gsub("<%?lua(.-)%?>", docode)
+ end
+ else
+ respdata = tf:read("*a")
+ end
+ tf:close()
+ else
+ respheader = "HTTP/1.1 404 Not Found\r\nConnection: close\r\nServer: eLua-miniweb\r\nContent-Type: text/html\r\n\r\nPage not found"
+ end
+ end
+ return respheader .. respdata
+end
+
+while true do
+ local sock, remoteip, err = net.accept( 80 )
+ print( "Got connection on socket", sock )
+ print( "Remote ip: " .. net.unpackip( remoteip, "*s" ) )
+ local response, err2 = net.recv( sock, 1024 )
+ print "Got request"
+ local httpdata = process( response )
+ if #httpdata > 0 then
+ print "Sending response"
+ net.send( sock, httpdata )
+ end
+ net.close( sock )
+ reqdata = {}
+ collectgarbage('collect')
+end
Modified: branches/eagle_mmc/romfs/morse.lua
===================================================================
--- branches/eagle_mmc/romfs/morse.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/morse.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,11 +6,11 @@
local pwmid, tmrid, ledpin
if pd.board() == "EK-LM3S8962" or pd.board() == "EK-LM3S6965" then
- pwmid, tmrid, ledpin = 1, 1, "PF_0"
+ wmid, tmrid, ledpin = 1, 1, pio.PF_0
elseif pd.board() == "EAGLE-100" then
- pwmid, tmrid, ledpin = 1, 1, "PE_1"
+ wmid, tmrid, ledpin = 1, 1, pio.PE_1
elseif pd.board() == "SAM7-EX256" then
- pwmid, tmrid, ledpin = 0, 1, "PB_20"
+ pwmid, tmrid, ledpin = 0, 1, pio.PB_20
tmr.setclock( 1, 100000 )
else
print( pd.board() .. " not supported with this example" )
@@ -55,15 +55,15 @@
------------ Auxiliar Functions ------------
local function play(m)
- term.putstr(m)
+ term.print(m)
if m == ' ' then
tmr.delay(tmrid, 2 * dotDelay)
else
- gpio[ledpin] = 1
+ pio.pin.sethigh( ledpin )
pwm.start(pwmid)
tmr.delay(tmrid, m == '.' and dotDelay or 3 * dotDelay)
pwm.stop(pwmid)
- gpio[ledpin] = 0
+ pio.pin.setlow( ledpin )
tmr.delay(tmrid, dotDelay)
end
end
@@ -93,24 +93,24 @@
end
------------ Main Program ------------
-gpio.dir[ledpin] = gpio.OUTPUT
+pio.pin.setdir( pio.OUTPUT, ledpin )
pwm.setup( pwmid, playFreq, 50 )
while true do
term.clrscr()
- term.gotoxy(0, 0)
+ term.moveto(1, 1)
print("Welcome to eLua Morse Playing on " .. pd.cpu())
io.write("Enter phrase (empty phrase to exit): ")
local msg, enabled = io.read(), true
if #msg == 0 then break end
- term.putstr(' ')
- while term.getch(term.NOWAIT) ~= -1 do end -- flush
+ term.print(' ')
+ while term.getchar(term.NOWAIT) ~= -1 do end -- flush
while enabled do -- Main Loop
for i = 1, #msg do -- msg loop
local ch = msg:sub(i, i):upper()
- term.putstr(ch) -- show what will be played
+ term.print(ch) -- show what will be played
if ch ~= ' ' and Morse[ch] then
for j = 1, #Morse[ch] do -- Morse symbol loop
play(Morse[ch]:sub(j,j)) -- play each morse symbol
@@ -119,7 +119,7 @@
play(' ') play(' ') -- Between words
end
play(' ') -- Extra between words & lett
- key = term.getch(term.NOWAIT) -- Handle UI actions
+ key = term.getchar(term.NOWAIT) -- Handle UI actions
if key ~= -1 then
if HandleKbd(key) then
enabled = false
Modified: branches/eagle_mmc/romfs/piano.lua
===================================================================
--- branches/eagle_mmc/romfs/piano.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/piano.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -26,35 +26,35 @@
-- Write the curent octave
function show_octave()
- term.putstrxy( 2, 4, "Oct: " .. tostring( oct ) .. "(+/-)" )
- term.gotoxy( 2, 19 )
+ term.print( 2, 4, "Oct: " .. tostring( oct ) .. "(+/-)" )
+ term.moveto( 2, 19 )
end
-- Write the current pause between notes
function show_pause()
- term.gotoxy( 2, 5 )
+ term.moveto( 2, 5 )
term.clreol()
- term.putstrxy( 2, 5, "Pause between notes: " .. tostring( pause ) .. "ms (</>)" )
- term.gotoxy( 2, 19 )
+ term.print( 2, 5, "Pause between notes: " .. tostring( pause ) .. "ms (</>)" )
+ term.moveto( 2, 19 )
end
-- Show the main interface
function show_all()
- term.putstrxy( 2, 2, "eLua piano demo" )
+ term.print( 2, 2, "eLua piano demo" )
show_octave()
show_pause()
- term.putstrxy( 4, 7, " w r t u i o [ ] " )
- term.putstrxy( 4, 8, " | | | | | | | | " )
- term.putstrxy( 4, 9, " A# C# D# F# G# A# C# D# " )
- term.putstrxy( 4, 10, "A BC D EF G A BC D E" )
- term.putstrxy( 4, 11, "| || | || | | || | |" )
- term.putstrxy( 4, 12, "a sd f gh j k l; ' \\" )
- term.putstrxy( 2, 14, "Use above keys to play notes." )
- term.putstrxy( 2, 15, "+/- to change octave." )
- term.putstrxy( 2, 16, "</> to change pause between notes." )
- term.putstrxy( 2, 17, "Space to stop playing." )
- term.putstrxy( 2, 18, "ESC to exit." )
- term.gotoxy( 2, 19 )
+ term.print( 4, 7, " w r t u i o [ ] " )
+ term.print( 4, 8, " | | | | | | | | " )
+ term.print( 4, 9, " A# C# D# F# G# A# C# D# " )
+ term.print( 4, 10, "A BC D EF G A BC D E" )
+ term.print( 4, 11, "| || | || | | || | |" )
+ term.print( 4, 12, "a sd f gh j k l; ' \\" )
+ term.print( 2, 14, "Use above keys to play notes." )
+ term.print( 2, 15, "+/- to change octave." )
+ term.print( 2, 16, "</> to change pause between notes." )
+ term.print( 2, 17, "Space to stop playing." )
+ term.print( 2, 18, "ESC to exit." )
+ term.moveto( 2, 19 )
end
-- Conversion of note to frequency
@@ -67,7 +67,7 @@
pwm.setclock( pwmid, 1000000 )
show_all()
while true do
- local key = term.getch( term.WAIT )
+ local key = term.getchar()
if key == term.KC_ESC then break end
local res, strkey = pcall( string.char, key )
if res then
@@ -99,4 +99,4 @@
pwm.stop( pwmid )
term.clrscr()
-term.gotoxy( 1, 1 )
+term.moveto( 1, 1 )
Modified: branches/eagle_mmc/romfs/pong.lua
===================================================================
--- branches/eagle_mmc/romfs/pong.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/pong.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,129 +1,124 @@
---[[ To Do
- External Loop to play again, w/ UI msg
- Function lm3s_init will become a separate module, require()d here
---]]
-
-require("LM3S")
-
-function drawPaddle( y, color )
- disp.stringdraw("|", 0, y, color)
- disp.stringdraw("|", 0, y+4, color)
- disp.stringdraw("|", 0, y+8, color)
-end
-
-function updateBallPos()
- if( bx >= 121 or bx <= 4) then
- dx = -dx;
- end
-
- if(( by >= 89 ) or ( by <= 0 )) then
- dy = -dy;
- end
- disp.stringdraw( ball, bx, by, 0 )
- bx, by = ( bx + dx ), ( by + dy );
- disp.stringdraw( ball, bx, by, 15 )
-end
-
-function updatePaddlePos()
- if LM3S.btnpressed( LM3S.BTN_UP ) then
- if ( py > 0 ) then
- drawPaddle( py, 0 )
- py = py - 1
- drawPaddle( py, 11 )
- end
- elseif LM3S.btnpressed( LM3S.BTN_DOWN ) then
- if ( py < 80 ) then
- drawPaddle( py, 0 )
- py = py + 1
- drawPaddle( py, 11 )
- end
- else
- tmr.delay( 0, 400 ) -- Maintain function processing time aprox the same
- end
-end
-
------------- MAIN ------------
-disp.init(1000000)
-
-term.clrscr()
-term.gotoxy( 5, 1 )
-print( "Welcome to eLua Pong on a RIT display" )
-disp.stringdraw( "eLua Pong", 30, 40, 11 )
-tmr.delay ( 0, 2000000 )
-
-highscore = 0
-
-while (true) do
- play = false
-
- bx, by = 5, 48
- dx, dy = 1, 1
- py = 48
-
- score = 0
- dscore = 1
- ball = "*"
- time = 10000
-
- change = 0
-
- disp.clear()
- drawPaddle( py, 11 )
-
- while ( true ) do
- for i = 0, 1 do
- updatePaddlePos()
- tmr.delay ( 0, time )
- end
- updateBallPos()
- if ( bx == 4 ) then
- if (( by+8 < py ) or ( by > py+16 )) then
- break
- else
- score = score + dscore
- end
- end
-
- if change == 0 then
- if LM3S.btnpressed( LM3S.BTN_RIGHT ) and time > 0 then
- change = 1
- elseif LM3S.btnpressed( LM3S.BTN_LEFT ) and dscore > 1 then
- change = -1
- end
- end
-
- if ( LM3S.btnpressed( LM3S.BTN_RIGHT ) ) == false and ( LM3S.btnpressed( LM3S.BTN_LEFT ) ) == false then
- if change == 1 then
- time = time - 2000
- dscore = dscore + 1
- elseif change == -1 then
- time = time + 2000
- dscore = dscore - 1
- end
- change = 0
- end
-
- disp.stringdraw( tostring( dscore ), 118, 0, 6 )
-
- end
-
- if score > highscore then
- highscore = score
- end
-
- disp.clear()
- disp.stringdraw( "Game Over :(", 30, 20, 11 )
- disp.stringdraw( "Your score was " .. tostring( score ), 15, 40, 11 )
- disp.stringdraw( "High score: " .. tostring( highscore ), 15, 50, 11 )
- disp.stringdraw( "SELECT to restart", 6, 70, 11 )
- for i=0, 500000 do
- if LM3S.btnpressed( LM3S.BTN_SELECT ) then
- play = true
- break
- end
- end
- if play == false then
- disp.off()
- break
- end
+require("LM3S")
+
+function drawPaddle( y, color )
+ disp.print("|", 0, y, color)
+ disp.print("|", 0, y+4, color)
+ disp.print("|", 0, y+8, color)
end
+
+function updateBallPos()
+ if( bx >= 121 or bx <= 4) then
+ dx = -dx;
+ end
+
+ if(( by >= 89 ) or ( by <= 0 )) then
+ dy = -dy;
+ end
+ disp.print( ball, bx, by, 0 )
+ bx, by = ( bx + dx ), ( by + dy );
+ disp.print( ball, bx, by, 15 )
+end
+
+function updatePaddlePos()
+ if LM3S.btnpressed( LM3S.BTN_UP ) then
+ if ( py > 0 ) then
+ drawPaddle( py, 0 )
+ py = py - 1
+ drawPaddle( py, 11 )
+ end
+ elseif LM3S.btnpressed( LM3S.BTN_DOWN ) then
+ if ( py < 80 ) then
+ drawPaddle( py, 0 )
+ py = py + 1
+ drawPaddle( py, 11 )
+ end
+ else
+ tmr.delay( 0, 400 ) -- Maintain function processing time aprox the same
+ end
+end
+
+------------ MAIN ------------
+disp.init(1000000)
+
+term.clrscr()
+term.moveto( 5, 1 )
+print( "Welcome to eLua Pong on a RIT display" )
+disp.print( "eLua Pong", 30, 40, 11 )
+tmr.delay ( 0, 2000000 )
+
+highscore = 0
+
+while (true) do
+ play = false
+
+ bx, by = 5, 48
+ dx, dy = 1, 1
+ py = 48
+
+ score = 0
+ dscore = 1
+ ball = "*"
+ time = 10000
+
+ change = 0
+
+ disp.clear()
+ drawPaddle( py, 11 )
+
+ while ( true ) do
+ for i = 0, 1 do
+ updatePaddlePos()
+ tmr.delay ( 0, time )
+ end
+ updateBallPos()
+ if ( bx == 4 ) then
+ if (( by+8 < py ) or ( by > py+16 )) then
+ break
+ else
+ score = score + dscore
+ end
+ end
+
+ if change == 0 then
+ if LM3S.btnpressed( LM3S.BTN_RIGHT ) and time > 0 then
+ change = 1
+ elseif LM3S.btnpressed( LM3S.BTN_LEFT ) and dscore > 1 then
+ change = -1
+ end
+ end
+
+ if ( LM3S.btnpressed( LM3S.BTN_RIGHT ) ) == false and ( LM3S.btnpressed( LM3S.BTN_LEFT ) ) == false then
+ if change == 1 then
+ time = time - 2000
+ dscore = dscore + 1
+ elseif change == -1 then
+ time = time + 2000
+ dscore = dscore - 1
+ end
+ change = 0
+ end
+
+ disp.print( tostring( dscore ), 118, 0, 6 )
+
+ end
+
+ if score > highscore then
+ highscore = score
+ end
+
+ disp.clear()
+ disp.print( "Game Over :(", 30, 20, 11 )
+ disp.print( "Your score was " .. tostring( score ), 15, 40, 11 )
+ disp.print( "High score: " .. tostring( highscore ), 15, 50, 11 )
+ disp.print( "SELECT to restart", 6, 70, 11 )
+ for i=0, 500000 do
+ if LM3S.btnpressed( LM3S.BTN_SELECT ) then
+ play = true
+ break
+ end
+ end
+ if play == false then
+ disp.off()
+ break
+ end
+end
Modified: branches/eagle_mmc/romfs/pwmled.lua
===================================================================
--- branches/eagle_mmc/romfs/pwmled.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/pwmled.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
-- Control LED intensity with PWM
local pwmid, tmrid, ledpin
-if pd.board() == 'EK-LM3S8962' or pd.board() == 'EK-LM3S6965' or pd.board() == 'EAGLE-100' then
+if pd.board() == 'EK-LM3S8962' or pd.board() == 'EK-LM3S6965' or pd.board() == 'ET-STM32' or pd.board() == 'EAGLE-100' then
pwmid, tmrid = 0, 1
pwm.setclock( pwmid, 25000000 )
else
@@ -12,9 +12,10 @@
print "Control LED with PWM (fade up/down)"
print "Press any key to exit"
local crtduty, incr = 10, 5
+tmr.start( tmrid )
pwm.setup( pwmid, 50000, crtduty )
pwm.start( pwmid )
-while uart.recv( 0, 0, 0 ) < 0 do
+while uart.getchar( 0, 0 ) == "" do
if crtduty == 95 or crtduty == 5 then
incr = -incr
end
Modified: branches/eagle_mmc/romfs/test.lua
===================================================================
--- branches/eagle_mmc/romfs/test.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/test.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,4 +1,5 @@
-print "<html><body>"
-print "Hello from eLua!<br>"
-print 'Press <a href="/">here</a> to return to the main page.'
-print "</body></html>"
+print "<html><body>"
+print "Hello from eLua!<br>"
+print 'Press <a href="/">here</a> to return to the main page.'
+print "</body></html>"
+
Modified: branches/eagle_mmc/romfs/tvbgone.lua
===================================================================
--- branches/eagle_mmc/romfs/tvbgone.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/romfs/tvbgone.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -12,16 +12,16 @@
if pd.board() == 'EK-LM3S8962' or pd.board() == 'EK-LM3S6965' then
pwmid, tmrid = 2, 1
pwm.setclock( pwmid, 25000000 )
- led, startpin, exitpin = "PF_0", "PF_1", "PE_1"
+ led, startpin, exitpin = pio.PF_0, pio.PF_1, pio.PE_1
else
print( pd.board() .. " not supported with this example" )
return
end
-- Setup PIO
-gpio.dir[ led ] = gpio.OUTPUT
-gpio.dir[ startpin ], gpio.dir[ exitpin ] = gpio.INPUT, gpio.INPUT
-gpio.pull[ startpin ], gpio.pull[ exitpin ] = gpio.PULLUP, gpio.PULLUP
+pio.pin.setdir( pio.OUTPUT, led )
+pio.pin.setdir( pio.INPUT, startpin, exitpin )
+pio.pin.setpull( pio.PULLUP, startpin, exitpin )
-- Local variables
local _, fstr, freq, timesstr, ontime, offtime, runme
@@ -30,14 +30,14 @@
collectgarbage( "stop" )
runme = true
while runme do
- while gpio[ startpin ] == 1 do
- if gpio[ exitpin ] == 0 then
+ while pio.pin.getval( startpin ) == 1 do
+ if pio.pin.getval( exitpin ) == 0 then
runme = false
break
end
end
if not runme then break end
- gpio[ led ] = 1
+ pio.pin.sethigh( led )
codes:seek( "set", 0 )
while true do
fstr = codes:read( 4 )
@@ -53,7 +53,7 @@
pwm.stop( pwmid )
if offtime == 0 then break end
tmr.delay( tmrid, offtime * 10 )
- if gpio[ exitpin ] == 0 then
+ if pio.pin.getval( exitpin ) == 0 then
runme = false
break
end
@@ -61,7 +61,7 @@
if not runme then break end
tmr.delay( tmrid, 250000 )
end
- gpio[ led ] = 0
+ pio.pin.setlow( led )
if not runme then break end
tmr.delay( tmrid, 500000 )
end
Added: branches/eagle_mmc/run_elua_sim.sh
===================================================================
--- branches/eagle_mmc/run_elua_sim.sh 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/run_elua_sim.sh 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+stty -echo raw -igncr
+./elua_lua_linux.elf
+stty echo cooked
Property changes on: branches/eagle_mmc/run_elua_sim.sh
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/buf.c
===================================================================
--- branches/eagle_mmc/src/buf.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/buf.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -90,9 +90,11 @@
int buf_write( unsigned resid, unsigned resnum, t_buf_data *data )
{
BUF_GETPTR( resid, resnum );
-
- memcpy( &pbuf->buf[ pbuf->wptr ], data, BUF_REALDSIZE( pbuf ) );
+ const char* s = ( const char* )data;
+ char* d = ( char* )( pbuf->buf + pbuf->wptr );
+ DUFF_DEVICE_8( BUF_REALDSIZE( pbuf ), *d++ = *s++ );
+
BUF_MOD_INCR( pbuf, wptr );
if( pbuf->count == BUF_REALSIZE( pbuf ) )
@@ -143,14 +145,17 @@
if( READ16( pbuf->count ) == 0 )
return PLATFORM_UNDERFLOW;
- memcpy( data, &pbuf->buf[ pbuf->rptr ], BUF_REALDSIZE( pbuf ) );
+ const char* s = ( const char* )( pbuf->buf + pbuf->rptr );
+ char* d = ( char* )data;
+
+ DUFF_DEVICE_8( BUF_REALDSIZE( pbuf ), *d++ = *s++ );
platform_cpu_disable_interrupts();
pbuf->count --;
BUF_MOD_INCR( pbuf, rptr );
platform_cpu_enable_interrupts();
- return PLATFORM_OK;
+ return PLATFORM_OK;
}
#endif // #ifdef BUF_ENABLE
Modified: branches/eagle_mmc/src/common.c
===================================================================
--- branches/eagle_mmc/src/common.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/common.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -8,9 +8,106 @@
#include "buf.h"
#include <stdio.h>
#include <stdlib.h>
+#include <ctype.h>
#include "math.h"
#include "elua_adc.h"
+#include "term.h"
+#include "xmodem.h"
+// ****************************************************************************
+// XMODEM support code
+
+#ifdef BUILD_XMODEM
+
+static void xmodem_send( u8 data )
+{
+ platform_uart_send( CON_UART_ID, data );
+}
+
+static int xmodem_recv( u32 timeout )
+{
+ return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, timeout );
+}
+
+#endif // #ifdef BUILD_XMODEM
+
+// ****************************************************************************
+// Terminal support code
+
+#ifdef BUILD_TERM
+
+#define TERM_TIMEOUT 100000
+
+static void term_out( u8 data )
+{
+ platform_uart_send( CON_UART_ID, data );
+}
+
+static int term_in( int mode )
+{
+ if( mode == TERM_INPUT_DONT_WAIT )
+ return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, 0 );
+ else
+ return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, PLATFORM_UART_INFINITE_TIMEOUT );
+}
+
+static int term_translate( int data )
+{
+ int c;
+
+ if( isprint( data ) )
+ return data;
+ else if( data == 0x1B ) // escape sequence
+ {
+ // If we don't get a second char, we got a simple "ESC", so return KC_ESC
+ // If we get a second char it must be '[', the next one is relevant for us
+ if( platform_uart_recv( CON_UART_ID, CON_TIMER_ID, TERM_TIMEOUT ) == -1 )
+ return KC_ESC;
+ if( ( c = platform_uart_recv( CON_UART_ID, CON_TIMER_ID, TERM_TIMEOUT ) ) == -1 )
+ return KC_UNKNOWN;
+ switch( c )
+ {
+ case 0x41:
+ return KC_UP;
+ case 0x42:
+ return KC_DOWN;
+ case 0x43:
+ return KC_RIGHT;
+ case 0x44:
+ return KC_LEFT;
+ }
+ }
+ else if( data == 0x0D )
+ {
+ // CR/LF sequence, read the second char (LF) if applicable
+ platform_uart_recv( CON_UART_ID, CON_TIMER_ID, TERM_TIMEOUT );
+ return KC_ENTER;
+ }
+ else
+ {
+ switch( data )
+ {
+ case 0x09:
+ return KC_TAB;
+ case 0x16:
+ return KC_PAGEDOWN;
+ case 0x15:
+ return KC_PAGEUP;
+ case 0x05:
+ return KC_END;
+ case 0x01:
+ return KC_HOME;
+ case 0x7F:
+ case 0x08:
+ return KC_BACKSPACE;
+ }
+ }
+ return KC_UNKNOWN;
+}
+
+#endif // #ifdef BUILD_TERM
+
+
// *****************************************************************************
// std functions and platform initialization
@@ -20,9 +117,9 @@
platform_uart_send( CON_UART_ID, c );
}
-static int uart_recv()
+static int uart_recv( s32 to )
{
- return platform_uart_recv( CON_UART_ID, 0, PLATFORM_UART_INFINITE_TIMEOUT );
+ return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, to );
}
void cmn_platform_init()
@@ -30,6 +127,16 @@
// Set the send/recv functions
std_set_send_func( uart_send );
std_set_get_func( uart_recv );
+
+#ifdef BUILD_XMODEM
+ // Initialize XMODEM
+ xmodem_init( xmodem_send, xmodem_recv );
+#endif
+
+#ifdef BUILD_TERM
+ // Initialize terminal
+ term_init( TERM_LINES, TERM_COLS, term_out, term_in, term_translate );
+#endif
}
// ****************************************************************************
@@ -167,7 +274,7 @@
int platform_timer_exists( unsigned id )
{
#if VTMR_NUM_TIMERS > 0
- if( TIMER_IS_VIRTUAL( id ) )
+ if( id >= VTMR_FIRST_ID )
return TIMER_IS_VIRTUAL( id );
else
#endif
@@ -235,8 +342,17 @@
}
// ****************************************************************************
+// CAN functions
+
+int platform_can_exists( unsigned id )
+{
+ return id < NUM_CAN;
+}
+
+// ****************************************************************************
// SPI functions
+
int platform_spi_exists( unsigned id )
{
return id < NUM_SPI;
@@ -261,8 +377,6 @@
// ****************************************************************************
// ADC functions
-
-
int platform_adc_exists( unsigned id )
{
return id < NUM_ADC;
@@ -272,7 +386,8 @@
u32 platform_adc_op( unsigned id, int op, u32 data )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
u32 res = 0;
switch( op )
@@ -281,47 +396,71 @@
res = pow( 2, ADC_BIT_RESOLUTION ) - 1;
break;
- case PLATFORM_ADC_GET_SMOOTHING:
- res = (u16) 1 << s->logsmoothlen;
- break;
-
case PLATFORM_ADC_SET_SMOOTHING:
res = adc_update_smoothing( id, ( u8 )intlog2( ( unsigned ) data ) );
break;
- case PLATFORM_ADC_SET_NONBLOCKING:
- s->nonblocking = data;
+ case PLATFORM_ADC_SET_BLOCKING:
+ s->blocking = data;
break;
+
+ case PLATFORM_ADC_IS_DONE:
+ res = ( s->op_pending == 0 );
+ break;
- case PLATFORM_ADC_FLUSH:
- adc_flush_smoothing( id );
- buf_flush( BUF_ID_ADC, id );
+ case PLATFORM_ADC_OP_SET_TIMER:
+ if ( d->timer_id != data )
+ d->running = 0;
+ platform_adc_stop( id );
+ d->timer_id = data;
break;
+
+ case PLATFORM_ADC_OP_SET_CLOCK:
+ res = platform_adc_setclock( id, data );
+ break;
+
+ case PLATFORM_ADC_SET_FREERUNNING:
+ s->freerunning = data;
+ break;
}
return res;
}
-#endif
+#endif // #ifdef BUILD_ADC
// ****************************************************************************
// Allocator support
+#define MIN_ALIGN 8
+#define MIN_ALIGN_SHIFT 3
+
extern char end[];
void* platform_get_first_free_ram( unsigned id )
{
void* mstart[] = MEM_START_ADDRESS;
-
- return id >= sizeof( mstart ) / sizeof( void* ) ? NULL : mstart[ id ];
+ u32 p;
+
+ if( id >= sizeof( mstart ) / sizeof( void* ) )
+ return NULL;
+ p = ( u32 )mstart[ id ];
+ if( p & ( MIN_ALIGN - 1 ) )
+ p = ( ( p >> MIN_ALIGN_SHIFT ) + 1 ) << MIN_ALIGN_SHIFT;
+ return ( void* )p;
}
void* platform_get_last_free_ram( unsigned id )
{
void* mend[] = MEM_END_ADDRESS;
-
- return id >= sizeof( mend ) / sizeof( void* ) ? NULL : mend[ id ];
+ u32 p;
+
+ if( id >= sizeof( mend ) / sizeof( void* ) )
+ return NULL;
+ p = ( u32 )mend[ id ];
+ if( p & ( MIN_ALIGN - 1 ) )
+ p = ( ( p >> MIN_ALIGN_SHIFT ) - 1 ) << MIN_ALIGN_SHIFT;
+ return ( void* )p;
}
-
// ****************************************************************************
// Misc support
unsigned int intlog2( unsigned int v )
@@ -335,15 +474,3 @@
return r;
}
-u32 rndpow2( u32 v )
-{
- v--;
- v |= v >> 1;
- v |= v >> 2;
- v |= v >> 4;
- v |= v >> 8;
- v |= v >> 16;
- v++;
-
- return v;
-}
\ No newline at end of file
Modified: branches/eagle_mmc/src/elua_adc.c
===================================================================
--- branches/eagle_mmc/src/elua_adc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/elua_adc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,49 +6,153 @@
#include "elua_adc.h"
#include "platform.h"
#include <stdlib.h>
+#include "utils.h"
#define SMOOTH_REALSIZE( s ) ( ( u16 )1 << ( s->logsmoothlen ) )
// Primary set of pointers to channel states
-elua_adc_state adc_state[ NUM_ADC ];
+elua_adc_ch_state adc_ch_state[ NUM_ADC ];
+elua_adc_dev_state adc_dev_state;
-elua_adc_state *adc_get_ch_state( unsigned id )
+elua_adc_ch_state *adc_get_ch_state( unsigned id )
{
- return &adc_state[ id ];
+ return &adc_ch_state[ id ];
}
-// Initialize Configuration and Buffers
-void adc_init_state( unsigned id )
+elua_adc_dev_state *adc_get_dev_state( unsigned dev_id )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ return &adc_dev_state;
+}
+
+// Rewrite revice sequence
+void adc_update_dev_sequence( unsigned dev_id )
+{
+ elua_adc_dev_state *d = adc_get_dev_state( dev_id );
+ elua_adc_ch_state *s;
+ unsigned id;
+ if( d->ch_active != d->last_ch_active || d->force_reseq == 1 )
+ {
+ platform_cpu_disable_interrupts();
+ // Update channel sequence
+ d->seq_ctr = 0;
+ for( id = 0; id < NUM_ADC; id ++ )
+ {
+ if ( ( d->ch_active & ( ( u32 )1 << ( id ) ) ) > 0 )
+ {
+ s = adc_get_ch_state( id );
+ d->ch_state[ d->seq_ctr ] = s;
+ s->value_ptr = &( d->sample_buf[ d->seq_ctr ] );
+ s->value_fresh = 0;
+ d->seq_ctr++;
+ }
+ }
+ d->seq_len = d->seq_ctr;
+
+ // Null out remainder of sequence
+ while( d->seq_ctr < NUM_ADC )
+ d->ch_state[ d->seq_ctr++ ] = NULL;
+
+ d->seq_ctr = 0;
+
+ // Sync up hardware
+ platform_adc_update_sequence();
+
+ d->last_ch_active = d->ch_active;
+ d->seq_ctr = 0;
+ d->force_reseq = 0;
+ platform_cpu_enable_interrupts();
+ }
+}
+
+// Set up channel in preparation for sample acquisition
+int adc_setup_channel( unsigned id, u8 logcount )
+{
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+#if defined( BUF_ENABLE_ADC )
+ int res;
+
+ platform_cpu_disable_interrupts();
+ if( ( (u16) 1 << logcount ) != buf_get_size( BUF_ID_ADC, id ) )
+ {
+ res = buf_set( BUF_ID_ADC, id, logcount, BUF_DSIZE_U16 );
+ if ( res != PLATFORM_OK )
+ return res;
+ buf_flush( BUF_ID_ADC, id );
+ }
+#endif
+
+ s->reqsamples = (u16) 1 << logcount;
+ s->op_pending = 1;
+
+ ACTIVATE_CHANNEL( d, id );
+ platform_cpu_enable_interrupts();
+
+ return PLATFORM_OK;
+}
+
+// Initialize channel configuration and buffers
+void adc_init_ch_state( unsigned id )
+{
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+ INACTIVATE_CHANNEL(d, id);
+
// Initialize Configuration
s->op_pending = 0;
- s->nonblocking = 0;
- s->burst = 0;
+ s->blocking = 1;
s->smooth_ready = 0;
s->reqsamples = 0;
+ s->freerunning = 0;
s->id = id;
- s->timer_id = 0;
s->logsmoothlen = 0;
s->smoothidx = 0;
// Data Configuration
s->smoothsum = 0;
-
+
+#if defined( BUF_ENABLE_ADC )
// Buffer initialization
buf_set( BUF_ID_ADC, id, ADC_BUF_SIZE, BUF_DSIZE_U16 );
+#endif
+
+ // Set to run as fast as possible
+ platform_adc_setclock( id, 0 );
}
-int adc_update_smoothing( unsigned id, u8 loglen )
+void adc_init_dev_state( unsigned dev_id )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ elua_adc_dev_state *d = adc_get_dev_state( dev_id );
+ d->seq_id = 0;
+ d->running = 0;
+ d->ch_active = 0;
+ d->last_ch_active = 0;
+ d->force_reseq = 0;
+ d->skip_cycle = 0;
+}
+
+// Update smoothing buffer length
+// If operations are pending, stop them. If new length differs from
+// existing length, attempt to resize. Whether size is new or not,
+// re-initialize buffers so that they are ready for new data.
+int adc_update_smoothing( unsigned id, u8 loglen )
+{
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ // Stop sampling if still running
+ if ( s->op_pending == 1 )
+ {
+ platform_adc_stop( id );
+ }
+
+ // Update smoothing length if necessary
if( loglen != s->logsmoothlen )
{
s->logsmoothlen = loglen;
-
+
// Allocate and zero new smoothing buffer
if( ( s->smoothbuf = ( u16* )realloc( s->smoothbuf, ( SMOOTH_REALSIZE( s ) ) * sizeof( u16 ) ) ) == NULL )
{
@@ -57,16 +161,24 @@
if( loglen != 0 )
return PLATFORM_ERR;
}
+ }
- // Zero out and mark as empty
- adc_flush_smoothing( id );
- }
+ // Even if buffer isn't actually reconfigured, flush contents
+ adc_flush_smoothing( id );
+
+#if defined( BUF_ENABLE_ADC )
+ buf_flush( BUF_ID_ADC, id );
+#endif
+
return PLATFORM_OK;
}
+// Load oldest sample from the buffer, replace oldest value in smoothing ring
+// buffer with this new sample. Subtract previous oldest sample value from
+// sum and add new sample to sum.
void adc_smooth_data( unsigned id )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ elua_adc_ch_state *s = adc_get_ch_state( id );
u16 sample;
if( s->smoothidx == SMOOTH_REALSIZE( s ) )
@@ -79,7 +191,18 @@
s->smoothsum -= s->smoothbuf[ s->smoothidx ];
// Replace Oldest Value in Buffer
- buf_read( BUF_ID_ADC, id, ( t_buf_data* )&sample );
+#if defined( BUF_ENABLE_ADC )
+ if ( s->value_fresh == 1 )
+ {
+ sample = *( s->value_ptr );
+ s->value_fresh = 0;
+ }
+ else
+ buf_read( BUF_ID_ADC, id, ( t_buf_data* )&sample );
+#else
+ sample = *( s->value_ptr );
+ s->value_fresh = 0;
+#endif
s->smoothbuf[ s->smoothidx ] = sample;
// Add New Sample to Sum
@@ -88,12 +211,26 @@
s->smoothidx++;
}
+// Get samples from the buffer
+// If samples are available and...
+// Smoothing is enabled
+// If smoothing is warmed up, put oldest buffer sample into smoothing
+// buffer and return result of this sample averaged with length-1
+// previous samples which had been loaded into the smoothing buffer.
+// Decrements count of requested samples.
+//
+// Smoothing is off
+// Return results directly from the buffer. Decrements count of requested
+// samples.
+//
+// If samples are not available...
+// return 0
u16 adc_get_processed_sample( unsigned id )
{
- elua_adc_state *s = adc_get_ch_state( id );
- u16 sample;
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ u16 sample = 0;
- if ( buf_get_count( BUF_ID_ADC, id ) > 0 )
+ if ( adc_samples_available( id ) > 0 )
{
if ( ( s->logsmoothlen > 0) && ( s->smooth_ready == 1 ) )
{
@@ -102,59 +239,75 @@
if ( s->reqsamples > 0)
s->reqsamples -- ;
- return (u16) s->smoothsum >> s->logsmoothlen;
-
+ sample = (u16) ( s->smoothsum >> s->logsmoothlen );
}
else if ( s->logsmoothlen == 0 )
{
- buf_read( BUF_ID_ADC, id, ( t_buf_data* )&sample );
-
+#if defined( BUF_ENABLE_ADC )
+ if( s->value_fresh == 1 )
+ {
+ sample = *( s->value_ptr );
+ s->value_fresh = 0;
+ }
+ else
+ buf_read( BUF_ID_ADC, id, ( t_buf_data* )&sample );
+#else
+ sample = *( s->value_ptr );
+ s->value_fresh = 0;
+#endif
if ( s->reqsamples > 0)
s->reqsamples -- ;
-
- return sample;
}
}
- else
- return 0;
+ return sample;
}
+// Zero out and reset smoothing buffer
void adc_flush_smoothing( unsigned id )
{
- elua_adc_state *s = adc_get_ch_state( id );
- u8 i;
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ u16 i = 0;
s->smoothidx = 0;
s->smoothsum = 0;
s->smooth_ready = 0;
if ( s->logsmoothlen > 0 )
- {
- for( i = 0; i < ( SMOOTH_REALSIZE( s ) ); i ++ )
- s->smoothbuf[ i ] = 0;
- }
+ DUFF_DEVICE_8( SMOOTH_REALSIZE( s ), s->smoothbuf[ i++ ] = 0 );
}
+// Number of samples requested that have not yet been removed from the buffer
u16 adc_samples_requested( unsigned id )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ elua_adc_ch_state *s = adc_get_ch_state( id );
return s->reqsamples;
}
+// Return count of available samples in the buffer
u16 adc_samples_available( unsigned id )
{
- return ( u16 ) buf_get_count( BUF_ID_ADC, id );
+elua_adc_ch_state *s = adc_get_ch_state( id );
+
+#if defined( BUF_ENABLE_ADC )
+ u16 buffer_count = ( u16 )buf_get_count( BUF_ID_ADC, id );
+ return ( ( buffer_count == 0 ) ? s->value_fresh : buffer_count );
+#else
+ return s->value_fresh;
+#endif
}
-void adc_wait_pending( unsigned id )
+// If blocking is enabled, wait until we have enough samples or the current
+// sampling event has finished, returns number of available samples when
+// function does exit
+u16 adc_wait_samples( unsigned id, unsigned samples )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ elua_adc_ch_state *s = adc_get_ch_state( id );
- if ( s->nonblocking == 0 && s->op_pending == 1 )
- {
- while ( s->op_pending == 1 ) { ; }
- }
+ if( adc_samples_available( id ) < samples && s->blocking == 1 )
+ while( s->op_pending == 1 && adc_samples_available( id ) < samples );
+
+ return adc_samples_available( id );
}
+#endif
-#endif
\ No newline at end of file
Modified: branches/eagle_mmc/src/lua/ldump.c
===================================================================
--- branches/eagle_mmc/src/lua/ldump.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/ldump.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -91,24 +91,24 @@
DumpIntWithSize(x,D->target.sizeof_int,D);
}
-static void DumpSize(size_t x, DumpState* D)
+static void DumpSize(int32_t x, DumpState* D)
{
/* dump unsigned integer */
- switch(D->target.sizeof_size_t) {
+ switch(D->target.sizeof_strsize_t) {
case 1: {
if (x>0xFF) D->status=LUA_ERR_CC_INTOVERFLOW;
DumpChar(x,D);
} break;
case 2: {
if (x>0xFFFF) D->status=LUA_ERR_CC_INTOVERFLOW;
- unsigned short y=x;
+ uint16_t y=(uint16_t)x;
MaybeByteSwap((char*)&y,2,D);
DumpVar(y,D);
} break;
case 4: {
/* Reduce bounds to avoid messing 32-bit compilers up */
if (x>0xFFFFFFFE) D->status=LUA_ERR_CC_INTOVERFLOW;
- unsigned long y=x;
+ uint32_t y=x;
MaybeByteSwap((char*)&y,4,D);
DumpVar(y,D);
} break;
@@ -170,12 +170,12 @@
{
if (s==NULL || getstr(s)==NULL)
{
- size_t size=0;
+ strsize_t size=0;
DumpSize(size,D);
}
else
{
- size_t size=s->tsv.len+1; /* include trailing '\0' */
+ strsize_t size=s->tsv.len+1; /* include trailing '\0' */
DumpSize(size,D);
DumpBlock(getstr(s),size,D);
}
@@ -264,7 +264,7 @@
*h++=(char)LUAC_FORMAT;
*h++=(char)D->target.little_endian;
*h++=(char)D->target.sizeof_int;
- *h++=(char)D->target.sizeof_size_t;
+ *h++=(char)D->target.sizeof_strsize_t;
*h++=(char)sizeof(Instruction);
*h++=(char)D->target.sizeof_lua_Number;
*h++=(char)D->target.lua_Number_integral;
@@ -298,7 +298,7 @@
int test=1;
target.little_endian=*(char*)&test;
target.sizeof_int=sizeof(int);
- target.sizeof_size_t=sizeof(size_t);
+ target.sizeof_strsize_t=sizeof(strsize_t);
target.sizeof_lua_Number=sizeof(lua_Number);
target.lua_Number_integral=(((lua_Number)0.5)==0);
target.is_arm_fpa=0;
Modified: branches/eagle_mmc/src/lua/linit.c
===================================================================
--- branches/eagle_mmc/src/lua/linit.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/linit.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -19,6 +19,12 @@
#include "platform_conf.h"
#endif
+#ifdef LUA_REMOTE
+#include "auxmods.h"
+#define LUA_PLATFORM_LIBS_ROM \
+ _ROM( AUXLIB_LUARPC, luaopen_luarpc, rpc_map )
+#endif
+
static const luaL_Reg lualibs[] = {
{"", luaopen_base},
{LUA_LOADLIBNAME, luaopen_package},
Modified: branches/eagle_mmc/src/lua/liolib.c
===================================================================
--- branches/eagle_mmc/src/lua/liolib.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/liolib.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -30,12 +30,14 @@
#else
#define LUA_IO_GETFIELD(f) lua_rawgeti(L, LUA_REGISTRYINDEX, liolib_keys[f])
#define LUA_IO_SETFIELD(f) lua_rawseti(L, LUA_REGISTRYINDEX, liolib_keys[f])
-#endif
-static const char *const fnames[] = {"input", "output"};
/* "Pseudo-random" keys for the registry */
static const int liolib_keys[] = {(int)&luaL_callmeta, (int)&luaL_typerror, (int)&luaL_argerror};
+#endif
+static const char *const fnames[] = {"input", "output"};
+
+
static int pushresult (lua_State *L, int i, const char *filename) {
int en = errno; /* calls to Lua API may change this value */
if (i) {
Modified: branches/eagle_mmc/src/lua/lua.c
===================================================================
--- branches/eagle_mmc/src/lua/lua.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/lua.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -376,7 +376,11 @@
}
+#ifdef LUA_REMOTE
int main (int argc, char **argv) {
+#else
+int lua_main (int argc, char **argv) {
+#endif
int status;
struct Smain s;
lua_State *L = lua_open(); /* create state */
Modified: branches/eagle_mmc/src/lua/luac.c
===================================================================
--- branches/eagle_mmc/src/lua/luac.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/luac.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -104,7 +104,7 @@
++version;
else if (IS("-cci")) /* target integer size */
{
- int s = target.sizeof_int = target.sizeof_size_t = atoi(argv[++i])/8;
+ int s = target.sizeof_int = atoi(argv[++i])/8;
if (!(s==1 || s==2 || s==4)) fatal(LUA_QL("-cci") " must be 8, 16 or 32");
}
else if (IS("-ccn")) /* target lua_Number type and size */
@@ -224,7 +224,7 @@
int test=1;
target.little_endian=*(char*)&test;
target.sizeof_int=sizeof(int);
- target.sizeof_size_t=sizeof(size_t);
+ target.sizeof_strsize_t=sizeof(strsize_t);
target.sizeof_lua_Number=sizeof(lua_Number);
target.lua_Number_integral=(((lua_Number)0.5)==0);
target.is_arm_fpa=0;
Modified: branches/eagle_mmc/src/lua/luaconf.h
===================================================================
--- branches/eagle_mmc/src/lua/luaconf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/luaconf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -89,13 +89,14 @@
//## Modified for eLua
//## Defaults search modules path to our ROM File System
+
+#ifndef LUA_REMOTE
#define LUA_PATH_DEFAULT "\\ROM\\?.lua"
-/*
-** ## Original LUA_PATH_DEFAULT
+#else
#define LUA_PATH_DEFAULT \
".\\?.lua;" LUA_LDIR"?.lua;" LUA_LDIR"?\\init.lua;" \
LUA_CDIR"?.lua;" LUA_CDIR"?\\init.lua"
-*/
+#endif
#define LUA_CPATH_DEFAULT \
".\\?.dll;" LUA_CDIR"?.dll;" LUA_CDIR"loadall.dll"
@@ -103,12 +104,15 @@
#define LUA_ROOT "/usr/local/"
#define LUA_LDIR LUA_ROOT "share/lua/5.1/"
#define LUA_CDIR LUA_ROOT "lib/lua/5.1/"
+
+#ifndef LUA_REMOTE
#define LUA_PATH_DEFAULT "/rom/?.lua"
-/*
+#else
+
#define LUA_PATH_DEFAULT \
"./?.lua;" LUA_LDIR"?.lua;" LUA_LDIR"?/init.lua;" \
LUA_CDIR"?.lua;" LUA_CDIR"?/init.lua"
-*/
+#endif
#define LUA_CPATH_DEFAULT \
"./?.so;" LUA_CDIR"?.so;" LUA_CDIR"loadall.so"
#endif
@@ -313,7 +317,7 @@
** mean larger pauses which mean slower collection.) You can also change
** this value dynamically.
*/
-#define LUAI_GCPAUSE 200 /* 200% (wait memory to double before next GC) */
+#define LUAI_GCPAUSE 110 /* 110% (wait memory to grow 10% before next gc) */
/*
@@ -831,7 +835,9 @@
/* If you define the next macro you'll get the ability to set rotables as
metatables for tables/userdata/types (but the VM might run slower)
*/
-#define LUA_META_ROTABLES
+#ifndef LUA_CROSS_COMPILER
+#define LUA_META_ROTABLES
+#endif
#if LUA_OPTIMIZE_MEMORY == 2 && LUA_USE_POPEN
#error "Pipes not supported in aggresive optimization mode (LUA_OPTIMIZE_MEMORY=2)"
Modified: branches/eagle_mmc/src/lua/lundump.c
===================================================================
--- branches/eagle_mmc/src/lua/lundump.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/lundump.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -25,6 +25,9 @@
ZIO* Z;
Mbuffer* b;
const char* name;
+ int swap;
+ int numsize;
+ int toflt;
} LoadState;
#ifdef LUAC_TRUST_BINARIES
@@ -40,7 +43,6 @@
}
#endif
-#define LoadMem(S,b,n,size) LoadBlock(S,b,(n)*(size))
#define LoadByte(S) (lu_byte)LoadChar(S)
#define LoadVar(S,x) LoadMem(S,&x,1,sizeof(x))
#define LoadVector(S,b,n,size) LoadMem(S,b,n,size)
@@ -51,6 +53,49 @@
IF (r!=0, "unexpected end");
}
+static void LoadMem (LoadState* S, void* b, int n, size_t size)
+{
+ LoadBlock(S,b,n*size);
+ if (S->swap)
+ {
+ char* p=(char*) b;
+ char c;
+ switch (size)
+ {
+ case 1:
+ break;
+ case 2:
+ while (n--)
+ {
+ c=p[0]; p[0]=p[1]; p[1]=c;
+ p+=2;
+ }
+ break;
+ case 4:
+ while (n--)
+ {
+ c=p[0]; p[0]=p[3]; p[3]=c;
+ c=p[1]; p[1]=p[2]; p[2]=c;
+ p+=4;
+ }
+ break;
+ case 8:
+ while (n--)
+ {
+ c=p[0]; p[0]=p[7]; p[7]=c;
+ c=p[1]; p[1]=p[6]; p[6]=c;
+ c=p[2]; p[2]=p[5]; p[5]=c;
+ c=p[3]; p[3]=p[4]; p[4]=c;
+ p+=8;
+ }
+ break;
+ default:
+ IF(1, "bad size");
+ break;
+ }
+ }
+}
+
static int LoadChar(LoadState* S)
{
char x;
@@ -69,13 +114,43 @@
static lua_Number LoadNumber(LoadState* S)
{
lua_Number x;
- LoadVar(S,x);
+ if(S->toflt)
+ {
+ switch(S->numsize)
+ {
+ case 1: {
+ int8_t y;
+ LoadVar(S,y);
+ x = (lua_Number)y;
+ } break;
+ case 2: {
+ int16_t y;
+ LoadVar(S,y);
+ x = (lua_Number)y;
+ } break;
+ case 4: {
+ int32_t y;
+ LoadVar(S,y);
+ x = (lua_Number)y;
+ } break;
+ case 8: {
+ int64_t y;
+ LoadVar(S,y);
+ x = (lua_Number)y;
+ } break;
+ default: lua_assert(0);
+ }
+ }
+ else
+ {
+ LoadVar(S,x); /* should probably handle more cases for float here... */
+ }
return x;
}
static TString* LoadString(LoadState* S)
{
- size_t size;
+ int32_t size;
LoadVar(S,size);
if (size==0)
return NULL;
@@ -184,8 +259,13 @@
{
char h[LUAC_HEADERSIZE];
char s[LUAC_HEADERSIZE];
+ int intck = (((lua_Number)0.5)==0); /* 0=float, 1=int */
luaU_header(h);
LoadBlock(S,s,LUAC_HEADERSIZE);
+ S->swap=(s[6]!=h[6]); s[6]=h[6]; /* Check if byte-swapping is needed */
+ S->numsize=h[10]=s[10]; /* length of lua_Number */
+ S->toflt=(s[11]>intck); /* check if conversion from int lua_Number to flt is needed */
+ if(S->toflt) s[11]=h[11];
IF (memcmp(h,s,LUAC_HEADERSIZE)!=0, "bad header");
}
@@ -220,7 +300,7 @@
*h++=(char)LUAC_FORMAT;
*h++=(char)*(char*)&x; /* endianness */
*h++=(char)sizeof(int);
- *h++=(char)sizeof(size_t);
+ *h++=(char)sizeof(int32_t);
*h++=(char)sizeof(Instruction);
*h++=(char)sizeof(lua_Number);
*h++=(char)(((lua_Number)0.5)==0); /* is lua_Number integral? */
Modified: branches/eagle_mmc/src/lua/lundump.h
===================================================================
--- branches/eagle_mmc/src/lua/lundump.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/lua/lundump.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -7,14 +7,18 @@
#ifndef lundump_h
#define lundump_h
+#include <stdint.h>
+
#include "lobject.h"
#include "lzio.h"
+typedef uint32_t strsize_t;
+
/* info about target machine for cross-compilation */
typedef struct {
int little_endian;
int sizeof_int;
- int sizeof_size_t;
+ int sizeof_strsize_t;
int sizeof_lua_Number;
int lua_Number_integral;
int is_arm_fpa;
Added: branches/eagle_mmc/src/luarpc_elua_uart.c
===================================================================
--- branches/eagle_mmc/src/luarpc_elua_uart.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/luarpc_elua_uart.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,103 @@
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+#include "platform.h"
+#include "platform_conf.h"
+#include "luarpc_rpc.h"
+
+#ifdef BUILD_LUARPC
+
+int uart_timeout = PLATFORM_UART_INFINITE_TIMEOUT;
+
+/* Setup Transport */
+void transport_init (Transport *tpt)
+{
+ tpt->fd = INVALID_TRANSPORT;
+}
+
+/* Open Listener / Server */
+void transport_open_listener(lua_State *L, ServerHandle *handle)
+{
+ /* Get args & Set up connection */
+
+ handle->ltpt.fd = CON_UART_ID;
+}
+
+/* Open Connection / Client */
+int transport_open_connection(lua_State *L, Handle *handle)
+{
+ handle->tpt.fd = CON_UART_ID;
+ return 0;
+}
+
+/* Accept Connection */
+void transport_accept (Transport *tpt, Transport *atpt)
+{
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ atpt->fd = tpt->fd;
+}
+
+
+
+void transport_read_buffer (Transport *tpt, u8 *buffer, int length)
+{
+ int n = 0;
+ int c;
+ struct exception e;
+
+ while( n < length )
+ {
+ TRANSPORT_VERIFY_OPEN;
+ c = platform_uart_recv( CON_UART_ID, CON_TIMER_ID, uart_timeout );
+
+ if( c < 0 )
+ {
+ uart_timeout = 1000000; /* Reset and use timeout of 1s */
+ e.errnum = ERR_NODATA;
+ e.type = nonfatal;
+ Throw( e );
+ }
+ else
+ {
+ buffer[ n ] = ( u8 ) c;
+ n++;
+ }
+ /* After getting one char of a read, remainder should follow within a timeout of 0.1 sec */
+ uart_timeout = 100000;
+ }
+
+ uart_timeout = PLATFORM_UART_INFINITE_TIMEOUT;
+}
+
+void transport_write_buffer( Transport *tpt, const u8 *buffer, int length )
+{
+ int i;
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+
+ for( i = 0; i < length; i ++ )
+ platform_uart_send( CON_UART_ID, buffer[ i ] );
+}
+
+/* Check if data is available on connection without reading:
+ - 1 = data available, 0 = no data available */
+int transport_readable (Transport *tpt)
+{
+ return 1; /* no really easy way to check this unless platform support is added */
+}
+
+/* Check if transport is open:
+ - 1 = connection open, 0 = connection closed */
+int transport_is_open (Transport *tpt)
+{
+ return (tpt->fd != INVALID_TRANSPORT);
+}
+
+/* Shut down connection */
+void transport_close (Transport *tpt)
+{
+ tpt->fd = INVALID_TRANSPORT;
+}
+
+#endif
\ No newline at end of file
Added: branches/eagle_mmc/src/luarpc_posix_serial.c
===================================================================
--- branches/eagle_mmc/src/luarpc_posix_serial.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/luarpc_posix_serial.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,204 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/fcntl.h>
+#include <sys/file.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <sys/select.h>
+#include <sys/ioctl.h>
+#include <termios.h>
+#include <errno.h>
+#include <string.h>
+#include <alloca.h>
+
+/* FIXME: I know not all of the above is necessary, should pare it down sometime */
+
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+
+#include "luarpc_rpc.h"
+
+#ifdef LUARPC_ENABLE_SERIAL
+
+/* Setup Transport */
+void transport_init (Transport *tpt)
+{
+ tpt->fd = INVALID_TRANSPORT;
+}
+
+void transport_open( Transport *tpt, const char *path )
+{
+ struct termios options;
+ struct exception e;
+
+ tpt->fd = open(path , O_RDWR | O_NOCTTY | O_NDELAY );
+
+ if( tpt->fd == INVALID_TRANSPORT)
+ {
+ e.errnum = errno;
+ e.type = fatal;
+ Throw( e );
+ }
+
+ tcgetattr( tpt->fd, &options);
+
+ cfsetispeed( &options, B115200 );
+ cfsetospeed( &options, B115200 );
+
+ options.c_cflag |= (CLOCAL | CREAD);
+
+ /* raw processing */
+ options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG);
+ options.c_oflag &= ~OPOST;
+
+ /* 8N1 */
+ options.c_cflag &= ~PARENB;
+ options.c_cflag &= ~CSTOPB;
+ options.c_cflag &= ~CSIZE;
+ options.c_cflag |= CS8;
+
+ options.c_cc[VMIN] = 1;
+ options.c_cc[VTIME] = 10;
+
+ tcsetattr(tpt->fd, TCSANOW, &options);
+ fcntl(tpt->fd, F_SETFL, 0);
+}
+
+/* Open Listener / Server */
+void transport_open_listener(lua_State *L, ServerHandle *handle)
+{
+ check_num_args (L,2); /* 1st arg is path, 2nd is handle */
+ if (!lua_isstring (L,1))
+ my_lua_error (L,"first argument must be serial serial port");
+
+ transport_open( &handle->ltpt, lua_tostring (L,1) );
+
+ while( transport_readable ( &handle->ltpt ) == 0 ); /* wait for incoming data */
+}
+
+/* Open Connection / Client */
+int transport_open_connection(lua_State *L, Handle *handle)
+{
+ check_num_args (L,2); /* 1st arg is path, 2nd is handle */
+ if (!lua_isstring (L,1))
+ my_lua_error (L,"first argument must be serial serial port");
+
+ transport_open( &handle->tpt, lua_tostring (L,1) );
+
+ return 1;
+}
+
+/* Accept Connection */
+void transport_accept (Transport *tpt, Transport *atpt)
+{
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ atpt->fd = tpt->fd;
+}
+
+
+/* Read & Write to Transport */
+void transport_read_buffer (Transport *tpt, u8 *buffer, int length)
+{
+ int n;
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+
+ while( length > 0 )
+ {
+ TRANSPORT_VERIFY_OPEN;
+
+ n = read( tpt->fd, ( void * )buffer, length );
+
+ /* error handling */
+ if( n == 0 )
+ {
+ e.errnum = ERR_NODATA;
+ e.type = nonfatal;
+ Throw( e );
+ }
+
+ if( n < 0 )
+ {
+ e.errnum = errno;
+ e.type = fatal;
+ Throw( e );
+ }
+
+ buffer += n;
+ length -= n;
+ }
+}
+
+void transport_write_buffer( Transport *tpt, const u8 *buffer, int length )
+{
+ int n;
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+
+ n = write( tpt->fd, buffer,length );
+
+ if ( n != length )
+ {
+ e.errnum = errno;
+ e.type = fatal;
+ Throw( e );
+ }
+}
+
+/* Check if data is available on connection without reading:
+ - 1 = data available, 0 = no data available */
+int transport_readable (Transport *tpt)
+{
+ struct exception e;
+ fd_set rdfs;
+ int ret;
+ struct timeval tv;
+
+ if (tpt->fd == INVALID_TRANSPORT)
+ return 0;
+
+ FD_ZERO (&rdfs);
+ FD_SET (tpt->fd, &rdfs);
+
+ /* Wait up to five seconds. */
+ tv.tv_sec = 5;
+ tv.tv_usec = 0;
+
+ ret = select( tpt->fd+1, &rdfs, NULL, NULL, &tv );
+
+ if ( ret < 0 )
+ {
+ e.errnum = errno;
+ e.type = fatal;
+ Throw( e );
+ }
+
+ return ( ret > 0 );
+}
+
+/* Check if transport is open:
+ 1 = connection open, 0 = connection closed */
+int transport_is_open (Transport *tpt)
+{
+ return (tpt->fd != INVALID_TRANSPORT);
+}
+
+/* Shut down connection */
+void transport_close (Transport *tpt)
+{
+ if (tpt->fd != INVALID_TRANSPORT)
+ {
+ /* close (tpt->fd); -- not closing for now since atpt and ltpt use same fd,
+ should use some method to detect whether one has
+ already dropped, and properly close out on exit */
+
+ /* Send break to the other side to indicate to opposing side that connection is ending */
+ tcsendbreak(tpt->fd, 0);
+ tpt->fd = INVALID_TRANSPORT;
+ }
+}
+
+#endif /* LUARPC_ENABLE_SERIAL */
Modified: branches/eagle_mmc/src/main.c
===================================================================
--- branches/eagle_mmc/src/main.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/main.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -10,6 +10,9 @@
#include "lua.h"
#include "term.h"
#include "platform_conf.h"
+#ifdef ELUA_SIMULATOR
+#include "hostif.h"
+#endif
// Validate eLua configuratin options
#include "validate.h"
@@ -26,97 +29,6 @@
extern char etext[];
// ****************************************************************************
-// XMODEM support code
-
-#ifdef BUILD_XMODEM
-
-static void xmodem_send( u8 data )
-{
- platform_uart_send( CON_UART_ID, data );
-}
-
-static int xmodem_recv( u32 timeout )
-{
- return platform_uart_recv( CON_UART_ID, XMODEM_TIMER_ID, timeout );
-}
-
-#endif // #ifdef BUILD_XMODEM
-
-// ****************************************************************************
-// Terminal support code
-
-#ifdef BUILD_TERM
-
-static void term_out( u8 data )
-{
- platform_uart_send( CON_UART_ID, data );
-}
-
-static int term_in( int mode )
-{
- if( mode == TERM_INPUT_DONT_WAIT )
- return platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, 0 );
- else
- return platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, PLATFORM_UART_INFINITE_TIMEOUT );
-}
-
-static int term_translate( u8 data )
-{
- int c;
-
- if( isprint( data ) )
- return data;
- else if( data == 0x1B ) // escape sequence
- {
- // If we don't get a second char, we got a simple "ESC", so return KC_ESC
- // If we get a second char it must be '[', the next one is relevant for us
- if( platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, TERM_TIMEOUT ) == -1 )
- return KC_ESC;
- if( ( c = platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, TERM_TIMEOUT ) ) == -1 )
- return KC_UNKNOWN;
- switch( c )
- {
- case 0x41:
- return KC_UP;
- case 0x42:
- return KC_DOWN;
- case 0x43:
- return KC_RIGHT;
- case 0x44:
- return KC_LEFT;
- }
- }
- else if( data == 0x0D )
- {
- // CR/LF sequence, read the second char (LF) if applicable
- platform_uart_recv( CON_UART_ID, TERM_TIMER_ID, TERM_TIMEOUT );
- return KC_ENTER;
- }
- else
- {
- switch( data )
- {
- case 0x09:
- return KC_TAB;
- case 0x16:
- return KC_PAGEDOWN;
- case 0x15:
- return KC_PAGEUP;
- case 0x05:
- return KC_END;
- case 0x01:
- return KC_HOME;
- case 0x7F:
- case 0x08:
- return KC_BACKSPACE;
- }
- }
- return KC_UNKNOWN;
-}
-
-#endif // #ifdef BUILD_TERM
-
-// ****************************************************************************
// Program entry point
int main( void )
@@ -139,16 +51,6 @@
// Register the ROM filesystem
dm_register( romfs_init() );
-#ifdef BUILD_XMODEM
- // Initialize XMODEM
- xmodem_init( xmodem_send, xmodem_recv );
-#endif
-
-#ifdef BUILD_TERM
- // Initialize terminal
- term_init( TERM_LINES, TERM_COLS, term_out, term_in, term_translate );
-#endif
-
#ifdef FS_AUTORUN
// Autorun: if "autorun.lua" is found in the file system, run it first
if( ( fp = fopen( FS_AUTORUN, "r" ) ) != NULL )
@@ -170,5 +72,11 @@
else
shell_start();
+#ifdef ELUA_SIMULATOR
+ hostif_exit(0);
+ return 0;
+#else
while( 1 );
+#endif
}
+
Modified: branches/eagle_mmc/src/modules/adc.c
===================================================================
--- branches/eagle_mmc/src/modules/adc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/adc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -4,6 +4,7 @@
#include "lualib.h"
#include "lauxlib.h"
#include "platform.h"
+#include "common.h"
#include "auxmods.h"
#include "lrotable.h"
#include "platform_conf.h"
@@ -11,67 +12,72 @@
#ifdef BUILD_ADC
-// Lua: sample( id )
-static int adc_sample( lua_State* L )
+// Lua: data = maxval( id )
+static int adc_maxval( lua_State* L )
{
unsigned id;
- int res;
+ u32 res;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
- res = platform_adc_sample( id );
-
- if ( res != PLATFORM_OK )
- return luaL_error( L, "burst failed" );
-
- return 0;
+ res = platform_adc_op( id, PLATFORM_ADC_GET_MAXVAL, 0 );
+ lua_pushinteger( L, res );
+ return 1;
}
-// Lua: maxval( id )
-static int adc_maxval( lua_State* L )
+// Lua: realclock = setclock( id, clock, [timer_id] )
+static int adc_setclock( lua_State* L )
{
- unsigned id;
- u32 res;
+ u32 clock;
+ unsigned id, timer_id = 0;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
- res = platform_adc_op( id, PLATFORM_ADC_GET_MAXVAL, 0 );
- lua_pushinteger( L, res );
+ clock = luaL_checkinteger( L, 2 );
+ if ( clock > 0 )
+ {
+ timer_id = luaL_checkinteger( L, 3 );
+ MOD_CHECK_ID( timer, timer_id );
+ MOD_CHECK_RES_ID( adc, id, timer, timer_id );
+ }
+
+ platform_adc_op( id, PLATFORM_ADC_OP_SET_TIMER, timer_id );
+ clock = platform_adc_op( id, PLATFORM_ADC_OP_SET_CLOCK, clock );
+ lua_pushinteger( L, clock );
return 1;
}
-// Lua: samplesready( id )
-static int adc_samples_ready( lua_State* L )
+// Lua: data = isdone( id )
+static int adc_isdone( lua_State* L )
{
unsigned id;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
- lua_pushinteger( L, adc_samples_available( id ) );
+ lua_pushinteger( L, platform_adc_op( id, PLATFORM_ADC_IS_DONE, 0 ) );
return 1;
}
-// Lua: setmode( id, mode )
-static int adc_set_mode( lua_State* L )
+// Lua: setblocking( id, mode )
+static int adc_setblocking( lua_State* L )
{
unsigned id, mode;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
mode = luaL_checkinteger( L, 2 );
- platform_adc_op( id, PLATFORM_ADC_SET_NONBLOCKING, mode );
+ platform_adc_op( id, PLATFORM_ADC_SET_BLOCKING, mode );
return 0;
}
// Lua: setsmoothing( id, length )
-static int adc_set_smoothing( lua_State* L )
+static int adc_setsmoothing( lua_State* L )
{
unsigned id, length, res;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
-
length = luaL_checkinteger( L, 2 );
if ( !( length & ( length - 1 ) ) )
{
@@ -83,101 +89,141 @@
}
else
return luaL_error( L, "length must be power of 2" );
-
}
-// Lua: getsmoothing( id )
-static int adc_get_smoothing( lua_State* L )
+// Lua: sample( id, count )
+static int adc_sample( lua_State* L )
{
- unsigned id;
- u32 res;
+ unsigned id, count, nchans = 1;
+ int res, i;
- id = luaL_checkinteger( L, 1 );
- MOD_CHECK_ID( adc, id );
- res = platform_adc_op( id, PLATFORM_ADC_GET_SMOOTHING, 0 );
- lua_pushinteger( L, res );
- return 1;
+ count = luaL_checkinteger( L, 2 );
+ if ( ( count == 0 ) || count & ( count - 1 ) )
+ return luaL_error( L, "count must be power of 2 and > 0" );
+
+ // If first parameter is a table, extract channel list
+ if ( lua_istable( L, 1 ) == 1 )
+ {
+ nchans = lua_objlen(L, 1);
+
+ // Get/check list of channels and setup
+ for( i = 0; i < nchans; i++ )
+ {
+ lua_rawgeti( L, 1, i+1 );
+ id = luaL_checkinteger( L, -1 );
+ MOD_CHECK_ID( adc, id );
+
+ res = adc_setup_channel( id, intlog2( count ) );
+ if ( res != PLATFORM_OK )
+ return luaL_error( L, "sampling setup failed" );
+ }
+ // Initiate sampling
+ platform_adc_start_sequence();
+ }
+ else if ( lua_isnumber( L, 1 ) == 1 )
+ {
+ id = luaL_checkinteger( L, 1 );
+ MOD_CHECK_ID( adc, id );
+
+ res = adc_setup_channel( id, intlog2( count ) );
+ if ( res != PLATFORM_OK )
+ return luaL_error( L, "sampling setup failed" );
+
+ platform_adc_start_sequence();
+ }
+ else
+ {
+ return luaL_error( L, "invalid channel selection" );
+ }
+ return 0;
}
-// Lua: flush( id )
-static int adc_flush( lua_State* L )
+
+// Lua: val = getsample( id )
+static int adc_getsample( lua_State* L )
{
unsigned id;
- u32 res;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
- res = platform_adc_op( id, PLATFORM_ADC_FLUSH, 0 );
- lua_pushinteger( L, res );
- return 1;
+
+ // If we have at least one sample, return it
+ if ( adc_wait_samples( id, 1 ) >= 1 )
+ {
+ lua_pushinteger( L, adc_get_processed_sample( id ) );
+ return 1;
+ }
+ return 0;
}
-// Lua: burst( id, count, timer_id, frequency )
-static int adc_burst( lua_State* L )
+#if defined( BUF_ENABLE_ADC )
+// Lua: table_of_vals = getsamples( id, [count] )
+static int adc_getsamples( lua_State* L )
{
- unsigned id, timer_id, count;
- u32 frequency;
- int res;
+ unsigned id, i;
+ u16 bcnt, count = 0;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
- count = luaL_checkinteger( L, 2 );
- timer_id = luaL_checkinteger( L, 3 );
- MOD_CHECK_ID( timer, timer_id );
- frequency = luaL_checkinteger( L, 4 );
+
+ if ( lua_isnumber(L, 2) == 1 )
+ count = ( u16 )lua_tointeger(L, 2);
- if ( ( count == 0 ) || count & ( count - 1 ) )
- return luaL_error( L, "count must be power of 2 and > 0" );
+ bcnt = adc_wait_samples( id, count );
- res = platform_adc_burst( id, intlog2( count ), timer_id, frequency );
- if ( res != PLATFORM_OK )
- return luaL_error( L, "burst failed" );
-
+ // If count is zero, grab all samples
+ if ( count == 0 )
+ count = bcnt;
+
+ // Don't pull more samples than are available
+ if ( count > bcnt )
+ count = bcnt;
+
+ lua_createtable( L, count, 0 );
+ for( i = 1; i <= count; i ++ )
+ {
+ lua_pushinteger( L, adc_get_processed_sample( id ) );
+ lua_rawseti( L, -2, i );
+ }
return 0;
}
-// Lua: getsamples( id, count )
-static int adc_get_samples( lua_State* L )
+// Lua: insertsamples(id, table, idx, count)
+static int adc_insertsamples( lua_State* L )
{
- unsigned id, i, count;
- int total = lua_gettop( L );
- u16 nsamps;
+ unsigned id, i, startidx;
+ u16 bcnt, count, zcount;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( adc, id );
- nsamps = adc_samples_available( id );
- if ( total == 2 )
- count = luaL_checkinteger( L, 2 );
- else
- count = nsamps;
-
- if ( count == 0 ) { count = nsamps; } // count = 0 means grab all samples
+ luaL_checktype(L, 2, LUA_TTABLE);
- adc_wait_pending( id );
+ startidx = luaL_checkinteger( L, 3 );
+ if ( startidx <= 0 )
+ return luaL_error( L, "idx must be > 0" );
+
+ count = luaL_checkinteger(L, 4 );
+ if ( count == 0 )
+ return luaL_error( L, "count must be > 0" );
- if ( nsamps > 0 && nsamps >= count )
+ bcnt = adc_wait_samples( id, count );
+
+ for( i = startidx; i < ( count + startidx ); i ++ )
{
- if ( nsamps == 1 || count == 1 )
- {
- lua_pushinteger( L, adc_get_processed_sample( id ) );
- }
- else
- {
- lua_createtable( L, count, 0 );
- for( i = 0; i < count; i ++ )
- {
- lua_pushinteger( L, adc_get_processed_sample( id ) );
- lua_rawseti( L, -2, i+1 );
- }
- }
- return 1;
+ if ( i < bcnt + startidx )
+ lua_pushinteger( L, adc_get_processed_sample( id ) );
+ else
+ lua_pushnil( L ); // nil-out values where we don't have enough samples
+
+ lua_rawseti( L, 2, i );
}
+
return 0;
}
+#endif
-
// Module function map
#define MIN_OPT_LEVEL 2
#include "lrodefs.h"
@@ -185,13 +231,15 @@
{
{ LSTRKEY( "sample" ), LFUNCVAL( adc_sample ) },
{ LSTRKEY( "maxval" ), LFUNCVAL( adc_maxval ) },
- { LSTRKEY( "samplesready" ), LFUNCVAL( adc_samples_ready ) },
- { LSTRKEY( "setmode" ), LFUNCVAL( adc_set_mode ) },
- { LSTRKEY( "setsmoothing" ), LFUNCVAL( adc_set_smoothing ) },
- { LSTRKEY( "getsmoothing" ), LFUNCVAL( adc_get_smoothing ) },
- { LSTRKEY( "burst" ), LFUNCVAL( adc_burst ) },
- { LSTRKEY( "flush" ), LFUNCVAL( adc_flush ) },
- { LSTRKEY( "getsamples" ), LFUNCVAL( adc_get_samples ) },
+ { LSTRKEY( "setclock" ), LFUNCVAL( adc_setclock ) },
+ { LSTRKEY( "isdone" ), LFUNCVAL( adc_isdone ) },
+ { LSTRKEY( "setblocking" ), LFUNCVAL( adc_setblocking ) },
+ { LSTRKEY( "setsmoothing" ), LFUNCVAL( adc_setsmoothing ) },
+ { LSTRKEY( "getsample" ), LFUNCVAL( adc_getsample ) },
+#if defined( BUF_ENABLE_ADC )
+ { LSTRKEY( "getsamples" ), LFUNCVAL( adc_getsamples ) },
+ { LSTRKEY( "insertsamples" ), LFUNCVAL( adc_insertsamples ) },
+#endif
{ LNILKEY, LNILVAL }
};
@@ -200,4 +248,4 @@
LREGISTER( L, AUXLIB_ADC, adc_map );
}
-#endif
\ No newline at end of file
+#endif
Modified: branches/eagle_mmc/src/modules/auxmods.h
===================================================================
--- branches/eagle_mmc/src/modules/auxmods.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/auxmods.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,12 +6,15 @@
#include "lua.h"
-#define AUXLIB_PIO "gpio"
+#define AUXLIB_PIO "pio"
LUALIB_API int ( luaopen_pio )( lua_State *L );
#define AUXLIB_SPI "spi"
LUALIB_API int ( luaopen_spi )( lua_State *L );
+#define AUXLIB_CAN "can"
+LUALIB_API int ( luaopen_can )( lua_State *L );
+
#define AUXLIB_TMR "tmr"
LUALIB_API int ( luaopen_tmr )( lua_State *L );
@@ -42,10 +45,21 @@
#define AUXLIB_ADC "adc"
LUALIB_API int ( luaopen_adc )( lua_State *L );
+#define AUXLIB_LUARPC "rpc"
+LUALIB_API int ( luaopen_luarpc )( lua_State *L );
+
// Helper macros
#define MOD_CHECK_ID( mod, id )\
if( !platform_ ## mod ## _exists( id ) )\
return luaL_error( L, #mod" %d does not exist", ( unsigned )id )
+#define MOD_CHECK_RES_ID( mod, id, resmod, resid )\
+ if( !platform_ ## mod ## _check_ ## resmod ## _id( id, resid ) )\
+ return luaL_error( L, #resmod" %d not valid with " #mod " %d", ( unsigned )resid, ( unsigned )id )
+
+#define MOD_REG_NUMBER( L, name, val )\
+ lua_pushnumber( L, val );\
+ lua_setfield( L, -2, name )
+
#endif
Added: branches/eagle_mmc/src/modules/can.c
===================================================================
--- branches/eagle_mmc/src/modules/can.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/can.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,84 @@
+// Module for interfacing Lua code with a Controller Area Network (CAN)
+
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+#include "platform.h"
+#include "auxmods.h"
+#include "lrotable.h"
+
+// Lua: setup( id, clock )
+static int can_setup( lua_State* L )
+{
+ unsigned id;
+ u32 clock, res;
+
+ id = luaL_checkinteger( L, 1 );
+ MOD_CHECK_ID( can, id );
+ clock = luaL_checkinteger( L, 2 );
+ res = platform_can_setup( id, clock );
+ lua_pushinteger( L, res );
+ return 1;
+}
+
+// Lua: send( id, canid, canidtype, message )
+static int can_send( lua_State* L )
+{
+ size_t len;
+ int id, canid, idtype;
+ const char *data;
+
+ id = luaL_checkinteger( L, 1 );
+ MOD_CHECK_ID( can, id );
+ canid = luaL_checkinteger( L, 2 );
+ idtype = luaL_checkinteger( L, 3 );
+ data = luaL_checklstring (L, 4, &len);
+ if ( len > PLATFORM_CAN_MAXLEN )
+ return luaL_error( L, "message exceeds max length" );
+
+ platform_can_send( id, canid, idtype, len, ( const u8 * )data );
+
+ return 0;
+}
+
+// Lua: canid, canidtype, message = recv( id )
+static int can_recv( lua_State* L )
+{
+ u8 len;
+ int id;
+ u32 canid;
+ u8 idtype, data[ 8 ];
+
+ id = luaL_checkinteger( L, 1 );
+ MOD_CHECK_ID( can, id );
+
+ platform_can_recv( id, &canid, &idtype, &len, data );
+ lua_pushinteger( L, canid );
+ lua_pushinteger( L, idtype );
+ lua_pushlstring (L, ( const char * )data, ( size_t )len);
+
+ return 3;
+}
+
+
+// Module function map
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+const LUA_REG_TYPE can_map[] =
+{
+ { LSTRKEY( "setup" ), LFUNCVAL( can_setup ) },
+ { LSTRKEY( "send" ), LFUNCVAL( can_send ) },
+ { LSTRKEY( "recv" ), LFUNCVAL( can_recv ) },
+ { LNILKEY, LNILVAL }
+};
+
+LUALIB_API int luaopen_can( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ return 0;
+#else // #if LUA_OPTIMIZE_MEMORY > 0
+ luaL_register( L, AUXLIB_CAN, can_map );
+
+ return 1;
+#endif // #if LUA_OPTIMIZE_MEMORY > 0
+}
Added: branches/eagle_mmc/src/modules/luarpc.c
===================================================================
--- branches/eagle_mmc/src/modules/luarpc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/luarpc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,1708 @@
+/*****************************************************************************
+* Lua-RPC library, Copyright (C) 2001 Russell L. Smith. All rights reserved. *
+* Email: russ at q12.org Web: www.q12.org *
+* For documentation, see http://www.q12.org/lua. For the license agreement, *
+* see the file LICENSE that comes with this distribution. *
+*****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <alloca.h>
+
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+
+#ifndef LUA_CROSS_COMPILER
+#include "platform.h"
+#include "platform_conf.h"
+#endif
+#include "lrotable.h"
+
+#include "luarpc_rpc.h"
+
+
+#ifdef BUILD_LUARPC
+
+/* Support for Compiling with rotables */
+#ifdef LUA_OPTIMIZE_MEMORY
+#define LUA_ISCALLABLE(state, idx) ( lua_isfunction( state, idx ) || lua_islightfunction( state, idx ) )
+#else
+#define LUA_ISCALLABLE(state, idx) lua_isfunction( state, idx )
+#endif
+
+struct exception_context the_exception_context[ 1 ];
+
+static void errorMessage (const char *msg, va_list ap)
+{
+ fflush (stdout);
+ fflush (stderr);
+ fprintf (stderr,"\nError: ");
+ vfprintf (stderr,msg,ap);
+ fprintf (stderr,"\n\n");
+ fflush (stderr);
+}
+
+
+DOGCC(static void panic (const char *msg, ...)
+ __attribute__ ((noreturn,unused));)
+static void panic (const char *msg, ...)
+{
+ va_list ap;
+ va_start (ap,msg);
+ errorMessage (msg,ap);
+ exit (1);
+}
+
+
+DOGCC(static void rpcdebug (const char *msg, ...)
+ __attribute__ ((noreturn,unused));)
+static void rpcdebug (const char *msg, ...)
+{
+ va_list ap;
+ va_start (ap,msg);
+ errorMessage (msg,ap);
+ abort();
+}
+
+/* enums for variable types, commands, and status codes */
+
+enum {
+ RPC_NIL=0,
+ RPC_NUMBER,
+ RPC_BOOLEAN,
+ RPC_STRING,
+ RPC_TABLE,
+ RPC_TABLE_END,
+ RPC_FUNCTION,
+ RPC_FUNCTION_END
+};
+
+enum
+{
+ RPC_CMD_CALL = 1,
+ RPC_CMD_GET,
+ RPC_CMD_CON,
+ RPC_CMD_NEWINDEX
+};
+
+enum
+{
+ RPC_READY = 64,
+ RPC_UNSUPPORTED_CMD,
+ RPC_DONE
+};
+
+enum { RPC_PROTOCOL_VERSION = 3 };
+
+
+/* return a string representation of an error number */
+
+static const char * errorString (int n)
+{
+ switch (n) {
+ case ERR_EOF: return "connection closed unexpectedly (\"end of file\")";
+ case ERR_CLOSED: return "operation requested on a closed transport";
+ case ERR_PROTOCOL: return "error in the received LuaRPC protocol";
+ case ERR_COMMAND: return "undefined RPC command";
+ case ERR_DATALINK: return "transmission error at data link level";
+ case ERR_NODATA: return "no data received when attempting to read";
+ case ERR_BADFNAME: return "function name is too long";
+ case RPC_UNSUPPORTED_CMD: return "an unsupported action was requested";
+ case ERR_HEADER: return "header exchanged failed";
+ default: return transport_strerror (n);
+ }
+}
+
+
+/****************************************************************************/
+/* transport layer generics */
+
+/* read from the transport into a string buffer. */
+
+static void transport_read_string( Transport *tpt, const char *buffer, int length )
+{
+ transport_read_buffer( tpt, ( u8 * )buffer, length );
+}
+
+
+/* write a string buffer to the transport */
+
+static void transport_write_string( Transport *tpt, const char *buffer, int length )
+{
+ transport_write_buffer( tpt, ( u8 * )buffer, length );
+}
+
+
+/* read a u8 from the transport */
+
+static u8 transport_read_u8( Transport *tpt )
+{
+ u8 b;
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ transport_read_buffer( tpt, &b, 1 );
+ return b;
+}
+
+
+/* write a u8 to the transport */
+
+static void transport_write_u8( Transport *tpt, u8 x )
+{
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ transport_write_buffer( tpt, &x, 1 );
+}
+
+static void swap_bytes( char *number, size_t numbersize )
+{
+ int i;
+ for (i=0; i<numbersize/2; i++)
+ {
+ char temp = number[i];
+ number[i] = number[numbersize-1-i];
+ number[numbersize-1-i] = temp;
+ }
+}
+
+union u32_bytes {
+ uint32_t i;
+ uint8_t b[ 4 ];
+};
+
+/* read a u32 from the transport */
+static u32 transport_read_u32( Transport *tpt )
+{
+ union u32_bytes ub;
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ transport_read_buffer ( tpt, ub.b, 4 );
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( (char *)ub.b, 4 );
+ return ub.i;
+}
+
+
+/* write a u32 to the transport */
+static void transport_write_u32( Transport *tpt, u32 x )
+{
+ union u32_bytes ub;
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ ub.i = ( uint32_t )x;
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( ( char * )ub.b, 4 );
+ transport_write_buffer( tpt, ub.b, 4 );
+}
+
+/* read a lua number from the transport */
+
+static lua_Number transport_read_number( Transport *tpt )
+{
+ lua_Number x;
+ u8 b[ tpt->lnum_bytes ];
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+ transport_read_buffer ( tpt, b, tpt->lnum_bytes );
+
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( ( char * )b, tpt->lnum_bytes );
+
+ if( tpt->net_intnum != tpt->loc_intnum )
+ {
+ switch( tpt->lnum_bytes )
+ {
+ case 1: {
+ int8_t y = *( int8_t * )b;
+ x = ( lua_Number )y;
+ } break;
+ case 2: {
+ int16_t y = *( int16_t * )b;
+ x = ( lua_Number )y;
+ } break;
+ case 4: {
+ int32_t y = *( int32_t * )b;
+ x = ( lua_Number )y;
+ } break;
+ case 8: {
+ int64_t y = *( int64_t * )b;
+ x = ( lua_Number )y;
+ } break;
+ default: lua_assert(0);
+ }
+ }
+ else
+ x = ( lua_Number ) *( lua_Number * )b;
+
+ return x;
+}
+
+
+/* write a lua number to the transport */
+static void transport_write_number (Transport *tpt, lua_Number x)
+{
+ struct exception e;
+ TRANSPORT_VERIFY_OPEN;
+
+ if( tpt->net_intnum )
+ {
+ switch( tpt->lnum_bytes )
+ {
+ case 1: {
+ int8_t y = ( int8_t )x;
+ transport_write_buffer( tpt, ( char * )&y, 1 );
+ } break;
+ case 2: {
+ int16_t y = ( int16_t )x;
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( ( char * )&y, 2 );
+ transport_write_buffer( tpt, ( char * )&y, 2 );
+ } break;
+ case 4: {
+ int32_t y = ( int32_t )x;
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( ( char * )&y, 4 );
+ transport_write_buffer( tpt, (char *)&y, 4 );
+ } break;
+ case 8: {
+ int64_t y = ( int64_t )x;
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( ( char * )&y, 8 );
+ transport_write_buffer( tpt, (char *)&y, 8 );
+ } break;
+ default: lua_assert(0);
+ }
+ }
+ else
+ {
+ if( tpt->net_little != tpt->loc_little )
+ swap_bytes( ( char * )&x, 8 );
+ transport_write_buffer( tpt, ( char * )&x, 8 );
+ }
+}
+
+
+
+/****************************************************************************/
+/* lua utility */
+
+/* replacement for lua_error that resets the exception stack before leaving
+ * Lua-RPC.
+ */
+
+void my_lua_error( lua_State *L, const char *errmsg )
+{
+ lua_pushstring( L, errmsg );
+ lua_error( L );
+}
+
+int check_num_args( lua_State *L, int desired_n )
+{
+ int n = lua_gettop( L ); /* number of arguments on stack */
+ if ( n != desired_n )
+ {
+ char s[ 100 ]; /* @@@ can we cut this down? */
+ sprintf( s, "must have %d argument%c", desired_n,
+ ( desired_n == 1 ) ? '\0' : 's' );
+ my_lua_error( L, s );
+ }
+ return n;
+}
+
+static int ismetatable_type( lua_State *L, int ud, const char *tname )
+{
+ if( lua_getmetatable( L, ud ) ) { /* does it have a metatable? */
+ lua_getfield( L, LUA_REGISTRYINDEX, tname ); /* get correct metatable */
+ if( lua_rawequal( L, -1, -2 ) ) { /* does it have the correct mt? */
+ lua_pop( L, 2 ); /* remove both metatables */
+ return 1;
+ }
+ }
+ return 0;
+}
+
+
+
+/****************************************************************************/
+/* read and write lua variables to a transport.
+ * these functions do little error handling of their own, but they call transport
+ * functions which may throw exceptions, so calls to these functions must be
+ * wrapped in a Try block.
+ */
+
+/* write a table at the given index in the stack. the index must be absolute
+ * (i.e. positive).
+ */
+
+static void write_variable( Transport *tpt, lua_State *L, int var_index );
+static int read_variable( Transport *tpt, lua_State *L );
+
+static void write_table( Transport *tpt, lua_State *L, int table_index )
+{
+ lua_pushnil( L ); /* push first key */
+ while ( lua_next( L, table_index ) )
+ {
+ /* next key and value were pushed on the stack */
+ write_variable( tpt, L, lua_gettop( L ) - 1 );
+ write_variable( tpt, L, lua_gettop( L ) );
+ /* remove value, keep key for next iteration */
+ lua_pop( L, 1 );
+ }
+}
+
+static int writer( lua_State *L, const void* b, size_t size, void* B ) {
+ (void)L;
+ luaL_addlstring((luaL_Buffer*) B, (const char *)b, size);
+ return 0;
+}
+
+#include "lundump.h"
+#include "ldo.h"
+
+static void write_function( Transport *tpt, lua_State *L, int var_index )
+{
+ TValue *o;
+ luaL_Buffer b;
+ DumpTargetInfo target;
+
+ target.little_endian=tpt->net_little;
+ target.sizeof_int=sizeof(int);
+ target.sizeof_strsize_t=sizeof(strsize_t);
+ target.sizeof_lua_Number=tpt->lnum_bytes;
+ target.lua_Number_integral=tpt->net_intnum;
+ target.is_arm_fpa=0;
+
+ /* push function onto stack, serialize to string */
+ lua_pushvalue( L, var_index );
+ luaL_buffinit( L, &b );
+ lua_lock(L);
+ o = L->top - 1;
+ luaU_dump_crosscompile(L,clvalue(o)->l.p,writer,&b,0,target);
+ lua_unlock(L);
+ /* put string representation on stack and send it */
+ luaL_pushresult( &b );
+ write_variable( tpt, L, lua_gettop( L ) );
+
+ /* Remove function & dumped string from stack*/
+ lua_pop( L, 2 );
+}
+
+
+/* write a variable at the given index in the stack. the index must be absolute
+ * (i.e. positive).
+ */
+
+static void write_variable( Transport *tpt, lua_State *L, int var_index )
+{
+ int stack_at_start = lua_gettop( L );
+
+ switch( lua_type( L, var_index ) )
+ {
+ case LUA_TNUMBER:
+ transport_write_u8( tpt, RPC_NUMBER );
+ transport_write_number( tpt, lua_tonumber( L, var_index ) );
+ break;
+
+ case LUA_TSTRING:
+ {
+ const char *s;
+ u32 len;
+ transport_write_u8( tpt, RPC_STRING );
+ s = lua_tostring( L, var_index );
+ len = lua_strlen( L, var_index );
+ transport_write_u32( tpt, len );
+ transport_write_string( tpt, s, len );
+ break;
+ }
+
+ case LUA_TTABLE:
+ transport_write_u8( tpt, RPC_TABLE );
+ write_table( tpt, L, var_index );
+ transport_write_u8( tpt, RPC_TABLE_END );
+ break;
+
+ case LUA_TNIL:
+ transport_write_u8( tpt, RPC_NIL );
+ break;
+
+ case LUA_TBOOLEAN:
+ transport_write_u8( tpt,RPC_BOOLEAN );
+ transport_write_u8( tpt, ( u8 )lua_toboolean( L, var_index ) );
+ break;
+
+ case LUA_TFUNCTION:
+ transport_write_u8( tpt, RPC_FUNCTION );
+ write_function( tpt, L, var_index );
+ transport_write_u8( tpt, RPC_FUNCTION_END );
+ break;
+
+ case LUA_TUSERDATA:
+ my_lua_error( L, "can't pass user data to a remote function" );
+ break;
+
+ case LUA_TTHREAD:
+ my_lua_error( L, "can't pass threads to a remote function" );
+ break;
+
+ case LUA_TLIGHTUSERDATA:
+ my_lua_error( L, "can't pass light user data to a remote function" );
+ break;
+ }
+ MYASSERT( lua_gettop( L ) == stack_at_start );
+}
+
+
+/* read a table and push in onto the stack */
+static void read_table( Transport *tpt, lua_State *L )
+{
+ int table_index;
+ lua_newtable( L );
+ table_index = lua_gettop( L );
+ for ( ;; )
+ {
+ if( !read_variable( tpt, L ) )
+ return;
+ read_variable( tpt, L );
+ lua_rawset( L, table_index );
+ }
+}
+
+static void read_function( Transport *tpt, lua_State *L )
+{
+ const char *b;
+ size_t len;
+
+ for( ;; )
+ {
+ if( !read_variable( tpt, L ) )
+ return;
+
+ b = luaL_checklstring( L, -1, &len );
+ luaL_loadbuffer( L, b, len, b );
+ lua_insert( L, -2 );
+ lua_pop( L, 1 );
+ }
+}
+
+
+/* read a variable and push in onto the stack. this returns 1 if a "normal"
+ * variable was read, or 0 if an end-table marker was read (in which case
+ * nothing is pushed onto the stack).
+ */
+
+static int read_variable( Transport *tpt, lua_State *L )
+{
+ struct exception e;
+ u8 type = transport_read_u8( tpt );
+
+ switch( type )
+ {
+ case RPC_NIL:
+ lua_pushnil( L );
+ break;
+
+ case RPC_BOOLEAN:
+ lua_pushboolean( L, transport_read_u8( tpt ) );
+ break;
+
+ case RPC_NUMBER:
+ lua_pushnumber( L, transport_read_number( tpt ) );
+ break;
+
+ case RPC_STRING:
+ {
+ u32 len = transport_read_u32( tpt );
+ char *s = ( char * )alloca( len + 1 );
+ transport_read_string( tpt, s, len );
+ s[ len ] = 0;
+ lua_pushlstring( L, s, len );
+ break;
+ }
+
+ case RPC_TABLE:
+ read_table( tpt, L );
+ break;
+
+ case RPC_TABLE_END:
+ return 0;
+
+ case RPC_FUNCTION:
+ read_function( tpt, L );
+ break;
+
+ case RPC_FUNCTION_END:
+ return 0;
+
+ default:
+ e.errnum = type;
+ e.type = fatal;
+ Throw( e );
+ }
+ return 1;
+}
+
+
+/****************************************************************************/
+/* rpc utility */
+
+/* functions for sending and receving headers
+ */
+
+static void client_negotiate( Transport *tpt )
+{
+ struct exception e;
+ char header[ 8 ];
+ int x = 1;
+
+ tpt->loc_little = (char)*(char*)&x;
+ tpt->lnum_bytes = (char)sizeof(lua_Number);
+ tpt->loc_intnum = (char)(((lua_Number)0.5)==0);
+
+ /* write the protocol header */
+ header[0] = 'L';
+ header[1] = 'R';
+ header[2] = 'P';
+ header[3] = 'C';
+ header[4] = RPC_PROTOCOL_VERSION;
+ header[5] = tpt->loc_little;
+ header[6] = tpt->lnum_bytes;
+ header[7] = tpt->loc_intnum;
+ transport_write_string( tpt, header, sizeof( header ) );
+
+
+ /* read response with wire configuration */
+ transport_read_string( tpt, header, sizeof( header ) );
+ if( header[0] != 'L' ||
+ header[1] != 'R' ||
+ header[2] != 'P' ||
+ header[3] != 'C' ||
+ header[4] != RPC_PROTOCOL_VERSION )
+ {
+ e.errnum = ERR_HEADER;
+ e.type = nonfatal;
+ Throw( e );
+ }
+
+ tpt->net_little = header[5];
+ tpt->lnum_bytes = header[6];
+ tpt->net_intnum = header[7];
+}
+
+static void server_negotiate( Transport *tpt )
+{
+ struct exception e;
+ char header[ 8 ];
+ int x = 1;
+
+ tpt->net_little = tpt->loc_little = (char)*(char*)&x;
+ tpt->lnum_bytes = (char)sizeof(lua_Number);
+ tpt->net_intnum = tpt->loc_intnum = (char)(((lua_Number)0.5)==0);
+
+
+ /* check that the header is ok */
+ transport_read_string( tpt, header, sizeof( header ) );
+ if( header[0] != 'L' ||
+ header[1] != 'R' ||
+ header[2] != 'P' ||
+ header[3] != 'C' ||
+ header[4] != RPC_PROTOCOL_VERSION )
+ {
+ e.errnum = ERR_HEADER;
+ e.type = nonfatal;
+ Throw( e );
+ }
+
+ /* check if endianness differs, if so use big endian order */
+ if( header[ 5 ] != tpt->loc_little )
+ header[ 5 ] = tpt->net_little = 0;
+
+ /* set number precision to lowest common denominator */
+ if( header[ 6 ] > tpt->lnum_bytes )
+ header[ 6 ] = tpt->lnum_bytes;
+ if( header[ 6 ] < tpt->lnum_bytes )
+ tpt->lnum_bytes = header[ 6 ];
+
+ /* if lua_Number is integer on either side, use integer */
+ if( header[ 7 ] != tpt->loc_intnum )
+ header[ 7 ] = tpt->net_intnum = 1;
+
+ transport_write_string( tpt, header, sizeof( header ) );
+}
+
+/****************************************************************************/
+/* client side handle and handle helper userdata objects.
+ *
+ * a handle userdata (handle to a RPC server) is a pointer to a Handle object.
+ * a helper userdata is a pointer to a Helper object.
+ *
+ * helpers let us make expressions like:
+ * handle.funcname (a,b,c)
+ * "handle.funcname" returns the helper object, which calls the remote
+ * function.
+ */
+
+/* global error handling */
+static int global_error_handler = LUA_NOREF; /* function reference */
+
+/* handle a client or server side error. NOTE: this function may or may not
+ * return. the handle `h' may be 0.
+ */
+
+void deal_with_error(lua_State *L, Handle *h, const char *error_string)
+{
+ if( global_error_handler != LUA_NOREF )
+ {
+ lua_getref( L, global_error_handler );
+ lua_pushstring( L, error_string );
+ lua_pcall( L, 1, 0, 0 );
+ }
+ else
+ my_lua_error( L, error_string );
+}
+
+
+Handle *handle_create( lua_State *L )
+{
+ Handle *h = ( Handle * )lua_newuserdata( L, sizeof( Handle ) );
+ luaL_getmetatable( L, "rpc.handle" );
+ lua_setmetatable( L, -2 );
+ h->error_handler = LUA_NOREF;
+ h->async = 0;
+ h->read_reply_count = 0;
+ return h;
+}
+
+static Helper *helper_create( lua_State *L, Handle *handle, const char *funcname )
+{
+ Helper *h = ( Helper * )lua_newuserdata( L, sizeof( Helper ) );
+ luaL_getmetatable( L, "rpc.helper" );
+ lua_setmetatable( L, -2 );
+ h->handle = handle;
+ h->parent = NULL;
+ h->nparents = 0;
+ strncpy ( h->funcname, funcname, NUM_FUNCNAME_CHARS );
+ return h;
+}
+
+
+/* indexing a handle returns a helper */
+static int handle_index (lua_State *L)
+{
+ const char *s;
+ Helper *h;
+
+ MYASSERT( lua_gettop( L ) == 2 );
+ MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
+
+ if( lua_type( L, 2 ) != LUA_TSTRING )
+ my_lua_error( L, "can't index a handle with a non-string" );
+ s = lua_tostring( L, 2 );
+ if ( strlen( s ) > NUM_FUNCNAME_CHARS - 1 )
+ my_lua_error( L, "function name is too long" );
+
+ h = helper_create( L, ( Handle * )lua_touserdata( L, 1 ), s );
+
+ /* return the helper object */
+ return 1;
+}
+
+static int helper_newindex( lua_State *L );
+
+/* indexing a handle returns a helper */
+static int handle_newindex( lua_State *L )
+{
+ const char *s;
+ Helper *h;
+
+ MYASSERT( lua_gettop( L ) == 3 );
+ MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
+
+ if( lua_type( L, 2 ) != LUA_TSTRING )
+ my_lua_error( L, "can't index a handle with a non-string" );
+ s = lua_tostring( L, 2 );
+ if ( strlen( s ) > NUM_FUNCNAME_CHARS - 1 )
+ my_lua_error( L, "function name is too long" );
+
+ h = helper_create( L, ( Handle * )lua_touserdata( L, 1 ), "" );
+ lua_replace(L, 1);
+
+ helper_newindex( L );
+
+ return 0;
+}
+
+/* replays series of indexes to remote side as a string */
+static void helper_remote_index( Helper *helper )
+{
+ int i, len;
+ Helper **hstack;
+ Transport *tpt = &helper->handle->tpt;
+
+ /* get length of name & make stack of helpers */
+ len = strlen( helper->funcname );
+ if( helper->nparents > 0 )
+ {
+ hstack = ( Helper ** )alloca( sizeof( Helper * ) * helper->nparents );
+ hstack[ helper->nparents - 1 ] = helper->parent;
+ len += strlen( hstack[ helper->nparents - 1 ]->funcname ) + 1;
+
+ for(i = helper->nparents - 1 ; i > 0 ; i -- )
+ {
+ hstack[ i - 1 ] = hstack[ i ]->parent;
+ len += strlen( hstack[ i ]->funcname ) + 1;
+ }
+ }
+
+ transport_write_u32( tpt, len );
+ /* replay helper key names */
+ if( helper->nparents > 0)
+ {
+ for( i = 0 ; i < helper->nparents ; i ++ )
+ {
+ transport_write_string( tpt, hstack[ i ]->funcname, strlen( hstack[ i ]->funcname ) );
+ transport_write_string( tpt, ".", 1 );
+ }
+ }
+ transport_write_string( tpt, helper->funcname, strlen( helper->funcname ) );
+}
+
+static void helper_wait_ready( Transport *tpt, u8 cmd )
+{
+ struct exception e;
+ u8 cmdresp;
+
+ transport_write_u8( tpt, cmd );
+ cmdresp = transport_read_u8( tpt );
+ if( cmdresp != RPC_READY )
+ {
+ e.errnum = ERR_PROTOCOL;
+ e.type = nonfatal;
+ Throw( e );
+ }
+
+}
+
+static int helper_get(lua_State *L, Helper *helper )
+{
+ struct exception e;
+ int freturn = 0;
+ Transport *tpt = &helper->handle->tpt;
+
+ Try
+ {
+ int len;
+ u8 cmdresp;
+ /* write function name */
+ len = strlen( helper->funcname );
+ helper_wait_ready( tpt, RPC_CMD_GET );
+ helper_remote_index( helper );
+
+ read_variable( tpt, L );
+
+ freturn = 1;
+ }
+ Catch( e )
+ {
+ switch( e.type )
+ {
+ case fatal:
+ if ( e.errnum == ERR_CLOSED )
+ my_lua_error( L, "can't refer to a remote function after the handle has been closed" );
+ deal_with_error( L, helper->handle, errorString( e.errnum ) );
+ transport_close( tpt );
+ break;
+ case nonfatal:
+ deal_with_error( L, helper->handle, errorString( e.errnum ) );
+ lua_pushnil( L );
+ return 1;
+ break;
+ default:
+ deal_with_error( L, helper->handle, errorString( e.errnum ) );
+ transport_close( tpt );
+ break;
+ }
+ }
+ return freturn;
+}
+
+
+// static int helper_async( lua_State *L )
+// {
+// /* first read out any pending return values for old async calls */
+// for (; h->handle->read_reply_count > 0; h->handle->read_reply_count--) {
+// ret_code = transport_read_u8 (tpt); /* return code */
+// if( ret_code == 0 )
+// {
+// /* read return arguments, ignore everything we read */
+// nret = transport_read_u32( tpt );
+//
+// for (i=0; i < ( ( int ) nret ); i++)
+// read_variable (tpt,L);
+//
+// lua_pop (L,nret);
+// }
+// else
+// {
+// /* read error and handle it */
+// u32 code = transport_read_u32( tpt );
+// u32 len = transport_read_u32( tpt );
+// char *err_string = ( char * )alloca( len + 1 );
+// transport_read_string( tpt, err_string, len );
+// err_string[ len ] = 0;
+//
+// deal_with_error( L, h->handle, err_string );
+// freturn = 0;
+// }
+// }
+// }
+
+
+static int helper_call (lua_State *L)
+{
+ struct exception e;
+ int freturn = 0;
+ Helper *h;
+ Transport *tpt;
+ MYASSERT( lua_gettop( L ) >= 1 );
+ MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.helper" ) );
+
+ /* get helper object and its transport */
+ h = ( Helper * )lua_touserdata( L, 1 );
+ tpt = &h->handle->tpt;
+
+ /* capture special calls, otherwise execute normal remote call */
+ if( strcmp("get", h->funcname ) == 0 )
+ {
+ helper_get( L, h->parent );
+ freturn = 1;
+ }
+ else
+ {
+ Try
+ {
+ int i,n;
+ u32 nret,ret_code;
+ u8 cmdresp;
+
+ /* write function name */
+ helper_wait_ready( tpt, RPC_CMD_CALL );
+ helper_remote_index( h );
+
+ /* write number of arguments */
+ n = lua_gettop( L );
+ transport_write_u32( tpt, n - 1 );
+
+ /* write each argument */
+ for( i = 2; i <= n; i ++ )
+ write_variable( tpt, L, i );
+
+ /* if we're in async mode, we're done */
+ if ( h->handle->async )
+ {
+ h->handle->read_reply_count++;
+ freturn = 0;
+ }
+
+ /* read return code */
+ ret_code = transport_read_u8( tpt );
+
+ if ( ret_code== 0 )
+ {
+ /* read return arguments */
+ nret = transport_read_u32( tpt );
+
+ for ( i = 0; i < ( ( int ) nret ); i ++ )
+ read_variable( tpt, L );
+
+ freturn = ( int )nret;
+ }
+ else
+ {
+ /* read error and handle it */
+ u32 code = transport_read_u32( tpt );
+ u32 len = transport_read_u32( tpt );
+ char *err_string = ( char * )alloca( len + 1 );
+ transport_read_string( tpt, err_string, len );
+ err_string[ len ] = 0;
+
+ deal_with_error( L, h->handle, err_string );
+ freturn = 0;
+ }
+ }
+ Catch( e )
+ {
+ switch( e.type )
+ {
+ case fatal:
+ if ( e.errnum == ERR_CLOSED )
+ my_lua_error( L, "can't refer to a remote function after the handle has been closed" );
+ deal_with_error( L, h->handle, errorString( e.errnum ) );
+ transport_close( tpt );
+ break;
+ case nonfatal:
+ deal_with_error( L, h->handle, errorString( e.errnum ) );
+ lua_pushnil( L );
+ return 1;
+ break;
+ default:
+ deal_with_error( L, h->handle, errorString( e.errnum ) );
+ transport_close( tpt );
+ break;
+ }
+ }
+ }
+ return freturn;
+}
+
+static int helper_newindex( lua_State *L )
+{
+ struct exception e;
+ int freturn = 0;
+ int ret_code;
+ Helper *h;
+ Transport *tpt;
+ MYASSERT( lua_isuserdata( L, -3 ) && ismetatable_type( L, -3, "rpc.helper" ) );
+ MYASSERT( lua_isstring( L, -2 ) );
+
+ /* get helper object and its transport */
+ h = ( Helper * )lua_touserdata( L, -3 );
+ tpt = &h->handle->tpt;
+
+ Try
+ {
+ int len;
+ u8 cmdresp;
+
+ /* write function name */
+ len = strlen( h->funcname );
+ helper_wait_ready( tpt, RPC_CMD_NEWINDEX );
+ helper_remote_index( h );
+
+ write_variable( tpt, L, lua_gettop( L ) - 1 );
+ write_variable( tpt, L, lua_gettop( L ) );
+
+ ret_code = transport_read_u8( tpt );
+ if( ret_code != 0 )
+ {
+ /* read error and handle it */
+ u32 code = transport_read_u32( tpt );
+ u32 len = transport_read_u32( tpt );
+ char *err_string = ( char * )alloca( len + 1 );
+ transport_read_string( tpt, err_string, len );
+ err_string[ len ] = 0;
+
+ deal_with_error( L, h->handle, err_string );
+ }
+
+ freturn = 0;
+ }
+ Catch( e )
+ {
+ switch( e.type )
+ {
+ case fatal:
+ if ( e.errnum == ERR_CLOSED )
+ my_lua_error( L, "can't refer to a remote function after the handle has been closed" );
+ deal_with_error( L, h->handle, errorString( e.errnum ) );
+ transport_close( tpt );
+ break;
+ case nonfatal:
+ deal_with_error( L, h->handle, errorString( e.errnum ) );
+ lua_pushnil( L );
+ return 1;
+ break;
+ default:
+ deal_with_error( L, h->handle, errorString( e.errnum ) );
+ transport_close( tpt );
+ break;
+ }
+ }
+ return freturn;
+}
+
+
+static Helper *helper_append( lua_State *L, Helper *helper, const char *funcname )
+{
+ Helper *h = ( Helper * )lua_newuserdata( L, sizeof( Helper ) );
+ luaL_getmetatable( L, "rpc.helper" );
+ lua_setmetatable( L, -2 );
+ h->handle = helper->handle;
+ h->parent = helper;
+ h->nparents = helper->nparents + 1;
+ strncpy ( h->funcname, funcname, NUM_FUNCNAME_CHARS );
+ return h;
+}
+
+/* indexing a handle returns a helper */
+static int helper_index (lua_State *L)
+{
+ const char *s;
+ Helper *h;
+
+ MYASSERT( lua_gettop( L ) == 2 );
+ MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.helper" ) );
+
+ if( lua_type( L, 2 ) != LUA_TSTRING )
+ my_lua_error( L, "can't index a handle with a non-string" );
+ s = lua_tostring( L, 2 );
+ if ( strlen( s ) > NUM_FUNCNAME_CHARS - 1 )
+ my_lua_error( L, "function name is too long" );
+
+ h = helper_append( L, ( Helper * )lua_touserdata( L, 1 ), s );
+
+ return 1;
+}
+
+/****************************************************************************/
+/* server side handle userdata objects. */
+
+static ServerHandle *server_handle_create( lua_State *L )
+{
+ ServerHandle *h = ( ServerHandle * )lua_newuserdata( L, sizeof( ServerHandle ) );
+ luaL_getmetatable( L, "rpc.server_handle" );
+ lua_setmetatable( L, -2 );
+
+ h->link_errs = 0;
+
+ transport_init( &h->ltpt );
+ transport_init( &h->atpt );
+ return h;
+}
+
+static void server_handle_shutdown( ServerHandle *h )
+{
+ transport_close( &h->ltpt );
+ transport_close( &h->atpt );
+}
+
+static void server_handle_destroy( ServerHandle *h )
+{
+ server_handle_shutdown( h );
+}
+
+/****************************************************************************/
+/* remote function calling (client side) */
+
+/* rpc_connect (ip_address, port)
+ * returns a handle to the new connection, or nil if there was an error.
+ * if there is an RPC error function defined, it will be called on error.
+ */
+
+static int rpc_connect( lua_State *L )
+{
+ struct exception e;
+ Handle *handle = 0;
+
+ Try
+ {
+ handle = handle_create ( L );
+ transport_open_connection( L, handle );
+
+ transport_write_u8( &handle->tpt, RPC_CMD_CON );
+ client_negotiate( &handle->tpt );
+ }
+ Catch( e )
+ {
+ deal_with_error( L, 0, errorString( e.errnum ) );
+ lua_pushnil( L );
+ }
+ return 1;
+}
+
+
+/* rpc_close (handle)
+ * this closes the transport, but does not free the handle object. that's
+ * because the handle will still be in the user's name space and might be
+ * referred to again. we'll let garbage collection free the object.
+ * it's a lua runtime error to refer to a transport after it has been closed.
+ */
+
+static int rpc_close( lua_State *L )
+{
+ check_num_args( L, 1 );
+
+ if( lua_isuserdata( L, 1 ) )
+ {
+ if( ismetatable_type( L, 1, "rpc.handle" ) )
+ {
+ Handle *handle = ( Handle * )lua_touserdata( L, 1 );
+ transport_close( &handle->tpt );
+ return 0;
+ }
+ if( ismetatable_type( L, 1, "rpc.server_handle" ) )
+ {
+ ServerHandle *handle = ( ServerHandle * )lua_touserdata( L, 1 );
+ server_handle_shutdown( handle );
+ return 0;
+ }
+ }
+
+ my_lua_error(L,"argument must be an RPC handle");
+ return 0;
+}
+
+
+/* rpc_async (handle,)
+ * this sets a handle's asynchronous calling mode (0/nil=off, other=on).
+ * (this is for the client only).
+ */
+/* @@@ This should probably be adjusted to be in line with our new multiple command architecture */
+static int rpc_async (lua_State *L)
+{
+ Handle *handle;
+ check_num_args( L, 2 );
+
+ if ( !lua_isuserdata( L, 1 ) || !ismetatable_type( L, 1, "rpc.handle" ) )
+ my_lua_error( L, "first argument must be an RPC client handle" );
+
+ handle = ( Handle * )lua_touserdata( L, 1 );
+
+ if ( lua_isnil( L, 2 ) || ( lua_isnumber( L, 2 ) && lua_tonumber( L, 2 ) == 0) )
+ handle->async = 0;
+ else
+ handle->async = 1;
+
+ return 0;
+}
+
+/****************************************************************************/
+/* lua remote function server */
+
+/* read function call data and execute the function. this function empties the
+ * stack on entry and exit. This sets a custom error handler to catch errors
+ * around the function call.
+ */
+
+static void read_cmd_call( Transport *tpt, lua_State *L )
+{
+ int i, stackpos, good_function, nargs;
+ u32 len;
+ char *funcname;
+ char *token = NULL;
+
+ /* read function name */
+ len = transport_read_u32( tpt ); /* function name string length */
+ funcname = ( char * )alloca( len + 1 );
+ transport_read_string( tpt, funcname, len );
+ funcname[ len ] = 0;
+
+ /* get function */
+ /* @@@ perhaps handle more like variables instead of using a long string? */
+ /* @@@ also strtok is not thread safe */
+ token = strtok( funcname, "." );
+ lua_getglobal( L, token );
+ token = strtok( NULL, "." );
+ while( token != NULL )
+ {
+ lua_getfield( L, -1, token );
+ token = strtok( NULL, "." );
+ }
+ stackpos = lua_gettop( L ) - 1;
+ good_function = LUA_ISCALLABLE( L, -1 );
+
+ /* read number of arguments */
+ nargs = transport_read_u32( tpt );
+
+ /* read in each argument, leave it on the stack */
+ for ( i = 0; i < nargs; i ++ )
+ read_variable( tpt, L );
+
+ /* call the function */
+ if( good_function )
+ {
+ int nret, error_code;
+ error_code = lua_pcall( L, nargs, LUA_MULTRET, 0 );
+
+ /* handle errors */
+ if ( error_code )
+ {
+ size_t len;
+ const char *errmsg;
+ errmsg = lua_tolstring (L, -1, &len);
+ transport_write_u8( tpt, 1 );
+ transport_write_u32( tpt, error_code );
+ transport_write_u32( tpt, len );
+ transport_write_string( tpt, errmsg, len );
+ }
+ else
+ {
+ /* pass the return values back to the caller */
+ transport_write_u8( tpt, 0 );
+ nret = lua_gettop( L ) - stackpos;
+ transport_write_u32( tpt, nret );
+ for ( i = 0; i < nret; i ++ )
+ write_variable( tpt, L, stackpos + 1 + i );
+ }
+ }
+ else
+ {
+ /* bad function */
+ const char *msg = "undefined function: ";
+ int errlen = strlen( msg ) + len;
+ transport_write_u8( tpt, 1 );
+ transport_write_u32( tpt, LUA_ERRRUN );
+ transport_write_u32( tpt, errlen );
+ transport_write_string( tpt, msg, strlen( msg ) );
+ transport_write_string( tpt, funcname, len );
+ }
+ /* empty the stack */
+ lua_settop ( L, 0 );
+}
+
+
+static void read_cmd_get( Transport *tpt, lua_State *L )
+{
+ u32 len;
+ char *funcname;
+ char *token = NULL;
+
+ /* read function name */
+ len = transport_read_u32( tpt ); /* function name string length */
+ funcname = ( char * )alloca( len + 1 );
+ transport_read_string( tpt, funcname, len );
+ funcname[ len ] = 0;
+
+ /* get function */
+ /* @@@ perhaps handle more like variables instead of using a long string? */
+ /* @@@ also strtok is not thread safe */
+ token = strtok( funcname, "." );
+ lua_getglobal( L, token );
+ token = strtok( NULL, "." );
+ while( token != NULL )
+ {
+ lua_getfield( L, -1, token );
+ token = strtok( NULL, "." );
+ }
+
+ /* return top value on stack */
+ write_variable( tpt, L, lua_gettop( L ) );
+
+ /* empty the stack */
+ lua_settop ( L, 0 );
+}
+
+
+static void read_cmd_newindex( Transport *tpt, lua_State *L )
+{
+ u32 len;
+ char *funcname;
+ char *token = NULL;
+
+ /* read function name */
+ len = transport_read_u32( tpt ); /* function name string length */
+ funcname = ( char * )alloca( len + 1 );
+ transport_read_string( tpt, funcname, len );
+ funcname[ len ] = 0;
+
+ /* get function */
+ /* @@@ perhaps handle more like variables instead of using a long string? */
+ /* @@@ also strtok is not thread safe */
+ if( strlen( funcname ) > 0 ) /* */
+ {
+ token = strtok( funcname, "." );
+ lua_getglobal( L, token );
+ token = strtok( NULL, "." );
+ while( token != NULL )
+ {
+ lua_getfield( L, -1, token );
+ token = strtok( NULL, "." );
+ }
+ read_variable( tpt, L ); /* key */
+ read_variable( tpt, L ); /* value */
+ lua_settable( L, -3 ); /* set key to value on indexed table */
+ }
+ else
+ {
+ read_variable( tpt, L ); /* key */
+ read_variable( tpt, L ); /* value */
+ lua_setglobal( L, lua_tostring( L, -2 ) );
+ }
+ /* Write out 0 to indicate no error and that we're done */
+ transport_write_u8( tpt, 0 );
+
+ /*if ( error_code ) // Add some error handling later
+ {
+ size_t len;
+ const char *errmsg;
+ errmsg = lua_tolstring (L, -1, &len);
+ transport_write_u8( tpt, 1 );
+ transport_write_u32( tpt, error_code );
+ transport_write_u32( tpt, len );
+ transport_write_string( tpt, errmsg, len );
+ }*/
+
+ /* empty the stack */
+ lua_settop ( L, 0 );
+}
+
+
+static ServerHandle *rpc_listen_helper( lua_State *L )
+{
+ struct exception e;
+ ServerHandle *handle = 0;
+
+ Try
+ {
+ /* make server handle */
+ handle = server_handle_create( L );
+
+ /* make listening transport */
+ transport_open_listener( L, handle );
+ }
+ Catch( e )
+ {
+ if( handle )
+ server_handle_destroy( handle );
+
+ deal_with_error( L, 0, errorString( e.errnum ) );
+ return 0;
+ }
+ return handle;
+}
+
+
+/* rpc_listen (port) --> server_handle */
+static int rpc_listen( lua_State *L )
+{
+ ServerHandle *handle;
+
+ handle = rpc_listen_helper( L );
+ if ( handle == 0 )
+ printf( "Bad Handle!" );
+
+ return 1;
+}
+
+
+/* rpc_peek (server_handle) --> 0 or 1 */
+static int rpc_peek( lua_State *L )
+{
+ ServerHandle *handle;
+
+ check_num_args( L, 1 );
+ if ( !( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.server_handle" ) ) )
+ my_lua_error( L, "argument must be an RPC server handle" );
+
+ handle = ( ServerHandle * )lua_touserdata( L, 1 );
+
+ /* if accepting transport is open, see if there is any data to read */
+ if ( transport_is_open( &handle->atpt ) )
+ {
+ if ( transport_readable( &handle->atpt ) )
+ lua_pushnumber( L, 1 );
+ else
+ lua_pushnil( L );
+
+ return 1;
+ }
+
+ /* otherwise, see if there is a new connection on the listening transport */
+ if ( transport_is_open( &handle->ltpt ) )
+ {
+ if ( transport_readable( &handle->ltpt ) )
+ lua_pushnumber ( L, 1 );
+ else
+ lua_pushnil( L );
+
+ return 1;
+ }
+
+ lua_pushnumber( L, 0 );
+ return 1;
+}
+
+
+static void rpc_dispatch_helper( lua_State *L, ServerHandle *handle )
+{
+ struct exception e;
+
+ Try
+ {
+ /* if accepting transport is open, read function calls */
+ if ( transport_is_open( &handle->atpt ) )
+ {
+ Try
+ {
+ switch ( transport_read_u8( &handle->atpt ) )
+ {
+ case RPC_CMD_CALL:
+ transport_write_u8( &handle->atpt, RPC_READY );
+ read_cmd_call( &handle->atpt, L );
+ break;
+ case RPC_CMD_GET:
+ transport_write_u8( &handle->atpt, RPC_READY );
+ read_cmd_get( &handle->atpt, L );
+ break;
+ case RPC_CMD_CON: /* @@@ allow client to "reconnect", should support better mechanism */
+ server_negotiate( &handle->atpt );
+ break;
+ case RPC_CMD_NEWINDEX:
+ transport_write_u8( &handle->atpt, RPC_READY );
+ read_cmd_newindex( &handle->atpt, L );
+ break;
+ default:
+ transport_write_u8(&handle->atpt, RPC_UNSUPPORTED_CMD );
+ e.type = nonfatal;
+ e.errnum = ERR_COMMAND;
+ Throw( e );
+ }
+
+ handle->link_errs = 0;
+ }
+ Catch( e )
+ {
+ /* if the client has closed the connection, close our side
+ * gracefully too.
+ */
+ transport_close( &handle->atpt );
+
+ switch( e.type )
+ {
+ case fatal:
+ Throw( e );
+
+ case nonfatal:
+ handle->link_errs++;
+ if ( handle->link_errs > MAX_LINK_ERRS )
+ {
+ handle->link_errs = 0;
+ Throw( e );
+ }
+ break;
+
+ default:
+ Throw( e );
+ }
+ }
+ }
+ else
+ {
+ /* if accepting transport is not open, accept a new connection from the
+ * listening transport.
+ */
+ transport_accept( &handle->ltpt, &handle->atpt );
+
+ switch ( transport_read_u8( &handle->atpt ) )
+ {
+ case RPC_CMD_CON:
+ server_negotiate( &handle->atpt );
+ break;
+ default: /* connection must be established to issue any other commands */
+ e.type = nonfatal;
+ e.errnum = ERR_COMMAND;
+ Throw( e );
+ }
+ }
+ }
+ Catch( e )
+ {
+ switch( e.type )
+ {
+ case fatal:
+ server_handle_shutdown( handle );
+ deal_with_error( L, 0, errorString( e.errnum ) );
+ break;
+ case nonfatal:
+ transport_close( &handle->atpt );
+ break;
+ default:
+ Throw( e );
+ }
+ }
+}
+
+
+/* rpc_dispatch (server_handle) */
+
+static int rpc_dispatch( lua_State *L )
+{
+ ServerHandle *handle;
+ check_num_args( L, 1 );
+
+ if ( ! ( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.server_handle" ) ) )
+ my_lua_error( L, "argument must be an RPC server handle" );
+
+ handle = ( ServerHandle * )lua_touserdata( L, 1 );
+
+ rpc_dispatch_helper( L, handle );
+ return 0;
+}
+
+
+/* lrf_server (port) */
+
+static int rpc_server( lua_State *L )
+{
+ int shref;
+ ServerHandle *handle = rpc_listen_helper( L );
+
+ /* hack to anchor handle in registry */
+ /* @@@ this should be replaced when we create a system for multiple connections */
+ /* @@@ such a mechanism would likely likely create a table for multiple connections that we could service in an event loop */
+ shref = luaL_ref( L, LUA_REGISTRYINDEX );
+ lua_rawgeti(L, LUA_REGISTRYINDEX, shref );
+
+ while ( transport_is_open( &handle->ltpt ) )
+ rpc_dispatch_helper( L, handle );
+
+ luaL_unref( L, LUA_REGISTRYINDEX, shref );
+ server_handle_destroy( handle );
+ return 0;
+}
+
+/****************************************************************************/
+/* more error handling stuff */
+
+/* rpc_on_error ([handle,] error_handler)
+ */
+
+static int rpc_on_error( lua_State *L )
+{
+ check_num_args( L, 1 );
+
+ if( global_error_handler != LUA_NOREF )
+ lua_unref (L,global_error_handler);
+
+ global_error_handler = LUA_NOREF;
+
+ if ( LUA_ISCALLABLE( L, 1 ) )
+ global_error_handler = lua_ref( L, 1 );
+ else if ( lua_isnil( L, 1 ) )
+ { ;; }
+ else
+ my_lua_error( L, "bad arguments" );
+
+ /* @@@ add option for handle */
+ /* Handle *h = (Handle*) lua_touserdata (L,1); */
+ /* if (lua_isuserdata (L,1) && ismetatable_type(L, 1, "rpc.handle")); */
+
+ return 0;
+}
+
+/****************************************************************************/
+/* register RPC functions */
+
+
+
+#ifndef LUARPC_STANDALONE
+
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+
+const LUA_REG_TYPE rpc_handle[] =
+{
+ { LSTRKEY( "__index" ), LFUNCVAL( handle_index ) },
+ { LSTRKEY( "__newindex"), LFUNCVAL( handle_newindex )},
+ { LNILKEY, LNILVAL }
+};
+
+const LUA_REG_TYPE rpc_helper[] =
+{
+ { LSTRKEY( "__call" ), LFUNCVAL( helper_call ) },
+ { LSTRKEY( "__index" ), LFUNCVAL( helper_index ) },
+ { LSTRKEY( "__newindex" ), LFUNCVAL( helper_newindex ) },
+ { LNILKEY, LNILVAL }
+};
+
+const LUA_REG_TYPE rpc_server_handle[] =
+{
+ { LNILKEY, LNILVAL }
+};
+
+const LUA_REG_TYPE rpc_map[] =
+{
+ { LSTRKEY( "connect" ), LFUNCVAL( rpc_connect ) },
+ { LSTRKEY( "close" ), LFUNCVAL( rpc_close ) },
+ { LSTRKEY( "server" ), LFUNCVAL( rpc_server ) },
+ { LSTRKEY( "on_error" ), LFUNCVAL( rpc_on_error ) },
+ { LSTRKEY( "listen" ), LFUNCVAL( rpc_listen ) },
+ { LSTRKEY( "peek" ), LFUNCVAL( rpc_peek ) },
+ { LSTRKEY( "dispatch" ), LFUNCVAL( rpc_dispatch ) },
+ { LSTRKEY( "rpc_async" ), LFUNCVAL( rpc_async ) },
+#if LUA_OPTIMIZE_MEMORY > 0
+/* { LSTRKEY("mode"), LSTRVAL( LUARPC_MODE ) }, */
+#endif // #if LUA_OPTIMIZE_MEMORY > 0
+ { LNILKEY, LNILVAL }
+};
+
+
+LUALIB_API int luaopen_luarpc(lua_State *L)
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+ luaL_rometatable(L, "rpc.helper", (void*)rpc_helper);
+ luaL_rometatable(L, "rpc.handle", (void*)rpc_handle);
+ luaL_rometatable(L, "rpc.server_handle", (void*)rpc_server_handle);
+#else
+ luaL_register( L, "rpc", rpc_map );
+ lua_pushstring( L, LUARPC_MODE );
+ lua_setfield(L, -2, "mode");
+
+ luaL_newmetatable( L, "rpc.helper" );
+ luaL_register( L, NULL, rpc_helper );
+
+ luaL_newmetatable( L, "rpc.handle" );
+ luaL_register( L, NULL, rpc_handle );
+
+ luaL_newmetatable( L, "rpc.server_handle" );
+#endif
+ return 1;
+}
+
+#else
+
+static const luaL_reg rpc_handle[] =
+{
+ { "__index", handle_index },
+ { "__newindex", handle_newindex },
+ { NULL, NULL }
+};
+
+static const luaL_reg rpc_helper[] =
+{
+ { "__call", helper_call },
+ { "__index", helper_index },
+ { "__newindex", helper_newindex },
+ { NULL, NULL }
+};
+
+static const luaL_reg rpc_server_handle[] =
+{
+ { NULL, NULL }
+};
+
+static const luaL_reg rpc_map[] =
+{
+ { "connect", rpc_connect },
+ { "close", rpc_close },
+ { "server", rpc_server },
+ { "on_error", rpc_on_error },
+ { "listen", rpc_listen },
+ { "peek", rpc_peek },
+ { "dispatch", rpc_dispatch },
+ { "rpc_async", rpc_async },
+ { NULL, NULL }
+};
+
+
+LUALIB_API int luaopen_luarpc(lua_State *L)
+{
+ luaL_register( L, "rpc", rpc_map );
+ lua_pushstring(L, LUARPC_MODE);
+ lua_setfield(L, -2, "mode");
+
+ luaL_newmetatable( L, "rpc.helper" );
+ luaL_register( L, NULL, rpc_helper );
+
+ luaL_newmetatable( L, "rpc.handle" );
+ luaL_register( L, NULL, rpc_handle );
+
+ luaL_newmetatable( L, "rpc.server_handle" );
+
+ return 1;
+}
+
+#endif
+
+#endif
Modified: branches/eagle_mmc/src/modules/net.c
===================================================================
--- branches/eagle_mmc/src/modules/net.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/net.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -140,7 +140,6 @@
return luaL_error( L, "invalid format" );
}
-static luaL_Buffer net_recv_buff;
// Lua: res, err = recv( sock, maxsize, [ timer_id, timeout ] ) or
// res, err = recv( sock, "*l", [ timer_id, timeout ] )
static int net_recv( lua_State *L )
@@ -150,7 +149,8 @@
s16 lastchar = ELUA_NET_NO_LASTCHAR;
unsigned timer_id = 0;
u32 timeout = 0;
-
+ luaL_Buffer net_recv_buff;
+
if( lua_isnumber( L, 2 ) ) // invocation with maxsize
maxsize = ( elua_net_size )luaL_checkinteger( L, 2 );
else // invocation with line mode
Modified: branches/eagle_mmc/src/modules/pio.c
===================================================================
--- branches/eagle_mmc/src/modules/pio.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/pio.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -8,293 +8,343 @@
#include "lrotable.h"
#include "platform_conf.h"
#include <stdio.h>
+#include <string.h>
#include <ctype.h>
-#include <string.h>
-// PIO constants
+// PIO public constants
#define PIO_DIR_OUTPUT 0
#define PIO_DIR_INPUT 1
-#define PIO_PULLUP 0
-#define PIO_PULLDOWN 1
-#define PIO_NOPULL 2
-#define PIO_MAX_STRSIZE 16
-#define PIO_MAX_TOKENSIZE 5
-// Helper: scan to the next occurence of a given char and return
-// the type found (string or number). The last token, number and
-// type are held in the global variables pio_p_token, pio_p_num
-// and pio_p_type. The function returns the next position in buffer
-// (after delim) or NULL for error or empty string.
+// PIO private constants
+#define PIO_PORT_OP 0
+#define PIO_PIN_OP 1
-#define PIO_SCAN_NUMBER 0
-#define PIO_SCAN_STRING 1
-#define PIO_SCAN_ERROR 2
+// Local operation masks for all the ports
+static pio_type pio_masks[ PLATFORM_IO_PORTS ];
-static char pio_p_token[ PIO_MAX_TOKENSIZE + 1 ];
-static int pio_p_num;
-static int pio_p_type;
+// ****************************************************************************
+// Generic helper functions
-const char* pio_scan_next( const char* src, int delim )
+// Helper function: clear all masks
+static void pioh_clear_masks()
{
- int isnum = 1, cnt = 0;
- char *ptoken;
+ int i;
+
+ for( i = 0; i < PLATFORM_IO_PORTS; i ++ )
+ pio_masks[ i ] = 0;
+}
- pio_p_num = 0;
- ptoken = pio_p_token;
- pio_p_type = PIO_SCAN_ERROR;
- while( *src && *src != delim )
+// Helper function: pin operations
+// Gets the stack index of the first pin and the operation
+static int pioh_set_pins( lua_State* L, int stackidx, int op )
+{
+ int total = lua_gettop( L );
+ int i, v, port, pin;
+
+ pioh_clear_masks();
+
+ // Get all masks
+ for( i = stackidx; i <= total; i ++ )
{
- *ptoken ++ = *src;
- if( isnum && isdigit( *src ) )
- pio_p_num = ( pio_p_num << 3 ) + ( pio_p_num << 1 ) + *src - '0';
- else
- isnum = 0;
- src ++;
- if( ++cnt > PIO_MAX_TOKENSIZE )
- return NULL;
+ v = luaL_checkinteger( L, i );
+ port = PLATFORM_IO_GET_PORT( v );
+ pin = PLATFORM_IO_GET_PIN( v );
+ if( PLATFORM_IO_IS_PORT( v ) || !platform_pio_has_port( port ) || !platform_pio_has_pin( port, pin ) )
+ return luaL_error( L, "invalid pin" );
+ pio_masks[ port ] |= 1 << pin;
}
- *ptoken = '\0';
- pio_p_type = isnum && cnt > 0 ? PIO_SCAN_NUMBER : PIO_SCAN_STRING;
- return src;
+
+ // Ask platform to execute the given operation
+ for( i = 0; i < PLATFORM_IO_PORTS; i ++ )
+ if( pio_masks[ i ] )
+ if( !platform_pio_op( i, pio_masks[ i ], op ) )
+ return luaL_error( L, "invalid PIO operation" );
+ return 0;
}
-// Helper: get port and pin number from port string (PA_2, P1_3 ...)
-// Also look for direction specifiers (PA_2_DIR) as well as pull
-// specifiers(P1_3_PULL)
-// Returns PIO_ERROR, PIO_PORT or PIO_PORT_AND_PIN
-// Also returns port number and pin mask by side effect (and mode)
-#define PIO_ERROR 0
-#define PIO_PORT 1
-#define PIO_PORT_AND_PIN 2
-#define PIO_MODE_INOUT 0
-#define PIO_MODE_DIR 1
-#define PIO_MODE_PULL 2
-static int pioh_parse_port( const char* key, int* pport, pio_type* ppinmask, int *pspin, int* pmode )
+// Helper function: port operations
+// Gets the stack index of the first port and the operation (also the mask)
+static int pioh_set_ports( lua_State* L, int stackidx, int op, pio_type mask )
{
- int spin = -1, epin = -1, i;
- const char* p;
-
- *pmode = PIO_MODE_INOUT;
- if( !key || *key != 'P' || strlen( key ) > PIO_MAX_STRSIZE )
- return PIO_ERROR;
+ int total = lua_gettop( L );
+ int i, v, port;
- // Get port first
- p = pio_scan_next( key + 1, '_' );
- if( pio_p_type == PIO_SCAN_ERROR )
- return PIO_ERROR;
- else if( pio_p_type == PIO_SCAN_NUMBER )
+ pioh_clear_masks();
+
+ // Get all masks
+ for( i = stackidx; i <= total; i ++ )
{
- if( PIO_PREFIX != '0' )
- return PIO_ERROR;
- *pport = pio_p_num;
+ v = luaL_checkinteger( L, i );
+ port = PLATFORM_IO_GET_PORT( v );
+ if( !PLATFORM_IO_IS_PORT( v ) || !platform_pio_has_port( port ) )
+ return luaL_error( L, "invalid port" );
+ pio_masks[ port ] = mask;
}
- else
- {
- if( PIO_PREFIX != 'A' || strlen( pio_p_token ) != 1 || !isupper( pio_p_token[ 0 ] ) )
- return PIO_ERROR;
- *pport = pio_p_token[ 0 ] - 'A';
- }
- if( !platform_pio_has_port( *pport ) )
- return PIO_ERROR;
- if( *p == '\0' )
- return PIO_PORT;
+
+ // Ask platform to execute the given operation
+ for( i = 0; i < PLATFORM_IO_PORTS; i ++ )
+ if( pio_masks[ i ] )
+ if( !platform_pio_op( i, pio_masks[ i ], op ) )
+ return luaL_error( L, "invalid PIO operation" );
+ return 0;
+}
- // Scan next three tokens
- // The first can be either a number or a pull/dir spec
- // The second can be either a number or a pull/dir spec
- // The last one can only be a pull/dir spec
- for( i = 0; i < 3; i ++ )
- {
- p = pio_scan_next( p + 1, '_' );
- if( pio_p_type == PIO_SCAN_ERROR )
- return PIO_ERROR;
- else if( pio_p_type == PIO_SCAN_STRING )
- goto handle_dir_pull;
- else switch( i ) // token is a number
- {
- case 0:
- spin = pio_p_num;
- break;
+// ****************************************************************************
+// Pin/port helper functions
- case 1:
- epin = pio_p_num;
- break;
+static int pio_gen_setdir( lua_State *L, int optype )
+{
+ int op = luaL_checkinteger( L, 1 );
- case 2:
- return PIO_ERROR;
- }
- if( *p == '\0' ) // no more tokens
- goto finalize;
- }
+ if( op == PIO_DIR_INPUT )
+ op = optype == PIO_PIN_OP ? PLATFORM_IO_PIN_DIR_INPUT : PLATFORM_IO_PORT_DIR_INPUT;
+ else if( op == PIO_DIR_OUTPUT )
+ op = optype == PIO_PIN_OP ? PLATFORM_IO_PIN_DIR_OUTPUT : PLATFORM_IO_PORT_DIR_OUTPUT;
+ else
+ return luaL_error( L, "invalid direction" );
+ if( optype == PIO_PIN_OP )
+ pioh_set_pins( L, 2, op );
+ else
+ pioh_set_ports( L, 2, op, PLATFORM_IO_ALL_PINS );
+ return 0;
+}
- // Handle the "_DIR" and "_PULL" suffixes
-handle_dir_pull:
- if( !strcmp( pio_p_token, "DIR" ) && *p == '\0' )
- *pmode = PIO_MODE_DIR;
- else if( !strcmp( pio_p_token, "PULL" ) && *p == '\0' )
- *pmode = PIO_MODE_PULL;
+static int pio_gen_setpull( lua_State *L, int optype )
+{
+ int op = luaL_checkinteger( L, 1 );
+
+ if( ( op != PLATFORM_IO_PIN_PULLUP ) &&
+ ( op != PLATFORM_IO_PIN_PULLDOWN ) &&
+ ( op != PLATFORM_IO_PIN_NOPULL ) )
+ return luaL_error( L, "invalid pull type" );
+ if( optype == PIO_PIN_OP )
+ pioh_set_pins( L, 2, op );
else
- return PIO_ERROR;
+ pioh_set_ports( L, 2, op, PLATFORM_IO_ALL_PINS );
+ return 0;
+}
-finalize:
- // Build mask if needed
- if( spin != -1 )
- {
- if( !platform_pio_has_pin( *pport, spin ) || ( ( epin != -1 ) && !platform_pio_has_pin( *pport, epin ) ) )
- return PIO_ERROR;
- *pspin = spin;
- if( epin == -1 )
- *ppinmask = 1 << spin;
- else
- if( epin < spin )
- return PIO_ERROR;
- else
- if( epin - spin + 1 == sizeof( pio_type ) << 3 )
- *ppinmask = PLATFORM_IO_ALL_PINS;
- else
- *ppinmask = ( ( 1 << ( epin - spin + 1 ) ) - 1 ) << spin;
- return PIO_PORT_AND_PIN;
- }
- return PIO_PORT;
+static int pio_gen_setval( lua_State *L, int optype, pio_type val, int stackidx )
+{
+ if( ( optype == PIO_PIN_OP ) && ( val != 1 ) && ( val != 0 ) )
+ return luaL_error( L, "invalid pin value" );
+ if( optype == PIO_PIN_OP )
+ pioh_set_pins( L, stackidx, val == 1 ? PLATFORM_IO_PIN_SET : PLATFORM_IO_PIN_CLEAR );
+ else
+ pioh_set_ports( L, stackidx, PLATFORM_IO_PORT_SET_VALUE, val );
+ return 0;
}
-// __index metafunction for PIO
-// Return the value read from the given port/pin (nothing for error)
-static int pio_mt_index( lua_State* L )
+// ****************************************************************************
+// Pin operations
+
+// Lua: pio.pin.setdir( pio.INPUT | pio.OUTPUT, pin1, pin2, ..., pinn )
+static int pio_pin_setdir( lua_State *L )
{
- const char *key = luaL_checkstring( L, 2 );
- int port, spin, res, mode;
- pio_type value, pinmask;
+ return pio_gen_setdir( L, PIO_PIN_OP );
+}
- if( ( res = pioh_parse_port( key, &port, &pinmask, &spin, &mode ) == PIO_ERROR ) )
- return 0;
- if( mode != PIO_MODE_INOUT )
- return 0;
- if( res == PIO_PORT )
- value = platform_pio_op( port, PLATFORM_IO_READ_IN_MASK, PLATFORM_IO_PORT_GET_VALUE );
- else
- if( pinmask & ( pinmask - 1 ) )
+// Lua: pio.pin.setpull( pio.PULLUP | pio.PULLDOWN | pio.NOPULL, pin1, pin2, ..., pinn )
+static int pio_pin_setpull( lua_State *L )
+{
+ return pio_gen_setpull( L, PIO_PIN_OP );
+}
+
+// Lua: pio.pin.setval( 0|1, pin1, pin2, ..., pinn )
+static int pio_pin_setval( lua_State *L )
+{
+ pio_type val = ( pio_type )luaL_checkinteger( L, 1 );
+
+ return pio_gen_setval( L, PIO_PIN_OP, val, 2 );
+}
+
+// Lua: pio.pin.sethigh( pin1, pin2, ..., pinn )
+static int pio_pin_sethigh( lua_State *L )
+{
+ return pio_gen_setval( L, PIO_PIN_OP, 1, 1 );
+}
+
+// Lua: pio.pin.setlow( pin1, pin2, ..., pinn )
+static int pio_pin_setlow( lua_State *L )
+{
+ return pio_gen_setval( L, PIO_PIN_OP, 0, 1 );
+}
+
+// Lua: pin1, pin2, ..., pinn = pio.pin.getval( pin1, pin2, ..., pinn )
+static int pio_pin_getval( lua_State *L )
+{
+ pio_type value;
+ int v, i, port, pin;
+ int total = lua_gettop( L );
+
+ for( i = 1; i <= total; i ++ )
+ {
+ v = luaL_checkinteger( L, i );
+ port = PLATFORM_IO_GET_PORT( v );
+ pin = PLATFORM_IO_GET_PIN( v );
+ if( PLATFORM_IO_IS_PORT( v ) || !platform_pio_has_port( port ) || !platform_pio_has_pin( port, pin ) )
+ return luaL_error( L, "invalid pin" );
+ else
{
- value = platform_pio_op( port, PLATFORM_IO_READ_IN_MASK, PLATFORM_IO_PORT_GET_VALUE );
- value = ( value & pinmask ) >> spin;
+ value = platform_pio_op( port, 1 << pin, PLATFORM_IO_PIN_GET );
+ lua_pushinteger( L, value );
}
- else
- value = platform_pio_op( port, pinmask, PLATFORM_IO_PIN_GET );
- lua_pushinteger( L, value );
- return 1;
+ }
+ return total;
}
-// __newindex metafunction for PIO
-// Set the given value to the give port/pin, or the direction of the pin, or
-// the pullup/pulldown configuration
-static int pio_mt_newindex( lua_State* L )
+// ****************************************************************************
+// Port operations
+
+// Lua: pio.port.setdir( pio.INPUT | pio.OUTPUT, port1, port2, ..., portn )
+static int pio_port_setdir( lua_State *L )
{
- const char *key = luaL_checkstring( L, 2 );
- pio_type value = ( pio_type )luaL_checkinteger( L, 3 );
- int port, spin, res, mode;
- pio_type pinmask, temp;
+ return pio_gen_setdir( L, PIO_PORT_OP );
+}
- if( ( res = pioh_parse_port( key, &port, &pinmask, &spin, &mode ) == PIO_ERROR ) )
- return 0;
- switch( mode )
- {
- case PIO_MODE_INOUT: // set port/pin value
- if( res == PIO_PORT )
- platform_pio_op( port, value, PLATFORM_IO_PORT_SET_VALUE );
- else
- {
- temp = platform_pio_op( port, PLATFORM_IO_READ_OUT_MASK, PLATFORM_IO_PORT_GET_VALUE );
- value = ( temp & ~pinmask ) | ( value << spin );
- platform_pio_op( port, value, PLATFORM_IO_PORT_SET_VALUE );
- }
- break;
-
- case PIO_MODE_DIR: // set pin direction
- if( res == PIO_PORT )
- platform_pio_op( port, 0, value == PIO_DIR_INPUT ? PLATFORM_IO_PORT_DIR_INPUT : PLATFORM_IO_PORT_DIR_OUTPUT );
- else
- platform_pio_op( port, pinmask, value == PIO_DIR_INPUT ? PLATFORM_IO_PIN_DIR_INPUT : PLATFORM_IO_PIN_DIR_OUTPUT );
- break;
+// Lua: pio.port.setpull( pio.PULLUP | pio.PULLDOWN | pio.NOPULL, port1, port2, ..., portn )
+static int pio_port_setpull( lua_State *L )
+{
+ return pio_gen_setpull( L, PIO_PORT_OP );
+}
- case PIO_MODE_PULL: // pullup/pulldown configuration
- platform_pio_op( port, res == PIO_PORT ? PLATFORM_IO_ALL_PINS : pinmask, value );
- break;
- }
- return 0;
+// Lua: pio.port.setval( value, port1, port2, ..., portn )
+static int pio_port_setval( lua_State *L )
+{
+ pio_type val = ( pio_type )luaL_checkinteger( L, 1 );
+
+ return pio_gen_setval( L, PIO_PORT_OP, val, 2 );
}
-// __newindex metafunction for pio.dir
-// Set the direction of the given ports/pins
-static int pio_dir_mt_newindex( lua_State* L )
+// Lua: pio.port.sethigh( port1, port2, ..., portn )
+static int pio_port_sethigh( lua_State *L )
{
- const char* key = luaL_checkstring( L, 2 );
- pio_type value = ( pio_type )luaL_checkinteger( L, 3 );
- int port, spin, res, mode;
- pio_type pinmask;
+ return pio_gen_setval( L, PIO_PORT_OP, PLATFORM_IO_ALL_PINS, 1 );
+}
- if( ( res = pioh_parse_port( key, &port, &pinmask, &spin, &mode ) == PIO_ERROR ) )
- return 0;
- if( mode != PIO_MODE_INOUT )
- return 0;
- if( res == PIO_PORT )
- platform_pio_op( port, 0, value == PIO_DIR_INPUT ? PLATFORM_IO_PORT_DIR_INPUT : PLATFORM_IO_PORT_DIR_OUTPUT );
- else
- platform_pio_op( port, pinmask, value == PIO_DIR_INPUT ? PLATFORM_IO_PIN_DIR_INPUT : PLATFORM_IO_PIN_DIR_OUTPUT );
- return 0;
+// Lua: pio.port.setlow( port1, port2, ..., portn )
+static int pio_port_setlow( lua_State *L )
+{
+ return pio_gen_setval( L, PIO_PORT_OP, 0, 1 );
}
-// __newindex metafunction for pio.pull
-// Set the pull type (pullup, pulldown, nopin) to the given ports/pins
-static int pio_pull_mt_newindex( lua_State* L )
+// Lua: val1, val2, ..., valn = pio.port.getval( port1, port2, ..., portn )
+static int pio_port_getval( lua_State *L )
{
- const char* key = luaL_checkstring( L, 2 );
- pio_type value = ( pio_type )luaL_checkinteger( L, 3 );
- int port, spin, res, mode;
- pio_type pinmask;
+ pio_type value;
+ int v, i, port;
+ int total = lua_gettop( L );
+
+ for( i = 1; i <= total; i ++ )
+ {
+ v = luaL_checkinteger( L, i );
+ port = PLATFORM_IO_GET_PORT( v );
+ if( !PLATFORM_IO_IS_PORT( v ) || !platform_pio_has_port( port ) )
+ return luaL_error( L, "invalid port" );
+ else
+ {
+ value = platform_pio_op( port, PLATFORM_IO_ALL_PINS, PLATFORM_IO_PORT_GET_VALUE );
+ lua_pushinteger( L, value );
+ }
+ }
+ return total;
+}
- if( ( res = pioh_parse_port( key, &port, &pinmask, &spin, &mode ) == PIO_ERROR ) )
+// ****************************************************************************
+// The __index metamethod will return pin/port numeric identifiers
+
+static int pio_mt_index( lua_State* L )
+{
+ const char *key = luaL_checkstring( L ,2 );
+ int port = 0xFFFF, pin = 0xFFFF, isport = 0, sz;
+
+ if( !key || *key != 'P' )
return 0;
- if( mode != PIO_MODE_INOUT )
+ if( isupper( key[ 1 ] ) ) // PA, PB, ...
+ {
+ if( PIO_PREFIX != 'A' )
+ return 0;
+ port = key[ 1 ] - 'A';
+ if( key[ 2 ] == '\0' )
+ isport = 1;
+ else if( key[ 2 ] == '_' )
+ if( sscanf( key + 3, "%d%n", &pin, &sz ) != 1 || sz != strlen( key ) - 3 )
+ return 0;
+ }
+ else // P0, P1, ...
+ {
+ if( PIO_PREFIX != '0' )
+ return 0;
+ if( !strchr( key, '_' ) ) // parse port
+ {
+ if( sscanf( key + 1, "%d%n", &port, &sz ) != 1 || sz != strlen( key ) - 1 )
+ return 0;
+ isport = 1;
+ }
+ else // parse port_pin
+ if( sscanf( key + 1, "%d_%d%n", &port, &pin, &sz ) != 2 || sz != strlen( key ) - 1 )
+ return 0;
+ }
+ sz = -1;
+ if( isport )
+ {
+ if( platform_pio_has_port( port ) )
+ sz = PLATFORM_IO_ENCODE( port, 0, 1 );
+ }
+ else
+ {
+ if( platform_pio_has_port( port ) && platform_pio_has_pin( port, pin ) )
+ sz = PLATFORM_IO_ENCODE( port, pin, 0 );
+ }
+ if( sz == -1 )
return 0;
- platform_pio_op( port, res == PIO_PORT ? PLATFORM_IO_ALL_PINS : pinmask, value );
- return 0;
+ else
+ {
+ lua_pushinteger( L, sz );
+ return 1;
+ }
}
-// Module function map
+// ****************************************************************************
+// Pin function map
+
#define MIN_OPT_LEVEL 2
#include "lrodefs.h"
-static const LUA_REG_TYPE pio_dir_map[] =
+static const LUA_REG_TYPE pio_pin_map[] =
{
-#if LUA_OPTIMIZE_MEMORY > 0
- { LSTRKEY( "__metatable" ), LROVAL( pio_dir_map ) },
-#endif
- { LSTRKEY( "__newindex" ), LFUNCVAL( pio_dir_mt_newindex ) },
+ { LSTRKEY( "setdir" ), LFUNCVAL ( pio_pin_setdir ) },
+ { LSTRKEY( "setpull" ), LFUNCVAL( pio_pin_setpull ) },
+ { LSTRKEY( "setval" ), LFUNCVAL( pio_pin_setval ) },
+ { LSTRKEY( "sethigh" ), LFUNCVAL( pio_pin_sethigh ) },
+ { LSTRKEY( "setlow" ), LFUNCVAL( pio_pin_setlow ) },
+ { LSTRKEY( "getval" ), LFUNCVAL( pio_pin_getval ) },
{ LNILKEY, LNILVAL }
};
-static const LUA_REG_TYPE pio_pull_map[] =
+static const LUA_REG_TYPE pio_port_map[] =
{
-#if LUA_OPTIMIZE_MEMORY > 0
- { LSTRKEY( "__metatable" ), LROVAL( pio_pull_map ) },
-#endif
- { LSTRKEY( "__newindex" ), LFUNCVAL( pio_pull_mt_newindex ) },
+ { LSTRKEY( "setdir" ), LFUNCVAL ( pio_port_setdir ) },
+ { LSTRKEY( "setpull" ), LFUNCVAL( pio_port_setpull ) },
+ { LSTRKEY( "setval" ), LFUNCVAL( pio_port_setval ) },
+ { LSTRKEY( "sethigh" ), LFUNCVAL( pio_port_sethigh ) },
+ { LSTRKEY( "setlow" ), LFUNCVAL( pio_port_setlow ) },
+ { LSTRKEY( "getval" ), LFUNCVAL( pio_port_getval ) },
{ LNILKEY, LNILVAL }
};
-const LUA_REG_TYPE pio_map[] =
+const LUA_REG_TYPE pio_map[] =
{
#if LUA_OPTIMIZE_MEMORY > 0
- { LSTRKEY( "__metatable" ), LROVAL( pio_map ) },
+ { LSTRKEY( "pin" ), LROVAL( pio_pin_map ) },
+ { LSTRKEY( "port" ), LROVAL( pio_port_map ) },
{ LSTRKEY( "INPUT" ), LNUMVAL( PIO_DIR_INPUT ) },
{ LSTRKEY( "OUTPUT" ), LNUMVAL( PIO_DIR_OUTPUT ) },
{ LSTRKEY( "PULLUP" ), LNUMVAL( PLATFORM_IO_PIN_PULLUP ) },
{ LSTRKEY( "PULLDOWN" ), LNUMVAL( PLATFORM_IO_PIN_PULLDOWN ) },
{ LSTRKEY( "NOPULL" ), LNUMVAL( PLATFORM_IO_PIN_NOPULL ) },
- { LSTRKEY( "dir" ), LROVAL( pio_dir_map ) },
- { LSTRKEY( "pull" ), LROVAL( pio_pull_map ) },
+ { LSTRKEY( "__metatable" ), LROVAL( pio_map ) },
#endif
{ LSTRKEY( "__index" ), LFUNCVAL( pio_mt_index ) },
- { LSTRKEY( "__newindex" ), LFUNCVAL( pio_mt_newindex ) },
{ LNILKEY, LNILVAL }
};
@@ -304,35 +354,26 @@
return 0;
#else // #if LUA_OPTIMIZE_MEMORY > 0
luaL_register( L, AUXLIB_PIO, pio_map );
-
- // Set this table as its own metatable
+
+ // Set it as its own metatable
lua_pushvalue( L, -1 );
lua_setmetatable( L, -2 );
-
+
// Set constants for direction/pullups
- lua_pushnumber( L, PIO_DIR_INPUT );
- lua_setfield( L, -2, "INPUT" );
- lua_pushnumber( L, PIO_DIR_OUTPUT );
- lua_setfield( L, -2, "OUTPUT" );
- lua_pushnumber( L, PLATFORM_IO_PIN_PULLUP );
- lua_setfield( L, -2, "PULLUP" );
- lua_pushnumber( L, PLATFORM_IO_PIN_PULLDOWN );
- lua_setfield( L, -2, "PULLDOWN" );
- lua_pushnumber( L, PLATFORM_IO_PIN_NOPULL );
- lua_setfield( L, -2, "NOPULL" );
+ MOD_REG_NUMBER( L, "INPUT", PIO_DIR_INPUT );
+ MOD_REG_NUMBER( L, "OUTPUT", PIO_DIR_OUTPUT );
+ MOD_REG_NUMBER( L, "PULLUP", PLATFORM_IO_PIN_PULLUP );
+ MOD_REG_NUMBER( L, "PULLDOWN", PLATFORM_IO_PIN_PULLDOWN );
+ MOD_REG_NUMBER( L, "NOPULL", PLATFORM_IO_PIN_NOPULL );
- // Setup the new tables (dir and pull) inside pio
+ // Setup the new tables (pin and port) inside pio
lua_newtable( L );
- luaL_register( L, NULL, pio_dir_map );
- lua_pushvalue( L, -1 );
- lua_setmetatable( L, -2 );
- lua_setfield( L, -2, "dir" );
+ luaL_register( L, NULL, pio_pin_map );
+ lua_setfield( L, -2, "pin" );
lua_newtable( L );
- luaL_register( L, NULL, pio_pull_map );
- lua_pushvalue( L, -1 );
- lua_setmetatable( L, -2 );
- lua_setfield( L, -2, "pull" );
+ luaL_register( L, NULL, pio_port_map );
+ lua_setfield( L, -2, "port" );
return 1;
#endif // #if LUA_OPTIMIZE_MEMORY > 0
Modified: branches/eagle_mmc/src/modules/term.c
===================================================================
--- branches/eagle_mmc/src/modules/term.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/term.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -24,8 +24,8 @@
return 0;
}
-// Lua: gotoxy( x, y )
-static int luaterm_gotoxy( lua_State* L )
+// Lua: moveto( x, y )
+static int luaterm_moveto( lua_State* L )
{
unsigned x, y;
@@ -35,8 +35,8 @@
return 0;
}
-// Lua: up( lines )
-static int luaterm_up( lua_State* L )
+// Lua: moveup( lines )
+static int luaterm_moveup( lua_State* L )
{
unsigned delta;
@@ -45,8 +45,8 @@
return 0;
}
-// Lua: down( lines )
-static int luaterm_down( lua_State* L )
+// Lua: movedown( lines )
+static int luaterm_movedown( lua_State* L )
{
unsigned delta;
@@ -55,8 +55,8 @@
return 0;
}
-// Lua: left( cols )
-static int luaterm_left( lua_State* L )
+// Lua: moveleft( cols )
+static int luaterm_moveleft( lua_State* L )
{
unsigned delta;
@@ -65,8 +65,8 @@
return 0;
}
-// Lua: right( cols )
-static int luaterm_right( lua_State* L )
+// Lua: moveright( cols )
+static int luaterm_moveright( lua_State* L )
{
unsigned delta;
@@ -75,82 +75,39 @@
return 0;
}
-// Lua: lines = lines()
-static int luaterm_lines( lua_State* L )
+// Lua: lines = getlines()
+static int luaterm_getlines( lua_State* L )
{
lua_pushinteger( L, term_get_lines() );
return 1;
}
-// Lua: columns = cols()
-static int luaterm_cols( lua_State* L )
+// Lua: columns = getcols()
+static int luaterm_getcols( lua_State* L )
{
lua_pushinteger( L, term_get_cols() );
return 1;
}
-// Lua: put( c1, c2, ... )
-static int luaterm_put( lua_State* L )
+// Lua: print( string1, string2, ... )
+// or print( x, y, string1, string2, ... )
+static int luaterm_print( lua_State* L )
{
- int total = lua_gettop( L ), i;
- u8 data;
-
- for( i = 1; i <= total; i ++ )
- {
- data = ( u8 )luaL_checkinteger( L, 1 );
- term_putch( data );
- }
- return 0;
-}
-
-// Lua: putxy( x, y, c1, c2, ... )
-static int luaterm_putxy( lua_State* L )
-{
- int total = lua_gettop( L ), i;
- unsigned x, y;
- u8 data;
-
- x = ( unsigned )luaL_checkinteger( L, 1 );
- y = ( unsigned )luaL_checkinteger( L, 2 );
- term_gotoxy( x, y );
- for( i = 3; i <= total; i ++ )
- {
- data = ( u8 )luaL_checkinteger( L, i );
- term_putch( data );
- }
- return 0;
-}
-
-// Lua: putstr( string1, string2, ... )
-static int luaterm_putstr( lua_State* L )
-{
const char* buf;
size_t len, i;
- int total = lua_gettop( L ), s;
-
- for( s = 1; s <= total; s ++ )
- {
- luaL_checktype( L, s, LUA_TSTRING );
- buf = lua_tolstring( L, s, &len );
- for( i = 0; i < len; i ++ )
- term_putch( buf[ i ] );
- }
- return 0;
-}
+ int total = lua_gettop( L ), s = 1;
+ int x = -1, y = -1;
-// Lua: putstrxy( x, y, string1, string2, ... )
-static int luaterm_putstrxy( lua_State* L )
-{
- const char* buf;
- unsigned x, y;
- size_t len, i;
- int total = lua_gettop( L ), s;
-
- x = ( unsigned )luaL_checkinteger( L, 1 );
- y = ( unsigned )luaL_checkinteger( L, 2 );
- term_gotoxy( x, y );
- for( s = 3; s <= total; s ++ )
+ // Check if the function has integer arguments
+ if( lua_isnumber( L, 1 ) && lua_isnumber( L, 2 ) )
{
+ x = lua_tointeger( L, 1 );
+ y = lua_tointeger( L, 2 );
+ term_gotoxy( x, y );
+ s = 3;
+ }
+ for( ; s <= total; s ++ )
+ {
luaL_checktype( L, s, LUA_TSTRING );
buf = lua_tolstring( L, s, &len );
for( i = 0; i < len; i ++ )
@@ -159,26 +116,27 @@
return 0;
}
-// Lua: cursorx = cursorx()
-static int luaterm_cx( lua_State* L )
+// Lua: cursorx = getcx()
+static int luaterm_getcx( lua_State* L )
{
lua_pushinteger( L, term_get_cx() );
return 1;
}
-// Lua: cursory = cursory()
-static int luaterm_cy( lua_State* L )
+// Lua: cursory = getcy()
+static int luaterm_getcy( lua_State* L )
{
lua_pushinteger( L, term_get_cy() );
return 1;
}
-// Lua: key = getch( mode )
-static int luaterm_getch( lua_State* L )
+// Lua: key = getchar( [ mode ] )
+static int luaterm_getchar( lua_State* L )
{
- int temp;
+ int temp = TERM_INPUT_WAIT;
- temp = luaL_checkinteger( L, 1 );
+ if( lua_isnumber( L, 1 ) )
+ temp = lua_tointeger( L, 1 );
lua_pushinteger( L, term_getch( temp ) );
return 1;
}
@@ -216,20 +174,17 @@
{
{ LSTRKEY( "clrscr" ), LFUNCVAL( luaterm_clrscr ) },
{ LSTRKEY( "clreol" ), LFUNCVAL( luaterm_clreol ) },
- { LSTRKEY( "gotoxy" ), LFUNCVAL( luaterm_gotoxy ) },
- { LSTRKEY( "up" ), LFUNCVAL( luaterm_up ) },
- { LSTRKEY( "down" ), LFUNCVAL( luaterm_down ) },
- { LSTRKEY( "left" ), LFUNCVAL( luaterm_left ) },
- { LSTRKEY( "right" ), LFUNCVAL( luaterm_right ) },
- { LSTRKEY( "lines" ), LFUNCVAL( luaterm_lines ) },
- { LSTRKEY( "cols" ), LFUNCVAL( luaterm_cols ) },
- { LSTRKEY( "put" ), LFUNCVAL( luaterm_put ) },
- { LSTRKEY( "putstr" ), LFUNCVAL( luaterm_putstr ) },
- { LSTRKEY( "putxy" ), LFUNCVAL( luaterm_putxy ) },
- { LSTRKEY( "putstrxy" ), LFUNCVAL( luaterm_putstrxy ) },
- { LSTRKEY( "cursorx" ), LFUNCVAL( luaterm_cx ) },
- { LSTRKEY( "cursory" ), LFUNCVAL( luaterm_cy ) },
- { LSTRKEY( "getch" ), LFUNCVAL( luaterm_getch ) },
+ { LSTRKEY( "moveto" ), LFUNCVAL( luaterm_moveto ) },
+ { LSTRKEY( "moveup" ), LFUNCVAL( luaterm_moveup ) },
+ { LSTRKEY( "movedown" ), LFUNCVAL( luaterm_movedown ) },
+ { LSTRKEY( "moveleft" ), LFUNCVAL( luaterm_moveleft ) },
+ { LSTRKEY( "moveright" ), LFUNCVAL( luaterm_moveright ) },
+ { LSTRKEY( "getlines" ), LFUNCVAL( luaterm_getlines ) },
+ { LSTRKEY( "getcols" ), LFUNCVAL( luaterm_getcols ) },
+ { LSTRKEY( "print" ), LFUNCVAL( luaterm_print ) },
+ { LSTRKEY( "getcx" ), LFUNCVAL( luaterm_getcx ) },
+ { LSTRKEY( "getcy" ), LFUNCVAL( luaterm_getcy ) },
+ { LSTRKEY( "getchar" ), LFUNCVAL( luaterm_getchar ) },
#if LUA_OPTIMIZE_MEMORY > 0
{ LSTRKEY( "__metatable" ), LROVAL( term_map ) },
{ LSTRKEY( "NOWAIT" ), LNUMVAL( TERM_INPUT_DONT_WAIT ) },
@@ -264,3 +219,4 @@
return 0;
#endif // #ifdef BUILD_TERM
}
+
Modified: branches/eagle_mmc/src/modules/uart.c
===================================================================
--- branches/eagle_mmc/src/modules/uart.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/modules/uart.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -6,7 +6,18 @@
#include "platform.h"
#include "auxmods.h"
#include "lrotable.h"
+#include <string.h>
+#include <ctype.h>
+// Modes for the UART read function
+enum
+{
+ UART_READ_MODE_LINE,
+ UART_READ_MODE_NUMBER,
+ UART_READ_MODE_SPACE,
+ UART_READ_MODE_MAXSIZE
+};
+
// Lua: actualbaud = setup( id, baud, databits, parity, stopbits )
static int uart_setup( lua_State* L )
{
@@ -24,8 +35,8 @@
return 1;
}
-// Lua: send( id, string1, string2, ... )
-static int uart_send( lua_State* L )
+// Lua: write( id, string1, string2, ... )
+static int uart_write( lua_State* L )
{
int id;
const char* buf;
@@ -44,24 +55,108 @@
return 0;
}
-// Lua: data = recv( id, [ timer_id, timeout ] )
-static int uart_recv( lua_State* L )
+// Lua: data = read( id, format, [ timeout ], [ timer_id ] )
+static int uart_read( lua_State* L )
{
+ int id, res, mode, issign;
+ unsigned timer_id = 0;
+ s32 timeout = PLATFORM_UART_INFINITE_TIMEOUT, maxsize = 0, count = 0;
+ const char *fmt;
+ luaL_Buffer b;
+ char cres;
+
+ id = luaL_checkinteger( L, 1 );
+ MOD_CHECK_ID( uart, id );
+
+ // Check format
+ if( lua_isnumber( L, 2 ) )
+ {
+ if( ( maxsize = ( s32 )lua_tointeger( L, 2 ) ) < 0 )
+ return luaL_error( L, "invalid max size" );
+ mode = UART_READ_MODE_MAXSIZE;
+ }
+ else
+ {
+ fmt = luaL_checkstring( L, 2 );
+ if( !strcmp( fmt, "*l" ) )
+ mode = UART_READ_MODE_LINE;
+ else if( !strcmp( fmt, "*n" ) )
+ mode = UART_READ_MODE_NUMBER;
+ else if( !strcmp( fmt, "*s" ) )
+ mode = UART_READ_MODE_SPACE;
+ else
+ return luaL_error( L, "invalid format" );
+ }
+
+ // Check timeout and timer id
+ if( lua_gettop( L ) >= 3 )
+ {
+ timeout = luaL_checkinteger( L, 3 );
+ if( ( timeout < 0 ) && ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) )
+ return luaL_error( L, "invalid timeout value" );
+ if( ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) && ( timeout != 0 ) )
+ timer_id = luaL_checkinteger( L, 4 );
+ }
+
+ // Read data
+ luaL_buffinit( L, &b );
+ while( 1 )
+ {
+ if( ( res = platform_uart_recv( id, timer_id, timeout ) ) == -1 )
+ break;
+ cres = ( char )res;
+ count ++;
+ issign = ( count == 1 ) && ( ( res == '-' ) || ( res == '+' ) );
+ if( ( cres == '\n' ) && ( mode == UART_READ_MODE_LINE ) )
+ break;
+ if( !isdigit( cres ) && !issign && ( mode == UART_READ_MODE_NUMBER ) )
+ break;
+ if( isspace( cres ) && ( mode == UART_READ_MODE_SPACE ) )
+ break;
+ luaL_putchar( &b, cres );
+ if( ( count == maxsize ) && ( mode == UART_READ_MODE_MAXSIZE ) )
+ break;
+ }
+ luaL_pushresult( &b );
+
+ // Return an integer if needed
+ if( mode == UART_READ_MODE_NUMBER )
+ {
+ res = lua_tointeger( L, -1 );
+ lua_pop( L, 1 );
+ lua_pushinteger( L, res );
+ }
+ return 1;
+}
+
+// Lua: data = getchar( id, [ timeout ], [ timer_id ] )
+static int uart_getchar( lua_State* L )
+{
int id, res;
+ char cres;
unsigned timer_id = 0;
s32 timeout = PLATFORM_UART_INFINITE_TIMEOUT;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( uart, id );
+
+ // Check timeout and timer id
if( lua_gettop( L ) >= 2 )
{
- timer_id = luaL_checkinteger( L, 2 );
- timeout = luaL_checkinteger( L, 3 );
+ timeout = luaL_checkinteger( L, 2 );
if( ( timeout < 0 ) && ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) )
- timeout = 0x7FFFFFFF; // force timeout to its maximum value
+ return luaL_error( L, "invalid timeout value" );
+ if( ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) && ( timeout != 0 ) )
+ timer_id = luaL_checkinteger( L, 3 );
}
res = platform_uart_recv( id, timer_id, timeout );
- lua_pushinteger( L, res );
+ if( res == -1 )
+ lua_pushstring( L, "" );
+ else
+ {
+ cres = ( char )res;
+ lua_pushlstring( L, &cres, 1 );
+ }
return 1;
}
@@ -71,8 +166,9 @@
const LUA_REG_TYPE uart_map[] =
{
{ LSTRKEY( "setup" ), LFUNCVAL( uart_setup ) },
- { LSTRKEY( "send" ), LFUNCVAL( uart_send) },
- { LSTRKEY( "recv" ), LFUNCVAL( uart_recv ) },
+ { LSTRKEY( "write" ), LFUNCVAL( uart_write ) },
+ { LSTRKEY( "read" ), LFUNCVAL( uart_read ) },
+ { LSTRKEY( "getchar" ), LFUNCVAL( uart_getchar ) },
#if LUA_OPTIMIZE_MEMORY > 0
{ LSTRKEY( "PAR_EVEN" ), LNUMVAL( PLATFORM_UART_PARITY_EVEN ) },
{ LSTRKEY( "PAR_ODD" ), LNUMVAL( PLATFORM_UART_PARITY_ODD ) },
@@ -94,24 +190,16 @@
luaL_register( L, AUXLIB_UART, uart_map );
// Add the stop bits and parity constants (for uart.setup)
- lua_pushnumber( L, PLATFORM_UART_PARITY_EVEN );
- lua_setfield( L, -2, "PAR_EVEN" );
- lua_pushnumber( L, PLATFORM_UART_PARITY_ODD );
- lua_setfield( L, -2, "PAR_ODD" );
- lua_pushnumber( L, PLATFORM_UART_PARITY_NONE );
- lua_setfield( L, -2, "PAR_NONE" );
- lua_pushnumber( L, PLATFORM_UART_STOPBITS_1 );
- lua_setfield( L, -2, "STOP_1" );
- lua_pushnumber( L, PLATFORM_UART_STOPBITS_1_5 );
- lua_setfield( L, -2, "STOP_1_5" );
- lua_pushnumber( L, PLATFORM_UART_STOPBITS_2 );
- lua_setfield( L, -2, "STOP_2" );
+ MOD_REG_NUMBER( L, "PAR_EVEN", PLATFORM_UART_PARITY_EVEN );
+ MOD_REG_NUMBER( L, "PAR_ODD", PLATFORM_UART_PARITY_ODD );
+ MOD_REG_NUMBER( L, "PAR_NONE", PLATFORM_UART_PARITY_NONE );
+ MOD_REG_NUMBER( L, "STOP_1", PLATFORM_UART_STOPBITS_1 );
+ MOD_REG_NUMBER( L, "STOP_1_5", PLATFORM_UART_STOPBITS_1_5 );
+ MOD_REG_NUMBER( L, "STOP_2", PLATFORM_UART_STOPBITS_2 );
// Add the "none" and "infinite" constant used in recv()
- lua_pushnumber( L, 0 );
- lua_setfield( L, -2, "NO_TIMEOUT" );
- lua_pushnumber( L, PLATFORM_UART_INFINITE_TIMEOUT );
- lua_setfield( L, -2, "INF_TIMEOUT" );
+ MOD_REG_NUMBER( L, "NO_TIMEOUT", 0 );
+ MOD_REG_NUMBER( L, "INF_TIMEOUT", PLATFORM_UART_INFINITE_TIMEOUT );
return 1;
#endif // #if LUA_OPTIMIZE_MEMORY > 0
Modified: branches/eagle_mmc/src/newlib/genstd.c
===================================================================
--- branches/eagle_mmc/src/newlib/genstd.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/newlib/genstd.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -13,6 +13,7 @@
static p_std_send_char std_send_char_func;
static p_std_get_char std_get_char_func;
+int std_prev_char = -1;
// 'read'
static _ssize_t std_read( struct _reent *r, int fd, void* vptr, size_t len )
@@ -42,7 +43,14 @@
i = 0;
while( i < len )
{
- if( ( c = std_get_char_func() ) == -1 )
+ if( std_prev_char != -1 )
+ {
+ // We have a char from the previous run of std_read, so put it in the buffer
+ ptr[ i ++ ] = ( char )std_prev_char;
+ std_prev_char = -1;
+ continue;
+ }
+ if( ( c = std_get_char_func( STD_INFINITE_TIMEOUT ) ) == -1 )
break;
if( ( c == 8 ) || ( c == 0x7F ) ) // Backspace
{
@@ -55,19 +63,22 @@
}
continue;
}
- if( !isprint( c ) && c != '\n' && c != STD_CTRLZ_CODE )
+ if( !isprint( c ) && c != '\n' && c != '\r' && c != STD_CTRLZ_CODE )
continue;
if( c == STD_CTRLZ_CODE )
return 0;
- else
- std_send_char_func( DM_STDOUT_NUM, c );
- ptr[ i ] = c;
- if( c == '\n' )
+ std_send_char_func( DM_STDOUT_NUM, c );
+ if( c == '\r' || c == '\n' )
{
- std_send_char_func( DM_STDOUT_NUM, '\r' );
- return i + 1;
+ // Handle both '\r\n' and '\n\r' here
+ std_prev_char = std_get_char_func( STD_INTER_CHAR_TIMEOUT ); // consume the next char (\r or \n) if any
+ if( std_prev_char + c == '\r' + '\n' ) // we must ignore this character
+ std_prev_char = -1;
+ std_send_char_func( DM_STDOUT_NUM, '\r' + '\n' - c );
+ ptr[ i ] = '\n';
+ return i + 1;
}
- i ++;
+ ptr[ i ++ ] = c;
}
return len;
}
Modified: branches/eagle_mmc/src/newlib/stubs.c
===================================================================
--- branches/eagle_mmc/src/newlib/stubs.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/newlib/stubs.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -12,6 +12,7 @@
#include "platform_conf.h"
#include "genstd.h"
#include "utils.h"
+#include "salloc.h"
#ifdef USE_MULTIPLE_ALLOCATOR
#include "dlmalloc.h"
@@ -344,32 +345,35 @@
#endif
}
+#if defined( USE_MULTIPLE_ALLOCATOR ) || defined( USE_SIMPLE_ALLOCATOR )
+// Redirect all allocator calls to our dlmalloc/salloc
+
#ifdef USE_MULTIPLE_ALLOCATOR
-// Redirect all allocator calls to our dlmalloc
+#define CNAME( func ) dl##func
+#else
+#define CNAME( func ) s##func
+#endif
+
void* _malloc_r( struct _reent* r, size_t size )
{
- return dlmalloc( size );
+ return CNAME( malloc )( size );
}
void* _calloc_r( struct _reent* r, size_t nelem, size_t elem_size )
{
- return dlcalloc( nelem, elem_size );
+ return CNAME( calloc )( nelem, elem_size );
}
void _free_r( struct _reent* r, void* ptr )
{
- dlfree( ptr );
+ CNAME( free )( ptr );
}
void* _realloc_r( struct _reent* r, void* ptr, size_t size )
{
- return dlrealloc( ptr, size );
+ return CNAME( realloc )( ptr, size );
}
-void* _memalign_r( struct _reent* r, size_t align, size_t nbytes )
-{
- return dlmemalign( align, nbytes );
-}
#endif // #ifdef USE_MULTIPLE_ALLOCATOR
// *****************************************************************************
Modified: branches/eagle_mmc/src/platform/at91sam7x/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/at91sam7x/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/at91sam7x/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -30,15 +30,16 @@
# Toolset data
tools[ 'at91sam7x' ] = {}
-tools[ 'at91sam7x' ][ 'cccom' ] = "arm-elf-gcc -mcpu=arm7tdmi %s %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( modeflag, opt, local_include, cdefs )
-tools[ 'at91sam7x' ][ 'linkcom' ] = "arm-elf-gcc -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,entry -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( modeflag, ldscript, local_libs )
-tools[ 'at91sam7x' ][ 'ascom' ] = "arm-elf-gcc -x assembler-with-cpp %s -mcpu=arm7tdmi %s %s -D__ASSEMBLY__ -Wall -c $SOURCE -o $TARGET" % ( local_include, modeflag, cdefs )
+tools[ 'at91sam7x' ][ 'cccom' ] = "%s -mcpu=arm7tdmi %s %s $_CPPINCFLAGS -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, opt, cdefs )
+tools[ 'at91sam7x' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,entry -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], modeflag, ldscript, local_libs )
+tools[ 'at91sam7x' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=arm7tdmi %s %s -D__ASSEMBLY__ -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, cdefs )
# Programming function for LPC2888
def progfunc_at91sam7x( target, source, env ):
outname = output + ".elf"
- os.system( "arm-elf-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( "arm-elf-objcopy -O binary %s %s.bin" % ( outname, output ) )
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
tools[ 'at91sam7x' ][ 'progfunc' ] = progfunc_at91sam7x
+
Modified: branches/eagle_mmc/src/platform/at91sam7x/flash256.lds
===================================================================
--- branches/eagle_mmc/src/platform/at91sam7x/flash256.lds 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/at91sam7x/flash256.lds 2009-07-30 18:10:13 UTC (rev 371)
@@ -63,7 +63,9 @@
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_efixed = .;
- PROVIDE(etext = .);
+ PROVIDE(etext = .);
+ _fini = .;
+ *(.fini)
} >flash
.relocate : AT (_efixed)
@@ -77,6 +79,18 @@
_erelocate = .;
} >sram
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
.bss (NOLOAD) : {
_szero = .;
*(.bss .bss.*)
@@ -84,7 +98,7 @@
*(COMMON)
_ezero = .;
} >sram
-
+
end = .;
_sstack = 0x210000;
}
Modified: branches/eagle_mmc/src/platform/at91sam7x/flash512.lds
===================================================================
--- branches/eagle_mmc/src/platform/at91sam7x/flash512.lds 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/at91sam7x/flash512.lds 2009-07-30 18:10:13 UTC (rev 371)
@@ -64,6 +64,8 @@
. = ALIGN(4);
_efixed = .;
PROVIDE(etext = .);
+ _fini = .;
+ *(.fini)
} >flash
.relocate : AT (_efixed)
@@ -77,6 +79,18 @@
_erelocate = .;
} >sram
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
.bss (NOLOAD) : {
_szero = .;
*(.bss .bss.*)
Modified: branches/eagle_mmc/src/platform/at91sam7x/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/at91sam7x/platform.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/at91sam7x/platform.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -22,6 +22,17 @@
#include "platform_conf.h"
#include "buf.h"
+// "Stubs" used for our interrupt handlers
+// Just a trick to avoid interworking and some other complications
+
+#define INT_STUB( func )\
+ asm volatile(\
+ "push {lr}\n\t"\
+ "bl " #func "\n\t"\
+ "pop {r0}\n\t"\
+ "bx r0\n\t"\
+ )\
+
// ****************************************************************************
// Platform initialization
@@ -33,27 +44,33 @@
static const AT91S_TC* timer_base[] = { AT91C_BASE_TC0, AT91C_BASE_TC1, AT91C_BASE_TC2 };
#if VTMR_NUM_TIMERS > 0
-static void ISR_Tc2()
+void __isr_tc2_helper()
{
cmn_virtual_timer_cb();
AT91C_BASE_TC2->TC_SR;
- asm( "pop {r0}":: );
- asm( "bx r0":: );
}
+
+static void __attribute__((naked)) ISR_Tc2()
+{
+ INT_STUB( __isr_tc2_helper );
+}
#endif
// Buffered UART support
#ifdef BUF_ENABLE_UART
static volatile u32 c;
static AT91S_USART* pbase = CON_UART_ID == 0 ? AT91C_BASE_US0 : AT91C_BASE_US1;
-static void uart_rx_handler()
+void __uart_rx_handler_helper()
{
c = pbase->US_CSR;
c = pbase->US_RHR;
buf_write( BUF_ID_UART, CON_UART_ID, ( t_buf_data* )&c );
- asm( "pop {r0}":: );
- asm( "bx r0":: );
}
+
+static void __attribute__((naked)) uart_rx_handler()
+{
+ INT_STUB( __uart_rx_handler_helper );
+}
#endif
int platform_init()
@@ -168,7 +185,7 @@
case PLATFORM_IO_PORT_GET_VALUE:
pin->mask = 0x7FFFFFFF;
- pin->type = pinmask == PLATFORM_IO_READ_IN_MASK ? : PIO_INPUT : PIO_OUTPUT_0;
+ pin->type = pinmask == PLATFORM_IO_READ_IN_MASK ? PIO_INPUT : PIO_OUTPUT_0;
retval = PIO_Get( pin );
break;
Modified: branches/eagle_mmc/src/platform/at91sam7x/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/at91sam7x/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/at91sam7x/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -21,11 +21,9 @@
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
@@ -60,6 +58,7 @@
#endif
#define NUM_PWM 4
#define NUM_ADC 0
+#define NUM_CAN 0
// Enable RX buffering on UART
#define BUF_ENABLE_UART
Modified: branches/eagle_mmc/src/platform/avr32/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/avr32/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/avr32/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -11,16 +11,17 @@
# Toolset data
tools[ 'avr32' ] = {}
-tools[ 'avr32' ][ 'cccom' ] = "avr32-gcc -mpart=uc3a0512 %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, cdefs )
-tools[ 'avr32' ][ 'linkcom' ] = "avr32-gcc -nostartfiles -nostdlib -T %s -Wl,--gc-sections -Wl,-e,crt0 -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( ldscript, local_libs )
-tools[ 'avr32' ][ 'ascom' ] = "avr32-gcc -x assembler-with-cpp %s -mpart=uc3a0512 %s -Wall -c $SOURCE -o $TARGET" % ( local_include, cdefs )
+tools[ 'avr32' ][ 'cccom' ] = "%s -mpart=uc3a0512 %s $_CPPINCFLAGS -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, cdefs )
+tools[ 'avr32' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib -T %s -Wl,--gc-sections -Wl,-e,crt0 -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
+tools[ 'avr32' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mpart=uc3a0512 %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], cdefs )
# Programming function
def progfunc_avr32( target, source, env ):
outname = output + ".elf"
- os.system( "avr32-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( "avr32-objcopy -O ihex %s %s.hex" % ( outname, output ) )
+ os.system( "%s -O ihex %s %s.hex" % ( toolset[ 'bin' ], outname, output ) )
+
# print "Programming..."
# os.system( "batchisp3.sh -hardware usb -device at32uc3a0512 -operation erase f memory flash blankcheck loadbuffer %s program verify start reset 0" % ( output + ".hex" ) )
Modified: branches/eagle_mmc/src/platform/avr32/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/avr32/platform.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/avr32/platform.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -320,7 +320,7 @@
break;
case PLATFORM_IO_PORT_GET_VALUE:
- retval = platform_pio_get_port_reg( port, pinmask == PLATFORM_PIO_READ_IN_MASK ? PIO_REG_PVR : PIO_REG_OVR );
+ retval = platform_pio_get_port_reg( port, pinmask == PLATFORM_IO_READ_IN_MASK ? PIO_REG_PVR : PIO_REG_OVR );
break;
case PLATFORM_IO_PIN_GET:
Modified: branches/eagle_mmc/src/platform/avr32/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/avr32/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/avr32/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -22,11 +22,9 @@
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
@@ -60,6 +58,7 @@
#endif
#define NUM_PWM 0
#define NUM_ADC 0
+#define NUM_CAN 0
// Enable RX buffering on UART
#define BUF_ENABLE_UART
Modified: branches/eagle_mmc/src/platform/i386/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/i386/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/i386/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -9,14 +9,14 @@
# Toolset data
tools[ 'i386' ] = {}
-tools[ 'i386' ][ 'cccom' ] = "i686-elf-gcc %s %s -march=i386 -mfpmath=387 -m32 -ffunction-sections -fdata-sections -fno-builtin -fno-stack-protector %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, cdefs )
-tools[ 'i386' ][ 'linkcom' ] = "i686-elf-gcc -nostartfiles -nostdlib -march=i386 -mfpmath=387 -m32 -T %s -Wl,--gc-sections -Wl,-e,start -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( ldscript, local_libs )
-tools[ 'i386' ][ 'ascom' ] = "nasm -felf $SOURCE"
+tools[ 'i386' ][ 'cccom' ] = "%s %s $_CPPINCFLAGS -march=i386 -mfpmath=387 -m32 -ffunction-sections -fdata-sections -fno-builtin -fno-stack-protector %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, cdefs )
+tools[ 'i386' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib -march=i386 -mfpmath=387 -m32 -T %s -Wl,--gc-sections -Wl,-e,start -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
+tools[ 'i386' ][ 'ascom' ] = "%s -felf $SOURCE" % toolset[ 'asm' ]
# Programming function for i386 (not needed, empty function)
def progfunc_i386( target, source, env ):
outname = output + ".elf"
- os.system( "i686-elf-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Visit http://www.eluaproject.net for instructions on how to use your eLua ELF file"
tools[ 'i386' ][ 'progfunc' ] = progfunc_i386
Modified: branches/eagle_mmc/src/platform/i386/kb.c
===================================================================
--- branches/eagle_mmc/src/platform/i386/kb.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/i386/kb.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -8,6 +8,7 @@
#include "isr.h"
#include "type.h"
#include "utils.h"
+#include "term.h"
#define RSHIFT 0x36
#define LSHIFT 0x2A
@@ -21,42 +22,42 @@
* whatever you want using a macro, if you wish! */
const unsigned char kbdus[128] =
{
- 0, 27, '1', '2', '3', '4', '5', '6', '7', '8', /* 9 */
- '9', '0', '-', '=', '\b', /* Backspace */
- '\t', /* Tab */
- 'q', 'w', 'e', 'r', /* 19 */
- 't', 'y', 'u', 'i', 'o', 'p', '[', ']', '\n', /* Enter key */
- 0, /* 29 - Control */
- 'a', 's', 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* 39 */
- '\'', '`', 0, /* Left shift */
- '\\', 'z', 'x', 'c', 'v', 'b', 'n', /* 49 */
- 'm', ',', '.', '/', 0, /* Right shift */
+ 0, 27, '1', '2', '3', '4', '5', '6', '7', '8', /* 9 */
+ '9', '0', '-', '=', '\b', /* Backspace */
+ '\t', /* Tab */
+ 'q', 'w', 'e', 'r', /* 19 */
+ 't', 'y', 'u', 'i', 'o', 'p', '[', ']', '\n', /* Enter key */
+ 0, /* 29 - Control */
+ 'a', 's', 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* 39 */
+ '\'', '`', 0, /* Left shift */
+ '\\', 'z', 'x', 'c', 'v', 'b', 'n', /* 49 */
+ 'm', ',', '.', '/', 0, /* Right shift */
'*',
- 0, /* Alt */
- ' ', /* Space bar */
- 0, /* Caps lock */
- 0, /* 59 - F1 key ... > */
+ 0, /* Alt */
+ ' ', /* Space bar */
+ 0, /* Caps lock */
+ 0, /* 59 - F1 key ... > */
0, 0, 0, 0, 0, 0, 0, 0,
- 0, /* < ... F10 */
- 0, /* 69 - Num lock*/
- 0, /* Scroll Lock */
- 0, /* Home key */
- 0, /* Up Arrow */
- 0, /* Page Up */
+ 0, /* < ... F10 */
+ 0, /* 69 - Num lock*/
+ 0, /* Scroll Lock */
+ 0, /* Home key */
+ 0, /* Up Arrow */
+ 0, /* Page Up */
'-',
- 0, /* Left Arrow */
+ 0, /* Left Arrow */
0,
- 0, /* Right Arrow */
+ 0, /* Right Arrow */
'+',
- 0, /* 79 - End key*/
- 0, /* Down Arrow */
- 0, /* Page Down */
- 0, /* Insert Key */
- 0, /* Delete Key */
+ 0, /* 79 - End key*/
+ 0, /* Down Arrow */
+ 0, /* Page Down */
+ 0, /* Insert Key */
+ 0, /* Delete Key */
0, 0, 0,
- 0, /* F11 Key */
- 0, /* F12 Key */
- 0, /* All other keys are undefined */
+ 0, /* F11 Key */
+ 0, /* F12 Key */
+ 0, /* All other keys are undefined */
};
const unsigned char shift_kbdus[128] =
@@ -101,17 +102,23 @@
// Keyboard buffer
#define KBUF_SIZE 64
-static u8 kb_buffer[ KBUF_SIZE ];
+static int kb_buffer[ KBUF_SIZE ];
static u8 r_ptr;
static volatile u8 w_ptr;
+// Special keys lookup
+static const unsigned char skeys[] = { 0x48, 0x50, 0x4b, 0x4d, 0x47, 0x4f, 0x49, 0x51, 0, 0, 0, 1 };
+
/* Handles the keyboard interrupt */
void keyboard_handler(registers_t regs)
{
unsigned char scancode;
+ int i;
/* Read from the keyboard's data buffer */
- scancode = inb(0x60);
+ /* Ignore 0xE0 (extended indication) */
+ if( ( scancode = inb( 0x60 ) ) == 0xE0 )
+ return;
/* If the top bit of the byte we read from the keyboard is
* set, that means that a key has just been released */
@@ -127,18 +134,28 @@
}
else
{
- /* Here, a key was just pressed. Please note that if you
- * hold a key down, you will get repeated key press
- * interrupts. */
- /* Just to show you how this works, we simply translate
- * the keyboard scancode into an ASCII value, and then
- * display it to the screen. You can get creative and
- * use some flags to see if a shift is pressed and use a
- * different layout, or you can add another 128 entries
- * to the above layout to correspond to 'shift' being
- * held. If shift is held using the larger lookup table,
- * you would add 128 to the scancode when you look for it */
+ /* Check if this is a special key (will be used by the term module) */
+ for( i = 0; i < sizeof( skeys ) / sizeof( unsigned char ); i ++ )
+ if( skeys[ i ] == scancode )
+ {
+ kb_buffer[ w_ptr ] = TERM_FIRST_KEY + i;
+ w_ptr = ( w_ptr + 1 ) % KBUF_SIZE;
+ return;
+ }
+
+ /* Here, a key was just pressed. Please note that if you
+ * hold a key down, you will get repeated key press
+ * interrupts. */
+
+ /* Just to show you how this works, we simply translate
+ * the keyboard scancode into an ASCII value, and then
+ * display it to the screen. You can get creative and
+ * use some flags to see if a shift is pressed and use a
+ * different layout, or you can add another 128 entries
+ * to the above layout to correspond to 'shift' being
+ * held. If shift is held using the larger lookup table,
+ * you would add 128 to the scancode when you look for it */
if( ( scancode == RSHIFT ) || ( scancode == LSHIFT ) )
shift_pressed = 1;
else if( scancode == CTRL )
@@ -148,13 +165,13 @@
if( ( ( w_ptr + 1 ) % KBUF_SIZE ) != r_ptr )
{
unsigned char thechar = shift_pressed ? shift_kbdus[scancode] : kbdus[scancode];
- if( ctrl_pressed ) // Look for CTRL+Z (EOF)
- thechar = ( thechar == 'z' || thechar == 'Z' ) ? STD_CTRLZ_CODE : 0;
- if( thechar != 0 )
- {
+ if( ctrl_pressed ) // Look for CTRL+Z (EOF)
+ thechar = ( thechar == 'z' || thechar == 'Z' ) ? STD_CTRLZ_CODE : 0;
+ if( thechar != 0 )
+ {
kb_buffer[ w_ptr ] = thechar;
w_ptr = ( w_ptr + 1 ) % KBUF_SIZE;
- }
+ }
}
}
}
@@ -169,7 +186,7 @@
// Return a key from the keyboard (blocking!)
int keyboard_getch()
{
- u8 c;
+ int c;
while( r_ptr == w_ptr );
c = kb_buffer[ r_ptr ];
Modified: branches/eagle_mmc/src/platform/i386/monitor.c
===================================================================
--- branches/eagle_mmc/src/platform/i386/monitor.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/i386/monitor.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -94,26 +94,26 @@
res->op = res->p1 = res->p2 = 0;
switch( last )
{
- case 'J': // clrscr
+ case 'J': // clrscr
if( *p != '2' )
return 0;
res->op = ANSI_SEQ_CLRSCR;
break;
- case 'K': // clreol
+ case 'K': // clreol
res->op = ANSI_SEQ_CLREOL;
break;
- case 'H': // gotoxy
+ case 'H': // gotoxy
res->op = ANSI_SEQ_GOTOXY;
if( *p != 'H' )
sscanf( p, "%d;%d", &res->p1, &res->p2 );
break;
- case 'A': // up
- case 'B': // down
- case 'C': // right
- case 'D': // left
+ case 'A': // up
+ case 'B': // down
+ case 'C': // right
+ case 'D': // left
res->op = last - 'A' + ANSI_SEQ_UP;
sscanf( p, "%d", &res->p1 );
break;
@@ -153,47 +153,47 @@
if( isalpha( c ) )
{
monitor_ansi_inbuf[ monitor_ansi_count ] = '\0';
- ansi_op op;
- if( monitor_cvt_escape( monitor_ansi_inbuf, &op ) )
- {
- // Interpret out sequence
- switch( op.op )
- {
- case ANSI_SEQ_CLRSCR:
- monitor_clear();
- break;
+ ansi_op op;
+ if( monitor_cvt_escape( monitor_ansi_inbuf, &op ) )
+ {
+ // Interpret out sequence
+ switch( op.op )
+ {
+ case ANSI_SEQ_CLRSCR:
+ monitor_clear();
+ break;
- case ANSI_SEQ_CLREOL:
- prev = cursor_x;
- while( cursor_x++ < 80 )
- {
- location = video_memory + (cursor_y*80 + cursor_x);
- *location = ' ' | attribute;
- }
- cursor_x = prev;
- break;
+ case ANSI_SEQ_CLREOL:
+ prev = cursor_x;
+ while( cursor_x++ < 80 )
+ {
+ location = video_memory + (cursor_y*80 + cursor_x);
+ *location = ' ' | attribute;
+ }
+ cursor_x = prev;
+ break;
- case ANSI_SEQ_GOTOXY:
- cursor_y = ( u8int )op.p1;
- cursor_x = ( u8int )op.p2;
- move_cursor();
- break;
+ case ANSI_SEQ_GOTOXY:
+ cursor_y = ( u8int )op.p1 - 1;
+ cursor_x = ( u8int )op.p2 - 1;
+ move_cursor();
+ break;
- case ANSI_SEQ_UP:
- case ANSI_SEQ_LEFT:
- case ANSI_SEQ_RIGHT:
- case ANSI_SEQ_DOWN:
+ case ANSI_SEQ_UP:
+ case ANSI_SEQ_LEFT:
+ case ANSI_SEQ_RIGHT:
+ case ANSI_SEQ_DOWN:
{
- int xm = op.op == ANSI_SEQ_LEFT ? -1 : op.op == ANSI_SEQ_RIGHT ? 1 : 0;
- int ym = op.op == ANSI_SEQ_UP ? -1 : op.op == ANSI_SEQ_DOWN ? 1 : 0;
- cursor_x += xm * op.p1;
- cursor_y += ym * op.p1;
- move_cursor();
- break;
+ int xm = op.op == ANSI_SEQ_LEFT ? -1 : op.op == ANSI_SEQ_RIGHT ? 1 : 0;
+ int ym = op.op == ANSI_SEQ_UP ? -1 : op.op == ANSI_SEQ_DOWN ? 1 : 0;
+ cursor_x += xm * op.p1;
+ cursor_y += ym * op.p1;
+ move_cursor();
+ break;
}
}
- }
- monitor_reading_ansi = 0;
+ }
+ monitor_reading_ansi = 0;
}
return;
}
Modified: branches/eagle_mmc/src/platform/i386/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/i386/platform.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/i386/platform.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,6 +1,7 @@
// Platform-dependent functions
#include "platform.h"
+#include "platform_conf.h"
#include "type.h"
#include "devman.h"
#include "genstd.h"
@@ -8,12 +9,56 @@
#include <errno.h>
#include <string.h>
#include <ctype.h>
+#include "term.h"
// Platform specific includes
#include "monitor.h"
#include "descriptor_tables.h"
#include "kb.h"
+// ****************************************************************************
+// Terminal support code
+
+#ifdef BUILD_TERM
+
+static void i386_term_out( u8 data )
+{
+ monitor_put( data );
+}
+
+static int i386_term_in( int mode )
+{
+ if( mode == TERM_INPUT_DONT_WAIT )
+ return -1;
+ else
+ return keyboard_getch();
+}
+
+static int i386_term_translate( int data )
+{
+ int newdata = data;
+
+ if( data == 0 )
+ return KC_UNKNOWN;
+ else switch( data )
+ {
+ case '\n':
+ newdata = KC_ENTER;
+ break;
+
+ case '\t':
+ newdata = KC_TAB;
+ break;
+
+ case '\b':
+ newdata = KC_BACKSPACE;
+ break;
+ }
+ return newdata;
+}
+
+#endif // #ifdef BUILD_TERM
+
// *****************************************************************************
// std functions
static void scr_write( int fd, char c )
@@ -22,9 +67,17 @@
monitor_put( c );
}
-static int kb_read()
+static int kb_read( s32 to )
{
- return keyboard_getch();
+ int res;
+
+ if( to != STD_INFINITE_TIMEOUT )
+ return -1;
+ else
+ {
+ while( ( res = keyboard_getch() ) >= TERM_FIRST_KEY );
+ return res;
+ }
}
// ****************************************************************************
@@ -75,7 +128,12 @@
// Set the send/recv functions
std_set_send_func( scr_write );
std_set_get_func( kb_read );
-
+
+ // Set term functions
+#ifdef BUILD_TERM
+ term_init( TERM_LINES, TERM_COLS, i386_term_out, i386_term_in, i386_term_translate );
+#endif
+
// All done
return PLATFORM_OK;
}
Modified: branches/eagle_mmc/src/platform/i386/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/i386/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/i386/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -5,6 +5,7 @@
#include "auxmods.h"
#include "type.h"
+#include "stacks.h"
// *****************************************************************************
// Define here what components you want for this platform
@@ -12,15 +13,22 @@
#define BUILD_SHELL
#define BUILD_ROMFS
#define BUILD_CON_GENERIC
+#define BUILD_TERM
+#define TERM_LINES 25
+#define TERM_COLS 80
+
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PD, luaopen_pd, pd_map )\
- _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )
+// Bogus defines for common.c
#define CON_UART_ID 0
+#define CON_TIMER_ID 0
// *****************************************************************************
// Configuration data
@@ -35,6 +43,7 @@
#define NUM_TIMER 0
#define NUM_PWM 0
#define NUM_ADC 0
+#define NUM_CAN 0
// CPU frequency (needed by the CPU module, 0 if not used)
#define CPU_FREQUENCY 0
@@ -51,6 +60,6 @@
// (start address and end address)
u32 platform_get_lastmem();
#define MEM_START_ADDRESS { ( void* )end }
-#define MEM_END_ADDRESS { ( void* )( platform_get_lastmem() - 16384 - 1 ) }
+#define MEM_END_ADDRESS { ( void* )( platform_get_lastmem() - STACK_SIZE_TOTAL - 1 ) }
#endif // #ifndef __PLATFORM_CONF_H__
Added: branches/eagle_mmc/src/platform/i386/stacks.h
===================================================================
--- branches/eagle_mmc/src/platform/i386/stacks.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/i386/stacks.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,9 @@
+// Stack size definitions
+
+#ifndef __STACKS_H__
+#define __STACKS_H__
+
+#define STACK_SIZE_TOTAL 32768
+
+#endif
+
Modified: branches/eagle_mmc/src/platform/lm3s/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lm3s/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,19 +1,19 @@
# Configuration file for the LM3S microcontroller
+specific_files = "startup_gcc.c platform.c usart.c sysctl.c gpio.c ssi.c timer.c pwm.c ethernet.c systick.c flash.c interrupt.c cpu.c adc.c"
-specific_files = "startup_gcc.c platform.c usart.c sysctl.c gpio.c ssi.c timer.c pwm.c ethernet.c systick.c flash.c interrupt.c cpu.c adc.c mmc.c"
-if boardname != 'EAGLE-100':
+if boardname == 'EK-LM3S6965' or boardname == 'EK-LM3S8962':
specific_files = specific_files + " rit128x96x4.c disp.c"
-ldscript = "lm3s.ld"
+ cdefs = cdefs + " -DENABLE_DISP"
-# Compiler prefix
-# arm-elf- ELF compiler
-# arm-eabi- devkitARM EABI compiler
-# arm-none-eabi- CodeSourcery EABI compiler
-if boardname != 'EAGLE-100':
- cprefix= "arm-elf-"
+# The default for the Eagle 100 board is to start the image at 0x2000,
+# so that the built in Ethernet boot loader can be used to upload it
+if boardname == 'EAGLE-100':
+ linkopts = "-Wl,-Ttext,0x2000"
else:
- cprefix= "arm-eabi-"
+ linkopts = ""
+ldscript = "lm3s.ld"
+
# Prepend with path
specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
ldscript = "src/platform/%s/%s" % ( platform, ldscript )
@@ -22,18 +22,15 @@
# Toolset data
tools[ 'lm3s' ] = {}
-tools[ 'lm3s' ][ 'cccom' ] = cprefix + "gcc -mcpu=cortex-m3 -mthumb %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, cdefs )
-if cprefix == 'arm-elf-':
- tools[ 'lm3s' ][ 'linkcom' ] = cprefix + "gcc -nostartfiles -nostdlib -T %s -Wl,--gc-sections -Wl,-e,ResetISR -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( ldscript, local_libs )
-else:
- tools[ 'lm3s' ][ 'linkcom' ] = cprefix + "gcc -mthumb -mcpu=cortex-m3 -nostartfiles -T %s -Wl,--gc-sections -Wl,-e,ResetISR -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lm %s" % ( ldscript, local_libs )
-tools[ 'lm3s' ][ 'ascom' ] = cprefix + "gcc -x assembler-with-cpp %s -mcpu=cortex-m3 -mthumb %s -Wall -c $SOURCE -o $TARGET" % ( local_include, cdefs )
+tools[ 'lm3s' ][ 'cccom' ] = "%s -mcpu=cortex-m3 -mthumb %s $_CPPINCFLAGS -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, cdefs )
+tools[ 'lm3s' ][ 'linkcom' ] = "%s -mthumb -mcpu=cortex-m3 -nostartfiles -T %s %s -Wl,--gc-sections -Wl,-e,ResetISR -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lm %s" % ( toolset[ 'compile' ], ldscript, linkopts, local_libs )
+tools[ 'lm3s' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=cortex-m3 -mthumb %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], cdefs )
# Programming function
def progfunc_lm3s( target, source, env ):
outname = output + ".elf"
- os.system( cprefix + "size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( cprefix + "objcopy -O binary %s %s.bin" % ( outname, output ) )
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
tools[ 'lm3s' ][ 'progfunc' ] = progfunc_lm3s
Modified: branches/eagle_mmc/src/platform/lm3s/disp.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/disp.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lm3s/disp.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,4 +1,6 @@
-// Module for interfacing with Lua DISP code
+// eLua Module for LM3S RIT OLED Display Support
+// disp is a platform-dependent (LM3S) module, that binds to Lua the basic API
+// from Luminary Micro
#include "lua.h"
#include "lualib.h"
@@ -97,8 +99,8 @@
{ LSTRKEY( "on" ), LFUNCVAL( disp_on ) },
{ LSTRKEY( "off" ), LFUNCVAL( disp_off ) },
{ LSTRKEY( "clear" ), LFUNCVAL( disp_clear ) },
- { LSTRKEY( "stringdraw" ), LFUNCVAL( disp_stringDraw ) },
- { LSTRKEY( "imagedraw" ), LFUNCVAL( disp_imageDraw ) },
+ { LSTRKEY( "print" ), LFUNCVAL( disp_stringDraw ) },
+ { LSTRKEY( "draw" ), LFUNCVAL( disp_imageDraw ) },
{ LNILKEY, LNILVAL }
};
Modified: branches/eagle_mmc/src/platform/lm3s/lm3s.ld
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/lm3s.ld 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lm3s/lm3s.ld 2009-07-30 18:10:13 UTC (rev 371)
@@ -22,9 +22,9 @@
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_etext = .;
- PROVIDE(etext = .);
- _fini = . ;
- *(.fini)
+ PROVIDE(etext = .);
+ _fini = . ;
+ *(.fini)
} >flash
@@ -38,19 +38,19 @@
. = ALIGN(4);
_edata = .;
} >sram
-
- .ARM.extab :
- {
- *(.ARM.extab*)
- } >sram
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx*)
- } >sram
- __exidx_end = .;
-
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
.bss (NOLOAD) : {
_bss = .;
*(.bss .bss.*)
Modified: branches/eagle_mmc/src/platform/lm3s/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/platform.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lm3s/platform.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -108,7 +108,7 @@
// ****************************************************************************
// PIO
-// LM3S8962, LM3S6965, LM3S6918 (8 GPIO ports)
+// Same configuration on LM3S8962, LM3S6965, LM3S6918 (8 ports)
static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE };
@@ -179,7 +179,7 @@
// ****************************************************************************
// SPI
-// LM3S8962, LM3S6965, LM3S6918 (2 SPI ports)
+// Same configuration on LM3S8962, LM3S6965 and LM3S6918 (2 SPI ports)
// All possible LM3S SPIs defs
// FIXME this anticipates support for a platform with 2 SPI port
@@ -237,8 +237,12 @@
// ****************************************************************************
// UART
+<<<<<<< HEAD:src/platform/lm3s/platform.c
// LM3S8962, LM3S6918 (2 UARTs)
// LM3S6965 (3 UARTs)
+=======
+// Different configurations for LM3S8962, LM3S6918 (2 UARTs) and LM3S6965 (3 UARTs)
+>>>>>>> remotes/trunk:src/platform/lm3s/platform.c
// All possible LM3S uarts defs
static const u32 uart_base[] = { UART0_BASE, UART1_BASE, UART2_BASE };
@@ -337,7 +341,11 @@
// ****************************************************************************
// Timers
+<<<<<<< HEAD:src/platform/lm3s/platform.c
// LM3S8962, LM3S6965, LM3S6918 (4 timers)
+=======
+// Same on LM3S8962, LM3S6965 and LM3S6918 (4 timers)
+>>>>>>> remotes/trunk:src/platform/lm3s/platform.c
// All possible LM3S timers defs
static const u32 timer_base[] = { TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE };
@@ -375,6 +383,7 @@
{
case PLATFORM_TIMER_OP_START:
res = 0xFFFFFFFF;
+ TimerControlTrigger(base, TIMER_A, false);
TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
break;
@@ -401,8 +410,13 @@
// ****************************************************************************
// PWMs
+<<<<<<< HEAD:src/platform/lm3s/platform.c
// LM3S8962, LM3S6965 (6 PWM ports)
// LM3S6918 (0 PWM ports)
+=======
+// Similar on LM3S8962 and LM3S6965
+// LM3S6918 has no PWM
+>>>>>>> remotes/trunk:src/platform/lm3s/platform.c
// SYSCTL div data and actual div factors
const static u32 pwm_div_ctl[] = { SYSCTL_PWMDIV_1, SYSCTL_PWMDIV_2, SYSCTL_PWMDIV_4, SYSCTL_PWMDIV_8, SYSCTL_PWMDIV_16, SYSCTL_PWMDIV_32, SYSCTL_PWMDIV_64 };
@@ -518,155 +532,170 @@
const static u32 adc_ctls[] = { ADC_CTL_CH0, ADC_CTL_CH1, ADC_CTL_CH2, ADC_CTL_CH3 };
const static u32 adc_ints[] = { INT_ADC0, INT_ADC1, INT_ADC2, INT_ADC3 };
+int platform_adc_check_timer_id( unsigned id, unsigned timer_id )
+{
+ return ( ( timer_id >= ADC_TIMER_FIRST_ID ) && ( timer_id < ( ADC_TIMER_FIRST_ID + ADC_NUM_TIMERS ) ) );
+}
+
void platform_adc_stop( unsigned id )
{
- elua_adc_state *s = adc_get_ch_state( id );
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
- ADCSequenceDisable( ADC_BASE, s->id );
-
s->op_pending = 0;
+ INACTIVATE_CHANNEL(d, id);
- if ( s->burst )
+ // If there are no more active channels, stop the sequencer
+ if( d->ch_active == 0 )
{
- TimerControlTrigger( timer_base[s->timer_id], TIMER_A, false );
+ ADCSequenceDisable( ADC_BASE, d->seq_id );
+ d->running = 0;
}
}
// Handle ADC interrupts
void ADCIntHandler( void )
{
- unsigned long rawSample;
- unsigned id;
+ u32 tmpbuff[ NUM_ADC ];
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+ elua_adc_ch_state *s;
+
+ ADCIntClear( ADC_BASE, d->seq_id );
+ ADCSequenceDataGet( ADC_BASE, d->seq_id, tmpbuff );
+
+ d->seq_ctr = 0;
+
+ // Update smoothing and/or write to buffer if needed
+ while( d->seq_ctr < d->seq_len )
+ {
+ s = d->ch_state[ d->seq_ctr ];
+ d->sample_buf[ d->seq_ctr ] = ( u16 )tmpbuff[ d->seq_ctr ];
+ s->value_fresh = 1; // Mark sample as fresh
- // Check each sequence for a pending sample
- for( id = 0; id < NUM_ADC; id ++ )
- {
- if( ADCIntStatus(ADC_BASE, id, false) )
- {
- elua_adc_state *s = adc_get_ch_state( id );
-
- // Clear Interrupt & Get Sample
- ADCIntClear(ADC_BASE, id);
- ADCSequenceDataGet(ADC_BASE, id, &rawSample);
-
- buf_write( BUF_ID_ADC, id, ( t_buf_data* )&rawSample);
-
- // Fill in smoothing buffer until warmed up
- if ( s->logsmoothlen > 0 && s->smooth_ready == 0)
- adc_smooth_data( id );
-
- // If we have the number of requested samples, stop sampling
- if ( buf_get_count( BUF_ID_ADC, id ) >= s->reqsamples )
- {
- platform_adc_stop( id );
- }
- else if ( s->burst == 0 )
- {
- // Need to manually fire off sample request in single sample mode
- ADCProcessorTrigger( ADC_BASE, id );
- }
-
+ // Fill in smoothing buffer until warmed up
+ if ( s->logsmoothlen > 0 && s->smooth_ready == 0)
+ adc_smooth_data( s->id );
+
+#if defined( BUF_ENABLE_ADC )
+ else if ( s->reqsamples > 1 )
+ {
+ buf_write( BUF_ID_ADC, s->id, ( t_buf_data* )s->value_ptr );
+ s->value_fresh = 0;
}
+#endif
+
+ // If we have the number of requested samples, stop sampling
+ if ( adc_samples_available( s->id ) >= s->reqsamples && s->freerunning == 0 )
+ platform_adc_stop( s->id );
+
+ d->seq_ctr++;
}
+ d->seq_ctr = 0;
+
+ // Only attempt to refresh sequence order if still running
+ // This allows us to "cache" an old sequence if all channels
+ // finish at the same time
+ if ( d->running == 1 )
+ adc_update_dev_sequence( 0 );
+
+ if ( d->clocked == 0 && d->running == 1 )
+ {
+ // Need to manually fire off sample request in single sample mode
+ ADCProcessorTrigger( ADC_BASE, d->seq_id );
+ }
}
static void adcs_init()
{
unsigned id;
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
-
+
+ // Try ramping up max sampling rate
+ SysCtlADCSpeedSet(SYSCTL_ADCSPEED_500KSPS);
+ SysCtlADCSpeedSet(SYSCTL_ADCSPEED_1MSPS);
+
for( id = 0; id < NUM_ADC; id ++ )
{
- // Init ADC State Struct
- adc_init_state( id );
-
- // Make sure sequencer is disabled before making changes
- ADCSequenceDisable( ADC_BASE, id );
-
- // Conversion initiated on processor trigger
- ADCSequenceConfigure( ADC_BASE, id, ADC_TRIGGER_PROCESSOR, id ) ;
-
- // Samples go into sequencer of the same number as input channel
- ADCSequenceStepConfigure( ADC_BASE, id, 0, ADC_CTL_IE | ADC_CTL_END | adc_ctls[id] );
-
- ADCIntEnable(ADC_BASE, id);
- IntEnable(adc_ints[id]);
-
- // Restart Sequencer
- ADCSequenceEnable( ADC_BASE, id );
+ adc_init_ch_state( id );
}
+
+ // Perform sequencer setup
+ platform_adc_setclock( 0, 0 );
+ ADCIntEnable( ADC_BASE, d->seq_id );
+ IntEnable( adc_ints[ d->seq_id ] );
}
-// Get a single sample from the specified ADC channel
-int platform_adc_sample( unsigned id )
-{
- elua_adc_state *s = adc_get_ch_state( id );
- int res;
+u32 platform_adc_setclock( unsigned id, u32 frequency )
+{
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
// Make sure sequencer is disabled before making changes
- ADCSequenceDisable( ADC_BASE, id );
+ ADCSequenceDisable( ADC_BASE, d->seq_id );
- // If switching from burst, resize & flush buffer
- if ( s->burst == 1 )
+ if ( frequency > 0 )
{
- res = buf_set( BUF_ID_ADC, id, ADC_BUF_SIZE , BUF_DSIZE_U16 );
- if ( res != PLATFORM_OK )
- return res;
- // Need more general buf resizing... for now flush each time
- buf_flush( BUF_ID_ADC, id );
- s->burst = 0;
- s->reqsamples = 0;
+ d->clocked = 1;
+ // Set sequence id to be triggered repeatedly, with priority id
+ ADCSequenceConfigure( ADC_BASE, d->seq_id, ADC_TRIGGER_TIMER, d->seq_id );
+
+ // Set up timer trigger
+ TimerLoadSet( timer_base[ d->timer_id ], TIMER_A, SysCtlClockGet() / frequency );
+ frequency = SysCtlClockGet() / TimerLoadGet( timer_base[ d->timer_id ], TIMER_A );
}
-
- s->op_pending = 1;
- s->reqsamples += 1;
-
- // Conversion will run back-to-back until required samples are acquired
- ADCSequenceConfigure( ADC_BASE, id, ADC_TRIGGER_PROCESSOR, id ) ;
-
- // Start Sequencer
- ADCSequenceEnable( ADC_BASE, id );
- ADCProcessorTrigger( ADC_BASE, id );
-
- return PLATFORM_OK;
+ else
+ {
+ d->clocked = 0;
+ // Conversion will run back-to-back until required samples are acquired
+ ADCSequenceConfigure( ADC_BASE, d->seq_id, ADC_TRIGGER_PROCESSOR, d->seq_id ) ;
+ }
+
+ return frequency;
}
-
-int platform_adc_burst( unsigned id, u8 logcount, unsigned timer_id, u32 frequency )
-{
- elua_adc_state *s = adc_get_ch_state( id );
- int res;
+int platform_adc_update_sequence( )
+{
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
- // Make sure sequencer is disabled before making changes
- ADCSequenceDisable( ADC_BASE, id );
+ ADCSequenceDisable( ADC_BASE, d->seq_id );
- // If switching from non-burst, resize & flush buffer
- if (s->burst == 0 || ( (u16) 1 << logcount ) != buf_get_count( BUF_ID_ADC, id ) )
+ // NOTE: seq ctr should have an incrementer that will wrap appropriately..
+ d->seq_ctr = 0;
+ while( d->seq_ctr < d->seq_len-1 )
{
- res = buf_set( BUF_ID_ADC, id, logcount, BUF_DSIZE_U16 );
- if ( res != PLATFORM_OK )
- return res;
- // Need more general buf resizing... for now flush each time
- buf_flush( BUF_ID_ADC, id );
- s->burst = 1;
- s->reqsamples = 0;
+ ADCSequenceStepConfigure( ADC_BASE, d->seq_id, d->seq_ctr, adc_ctls[ d->ch_state[ d->seq_ctr ]->id ] );
+ d->seq_ctr++;
}
+ ADCSequenceStepConfigure( ADC_BASE, d->seq_id, d->seq_ctr, ADC_CTL_IE | ADC_CTL_END | adc_ctls[ d->ch_state[ d->seq_ctr ]->id ] );
+ d->seq_ctr = 0;
- s->timer_id = timer_id;
- s->op_pending = 1;
- s->reqsamples = (u16) 1 << logcount;
+ ADCSequenceEnable( ADC_BASE, d->seq_id );
+
+ return PLATFORM_OK;
+}
- // Set sequence id to be triggered repeatedly, with priority id
- ADCSequenceConfigure( ADC_BASE, id, ADC_TRIGGER_TIMER, id );
- // Restart Sequencer
- ADCSequenceEnable( ADC_BASE, id );
+int platform_adc_start_sequence()
+{
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
- // Setup timer and go
- TimerConfigure(timer_base[timer_id], TIMER_CFG_32_BIT_PER);
- TimerLoadSet(timer_base[timer_id], TIMER_A, SysCtlClockGet() / frequency);
- TimerControlTrigger(timer_base[timer_id], TIMER_A, true);
- TimerEnable(timer_base[timer_id], TIMER_A);
+ if( d->running != 1 )
+ {
+ adc_update_dev_sequence( 0 );
+
+ ADCSequenceEnable( ADC_BASE, d->seq_id );
+ d->running = 1;
+
+ if( d->clocked == 1 )
+ {
+ TimerControlTrigger(timer_base[d->timer_id], TIMER_A, true);
+ TimerEnable(timer_base[d->timer_id], TIMER_A);
+ }
+ else
+ {
+ ADCProcessorTrigger( ADC_BASE, d->seq_id );
+ }
+ }
return PLATFORM_OK;
}
Modified: branches/eagle_mmc/src/platform/lm3s/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/lm3s/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lm3s/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -22,6 +22,7 @@
#define BUILD_DNS
#define BUILD_CON_GENERIC
#define BUILD_ADC
+#define BUILD_LUARPC
//#define BUILD_CON_TCP
// *****************************************************************************
@@ -29,35 +30,48 @@
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
-#if (ELUA_BOARD == EK-LM3S6965) || (ELUA_BOARD == EK-LM3S8962)
-// LM3S board with RIT display
-#define BUILD_DISP_RIT
+#ifdef ENABLE_DISP
#define AUXLIB_DISP "disp"
LUALIB_API int ( luaopen_disp )( lua_State* L );
+#define DISPLINE _ROM( AUXLIB_DISP, luaopen_disp, disp_map )
+#else
+#define DISPLINE
+#endif
+#ifdef FORLM3S6918
+#define PWMLINE
+#else
+#define PWMLINE _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )
+#endif
+
+#ifdef BUILD_UIP
+#define NETLINE _ROM( AUXLIB_NET, luaopen_net, net_map )
+#else
+#define NETLINE
+#endif
+
#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
_ROM( AUXLIB_SPI, luaopen_spi, spi_map )\
_ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
_ROM( AUXLIB_PD, luaopen_pd, pd_map )\
_ROM( AUXLIB_UART, luaopen_uart, uart_map )\
+ PWMLINE\
_ROM( AUXLIB_TERM, luaopen_term, term_map )\
- _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
- _ROM( AUXLIB_NET, luaopen_net, net_map )\
+ NETLINE\
_ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
_ROM( AUXLIB_ADC, luaopen_adc, adc_map )\
- _ROM( AUXLIB_DISP, luaopen_disp, disp_map )\
+ _ROM( AUXLIB_LUARPC, luaopen_luarpc, rpc_map )\
+ DISPLINE\
_ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
#else
// LM3S board without RIT display
@@ -110,24 +124,34 @@
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 7
#define NUM_SPI 1
-#ifdef FORLM3S8962
+#ifdef FORLM3S6965
+ #define NUM_UART 3
+#else
#define NUM_UART 2
-#else
- #define NUM_UART 3
#endif
#define NUM_TIMER 4
-#define NUM_PWM 6
+#ifndef FORLM3S6918
+ #define NUM_PWM 6
+#else
+ #define NUM_PWM 0
+#endif
#define NUM_ADC 4
+#define NUM_CAN 0
// Enable RX buffering on UART
-#define BUF_ENABLE_UART
-#define CON_BUF_SIZE BUF_SIZE_128
+//#define BUF_ENABLE_UART
+//#define CON_BUF_SIZE BUF_SIZE_128
-// ADC Bit Depth for Built-in ADCs
+// ADC Configuration Params
#define ADC_BIT_RESOLUTION 10
#define BUF_ENABLE_ADC
#define ADC_BUF_SIZE BUF_SIZE_2
+// These should be adjusted to support multiple ADC devices
+#define ADC_TIMER_FIRST_ID 0
+#define ADC_NUM_TIMERS NUM_TIMER
+
+
// CPU frequency (needed by the CPU module, 0 if not used)
#define CPU_FREQUENCY SysCtlClockGet()
Modified: branches/eagle_mmc/src/platform/lpc288x/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/lpc288x/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lpc288x/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -31,15 +31,15 @@
# Toolset data
tools[ 'lpc288x' ] = {}
-tools[ 'lpc288x' ][ 'cccom' ] = "arm-elf-gcc -mcpu=arm7tdmi %s %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, modeflag, cdefs )
-tools[ 'lpc288x' ][ 'linkcom' ] = "arm-elf-gcc -mcpu=arm7tdmi -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,HardReset -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( modeflag, ldscript, local_libs )
-tools[ 'lpc288x' ][ 'ascom' ] = "arm-elf-gcc -x assembler-with-cpp %s -mcpu=arm7tdmi %s %s -Wall -c $SOURCE -o $TARGET" % ( local_include, modeflag, cdefs )
+tools[ 'lpc288x' ][ 'cccom' ] = "%s -mcpu=arm7tdmi %s $_CPPINCFLAGS %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, modeflag, cdefs )
+tools[ 'lpc288x' ][ 'linkcom' ] = "%s -mcpu=arm7tdmi -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,HardReset -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], modeflag, ldscript, local_libs )
+tools[ 'lpc288x' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=arm7tdmi %s %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, cdefs )
# Programming function for LPC2888
def progfunc_lpc288x( target, source, env ):
outname = output + ".elf"
- os.system( "arm-elf-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( "arm-elf-objcopy -O binary %s %s.bin" % ( outname, output ) )
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
tools[ 'lpc288x' ][ 'progfunc' ] = progfunc_lpc288x
Modified: branches/eagle_mmc/src/platform/lpc288x/lpc2888.lds
===================================================================
--- branches/eagle_mmc/src/platform/lpc288x/lpc2888.lds 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lpc288x/lpc2888.lds 2009-07-30 18:10:13 UTC (rev 371)
@@ -25,6 +25,8 @@
. = ALIGN(4);
_efixed = .;
PROVIDE(etext = .);
+ _fini = .;
+ *(.fini)
} >flash
.relocate : AT (_efixed)
@@ -37,6 +39,18 @@
_erelocate = .;
} >sram
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
.bss (NOLOAD) : {
_szero = .;
*(.bss .bss.*)
Deleted: branches/eagle_mmc/src/platform/lpc288x/main.c
===================================================================
--- branches/eagle_mmc/src/platform/lpc288x/main.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lpc288x/main.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,239 +0,0 @@
-/********************************************************************
- * Project: STR9-comStick GNU (UART)
- * File: main.c
- *
- * System: ARM9TDMI 32 Bit (STR912FW44X)
- * Compiler: GCC 4.0.3
- *
- * Date: 2006-12-20
- * Author: Applications at Hitex.de
- *
- * Rights: Hitex Development Tools GmbH
- * Greschbachstr. 12
- * D-76229 Karlsruhe
- ********************************************************************
- * Description:
- *
- * This file is part of the GNU Example chain
- * The code is bassed on usage of the STmicro library functions
- * This is a small implementation of UART1 feature echoing external input
- * The application runs in ARM mode with high optimization level.
- *
- ********************************************************************
- * History:
- *
- * Revision 1.0 2006/12/20 Gn
- * Initial revision
- ********************************************************************
- * This is a preliminary version.
- *
- * WARRANTY: HITEX warrants that the media on which the SOFTWARE is
- * furnished is free from defects in materials and workmanship under
- * normal use and service for a period of ninety (90) days. HITEX entire
- * liability and your exclusive remedy shall be the replacement of the
- * SOFTWARE if the media is defective. This Warranty is void if failure
- * of the media resulted from unauthorized modification, accident, abuse,
- * or misapplication.
- *
- * DISCLAIMER: OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED
- * "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES,
- * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING
- * OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR
- * LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT
- * OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGES.
- ********************************************************************/
-
-#include "defines.h"
-
-#define global extern /* to declare external variables and functions */
-#include "91x_lib.h"
-
-#include "main.h"
-#define GPIO_Alt1 0x01
-
-#define TxBufferSize (countof(TxBuffer) - 1)
-#define RxBufferSize 0xFF
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a) (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
- UART_InitTypeDef UART_InitStructure;
- u8 TxBuffer[] = "UART1 - 1,8,N,1 at 115.2k communication without flow control\n\r";
- u8 RxBuffer[RxBufferSize];
- u8 NbrOfDataToTransfer = TxBufferSize;
- u8 TxCounter = 0;
- u8 RxCounter = 0;
-
- GPIO_InitTypeDef GPIO_InitStructure;
- TIM_InitTypeDef TIM_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
- void SCU_Configuration(void);
- void GPIO_Configuration(void);
- void UART1_Configuration(void);
- static void Delay(u32 nCount);
-
-int main (void)
-{
-
- /* Configure the system clocks */
- SCU_Configuration();
- /* Configure the GPIOs */
- GPIO_Configuration();
- /* Configure and start the UART1 */
- UART1_Configuration();
-
- /* endless loop */
- while (1)
- {
- {
- if((UART_GetFlagStatus(UART1, UART_FLAG_RxFIFOEmpty) != SET)&&(RxCounter < RxBufferSize))
- {
- RxBuffer[0] = UART1->DR;
- UART_SendData(UART1, RxBuffer[0]);
- }
- }
-
- /* Turn OFF leds connected to P9.0, P9.1 pins */
- GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_SET);
-
- /* Insert delay */
- Delay(0x1FFFF);
-
- /* Turn ON leds connected to P9.0, P9.1 pins */
- GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_RESET);
-
- /* Insert delay */
- Delay(0x1FFFF);
- }
-}
-
-void SCU_Configuration(void)
-{
- SCU_MCLKSourceConfig(SCU_MCLK_OSC);
-
- SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */
- SCU_PLLCmd(ENABLE); /* PLL Enabled */
-
- SCU_MCLKSourceConfig(SCU_MCLK_PLL); /* MCLK = PLL */
-
- FMI_BankRemapConfig(4, 2, 0, 0x80000); /* Set Flash banks size & address */
- FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,\
- FMI_LVD_ENABLE, FMI_FREQ_HIGH); /* FMI Waite States */
-
- /* Enable VIC clock */
- SCU_AHBPeriphClockConfig(__VIC, ENABLE);
- SCU_AHBPeriphReset(__VIC, DISABLE);
-
- /* Set the PCLK Clock to MCLK/2 */
- SCU_PCLKDivisorConfig(SCU_PCLK_Div1);
-
- /* Enable the UART0 Clock */
- SCU_APBPeriphClockConfig(__UART1, ENABLE);
-
- /* Enable the clock for TIM0 and TIM1 */
- SCU_APBPeriphClockConfig(__TIM01, ENABLE);
- SCU_APBPeriphReset(__TIM01, DISABLE);
-
- SCU_APBPeriphClockConfig(__TIM23, ENABLE);
- SCU_APBPeriphReset(__TIM23, DISABLE);
-
-
-/* Enable the GPIO3 Clock */
- SCU_APBPeriphClockConfig(__GPIO3, ENABLE);
-
- SCU_APBPeriphClockConfig(__GPIO4, ENABLE); /* Enable the clock for the GPIO4 */
-
- /* Enable the __GPIO8 */
- SCU_APBPeriphClockConfig(__GPIO8 ,ENABLE);
- /* Enable the __GPIO9 */
- SCU_APBPeriphClockConfig(__GPIO9 ,ENABLE);
-}
-/* GPIO Configuration --------------------------------------------------------*/
-void GPIO_Configuration(void)
-{
- GPIO_DeInit(GPIO3);
- GPIO_DeInit(GPIO4); /* GPIO4 Deinitialization */
- GPIO_DeInit(GPIO9);
- /* IOs */
- GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
- GPIO_Init (GPIO4, &GPIO_InitStructure);
- /* onboard LED */
- GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
- GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
- GPIO_Init (GPIO9, &GPIO_InitStructure);
- GPIO_WriteBit(GPIO9, GPIO_Pin_0, Bit_RESET);
-
-/* configure UART1_Rx pin GPIO3.2*/
- GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
- GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
- GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
- GPIO_Init (GPIO3, &GPIO_InitStructure);
-
- /*Gonfigure UART1_Tx pin GPIO3.3*/
- GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
- GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
- GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
- GPIO_Init (GPIO3, &GPIO_InitStructure);
-
-}
-
-/* UART1 configuration -------------------------------------------------------*/
-void UART1_Configuration(void)
- {
-/* UART1 configured as follow:
- - Word Length = 8 Bits
- - One Stop Bit
- - No parity
- - BaudRate = 115200 baud
- - no Hardware flow control enabled (RTS and CTS signals)
- - Receive and transmit enabled
- - Receive and transmit FIFOs are enabled
- - Transmit and Receive FIFOs levels have 8 bytes depth
- */
- UART_InitStructure.UART_WordLength = UART_WordLength_8D;
- UART_InitStructure.UART_StopBits = UART_StopBits_1;
- UART_InitStructure.UART_Parity = UART_Parity_No ;
- UART_InitStructure.UART_BaudRate = 115200;
- UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
- UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx;
- UART_InitStructure.UART_FIFO = UART_FIFO_Enable;//UART_FIFO_Enable;
- UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
- UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
-
- UART_DeInit(UART1);
- UART_Init(UART1, &UART_InitStructure);
-
- /* Enable the UART0 */
- UART_Cmd(UART1, ENABLE);
-
- while(NbrOfDataToTransfer--)
- {
- UART_SendData(UART1, TxBuffer[TxCounter++]);
- while(UART_GetFlagStatus(UART1, UART_FLAG_TxFIFOFull) != RESET);
- }
-}
-
-/*******************************************************************************
-* Function Name : Delay
-* Description : Inserts a delay time.
-* Input : nCount: specifies the delay time length.
-*******************************************************************************/
-static void Delay(u32 nCount)
-{
- u32 j = 0;
-
- for(j = nCount; j != 0; j--);
-}
-/************************************** EOF *********************************/
Modified: branches/eagle_mmc/src/platform/lpc288x/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/lpc288x/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/lpc288x/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -21,11 +21,9 @@
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Configuration data
@@ -40,6 +38,7 @@
#define NUM_TIMER 2
#define NUM_PWM 0
#define NUM_ADC 0
+#define NUM_CAN 0
// CPU frequency (needed by the CPU module, 0 if not used)
#define CPU_FREQUENCY Fcclk
Added: branches/eagle_mmc/src/platform/sim/boot.s
===================================================================
--- branches/eagle_mmc/src/platform/sim/boot.s 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/boot.s 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,22 @@
+;
+; boot.s -- Kernel start location. Also defines multiboot header.
+; Based on Bran's kernel development tutorial file start.asm
+;
+
+[BITS 32] ; All instructions should be 32-bit.
+
+[GLOBAL start] ; Kernel entry point.
+[EXTERN main] ; This is the entry point of our C code
+[EXTERN platform_ll_init] ; Low level initializatin function
+[SECTION .text]
+
+start:
+
+ push ebx
+ call platform_ll_init
+
+ ; Execute the kernel:
+ call main ; call our main() function.
+ jmp $ ; Enter an infinite loop, to stop the processor
+ ; executing whatever rubbish is in the memory
+ ; after our kernel!
Added: branches/eagle_mmc/src/platform/sim/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/sim/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,24 @@
+# Configuration file for the linux backend
+
+specific_files = "boot.s utils.s hostif_%s.c platform.c host.c" % cputype.lower()
+ldscript = "i386.ld"
+
+# override default optimize settings (-Os is broken right now)
+opt = " -g -O0 "
+
+# Prepend with path
+specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
+ldscript = "src/platform/%s/%s" % ( platform, ldscript )
+
+# Toolset data
+tools[ 'sim' ] = {}
+tools[ 'sim' ][ 'cccom' ] = "%s %s $_CPPINCFLAGS -march=i386 -mfpmath=387 -m32 -ffunction-sections -fdata-sections -fno-builtin -fno-stack-protector %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, cdefs )
+tools[ 'sim' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib -march=i386 -mfpmath=387 -m32 -T %s -Wl,--gc-sections -Wl,-e,start -Wl,--allow-multiple-definition -Wl,-static -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
+tools[ 'sim' ][ 'ascom' ] = "%s -felf $SOURCE" % toolset[ 'asm' ]
+
+# Programming function for i386 (not needed, empty function)
+def progfunc_dummy( target, source, env ):
+ print "Run the simulator and enjoy :)"
+
+tools[ 'sim' ][ 'progfunc' ] = progfunc_dummy
+
Added: branches/eagle_mmc/src/platform/sim/host.c
===================================================================
--- branches/eagle_mmc/src/platform/sim/host.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/host.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,57 @@
+#include "host.h"
+
+#define __NR_read 3
+#define __NR_write 4
+#define __NR_mmap2 192
+#define __NR_exit 1
+
+int host_errno = 0;
+
+#define __syscall_return(type, res) do { \
+ if((unsigned long)(res) >= (unsigned long)(-125)) { \
+ host_errno = -(res); \
+ res = -1; \
+ } \
+ return (type) (res); \
+} while(0)
+
+#define _syscall1(type,name,type1,arg1) \
+type host_##name(type1 arg1) \
+{ \
+long __res; \
+__asm__ volatile ("int $0x80" \
+ : "=a" (__res) \
+ : "0" (__NR_##name),"b" ((long)(arg1))); \
+__syscall_return(type,__res); \
+}
+
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
+type host_##name(type1 arg1,type2 arg2,type3 arg3) \
+{ \
+long __res; \
+__asm__ volatile ("int $0x80" \
+ : "=a" (__res) \
+ : "0" (__NR_##name),"b" ((long)(arg1)),"c" ((long)(arg2)), \
+ "d" ((long)(arg3))); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+ type5,arg5,type6,arg6) \
+type host_##name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
+{ \
+long __res; \
+__asm__ volatile ("push %%ebp ; movl %%eax,%%ebp ; movl %1,%%eax ; int $0x80 ; pop %%ebp" \
+ : "=a" (__res) \
+ : "i" (__NR_##name),"b" ((long)(arg1)),"c" ((long)(arg2)), \
+ "d" ((long)(arg3)),"S" ((long)(arg4)),"D" ((long)(arg5)), \
+ "0" ((long)(arg6))); \
+ __syscall_return(type, __res); \
+}
+
+_syscall3(ssize_t, read, int, fd, void *, buf, size_t, count);
+_syscall3(ssize_t, write, int, fd, const void *, buf, size_t, count);
+_syscall6(void *,mmap2, void *,addr, size_t, length, int, prot, int, flags, int, fd, off_t, offset);
+_syscall1(void, exit, int, status);
+
Added: branches/eagle_mmc/src/platform/sim/host.h
===================================================================
--- branches/eagle_mmc/src/platform/sim/host.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/host.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,30 @@
+// host.h -- Defines syscall wrappers to access host OS.
+
+#ifndef _HOST_H
+#define _HOST_H
+
+#include <stddef.h>
+#include <sys/types.h>
+
+extern int host_errno;
+
+ssize_t host_read( int fd, void * buf, size_t count);
+ssize_t host_write( int fd, const void * buf, size_t count);
+
+#define PROT_READ 0x1 /* Page can be read. */
+#define PROT_WRITE 0x2 /* Page can be written. */
+#define PROT_EXEC 0x4 /* Page can be executed. */
+#define PROT_NONE 0x0 /* Page can not be accessed. */
+
+#define MAP_SHARED 0x01 /* Share changes. */
+#define MAP_PRIVATE 0x02 /* Changes are private. */
+#define MAP_FIXED 0x10 /* Interpret addr exactly. */
+#define MAP_ANONYMOUS 0x20 /* Don't use a file. */
+
+#define MAP_FAILED (void *)(-1)
+
+void *host_mmap2(void *addr, size_t length, int prot, int flags, int fd, off_t pgoffset);
+void host_exit(int status);
+
+#endif // _HOST_H
+
Added: branches/eagle_mmc/src/platform/sim/hostif.h
===================================================================
--- branches/eagle_mmc/src/platform/sim/hostif.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/hostif.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,22 @@
+// Host I/O operations for eLua 'simulator'
+
+#ifndef __HOSTIO_H__
+#define __HOSTIO_H__
+
+// Write a single character out to the screen.
+void hostif_put(char c);
+
+// Output a null-terminated ASCII string to the monitor.
+void hostif_write(const char *c);
+
+// Get a char from keyboard
+int hostif_getch();
+
+// Get memory
+void *hostif_getmem( unsigned size );
+
+// Terminate the simulator (exit program)
+void hostif_exit();
+
+#endif // __HOSTIO_H__
+
Added: branches/eagle_mmc/src/platform/sim/hostif_linux.c
===================================================================
--- branches/eagle_mmc/src/platform/sim/hostif_linux.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/hostif_linux.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,46 @@
+// Host I/O operations for eLua 'simulator'
+
+#include <ctype.h>
+#include <string.h>
+#include <stdio.h>
+#include "term.h"
+#include "host.h"
+#include "hostif.h"
+
+#define EOF (-1)
+#define STDIN_FILENO 0
+#define STDOUT_FILENO 1
+
+void hostif_put(char c)
+{
+ host_write(STDOUT_FILENO, &c, 1);
+}
+
+void hostif_write(const char *c)
+{
+ int i = 0;
+ while (c[i])
+ hostif_put(c[i++]);
+}
+
+int hostif_getch()
+{
+ unsigned char ch = 0;
+ if(host_read(STDIN_FILENO, &ch, 1) != 1) {
+ return EOF;
+ }
+ return (int)ch;
+
+}
+
+void* hostif_getmem( unsigned size )
+{
+ void *pmem = host_mmap2( 0, size, (PROT_READ|PROT_WRITE), (MAP_PRIVATE|MAP_ANONYMOUS), -1, 0 );
+ return pmem == MAP_FAILED ? NULL : pmem;
+}
+
+void hostif_exit()
+{
+ host_exit( 0 );
+}
+
Added: branches/eagle_mmc/src/platform/sim/i386.ld
===================================================================
--- branches/eagle_mmc/src/platform/sim/i386.ld 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/i386.ld 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,40 @@
+/* Link.ld -- Linker script for the kernel - ensure everything goes in the */
+/* Correct place. */
+/* Original file taken from Bran's Kernel Development */
+/* tutorials: http://www.osdever.net/bkerndev/index.php. */
+
+SECTIONS
+{
+
+ .text 0x100000 :
+ {
+ KEEP(*(.header))
+ code = .; _code = .; __code = .;
+ PROVIDE(stext = .);
+ *(.text .text.*)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ *(.gnu.linkonce.t.*)
+ . = ALIGN(4096);
+ PROVIDE(etext = .);
+ }
+
+ .data :
+ {
+ data = .; _data = .; __data = .;
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(4096);
+ }
+
+ .bss :
+ {
+ bss = .; _bss = .; __bss = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4096);
+ }
+
+ end = .; _end = .; __end = .;
+}
Copied: branches/eagle_mmc/src/platform/sim/platform.c (from rev 269, branches/eagle_mmc/src/platform/i386/platform.c)
===================================================================
--- branches/eagle_mmc/src/platform/i386/platform.c 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/src/platform/sim/platform.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,151 @@
+// Platform-dependent functions
+
+#include "platform.h"
+#include "platform_conf.h"
+#include "type.h"
+#include "devman.h"
+#include "genstd.h"
+#include <reent.h>
+#include <errno.h>
+#include <string.h>
+#include <ctype.h>
+#include "term.h"
+
+// Platform specific includes
+#include "hostif.h"
+
+// ****************************************************************************
+// Terminal support code
+
+#ifdef BUILD_TERM
+
+static void i386_term_out( u8 data )
+{
+ hostif_put( data );
+}
+
+static int i386_term_in( int mode )
+{
+ if( mode == TERM_INPUT_DONT_WAIT )
+ return -1;
+ else
+ return hostif_getch();
+}
+
+static int i386_term_translate( int data )
+{
+ int newdata = data;
+
+ if( data == 0 )
+ return KC_UNKNOWN;
+ else switch( data )
+ {
+ case '\n':
+ newdata = KC_ENTER;
+ break;
+
+ case '\t':
+ newdata = KC_TAB;
+ break;
+
+ case '\b':
+ newdata = KC_BACKSPACE;
+ break;
+
+ case 0x1B:
+ newdata = KC_ESC;
+ break;
+ }
+ return newdata;
+}
+
+#endif // #ifdef BUILD_TERM
+
+// *****************************************************************************
+// std functions
+static void scr_write( int fd, char c )
+{
+ fd = fd;
+ hostif_put( c );
+}
+
+static int kb_read( s32 to )
+{
+ int res;
+
+ if( to != STD_INFINITE_TIMEOUT )
+ return -1;
+ else
+ {
+ while( ( res = hostif_getch() ) >= TERM_FIRST_KEY );
+ return res;
+ }
+}
+
+// ****************************************************************************
+// Platform initialization (low-level and full)
+
+void *memory_start_address = 0;
+void *memory_end_address = 0;
+
+void platform_ll_init()
+{
+ // Initialise heap memory region.
+ memory_start_address = hostif_getmem( MEM_LENGTH );
+ memory_end_address = memory_start_address + MEM_LENGTH;
+}
+
+int platform_init()
+{
+ if( memory_start_address == NULL )
+ {
+ hostif_write( "platform_init(): mmap failed\n" );
+ return PLATFORM_ERR;
+ }
+
+ // Set the std input/output functions
+ // Set the send/recv functions
+ std_set_send_func( scr_write );
+ std_set_get_func( kb_read );
+
+ // Set term functions
+#ifdef BUILD_TERM
+ term_init( TERM_LINES, TERM_COLS, i386_term_out, i386_term_in, i386_term_translate );
+#endif
+
+ term_clrscr();
+ term_gotoxy( 1, 1 );
+
+ // All done
+ return PLATFORM_OK;
+}
+
+// ****************************************************************************
+// "Dummy" UART functions
+
+u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
+{
+ return 0;
+}
+
+void platform_uart_send( unsigned id, u8 data )
+{
+}
+
+int platform_s_uart_recv( unsigned id, s32 timeout )
+{
+ return -1;
+}
+
+// ****************************************************************************
+// "Dummy" timer functions
+
+void platform_s_timer_delay( unsigned id, u32 delay_us )
+{
+}
+
+u32 platform_s_timer_op( unsigned id, int op, u32 data )
+{
+ return 0;
+}
+
Copied: branches/eagle_mmc/src/platform/sim/platform_conf.h (from rev 269, branches/eagle_mmc/src/platform/i386/platform_conf.h)
===================================================================
--- branches/eagle_mmc/src/platform/i386/platform_conf.h 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/src/platform/sim/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,67 @@
+// eLua platform configuration
+
+#ifndef __PLATFORM_CONF_H__
+#define __PLATFORM_CONF_H__
+
+#include "auxmods.h"
+#include "type.h"
+#include "stacks.h"
+
+// *****************************************************************************
+// Define here what components you want for this platform
+
+#define BUILD_SHELL
+#define BUILD_ROMFS
+#define BUILD_CON_GENERIC
+#define BUILD_TERM
+
+#define TERM_LINES 25
+#define TERM_COLS 80
+
+// *****************************************************************************
+// Auxiliary libraries that will be compiled for this platform
+
+#define LUA_PLATFORM_LIBS_ROM\
+ _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
+ _ROM( AUXLIB_TERM, luaopen_term, term_map )
+
+// Bogus defines for common.c
+#define CON_UART_ID 0
+#define CON_TIMER_ID 0
+
+// *****************************************************************************
+// Configuration data
+
+// Virtual timers (0 if not used)
+#define VTMR_NUM_TIMERS 0
+
+// Number of resources (0 if not available/not implemented)
+#define NUM_PIO 0
+#define NUM_SPI 0
+#define NUM_UART 0
+#define NUM_TIMER 0
+#define NUM_PWM 0
+#define NUM_ADC 0
+#define NUM_CAN 0
+
+// CPU frequency (needed by the CPU module, 0 if not used)
+#define CPU_FREQUENCY 0
+
+// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
+#define PIO_PREFIX 'A'
+// Pins per port configuration:
+// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
+// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
+// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
+#define PIO_PINS_PER_PORT 0
+
+// Allocator data: define your free memory zones here in two arrays
+// (start address and end address)
+extern void *memory_start_address;
+extern void *memory_end_address;
+#define MEM_LENGTH (1024 * 1024)
+#define MEM_START_ADDRESS { ( void* )memory_start_address }
+#define MEM_END_ADDRESS { ( void* )memory_end_address }
+
+#endif // #ifndef __PLATFORM_CONF_H__
Added: branches/eagle_mmc/src/platform/sim/stacks.h
===================================================================
--- branches/eagle_mmc/src/platform/sim/stacks.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/stacks.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,9 @@
+// Stack size definitions
+
+#ifndef __STACKS_H__
+#define __STACKS_H__
+
+#define STACK_SIZE_TOTAL 32768
+
+#endif
+
Copied: branches/eagle_mmc/src/platform/sim/type.h (from rev 269, branches/eagle_mmc/src/platform/stm32/type.h)
===================================================================
--- branches/eagle_mmc/src/platform/stm32/type.h 2009-03-26 02:17:48 UTC (rev 269)
+++ branches/eagle_mmc/src/platform/sim/type.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,30 @@
+#ifndef __TYPE_H__
+#define __TYPE_H__
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+#define TRUE (1)
+#endif
+
+typedef unsigned char BYTE;
+typedef unsigned short WORD;
+typedef unsigned long DWORD;
+typedef unsigned int BOOL;
+
+typedef unsigned char u8;
+typedef signed char s8;
+typedef unsigned short u16;
+typedef signed short s16;
+typedef unsigned long u32;
+typedef signed long s32;
+typedef unsigned long long u64;
+typedef signed long long s64;
+
+#endif
Added: branches/eagle_mmc/src/platform/sim/utils.s
===================================================================
--- branches/eagle_mmc/src/platform/sim/utils.s 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/sim/utils.s 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,33 @@
+;
+; boot.s -- Kernel start location. Also defines multiboot header.
+; Based on Bran's kernel development tutorial file start.asm
+;
+
+[BITS 32] ; All instructions should be 32-bit.
+
+[GLOBAL longjmp]
+[SECTION .text]
+
+longjmp:
+ push ebp
+ mov ebp, esp
+
+ mov edi, [ebp+8] ; get jump buffer
+ mov eax, [ebp+12] ; store retval in j->eax
+ mov [edi], eax
+
+ mov ebp, [edi+24]
+
+ mov esp, [edi+28]
+
+ push dword [edi+32]
+
+ mov eax, [edi]
+ mov ebx, [edi+4]
+ mov ecx, [edi+8]
+ mov edx, [edi+12]
+ mov esi, [edi+16]
+ mov edi, [edi+20]
+
+ ret
+
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/cortexm3_macro.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/cortexm3_macro.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/cortexm3_macro.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,53 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : cortexm3_macro.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : Header file for cortexm3_macro.s.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __CORTEXM3_MACRO_H
-#define __CORTEXM3_MACRO_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_type.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void __WFI(void);
-void __WFE(void);
-void __SEV(void);
-void __ISB(void);
-void __DSB(void);
-void __DMB(void);
-void __SVC(void);
-u32 __MRS_CONTROL(void);
-void __MSR_CONTROL(u32 Control);
-u32 __MRS_PSP(void);
-void __MSR_PSP(u32 TopOfProcessStack);
-u32 __MRS_MSP(void);
-void __MSR_MSP(u32 TopOfMainStack);
-void __RESETPRIMASK(void);
-void __SETPRIMASK(void);
-u32 __READ_PRIMASK(void);
-void __RESETFAULTMASK(void);
-void __SETFAULTMASK(void);
-u32 __READ_FAULTMASK(void);
-void __BASEPRICONFIG(u32 NewPriority);
-u32 __GetBASEPRI(void);
-u16 __REV_HalfWord(u16 Data);
-u32 __REV_Word(u32 Data);
-
-#endif /* __CORTEXM3_MACRO_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Added: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/misc.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/misc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/misc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,219 @@
+/**
+ ******************************************************************************
+ * @file misc.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete STM32 Devices IRQ Channels list, please
+ refer to stm32f10x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+ at code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+ at endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Property changes on: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/misc.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_adc.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_adc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_adc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,58 +1,106 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_adc.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* ADC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_ADC_H
#define __STM32F10x_ADC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* ADC Init structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+
typedef struct
{
- u32 ADC_Mode;
- FunctionalState ADC_ScanConvMode;
- FunctionalState ADC_ContinuousConvMode;
- u32 ADC_ExternalTrigConv;
- u32 ADC_DataAlign;
- u8 ADC_NbrOfChannel;
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
+ dual mode.
+ This parameter can be a value of @ref ADC_mode */
+
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
+/**
+ * @}
+ */
-/* Exported constants --------------------------------------------------------*/
-#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
- ((*(u32*)&(PERIPH)) == ADC2_BASE) || \
- ((*(u32*)&(PERIPH)) == ADC3_BASE))
-
-#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
- ((*(u32*)&(PERIPH)) == ADC3_BASE))
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
-/* ADC dual mode -------------------------------------------------------------*/
-#define ADC_Mode_Independent ((u32)0x00000000)
-#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
-#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
-#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
-#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
-#define ADC_Mode_InjecSimult ((u32)0x00050000)
-#define ADC_Mode_RegSimult ((u32)0x00060000)
-#define ADC_Mode_FastInterl ((u32)0x00070000)
-#define ADC_Mode_SlowInterl ((u32)0x00080000)
-#define ADC_Mode_AlterTrig ((u32)0x00090000)
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3))
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode
+ * @{
+ */
+
+#define ADC_Mode_Independent ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
+
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_Mode_RegInjecSimult) || \
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
@@ -63,26 +111,31 @@
((MODE) == ADC_Mode_FastInterl) || \
((MODE) == ADC_Mode_SlowInterl) || \
((MODE) == ADC_Mode_AlterTrig))
+/**
+ * @}
+ */
-/* ADC extrenal trigger sources for regular channels conversion --------------*/
-/* for ADC1 and ADC2 */
-#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
-#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
-#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
-#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
-#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)
-/* for ADC1, ADC2 and ADC3 */
-#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
-#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
-/* for ADC3 */
-#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)
-#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)
-#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)
-#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)
-#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)
-#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
@@ -97,34 +150,45 @@
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+ * @}
+ */
-/* ADC data align ------------------------------------------------------------*/
-#define ADC_DataAlign_Right ((u32)0x00000000)
-#define ADC_DataAlign_Left ((u32)0x00000800)
+/** @defgroup ADC_data_align
+ * @{
+ */
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
-/* ADC channels --------------------------------------------------------------*/
-#define ADC_Channel_0 ((u8)0x00)
-#define ADC_Channel_1 ((u8)0x01)
-#define ADC_Channel_2 ((u8)0x02)
-#define ADC_Channel_3 ((u8)0x03)
-#define ADC_Channel_4 ((u8)0x04)
-#define ADC_Channel_5 ((u8)0x05)
-#define ADC_Channel_6 ((u8)0x06)
-#define ADC_Channel_7 ((u8)0x07)
-#define ADC_Channel_8 ((u8)0x08)
-#define ADC_Channel_9 ((u8)0x09)
-#define ADC_Channel_10 ((u8)0x0A)
-#define ADC_Channel_11 ((u8)0x0B)
-#define ADC_Channel_12 ((u8)0x0C)
-#define ADC_Channel_13 ((u8)0x0D)
-#define ADC_Channel_14 ((u8)0x0E)
-#define ADC_Channel_15 ((u8)0x0F)
-#define ADC_Channel_16 ((u8)0x10)
-#define ADC_Channel_17 ((u8)0x11)
+/** @defgroup ADC_channels
+ * @{
+ */
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+#define ADC_Channel_10 ((uint8_t)0x0A)
+#define ADC_Channel_11 ((uint8_t)0x0B)
+#define ADC_Channel_12 ((uint8_t)0x0C)
+#define ADC_Channel_13 ((uint8_t)0x0D)
+#define ADC_Channel_14 ((uint8_t)0x0E)
+#define ADC_Channel_15 ((uint8_t)0x0F)
+#define ADC_Channel_16 ((uint8_t)0x10)
+#define ADC_Channel_17 ((uint8_t)0x11)
+
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
@@ -134,17 +198,22 @@
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+ * @}
+ */
-/* ADC sampling times --------------------------------------------------------*/
-#define ADC_SampleTime_1Cycles5 ((u8)0x00)
-#define ADC_SampleTime_7Cycles5 ((u8)0x01)
-#define ADC_SampleTime_13Cycles5 ((u8)0x02)
-#define ADC_SampleTime_28Cycles5 ((u8)0x03)
-#define ADC_SampleTime_41Cycles5 ((u8)0x04)
-#define ADC_SampleTime_55Cycles5 ((u8)0x05)
-#define ADC_SampleTime_71Cycles5 ((u8)0x06)
-#define ADC_SampleTime_239Cycles5 ((u8)0x07)
+/** @defgroup ADC_sampling_time
+ * @{
+ */
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
((TIME) == ADC_SampleTime_7Cycles5) || \
((TIME) == ADC_SampleTime_13Cycles5) || \
@@ -153,25 +222,30 @@
((TIME) == ADC_SampleTime_55Cycles5) || \
((TIME) == ADC_SampleTime_71Cycles5) || \
((TIME) == ADC_SampleTime_239Cycles5))
+/**
+ * @}
+ */
-/* ADC extrenal trigger sources for injected channels conversion -------------*/
-/* For ADC1 and ADC2 */
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
-#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)
-/* For ADC1, ADC2 and ADC3 */
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
-#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
-/* For ADC3 */
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)
-#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)
-#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)
-#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)
-#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
+
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
@@ -185,27 +259,38 @@
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+ * @}
+ */
-/* ADC injected channel selection --------------------------------------------*/
-#define ADC_InjectedChannel_1 ((u8)0x14)
-#define ADC_InjectedChannel_2 ((u8)0x18)
-#define ADC_InjectedChannel_3 ((u8)0x1C)
-#define ADC_InjectedChannel_4 ((u8)0x20)
+/** @defgroup ADC_injected_channel_selection
+ * @{
+ */
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
+/**
+ * @}
+ */
-/* ADC analog watchdog selection ---------------------------------------------*/
-#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
-#define ADC_AnalogWatchdog_None ((u32)0x00000000)
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
@@ -213,88 +298,182 @@
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
-/* ADC interrupts definition -------------------------------------------------*/
-#define ADC_IT_EOC ((u16)0x0220)
-#define ADC_IT_AWD ((u16)0x0140)
-#define ADC_IT_JEOC ((u16)0x0480)
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
-#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))
+#define ADC_IT_EOC ((uint16_t)0x0220)
+#define ADC_IT_AWD ((uint16_t)0x0140)
+#define ADC_IT_JEOC ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC))
+/**
+ * @}
+ */
-/* ADC flags definition ------------------------------------------------------*/
-#define ADC_FLAG_AWD ((u8)0x01)
-#define ADC_FLAG_EOC ((u8)0x02)
-#define ADC_FLAG_JEOC ((u8)0x04)
-#define ADC_FLAG_JSTRT ((u8)0x08)
-#define ADC_FLAG_STRT ((u8)0x10)
+/** @defgroup ADC_flags_definition
+ * @{
+ */
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define ADC_FLAG_AWD ((uint8_t)0x01)
+#define ADC_FLAG_EOC ((uint8_t)0x02)
+#define ADC_FLAG_JEOC ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)
+#define ADC_FLAG_STRT ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT))
+/**
+ * @}
+ */
-/* ADC thresholds ------------------------------------------------------------*/
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-/* ADC injected offset -------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-/* ADC injected length -------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-/* ADC injected rank ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_rank
+ * @{
+ */
+
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-/* ADC regular length --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
-/* ADC regular rank ----------------------------------------------------------*/
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-/* ADC regular discontinuous mode number -------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions
+ * @{
+ */
+
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
-u32 ADC_GetDualModeConversionValue(void);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
-u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /*__STM32F10x_ADC_H */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_bkp.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_bkp.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_bkp.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,90 +1,130 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_bkp.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* BKP firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the BKP firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_BKP_H
#define __STM32F10x_BKP_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Tamper Pin active level */
-#define BKP_TamperPinLevel_High ((u16)0x0000)
-#define BKP_TamperPinLevel_Low ((u16)0x0001)
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+/** @addtogroup BKP
+ * @{
+ */
+
+/** @defgroup BKP_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Tamper_Pin_active_level
+ * @{
+ */
+
+#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+ * @}
+ */
-/* RTC output source to output on the Tamper pin */
-#define BKP_RTCOutputSource_None ((u16)0x0000)
-#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
-#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
-#define BKP_RTCOutputSource_Second ((u16)0x0300)
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+ * @{
+ */
+#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+ * @}
+ */
-/* Data Backup Register */
-#define BKP_DR1 ((u16)0x0004)
-#define BKP_DR2 ((u16)0x0008)
-#define BKP_DR3 ((u16)0x000C)
-#define BKP_DR4 ((u16)0x0010)
-#define BKP_DR5 ((u16)0x0014)
-#define BKP_DR6 ((u16)0x0018)
-#define BKP_DR7 ((u16)0x001C)
-#define BKP_DR8 ((u16)0x0020)
-#define BKP_DR9 ((u16)0x0024)
-#define BKP_DR10 ((u16)0x0028)
-#define BKP_DR11 ((u16)0x0040)
-#define BKP_DR12 ((u16)0x0044)
-#define BKP_DR13 ((u16)0x0048)
-#define BKP_DR14 ((u16)0x004C)
-#define BKP_DR15 ((u16)0x0050)
-#define BKP_DR16 ((u16)0x0054)
-#define BKP_DR17 ((u16)0x0058)
-#define BKP_DR18 ((u16)0x005C)
-#define BKP_DR19 ((u16)0x0060)
-#define BKP_DR20 ((u16)0x0064)
-#define BKP_DR21 ((u16)0x0068)
-#define BKP_DR22 ((u16)0x006C)
-#define BKP_DR23 ((u16)0x0070)
-#define BKP_DR24 ((u16)0x0074)
-#define BKP_DR25 ((u16)0x0078)
-#define BKP_DR26 ((u16)0x007C)
-#define BKP_DR27 ((u16)0x0080)
-#define BKP_DR28 ((u16)0x0084)
-#define BKP_DR29 ((u16)0x0088)
-#define BKP_DR30 ((u16)0x008C)
-#define BKP_DR31 ((u16)0x0090)
-#define BKP_DR32 ((u16)0x0094)
-#define BKP_DR33 ((u16)0x0098)
-#define BKP_DR34 ((u16)0x009C)
-#define BKP_DR35 ((u16)0x00A0)
-#define BKP_DR36 ((u16)0x00A4)
-#define BKP_DR37 ((u16)0x00A8)
-#define BKP_DR38 ((u16)0x00AC)
-#define BKP_DR39 ((u16)0x00B0)
-#define BKP_DR40 ((u16)0x00B4)
-#define BKP_DR41 ((u16)0x00B8)
-#define BKP_DR42 ((u16)0x00BC)
+/** @defgroup Data_Backup_Register
+ * @{
+ */
+#define BKP_DR1 ((uint16_t)0x0004)
+#define BKP_DR2 ((uint16_t)0x0008)
+#define BKP_DR3 ((uint16_t)0x000C)
+#define BKP_DR4 ((uint16_t)0x0010)
+#define BKP_DR5 ((uint16_t)0x0014)
+#define BKP_DR6 ((uint16_t)0x0018)
+#define BKP_DR7 ((uint16_t)0x001C)
+#define BKP_DR8 ((uint16_t)0x0020)
+#define BKP_DR9 ((uint16_t)0x0024)
+#define BKP_DR10 ((uint16_t)0x0028)
+#define BKP_DR11 ((uint16_t)0x0040)
+#define BKP_DR12 ((uint16_t)0x0044)
+#define BKP_DR13 ((uint16_t)0x0048)
+#define BKP_DR14 ((uint16_t)0x004C)
+#define BKP_DR15 ((uint16_t)0x0050)
+#define BKP_DR16 ((uint16_t)0x0054)
+#define BKP_DR17 ((uint16_t)0x0058)
+#define BKP_DR18 ((uint16_t)0x005C)
+#define BKP_DR19 ((uint16_t)0x0060)
+#define BKP_DR20 ((uint16_t)0x0064)
+#define BKP_DR21 ((uint16_t)0x0068)
+#define BKP_DR22 ((uint16_t)0x006C)
+#define BKP_DR23 ((uint16_t)0x0070)
+#define BKP_DR24 ((uint16_t)0x0074)
+#define BKP_DR25 ((uint16_t)0x0078)
+#define BKP_DR26 ((uint16_t)0x007C)
+#define BKP_DR27 ((uint16_t)0x0080)
+#define BKP_DR28 ((uint16_t)0x0084)
+#define BKP_DR29 ((uint16_t)0x0088)
+#define BKP_DR30 ((uint16_t)0x008C)
+#define BKP_DR31 ((uint16_t)0x0090)
+#define BKP_DR32 ((uint16_t)0x0094)
+#define BKP_DR33 ((uint16_t)0x0098)
+#define BKP_DR34 ((uint16_t)0x009C)
+#define BKP_DR35 ((uint16_t)0x00A0)
+#define BKP_DR36 ((uint16_t)0x00A4)
+#define BKP_DR37 ((uint16_t)0x00A8)
+#define BKP_DR38 ((uint16_t)0x00AC)
+#define BKP_DR39 ((uint16_t)0x00B0)
+#define BKP_DR40 ((uint16_t)0x00B4)
+#define BKP_DR41 ((uint16_t)0x00B8)
+#define BKP_DR42 ((uint16_t)0x00BC)
+
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
@@ -101,22 +141,54 @@
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Functions
+ * @{
+ */
+
void BKP_DeInit(void);
-void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
-void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
-void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
-void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
-u16 BKP_ReadBackupRegister(u16 BKP_DR);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_BKP_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_can.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_can.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_can.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,228 +1,466 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_can.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* CAN firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the CAN firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CAN_H
#define __STM32F10x_CAN_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* CAN init structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+ ((PERIPH) == CAN2))
+
+/**
+ * @brief CAN init structure definition
+ */
+
typedef struct
{
- FunctionalState CAN_TTCM;
- FunctionalState CAN_ABOM;
- FunctionalState CAN_AWUM;
- FunctionalState CAN_NART;
- FunctionalState CAN_RFLM;
- FunctionalState CAN_TXFP;
- u8 CAN_Mode;
- u8 CAN_SJW;
- u8 CAN_BS1;
- u8 CAN_BS2;
- u16 CAN_Prescaler;
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */
+
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set either to ENABLE or DISABLE. */
} CAN_InitTypeDef;
-/* CAN filter init structure definition */
+/**
+ * @brief CAN filter init structure definition
+ */
+
typedef struct
{
- u8 CAN_FilterNumber;
- u8 CAN_FilterMode;
- u8 CAN_FilterScale;
- u16 CAN_FilterIdHigh;
- u16 CAN_FilterIdLow;
- u16 CAN_FilterMaskIdHigh;
- u16 CAN_FilterMaskIdLow;
- u16 CAN_FilterFIFOAssignment;
- FunctionalState CAN_FilterActivation;
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
-/* CAN Tx message structure definition */
+/**
+ * @brief CAN Tx message structure definition
+ */
+
typedef struct
{
- u32 StdId;
- u32 ExtId;
- u8 IDE;
- u8 RTR;
- u8 DLC;
- u8 Data[8];
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
} CanTxMsg;
-/* CAN Rx message structure definition */
+/**
+ * @brief CAN Rx message structure definition
+ */
+
typedef struct
{
- u32 StdId;
- u32 ExtId;
- u8 IDE;
- u8 RTR;
- u8 DLC;
- u8 Data[8];
- u8 FMI;
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter can be a value between 0 to 0xFF */
} CanRxMsg;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-/* CAN sleep constants */
-#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */
-#define CANINITOK ((u8)0x01) /* CAN initialization failed */
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
-/* CAN operating mode */
-#define CAN_Mode_Normal ((u8)0x00) /* normal mode */
-#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */
-#define CAN_Mode_Silent ((u8)0x02) /* silent mode */
-#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode
+ * @{
+ */
+
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
-/* CAN synchronisation jump width */
-#define CAN_SJW_1tq ((u8)0x00) /* 1 time quantum */
-#define CAN_SJW_2tq ((u8)0x01) /* 2 time quantum */
-#define CAN_SJW_3tq ((u8)0x02) /* 3 time quantum */
-#define CAN_SJW_4tq ((u8)0x03) /* 4 time quantum */
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+ * @}
+ */
-/* time quantum in bit segment 1 */
-#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */
-#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */
-#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */
-#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */
-#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */
-#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */
-#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */
-#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */
-#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */
-#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */
-#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */
-#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */
-#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */
-#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */
-#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */
-#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+ * @}
+ */
-/* time quantum in bit segment 2 */
-#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */
-#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */
-#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */
-#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */
-#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */
-#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */
-#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */
-#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/* CAN clock prescaler */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/* CAN filter number */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+/**
+ * @}
+ */
-/* CAN filter mode */
-#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */
-#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#else
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
+
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
((MODE) == CAN_FilterMode_IdList))
+/**
+ * @}
+ */
-/* CAN filter scale */
-#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */
-#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
+
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
((SCALE) == CAN_FilterScale_32bit))
-/* CAN filter FIFO assignation */
-#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */
-#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
((FIFO) == CAN_FilterFIFO1))
-/* CAN Tx */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((u8)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((u32)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((u32)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((u8)0x08))
+/**
+ * @}
+ */
-/* CAN identifier type */
-#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */
-#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */
+/** @defgroup Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+ * @}
+ */
+/** @defgroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
-/* CAN remote transmission request */
-#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */
-#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */
+/**
+ * @}
+ */
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-/* CAN transmit constants */
-#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */
-#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */
-#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */
-#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */
+/**
+ * @}
+ */
-/* CAN receive FIFO number constants */
-#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */
-#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */
+
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/* CAN sleep constants */
-#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */
-#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */
+/**
+ * @}
+ */
-/* CAN wake up constants */
-#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */
-#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
-/* CAN flags */
-#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */
-#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */
-#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */
+#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+
+#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\
((FLAG) == CAN_FLAG_BOF))
-/* CAN interrupts */
-#define CAN_IT_RQCP0 ((u32)0x00000005) /* Request completed mailbox 0 */
-#define CAN_IT_RQCP1 ((u32)0x00000006) /* Request completed mailbox 1 */
-#define CAN_IT_RQCP2 ((u32)0x00000007) /* Request completed mailbox 2 */
-#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */
-#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */
-#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */
-#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */
-#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */
-#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */
-#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */
-#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */
-#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */
-#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */
-#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */
-#define CAN_IT_ERR ((u32)0x00008000) /* Error */
-#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */
-#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */
+/**
+ * @}
+ */
+/** @defgroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */
+#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */
+#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */
+
#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
@@ -237,27 +475,61 @@
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported function protypes ----------------------------------------------- */
-void CAN_DeInit(void);
-u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions
+ * @{
+ */
+
+void CAN_DeInit(CAN_TypeDef* CANx);
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
-u8 CAN_Transmit(CanTxMsg* TxMessage);
-u8 CAN_TransmitStatus(u8 TransmitMailbox);
-void CAN_CancelTransmit(u8 Mailbox);
-void CAN_FIFORelease(u8 FIFONumber);
-u8 CAN_MessagePending(u8 FIFONumber);
-void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
-u8 CAN_Sleep(void);
-u8 CAN_WakeUp(void);
-FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
-void CAN_ClearFlag(u32 CAN_FLAG);
-ITStatus CAN_GetITStatus(u32 CAN_IT);
-void CAN_ClearITPendingBit(u32 CAN_IT);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_CAN_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_crc.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_crc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_crc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,37 +1,93 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_crc.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* CRC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CRC_H
#define __STM32F10x_CRC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions
+ * @{
+ */
+
void CRC_ResetDR(void);
-u32 CRC_CalcCRC(u32 Data);
-u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength);
-u32 CRC_GetCRC(void);
-void CRC_SetIDRegister(u8 IDValue);
-u8 CRC_GetIDRegister(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_CRC_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dac.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dac.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dac.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,48 +1,94 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_dac.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* DAC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DAC_H
#define __STM32F10x_DAC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* DAC Init structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
typedef struct
{
- u32 DAC_Trigger;
- u32 DAC_WaveGeneration;
- u32 DAC_LFSRUnmask_TriangleAmplitude;
- u32 DAC_OutputBuffer;
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* DAC trigger selection */
-#define DAC_Trigger_None ((u32)0x00000000)
-#define DAC_Trigger_T6_TRGO ((u32)0x00000004)
-#define DAC_Trigger_T8_TRGO ((u32)0x0000000C)
-#define DAC_Trigger_T7_TRGO ((u32)0x00000014)
-#define DAC_Trigger_T5_TRGO ((u32)0x0000001C)
-#define DAC_Trigger_T2_TRGO ((u32)0x00000024)
-#define DAC_Trigger_T4_TRGO ((u32)0x0000002C)
-#define DAC_Trigger_Ext_IT9 ((u32)0x00000034)
-#define DAC_Trigger_Software ((u32)0x0000003C)
+/**
+ * @}
+ */
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in High-density devices*/
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in Connectivity line devices */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
@@ -53,41 +99,52 @@
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
-/* DAC wave generation */
-#define DAC_WaveGeneration_None ((u32)0x00000000)
-#define DAC_WaveGeneration_Noise ((u32)0x00000040)
-#define DAC_WaveGeneration_Triangle ((u32)0x00000080)
+/**
+ * @}
+ */
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
-/* DAC noise wave generation mask / triangle wave generation max amplitude */
-#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000)
-#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100)
-#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200)
-#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300)
-#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400)
-#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500)
-#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600)
-#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700)
-#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800)
-#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900)
-#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00)
-#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00)
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
-#define DAC_TriangleAmplitude_1 ((u32)0x00000000)
-#define DAC_TriangleAmplitude_3 ((u32)0x00000100)
-#define DAC_TriangleAmplitude_7 ((u32)0x00000200)
-#define DAC_TriangleAmplitude_15 ((u32)0x00000300)
-#define DAC_TriangleAmplitude_31 ((u32)0x00000400)
-#define DAC_TriangleAmplitude_63 ((u32)0x00000500)
-#define DAC_TriangleAmplitude_127 ((u32)0x00000600)
-#define DAC_TriangleAmplitude_255 ((u32)0x00000700)
-#define DAC_TriangleAmplitude_511 ((u32)0x00000800)
-#define DAC_TriangleAmplitude_1023 ((u32)0x00000900)
-#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00)
-#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00)
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
@@ -113,55 +170,113 @@
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
-/* DAC output buffer */
-#define DAC_OutputBuffer_Enable ((u32)0x00000000)
-#define DAC_OutputBuffer_Disable ((u32)0x00000002)
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
+/**
+ * @}
+ */
-/* DAC Channel selection */
-#define DAC_Channel_1 ((u32)0x00000000)
-#define DAC_Channel_2 ((u32)0x00000010)
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
-/* DAC data alignement */
-#define DAC_Align_12b_R ((u32)0x00000000)
-#define DAC_Align_12b_L ((u32)0x00000004)
-#define DAC_Align_8b_R ((u32)0x00000008)
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
-/* DAC wave generation */
-#define DAC_Wave_Noise ((u32)0x00000040)
-#define DAC_Wave_Triangle ((u32)0x00000080)
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
-/* DAC data ------------------------------------------------------------------*/
+/** @defgroup DAC_data
+ * @{
+ */
+
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions
+ * @{
+ */
+
void DAC_DeInit(void);
-void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState);
-void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(u32 DAC_Align, u16 Data);
-void DAC_SetChannel2Data(u32 DAC_Align, u16 Data);
-void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1);
-u16 DAC_GetDataOutputValue(u32 DAC_Channel);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+#ifdef __cplusplus
+}
+#endif
+
#endif /*__STM32F10x_DAC_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dbgmcu.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dbgmcu.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dbgmcu.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,55 +1,109 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_dbgmcu.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* DBGMCU firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the DBGMCU
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DBGMCU_H
#define __STM32F10x_DBGMCU_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#define DBGMCU_SLEEP ((u32)0x00000001)
-#define DBGMCU_STOP ((u32)0x00000002)
-#define DBGMCU_STANDBY ((u32)0x00000004)
-#define DBGMCU_IWDG_STOP ((u32)0x00000100)
-#define DBGMCU_WWDG_STOP ((u32)0x00000200)
-#define DBGMCU_TIM1_STOP ((u32)0x00000400)
-#define DBGMCU_TIM2_STOP ((u32)0x00000800)
-#define DBGMCU_TIM3_STOP ((u32)0x00001000)
-#define DBGMCU_TIM4_STOP ((u32)0x00002000)
-#define DBGMCU_CAN_STOP ((u32)0x00004000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((u32)0x00008000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((u32)0x00010000)
-#define DBGMCU_TIM5_STOP ((u32)0x00020000)
-#define DBGMCU_TIM6_STOP ((u32)0x00040000)
-#define DBGMCU_TIM7_STOP ((u32)0x00080000)
-#define DBGMCU_TIM8_STOP ((u32)0x00100000)
-
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-u32 DBGMCU_GetREVID(void);
-u32 DBGMCU_GetDEVID(void);
-void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState);
+/** @addtogroup DBGMCU
+ * @{
+ */
+/** @defgroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_DBGMCU_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dma.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dma.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_dma.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,178 +1,273 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_dma.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* DMA firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
#define __STM32F10x_DMA_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* DMA Init structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
typedef struct
{
- u32 DMA_PeripheralBaseAddr;
- u32 DMA_MemoryBaseAddr;
- u32 DMA_DIR;
- u32 DMA_BufferSize;
- u32 DMA_PeripheralInc;
- u32 DMA_MemoryInc;
- u32 DMA_PeripheralDataSize;
- u32 DMA_MemoryDataSize;
- u32 DMA_Mode;
- u32 DMA_Priority;
- u32 DMA_M2M;
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \
- ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))
+/**
+ * @}
+ */
-/* DMA data transfer direction -----------------------------------------------*/
-#define DMA_DIR_PeripheralDST ((u32)0x00000010)
-#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
+/**
+ * @}
+ */
-/* DMA peripheral incremented mode -------------------------------------------*/
-#define DMA_PeripheralInc_Enable ((u32)0x00000040)
-#define DMA_PeripheralInc_Disable ((u32)0x00000000)
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
-/* DMA memory incremented mode -----------------------------------------------*/
-#define DMA_MemoryInc_Enable ((u32)0x00000080)
-#define DMA_MemoryInc_Disable ((u32)0x00000000)
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
-/* DMA peripheral data size --------------------------------------------------*/
-#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
-#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
-/* DMA memory data size ------------------------------------------------------*/
-#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
-#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
-#define DMA_MemoryDataSize_Word ((u32)0x00000800)
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
-/* DMA circular/normal mode --------------------------------------------------*/
-#define DMA_Mode_Circular ((u32)0x00000020)
-#define DMA_Mode_Normal ((u32)0x00000000)
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+ * @}
+ */
-/* DMA priority level --------------------------------------------------------*/
-#define DMA_Priority_VeryHigh ((u32)0x00003000)
-#define DMA_Priority_High ((u32)0x00002000)
-#define DMA_Priority_Medium ((u32)0x00001000)
-#define DMA_Priority_Low ((u32)0x00000000)
+/** @defgroup DMA_priority_level
+ * @{
+ */
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
-/* DMA memory to memory ------------------------------------------------------*/
-#define DMA_M2M_Enable ((u32)0x00004000)
-#define DMA_M2M_Disable ((u32)0x00000000)
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
-/* DMA interrupts definition -------------------------------------------------*/
-#define DMA_IT_TC ((u32)0x00000002)
-#define DMA_IT_HT ((u32)0x00000004)
-#define DMA_IT_TE ((u32)0x00000008)
+/**
+ * @}
+ */
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-/* For DMA1 */
-#define DMA1_IT_GL1 ((u32)0x00000001)
-#define DMA1_IT_TC1 ((u32)0x00000002)
-#define DMA1_IT_HT1 ((u32)0x00000004)
-#define DMA1_IT_TE1 ((u32)0x00000008)
-#define DMA1_IT_GL2 ((u32)0x00000010)
-#define DMA1_IT_TC2 ((u32)0x00000020)
-#define DMA1_IT_HT2 ((u32)0x00000040)
-#define DMA1_IT_TE2 ((u32)0x00000080)
-#define DMA1_IT_GL3 ((u32)0x00000100)
-#define DMA1_IT_TC3 ((u32)0x00000200)
-#define DMA1_IT_HT3 ((u32)0x00000400)
-#define DMA1_IT_TE3 ((u32)0x00000800)
-#define DMA1_IT_GL4 ((u32)0x00001000)
-#define DMA1_IT_TC4 ((u32)0x00002000)
-#define DMA1_IT_HT4 ((u32)0x00004000)
-#define DMA1_IT_TE4 ((u32)0x00008000)
-#define DMA1_IT_GL5 ((u32)0x00010000)
-#define DMA1_IT_TC5 ((u32)0x00020000)
-#define DMA1_IT_HT5 ((u32)0x00040000)
-#define DMA1_IT_TE5 ((u32)0x00080000)
-#define DMA1_IT_GL6 ((u32)0x00100000)
-#define DMA1_IT_TC6 ((u32)0x00200000)
-#define DMA1_IT_HT6 ((u32)0x00400000)
-#define DMA1_IT_TE6 ((u32)0x00800000)
-#define DMA1_IT_GL7 ((u32)0x01000000)
-#define DMA1_IT_TC7 ((u32)0x02000000)
-#define DMA1_IT_HT7 ((u32)0x04000000)
-#define DMA1_IT_TE7 ((u32)0x08000000)
-/* For DMA2 */
-#define DMA2_IT_GL1 ((u32)0x10000001)
-#define DMA2_IT_TC1 ((u32)0x10000002)
-#define DMA2_IT_HT1 ((u32)0x10000004)
-#define DMA2_IT_TE1 ((u32)0x10000008)
-#define DMA2_IT_GL2 ((u32)0x10000010)
-#define DMA2_IT_TC2 ((u32)0x10000020)
-#define DMA2_IT_HT2 ((u32)0x10000040)
-#define DMA2_IT_TE2 ((u32)0x10000080)
-#define DMA2_IT_GL3 ((u32)0x10000100)
-#define DMA2_IT_TC3 ((u32)0x10000200)
-#define DMA2_IT_HT3 ((u32)0x10000400)
-#define DMA2_IT_TE3 ((u32)0x10000800)
-#define DMA2_IT_GL4 ((u32)0x10001000)
-#define DMA2_IT_TC4 ((u32)0x10002000)
-#define DMA2_IT_HT4 ((u32)0x10004000)
-#define DMA2_IT_TE4 ((u32)0x10008000)
-#define DMA2_IT_GL5 ((u32)0x10010000)
-#define DMA2_IT_TC5 ((u32)0x10020000)
-#define DMA2_IT_HT5 ((u32)0x10040000)
-#define DMA2_IT_TE5 ((u32)0x10080000)
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
@@ -198,59 +293,65 @@
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
-/* DMA flags definition ------------------------------------------------------*/
-/* For DMA1 */
-#define DMA1_FLAG_GL1 ((u32)0x00000001)
-#define DMA1_FLAG_TC1 ((u32)0x00000002)
-#define DMA1_FLAG_HT1 ((u32)0x00000004)
-#define DMA1_FLAG_TE1 ((u32)0x00000008)
-#define DMA1_FLAG_GL2 ((u32)0x00000010)
-#define DMA1_FLAG_TC2 ((u32)0x00000020)
-#define DMA1_FLAG_HT2 ((u32)0x00000040)
-#define DMA1_FLAG_TE2 ((u32)0x00000080)
-#define DMA1_FLAG_GL3 ((u32)0x00000100)
-#define DMA1_FLAG_TC3 ((u32)0x00000200)
-#define DMA1_FLAG_HT3 ((u32)0x00000400)
-#define DMA1_FLAG_TE3 ((u32)0x00000800)
-#define DMA1_FLAG_GL4 ((u32)0x00001000)
-#define DMA1_FLAG_TC4 ((u32)0x00002000)
-#define DMA1_FLAG_HT4 ((u32)0x00004000)
-#define DMA1_FLAG_TE4 ((u32)0x00008000)
-#define DMA1_FLAG_GL5 ((u32)0x00010000)
-#define DMA1_FLAG_TC5 ((u32)0x00020000)
-#define DMA1_FLAG_HT5 ((u32)0x00040000)
-#define DMA1_FLAG_TE5 ((u32)0x00080000)
-#define DMA1_FLAG_GL6 ((u32)0x00100000)
-#define DMA1_FLAG_TC6 ((u32)0x00200000)
-#define DMA1_FLAG_HT6 ((u32)0x00400000)
-#define DMA1_FLAG_TE6 ((u32)0x00800000)
-#define DMA1_FLAG_GL7 ((u32)0x01000000)
-#define DMA1_FLAG_TC7 ((u32)0x02000000)
-#define DMA1_FLAG_HT7 ((u32)0x04000000)
-#define DMA1_FLAG_TE7 ((u32)0x08000000)
-/* For DMA2 */
-#define DMA2_FLAG_GL1 ((u32)0x10000001)
-#define DMA2_FLAG_TC1 ((u32)0x10000002)
-#define DMA2_FLAG_HT1 ((u32)0x10000004)
-#define DMA2_FLAG_TE1 ((u32)0x10000008)
-#define DMA2_FLAG_GL2 ((u32)0x10000010)
-#define DMA2_FLAG_TC2 ((u32)0x10000020)
-#define DMA2_FLAG_HT2 ((u32)0x10000040)
-#define DMA2_FLAG_TE2 ((u32)0x10000080)
-#define DMA2_FLAG_GL3 ((u32)0x10000100)
-#define DMA2_FLAG_TC3 ((u32)0x10000200)
-#define DMA2_FLAG_HT3 ((u32)0x10000400)
-#define DMA2_FLAG_TE3 ((u32)0x10000800)
-#define DMA2_FLAG_GL4 ((u32)0x10001000)
-#define DMA2_FLAG_TC4 ((u32)0x10002000)
-#define DMA2_FLAG_HT4 ((u32)0x10004000)
-#define DMA2_FLAG_TE4 ((u32)0x10008000)
-#define DMA2_FLAG_GL5 ((u32)0x10010000)
-#define DMA2_FLAG_TC5 ((u32)0x10020000)
-#define DMA2_FLAG_HT5 ((u32)0x10040000)
-#define DMA2_FLAG_TE5 ((u32)0x10080000)
+/**
+ * @}
+ */
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
@@ -275,23 +376,62 @@
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+ * @}
+ */
-/* DMA Buffer Size -----------------------------------------------------------*/
+/** @defgroup DMA_Buffer_Size
+ * @{
+ */
+
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions
+ * @{
+ */
+
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);
-u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
-void DMA_ClearFlag(u32 DMA_FLAG);
-ITStatus DMA_GetITStatus(u32 DMA_IT);
-void DMA_ClearITPendingBit(u32 DMA_IT);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+void DMA_ClearFlag(uint32_t DMA_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+void DMA_ClearITPendingBit(uint32_t DMA_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /*__STM32F10x_DMA_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_exti.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_exti.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_exti.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,28 +1,51 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_exti.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* EXTI firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the EXTI firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_EXTI_H
#define __STM32F10x_EXTI_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* EXTI mode enumeration -----------------------------------------------------*/
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
@@ -30,8 +53,11 @@
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/* EXTI Trigger enumeration --------------------------------------------------*/
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
typedef enum
{
EXTI_Trigger_Rising = 0x08,
@@ -42,44 +68,61 @@
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
-/* EXTI Init Structure definition --------------------------------------------*/
typedef struct
{
- u32 EXTI_Line;
- EXTIMode_TypeDef EXTI_Mode;
- EXTITrigger_TypeDef EXTI_Trigger;
- FunctionalState EXTI_LineCmd;
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* EXTI Lines ----------------------------------------------------------------*/
-#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */
-#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */
-#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */
-#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */
-#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */
-#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */
-#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */
-#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */
-#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */
-#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */
-#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */
-#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */
-#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */
-#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */
-#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */
-#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */
-#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16
- Connected to the PVD Output */
-#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17
- Connected to the RTC Alarm event */
-#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18
- Connected to the USB Wakeup from
- suspend event */
+/**
+ * @}
+ */
-#define IS_EXTI_LINE(LINE) ((((LINE) & (u32)0xFFF80000) == 0x00) && ((LINE) != (u16)0x00))
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+ Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
@@ -89,19 +132,52 @@
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18))
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions
+ * @{
+ */
+
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
-FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
-void EXTI_ClearFlag(u32 EXTI_Line);
-ITStatus EXTI_GetITStatus(u32 EXTI_Line);
-void EXTI_ClearITPendingBit(u32 EXTI_Line);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_EXTI_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_flash.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_flash.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_flash.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,29 +1,51 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_flash.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* FLASH firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FLASH_H
#define __STM32F10x_FLASH_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-#ifdef _FLASH_PROG
-/* FLASH Status */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
typedef enum
{
FLASH_BUSY = 1,
@@ -32,177 +54,293 @@
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
-#endif
-/* Flash Latency -------------------------------------------------------------*/
-#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */
-#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */
-#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */
+/**
+ * @}
+ */
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
+/**
+ * @}
+ */
-/* Half Cycle Enable/Disable -------------------------------------------------*/
-#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */
-#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */
+/** @defgroup Half_Cycle_Enable_Disable
+ * @{
+ */
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
+/**
+ * @}
+ */
+/** @defgroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
-/* Prefetch Buffer Enable/Disable --------------------------------------------*/
-#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */
-#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */
-
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
+/**
+ * @}
+ */
-#ifdef _FLASH_PROG
-/* Option Bytes Write Protection ---------------------------------------------*/
-/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density
- ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
-#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */
-#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */
-#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */
-#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */
-#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */
-#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */
-#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */
-#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */
-#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */
-#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */
-#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */
-#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */
-#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */
-#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */
-#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */
-#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */
-#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */
-#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */
-#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */
-#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */
-#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */
-#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */
-#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */
-#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */
-#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */
-#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */
-#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */
-#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */
-#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */
-#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */
-#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */
-#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */
-/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density
- ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
-#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */
-#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */
-#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */
-#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */
-#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */
-#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */
-#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */
-#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */
-#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */
-#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */
-#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */
-#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */
-#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */
-#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */
-#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */
-#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */
-#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */
-#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */
-#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */
-#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */
-#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */
-#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */
-#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */
-#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */
-#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */
-#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */
-#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */
-#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */
-#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */
-#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */
-#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */
-#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */
-#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
+
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-/* Option Bytes IWatchdog ----------------------------------------------------*/
-#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */
-#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-/* Option Bytes nRST_STOP ----------------------------------------------------*/
-#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */
-#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-/* Option Bytes nRST_STDBY ---------------------------------------------------*/
-#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-/* FLASH Interrupts ----------------------------------------------------------*/
-#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */
-#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */
+/**
+ * @}
+ */
-#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
-/* FLASH Flags ---------------------------------------------------------------*/
-#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */
-#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */
-#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */
-#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */
-#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
-
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
-#endif
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void FLASH_SetLatency(u32 FLASH_Latency);
-void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess);
-void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer);
-#ifdef _FLASH_PROG
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions
+ * @{
+ */
+
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(u32 Page_Address);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
-FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data);
-FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data);
-FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data);
-FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
-FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY);
-u32 FLASH_GetUserOptionByte(void);
-u32 FLASH_GetWriteProtectionOptionByte(void);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
-void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG);
-void FLASH_ClearFlag(u16 FLASH_FLAG);
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
+void FLASH_ClearFlag(uint16_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(u32 Timeout);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
#endif
#endif /* __STM32F10x_FLASH_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_fsmc.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_fsmc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_fsmc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,327 +1,683 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_fsmc.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* FSMC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the FSMC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Timing parameters For NOR/SRAM Banks */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/** @defgroup FSMC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief Timing parameters For NOR/SRAM Banks
+ */
+
typedef struct
{
- u32 FSMC_AddressSetupTime;
- u32 FSMC_AddressHoldTime;
- u32 FSMC_DataSetupTime;
- u32 FSMC_BusTurnAroundDuration;
- u32 FSMC_CLKDivision;
- u32 FSMC_DataLatency;
- u32 FSMC_AccessMode;
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories. */
+
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories.*/
+
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between 0 and 0xFF.
+ @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is only used for multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+ This parameter can be a value between 1 and 0xF.
+ @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The value of this parameter depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don’t care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between 0 and 0xF in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
-/* FSMC NOR/SRAM Init structure definition */
+/**
+ * @brief FSMC NOR/SRAM Init structure definition
+ */
+
typedef struct
{
- u32 FSMC_Bank;
- u32 FSMC_DataAddressMux;
- u32 FSMC_MemoryType;
- u32 FSMC_MemoryDataWidth;
- u32 FSMC_BurstAccessMode;
- u32 FSMC_WaitSignalPolarity;
- u32 FSMC_WrapMode;
- u32 FSMC_WaitSignalActive;
- u32 FSMC_WriteOperation;
- u32 FSMC_WaitSignal;
- u32 FSMC_ExtendedMode;
- u32 FSMC_WriteBurst;
- /* Timing Parameters for write and read access if the ExtendedMode is not used*/
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
- /* Timing Parameters for write access if the ExtendedMode is used*/
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the databus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory bank.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
-/* Timing parameters For FSMC NAND and PCCARD Banks */
+/**
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks
+ */
+
typedef struct
{
- u32 FSMC_SetupTime;
- u32 FSMC_WaitSetupTime;
- u32 FSMC_HoldSetupTime;
- u32 FSMC_HiZSetupTime;
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between 0 and 0xFF.*/
+
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command deassertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ databus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
}FSMC_NAND_PCCARDTimingInitTypeDef;
-/* FSMC NAND Init structure definition */
+/**
+ * @brief FSMC NAND Init structure definition
+ */
+
typedef struct
{
- u32 FSMC_Bank;
- u32 FSMC_Waitfeature;
- u32 FSMC_MemoryDataWidth;
- u32 FSMC_ECC;
- u32 FSMC_ECCPageSize;
- u32 FSMC_AddressLowMapping;
- u32 FSMC_TCLRSetupTime;
- u32 FSMC_TARSetupTime;
- /* FSMC Common Space Timing */
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
- /* FSMC Attribute Space Timing */
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
-/* FSMC PCCARD Init structure definition */
+/**
+ * @brief FSMC PCCARD Init structure definition
+ */
+
typedef struct
{
- u32 FSMC_Waitfeature;
- u32 FSMC_AddressLowMapping;
- u32 FSMC_TCLRSetupTime;
- u32 FSMC_TARSetupTime;
- /* FSMC Common Space Timing */
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
- /* FSMC Attribute Space Timing */
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
- /* FSMC IO Space Timing */
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
}FSMC_PCCARDInitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/*-------------------------------FSMC Banks definitions ----------------------*/
-#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)
-#define FSMC_Bank2_NAND ((u32)0x00000010)
-#define FSMC_Bank3_NAND ((u32)0x00000100)
-#define FSMC_Bank4_PCCARD ((u32)0x00001000)
+/**
+ * @}
+ */
+/** @defgroup FSMC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Bank
+ * @{
+ */
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Bank
+ * @{
+ */
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
+/**
+ * @}
+ */
+
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
+ ((BANK) == FSMC_Bank1_NORSRAM4))
-
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND))
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
-
+
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
+ ((BANK) == FSMC_Bank4_PCCARD))
+/** @defgroup NOR_SRAM_Controller
+ * @{
+ */
-/*------------------------------- NOR/SRAM Banks -----------------------------*/
-/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/
-#define FSMC_DataAddressMux_Disable ((u32)0x00000000)
-#define FSMC_DataAddressMux_Enable ((u32)0x00000002)
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
+ ((MUX) == FSMC_DataAddressMux_Enable))
-/* FSMC Memory Type ----------------------------------------------------------*/
-#define FSMC_MemoryType_SRAM ((u32)0x00000000)
-#define FSMC_MemoryType_PSRAM ((u32)0x00000004)
-#define FSMC_MemoryType_NOR ((u32)0x00000008)
+/**
+ * @}
+ */
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
-
-/* FSMC Data Width ----------------------------------------------------------*/
-#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Width
+ * @{
+ */
+
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
-
-
-/* FSMC Burst Access Mode ----------------------------------------------------*/
-#define FSMC_BurstAccessMode_Disable ((u32)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+ * @}
+ */
-/* FSMC Wait Signal Polarity -------------------------------------------------*/
-#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
-
-/* FSMC Wrap Mode ------------------------------------------------------------*/
-#define FSMC_WrapMode_Disable ((u32)0x00000000)
-#define FSMC_WrapMode_Enable ((u32)0x00000400)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
-
-/* FSMC Wait Timing ----------------------------------------------------------*/
-#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-
-/* FSMC Write Operation ------------------------------------------------------*/
-#define FSMC_WriteOperation_Disable ((u32)0x00000000)
-#define FSMC_WriteOperation_Enable ((u32)0x00001000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
-/* FSMC Wait Signal ----------------------------------------------------------*/
-#define FSMC_WaitSignal_Disable ((u32)0x00000000)
-#define FSMC_WaitSignal_Enable ((u32)0x00002000)
+/**
+ * @}
+ */
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+ * @}
+ */
-/* FSMC Extended Mode --------------------------------------------------------*/
-#define FSMC_ExtendedMode_Disable ((u32)0x00000000)
-#define FSMC_ExtendedMode_Enable ((u32)0x00004000)
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
-
-/* FSMC Write Burst ----------------------------------------------------------*/
-#define FSMC_WriteBurst_Disable ((u32)0x00000000)
-#define FSMC_WriteBurst_Enable ((u32)0x00080000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
+/**
+ * @}
+ */
-/* FSMC Address Setup Time ---------------------------------------------------*/
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-/* FSMC Address Hold Time ----------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-/* FSMC Data Setup Time ------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-/* FSMC Bus Turn around Duration ---------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-/* FSMC CLK Division ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-/* FSMC Data Latency ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-/* FSMC Access Mode ----------------------------------------------------------*/
-#define FSMC_AccessMode_A ((u32)0x00000000)
-#define FSMC_AccessMode_B ((u32)0x10000000)
-#define FSMC_AccessMode_C ((u32)0x20000000)
-#define FSMC_AccessMode_D ((u32)0x30000000)
+/**
+ * @}
+ */
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B ((uint32_t)0x10000000)
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
-
-/*----------------------------- NAND and PCCARD Banks ------------------------*/
-/* FSMC Wait feature ---------------------------------------------------------*/
-#define FSMC_Waitfeature_Disable ((u32)0x00000000)
-#define FSMC_Waitfeature_Enable ((u32)0x00000002)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_PCCARD_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Wait_feature
+ * @{
+ */
+
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
((FEATURE) == FSMC_Waitfeature_Enable))
-
-/* FSMC Memory Data Width ----------------------------------------------------*/
-#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
-#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-
-/* FSMC ECC ------------------------------------------------------------------*/
-#define FSMC_ECC_Disable ((u32)0x00000000)
-#define FSMC_ECC_Enable ((u32)0x00000040)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC
+ * @{
+ */
+
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
((STATE) == FSMC_ECC_Enable))
-
-/* FSMC ECC Page Size --------------------------------------------------------*/
-#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size
+ * @{
+ */
+
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
((SIZE) == FSMC_ECCPageSize_8192Bytes))
-
-/* FSMC Address Low Mapping --------------------------------------------------*/
-#define FSMC_AddressLowMapping_Direct ((u32)0x00000000)
-#define FSMC_AddressLowMapping_InDirect ((u32)0x00000100)
-#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) || \
- ((MAPPING) == FSMC_AddressLowMapping_InDirect))
-/* FSMC TCLR Setup Time ------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TCLR_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-/* FSMC TAR Setup Time -------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-/* FSMC Setup Time ----------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-/* FSMC Wait Setup Time -----------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-/* FSMC Hold Setup Time -----------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-/* FSMC HiZ Setup Time ------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time
+ * @{
+ */
+
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-/* FSMC Interrupt sources ----------------------------------------------------*/
-#define FSMC_IT_RisingEdge ((u32)0x00000008)
-#define FSMC_IT_Level ((u32)0x00000010)
-#define FSMC_IT_FallingEdge ((u32)0x00000020)
+/**
+ * @}
+ */
-#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+/** @defgroup FSMC_Interrupt_sources
+ * @{
+ */
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
+#define FSMC_IT_Level ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
((IT) == FSMC_IT_Level) || \
((IT) == FSMC_IT_FallingEdge))
+/**
+ * @}
+ */
-/* FSMC Flags ----------------------------------------------------------------*/
-#define FSMC_FLAG_RisingEdge ((u32)0x00000001)
-#define FSMC_FLAG_Level ((u32)0x00000002)
-#define FSMC_FLAG_FallingEdge ((u32)0x00000004)
-#define FSMC_FLAG_FEMPT ((u32)0x00000040)
+/** @defgroup FSMC_Flags
+ * @{
+ */
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
((FLAG) == FSMC_FLAG_Level) || \
((FLAG) == FSMC_FLAG_FallingEdge) || \
((FLAG) == FSMC_FLAG_FEMPT))
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void FSMC_NORSRAMDeInit(u32 FSMC_Bank);
-void FSMC_NANDDeInit(u32 FSMC_Bank);
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Functions
+ * @{
+ */
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
@@ -329,17 +685,32 @@
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
-void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);
-u32 FSMC_GetECC(u32 FSMC_Bank);
-void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);
-void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);
-ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);
-void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /*__STM32F10x_FSMC_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_gpio.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_gpio.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_gpio.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,47 +1,72 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_gpio.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* GPIO firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_GPIO_H
#define __STM32F10x_GPIO_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \
- ((*(u32*)&(PERIPH)) == GPIOB_BASE) || \
- ((*(u32*)&(PERIPH)) == GPIOC_BASE) || \
- ((*(u32*)&(PERIPH)) == GPIOD_BASE) || \
- ((*(u32*)&(PERIPH)) == GPIOE_BASE) || \
- ((*(u32*)&(PERIPH)) == GPIOF_BASE) || \
- ((*(u32*)&(PERIPH)) == GPIOG_BASE))
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF) || \
+ ((PERIPH) == GPIOG))
-/* Output Maximum frequency selection ----------------------------------------*/
+/**
+ * @brief Output Maximum frequency selection
+ */
+
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
-
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
((SPEED) == GPIO_Speed_50MHz))
-
-/* Configuration Mode enumeration --------------------------------------------*/
+
+/**
+ * @brief Configuration Mode enumeration
+ */
+
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
@@ -57,44 +82,67 @@
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
-
-/* GPIO Init structure definition */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
typedef struct
{
- u16 GPIO_Pin;
- GPIOSpeed_TypeDef GPIO_Speed;
- GPIOMode_TypeDef GPIO_Mode;
+ uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
}GPIO_InitTypeDef;
-/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
+
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/* Exported constants --------------------------------------------------------*/
-/* GPIO pins define ----------------------------------------------------------*/
-#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */
-#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */
-#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */
-#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */
-#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */
-#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */
-#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */
-#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */
-#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */
-#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */
-#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */
-#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */
-#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */
-#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */
-#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */
-#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */
-#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */
+/**
+ * @}
+ */
-#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00))
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
@@ -111,35 +159,48 @@
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
-
-/* GPIO Remap define ---------------------------------------------------------*/
-#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */
-#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */
-#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */
-#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */
-#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */
-#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */
-#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */
-#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */
-#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
-#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
-#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */
-#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */
-#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */
-#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */
-#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */
-#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */
-#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */
-#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
-#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
-#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
-#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
-#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
-#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
-#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
-#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+/**
+ * @}
+ */
+/** @defgroup GPIO_Remap_define
+ * @{
+ */
+
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ to TIM2 Internal Trigger 1 for calibration
+ (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
@@ -147,28 +208,36 @@
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
- ((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \
+ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
- ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
- ((REMAP) == GPIO_Remap_SWJ_Disable))
+ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
+ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
+ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS))
-/* GPIO Port Sources ---------------------------------------------------------*/
-#define GPIO_PortSourceGPIOA ((u8)0x00)
-#define GPIO_PortSourceGPIOB ((u8)0x01)
-#define GPIO_PortSourceGPIOC ((u8)0x02)
-#define GPIO_PortSourceGPIOD ((u8)0x03)
-#define GPIO_PortSourceGPIOE ((u8)0x04)
-#define GPIO_PortSourceGPIOF ((u8)0x05)
-#define GPIO_PortSourceGPIOG ((u8)0x06)
+/**
+ * @}
+ */
+/** @defgroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE))
-
+
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
@@ -176,25 +245,32 @@
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
((PORTSOURCE) == GPIO_PortSourceGPIOG))
-
-/* GPIO Pin sources ----------------------------------------------------------*/
-#define GPIO_PinSource0 ((u8)0x00)
-#define GPIO_PinSource1 ((u8)0x01)
-#define GPIO_PinSource2 ((u8)0x02)
-#define GPIO_PinSource3 ((u8)0x03)
-#define GPIO_PinSource4 ((u8)0x04)
-#define GPIO_PinSource5 ((u8)0x05)
-#define GPIO_PinSource6 ((u8)0x06)
-#define GPIO_PinSource7 ((u8)0x07)
-#define GPIO_PinSource8 ((u8)0x08)
-#define GPIO_PinSource9 ((u8)0x09)
-#define GPIO_PinSource10 ((u8)0x0A)
-#define GPIO_PinSource11 ((u8)0x0B)
-#define GPIO_PinSource12 ((u8)0x0C)
-#define GPIO_PinSource13 ((u8)0x0D)
-#define GPIO_PinSource14 ((u8)0x0E)
-#define GPIO_PinSource15 ((u8)0x0F)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
@@ -211,27 +287,73 @@
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+
+/**
+ * @}
+ */
+
+/** @defgroup Ethernet_Media_Interface
+ * @{
+ */
+#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions
+ * @{
+ */
+
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
-u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
-u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
-void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
-void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
-void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_GPIO_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_i2c.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_i2c.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_i2c.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,89 +1,158 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_i2c.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* I2C firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_I2C_H
+#ifndef __STM32F10x_I2C_H
#define __STM32F10x_I2C_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* I2C Init structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
typedef struct
{
- u16 I2C_Mode;
- u16 I2C_DutyCycle;
- u16 I2C_OwnAddress1;
- u16 I2C_Ack;
- u16 I2C_AcknowledgedAddress;
- u32 I2C_ClockSpeed;
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-#define IS_I2C_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == I2C1_BASE) || \
- ((*(u32*)&(PERIPH)) == I2C2_BASE))
+/**
+ * @}
+ */
-/* I2C modes */
-#define I2C_Mode_I2C ((u16)0x0000)
-#define I2C_Mode_SMBusDevice ((u16)0x0002)
-#define I2C_Mode_SMBusHost ((u16)0x000A)
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
-/* I2C duty cycle in fast mode */
-#define I2C_DutyCycle_16_9 ((u16)0x4000)
-#define I2C_DutyCycle_2 ((u16)0xBFFF)
+/**
+ * @}
+ */
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
+/**
+ * @}
+ */
-/* I2C cknowledgementy */
-#define I2C_Ack_Enable ((u16)0x0400)
-#define I2C_Ack_Disable ((u16)0x0000)
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+#define I2C_Ack_Enable ((uint16_t)0x0400)
+#define I2C_Ack_Disable ((uint16_t)0x0000)
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
((STATE) == I2C_Ack_Disable))
+/**
+ * @}
+ */
-/* I2C transfer direction */
-#define I2C_Direction_Transmitter ((u8)0x00)
-#define I2C_Direction_Receiver ((u8)0x01)
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+#define I2C_Direction_Transmitter ((uint8_t)0x00)
+#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
-/* I2C acknowledged address defines */
-#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
-/* I2C registers */
-#define I2C_Register_CR1 ((u8)0x00)
-#define I2C_Register_CR2 ((u8)0x04)
-#define I2C_Register_OAR1 ((u8)0x08)
-#define I2C_Register_OAR2 ((u8)0x0C)
-#define I2C_Register_DR ((u8)0x10)
-#define I2C_Register_SR1 ((u8)0x14)
-#define I2C_Register_SR2 ((u8)0x18)
-#define I2C_Register_CCR ((u8)0x1C)
-#define I2C_Register_TRISE ((u8)0x20)
+/** @defgroup I2C_registers
+ * @{
+ */
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_DR ((uint8_t)0x10)
+#define I2C_Register_SR1 ((uint8_t)0x14)
+#define I2C_Register_SR2 ((uint8_t)0x18)
+#define I2C_Register_CCR ((uint8_t)0x1C)
+#define I2C_Register_TRISE ((uint8_t)0x20)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
@@ -93,46 +162,67 @@
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_CCR) || \
((REGISTER) == I2C_Register_TRISE))
+/**
+ * @}
+ */
-/* I2C SMBus alert pin level */
-#define I2C_SMBusAlert_Low ((u16)0x2000)
-#define I2C_SMBusAlert_High ((u16)0xDFFF)
+/** @defgroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
((ALERT) == I2C_SMBusAlert_High))
+/**
+ * @}
+ */
-/* I2C PEC position */
-#define I2C_PECPosition_Next ((u16)0x0800)
-#define I2C_PECPosition_Current ((u16)0xF7FF)
+/** @defgroup I2C_PEC_position
+ * @{
+ */
+#define I2C_PECPosition_Next ((uint16_t)0x0800)
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
((POSITION) == I2C_PECPosition_Current))
+/**
+ * @}
+ */
-/* I2C interrupts definition */
-#define I2C_IT_BUF ((u16)0x0400)
-#define I2C_IT_EVT ((u16)0x0200)
-#define I2C_IT_ERR ((u16)0x0100)
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (u16)0xF8FF) == 0x00) && ((IT) != 0x00))
+#define I2C_IT_BUF ((uint16_t)0x0400)
+#define I2C_IT_EVT ((uint16_t)0x0200)
+#define I2C_IT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
-/* I2C interrupts definition */
-#define I2C_IT_SMBALERT ((u32)0x01008000)
-#define I2C_IT_TIMEOUT ((u32)0x01004000)
-#define I2C_IT_PECERR ((u32)0x01001000)
-#define I2C_IT_OVR ((u32)0x01000800)
-#define I2C_IT_AF ((u32)0x01000400)
-#define I2C_IT_ARLO ((u32)0x01000200)
-#define I2C_IT_BERR ((u32)0x01000100)
-#define I2C_IT_TXE ((u32)0x06000080)
-#define I2C_IT_RXNE ((u32)0x06000040)
-#define I2C_IT_STOPF ((u32)0x02000010)
-#define I2C_IT_ADD10 ((u32)0x02000008)
-#define I2C_IT_BTF ((u32)0x02000004)
-#define I2C_IT_ADDR ((u32)0x02000002)
-#define I2C_IT_SB ((u32)0x02000001)
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (u16)0x20FF) == 0x00) && ((IT) != (u16)0x00))
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
+#define I2C_IT_PECERR ((uint32_t)0x01001000)
+#define I2C_IT_OVR ((uint32_t)0x01000800)
+#define I2C_IT_AF ((uint32_t)0x01000400)
+#define I2C_IT_ARLO ((uint32_t)0x01000200)
+#define I2C_IT_BERR ((uint32_t)0x01000100)
+#define I2C_IT_TXE ((uint32_t)0x06000080)
+#define I2C_IT_RXNE ((uint32_t)0x06000040)
+#define I2C_IT_STOPF ((uint32_t)0x02000010)
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)
+#define I2C_IT_BTF ((uint32_t)0x02000004)
+#define I2C_IT_ADDR ((uint32_t)0x02000002)
+#define I2C_IT_SB ((uint32_t)0x02000001)
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
@@ -140,34 +230,47 @@
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+ * @}
+ */
-/* I2C flags definition */
-/* SR2 register flags */
-#define I2C_FLAG_DUALF ((u32)0x00800000)
-#define I2C_FLAG_SMBHOST ((u32)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)
-#define I2C_FLAG_GENCALL ((u32)0x00100000)
-#define I2C_FLAG_TRA ((u32)0x00040000)
-#define I2C_FLAG_BUSY ((u32)0x00020000)
-#define I2C_FLAG_MSL ((u32)0x00010000)
-/* SR1 register flags */
-#define I2C_FLAG_SMBALERT ((u32)0x10008000)
-#define I2C_FLAG_TIMEOUT ((u32)0x10004000)
-#define I2C_FLAG_PECERR ((u32)0x10001000)
-#define I2C_FLAG_OVR ((u32)0x10000800)
-#define I2C_FLAG_AF ((u32)0x10000400)
-#define I2C_FLAG_ARLO ((u32)0x10000200)
-#define I2C_FLAG_BERR ((u32)0x10000100)
-#define I2C_FLAG_TXE ((u32)0x10000080)
-#define I2C_FLAG_RXNE ((u32)0x10000040)
-#define I2C_FLAG_STOPF ((u32)0x10000010)
-#define I2C_FLAG_ADD10 ((u32)0x10000008)
-#define I2C_FLAG_BTF ((u32)0x10000004)
-#define I2C_FLAG_ADDR ((u32)0x10000002)
-#define I2C_FLAG_SB ((u32)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0x20FF) == 0x00) && ((FLAG) != (u16)0x00))
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+/**
+ * @brief SR2 register flags
+ */
+
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
+/**
+ * @brief SR1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)
+#define I2C_FLAG_AF ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+#define I2C_FLAG_SB ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
@@ -179,46 +282,85 @@
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB))
+/**
+ * @}
+ */
-/* I2C Events */
-/* EV1 */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */
+/** @defgroup I2C_Events
+ * @{
+ */
-/* EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */
-
-/* EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+/**
+ * @brief EV1
+ */
-/* EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-/* EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */
+/**
+ * @brief EV2
+ */
-/* EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */
+/**
+ * @brief EV3
+ */
-/* EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((u32)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-/* EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-/* EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/* EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */
+/**
+ * @brief EV4
+ */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
+/**
+ * @brief EV5
+ */
+
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief EV6
+ */
+
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+
+/**
+ * @brief EV7
+ */
+
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/**
+ * @brief EV8
+ */
+
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+
+/**
+ * @brief EV8_2
+ */
+
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/**
+ * @brief EV9
+ */
+
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief EV3_2
+ */
+
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
@@ -236,16 +378,47 @@
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+ * @}
+ */
-/* I2C own address1 -----------------------------------------------------------*/
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/* I2C clock speed ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_clock_speed
+ * @{
+ */
+
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions
+ * @{
+ */
+
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
@@ -255,30 +428,45 @@
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
-void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
-u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
-u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
-u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /*__STM32F10x_I2C_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_iwdg.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_iwdg.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_iwdg.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,44 +1,78 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_iwdg.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* IWDG firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IWDG_H
#define __STM32F10x_IWDG_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Write access to IWDG_PR and IWDG_RLR registers */
-#define IWDG_WriteAccess_Enable ((u16)0x5555)
-#define IWDG_WriteAccess_Disable ((u16)0x0000)
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
-/* IWDG prescaler */
-#define IWDG_Prescaler_4 ((u8)0x00)
-#define IWDG_Prescaler_8 ((u8)0x01)
-#define IWDG_Prescaler_16 ((u8)0x02)
-#define IWDG_Prescaler_32 ((u8)0x03)
-#define IWDG_Prescaler_64 ((u8)0x04)
-#define IWDG_Prescaler_128 ((u8)0x05)
-#define IWDG_Prescaler_256 ((u8)0x06)
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
@@ -46,24 +80,60 @@
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
-/* IWDG Flag */
-#define IWDG_FLAG_PVU ((u16)0x0001)
-#define IWDG_FLAG_RVU ((u16)0x0002)
+/** @defgroup IWDG_Flag
+ * @{
+ */
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
-
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
-void IWDG_SetPrescaler(u8 IWDG_Prescaler);
-void IWDG_SetReload(u16 Reload);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
-FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_IWDG_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_lib.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_lib.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_lib.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,124 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_lib.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file includes the peripherals header files in the
-* user application.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_LIB_H
-#define __STM32F10x_LIB_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
-
-#ifdef _ADC
- #include "stm32f10x_adc.h"
-#endif /*_ADC */
-
-#ifdef _BKP
- #include "stm32f10x_bkp.h"
-#endif /*_BKP */
-
-#ifdef _CAN
- #include "stm32f10x_can.h"
-#endif /*_CAN */
-
-#ifdef _CRC
- #include "stm32f10x_crc.h"
-#endif /*_CRC */
-
-#ifdef _DAC
- #include "stm32f10x_dac.h"
-#endif /*_DAC */
-
-#ifdef _DBGMCU
- #include "stm32f10x_dbgmcu.h"
-#endif /*_DBGMCU */
-
-#ifdef _DMA
- #include "stm32f10x_dma.h"
-#endif /*_DMA */
-
-#ifdef _EXTI
- #include "stm32f10x_exti.h"
-#endif /*_EXTI */
-
-#ifdef _FLASH
- #include "stm32f10x_flash.h"
-#endif /*_FLASH */
-
-#ifdef _FSMC
- #include "stm32f10x_fsmc.h"
-#endif /*_FSMC */
-
-#ifdef _GPIO
- #include "stm32f10x_gpio.h"
-#endif /*_GPIO */
-
-#ifdef _I2C
- #include "stm32f10x_i2c.h"
-#endif /*_I2C */
-
-#ifdef _IWDG
- #include "stm32f10x_iwdg.h"
-#endif /*_IWDG */
-
-#ifdef _NVIC
- #include "stm32f10x_nvic.h"
-#endif /*_NVIC */
-
-#ifdef _PWR
- #include "stm32f10x_pwr.h"
-#endif /*_PWR */
-
-#ifdef _RCC
- #include "stm32f10x_rcc.h"
-#endif /*_RCC */
-
-#ifdef _RTC
- #include "stm32f10x_rtc.h"
-#endif /*_RTC */
-
-#ifdef _SDIO
- #include "stm32f10x_sdio.h"
-#endif /*_SDIO */
-
-#ifdef _SPI
- #include "stm32f10x_spi.h"
-#endif /*_SPI */
-
-#ifdef _SysTick
- #include "stm32f10x_systick.h"
-#endif /*_SysTick */
-
-#ifdef _TIM
- #include "stm32f10x_tim.h"
-#endif /*_TIM */
-
-#ifdef _USART
- #include "stm32f10x_usart.h"
-#endif /*_USART */
-
-#ifdef _WWDG
- #include "stm32f10x_wwdg.h"
-#endif /*_WWDG */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void debug(void);
-
-#endif /* __STM32F10x_LIB_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_map.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_map.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_map.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7603 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_map.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the peripheral register's definitions,
-* bits definitions and memory mapping.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_MAP_H
-#define __STM32F10x_MAP_H
-
-#ifndef EXT
- #define EXT extern
-#endif /* EXT */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_conf.h"
-#include "stm32f10x_type.h"
-#include "cortexm3_macro.h"
-
-/* Exported types ------------------------------------------------------------*/
-/******************************************************************************/
-/* Peripheral registers structures */
-/******************************************************************************/
-
-/*------------------------ Analog to Digital Converter -----------------------*/
-typedef struct
-{
- vu32 SR;
- vu32 CR1;
- vu32 CR2;
- vu32 SMPR1;
- vu32 SMPR2;
- vu32 JOFR1;
- vu32 JOFR2;
- vu32 JOFR3;
- vu32 JOFR4;
- vu32 HTR;
- vu32 LTR;
- vu32 SQR1;
- vu32 SQR2;
- vu32 SQR3;
- vu32 JSQR;
- vu32 JDR1;
- vu32 JDR2;
- vu32 JDR3;
- vu32 JDR4;
- vu32 DR;
-} ADC_TypeDef;
-
-/*------------------------ Backup Registers ----------------------------------*/
-typedef struct
-{
- u32 RESERVED0;
- vu16 DR1;
- u16 RESERVED1;
- vu16 DR2;
- u16 RESERVED2;
- vu16 DR3;
- u16 RESERVED3;
- vu16 DR4;
- u16 RESERVED4;
- vu16 DR5;
- u16 RESERVED5;
- vu16 DR6;
- u16 RESERVED6;
- vu16 DR7;
- u16 RESERVED7;
- vu16 DR8;
- u16 RESERVED8;
- vu16 DR9;
- u16 RESERVED9;
- vu16 DR10;
- u16 RESERVED10;
- vu16 RTCCR;
- u16 RESERVED11;
- vu16 CR;
- u16 RESERVED12;
- vu16 CSR;
- u16 RESERVED13[5];
- vu16 DR11;
- u16 RESERVED14;
- vu16 DR12;
- u16 RESERVED15;
- vu16 DR13;
- u16 RESERVED16;
- vu16 DR14;
- u16 RESERVED17;
- vu16 DR15;
- u16 RESERVED18;
- vu16 DR16;
- u16 RESERVED19;
- vu16 DR17;
- u16 RESERVED20;
- vu16 DR18;
- u16 RESERVED21;
- vu16 DR19;
- u16 RESERVED22;
- vu16 DR20;
- u16 RESERVED23;
- vu16 DR21;
- u16 RESERVED24;
- vu16 DR22;
- u16 RESERVED25;
- vu16 DR23;
- u16 RESERVED26;
- vu16 DR24;
- u16 RESERVED27;
- vu16 DR25;
- u16 RESERVED28;
- vu16 DR26;
- u16 RESERVED29;
- vu16 DR27;
- u16 RESERVED30;
- vu16 DR28;
- u16 RESERVED31;
- vu16 DR29;
- u16 RESERVED32;
- vu16 DR30;
- u16 RESERVED33;
- vu16 DR31;
- u16 RESERVED34;
- vu16 DR32;
- u16 RESERVED35;
- vu16 DR33;
- u16 RESERVED36;
- vu16 DR34;
- u16 RESERVED37;
- vu16 DR35;
- u16 RESERVED38;
- vu16 DR36;
- u16 RESERVED39;
- vu16 DR37;
- u16 RESERVED40;
- vu16 DR38;
- u16 RESERVED41;
- vu16 DR39;
- u16 RESERVED42;
- vu16 DR40;
- u16 RESERVED43;
- vu16 DR41;
- u16 RESERVED44;
- vu16 DR42;
- u16 RESERVED45;
-} BKP_TypeDef;
-
-/*------------------------ Controller Area Network ---------------------------*/
-typedef struct
-{
- vu32 TIR;
- vu32 TDTR;
- vu32 TDLR;
- vu32 TDHR;
-} CAN_TxMailBox_TypeDef;
-
-typedef struct
-{
- vu32 RIR;
- vu32 RDTR;
- vu32 RDLR;
- vu32 RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-typedef struct
-{
- vu32 FR1;
- vu32 FR2;
-} CAN_FilterRegister_TypeDef;
-
-typedef struct
-{
- vu32 MCR;
- vu32 MSR;
- vu32 TSR;
- vu32 RF0R;
- vu32 RF1R;
- vu32 IER;
- vu32 ESR;
- vu32 BTR;
- u32 RESERVED0[88];
- CAN_TxMailBox_TypeDef sTxMailBox[3];
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
- u32 RESERVED1[12];
- vu32 FMR;
- vu32 FM1R;
- u32 RESERVED2;
- vu32 FS1R;
- u32 RESERVED3;
- vu32 FFA1R;
- u32 RESERVED4;
- vu32 FA1R;
- u32 RESERVED5[8];
- CAN_FilterRegister_TypeDef sFilterRegister[14];
-} CAN_TypeDef;
-
-/*------------------------ CRC calculation unit ------------------------------*/
-typedef struct
-{
- vu32 DR;
- vu8 IDR;
- u8 RESERVED0;
- u16 RESERVED1;
- vu32 CR;
-} CRC_TypeDef;
-
-
-/*------------------------ Digital to Analog Converter -----------------------*/
-typedef struct
-{
- vu32 CR;
- vu32 SWTRIGR;
- vu32 DHR12R1;
- vu32 DHR12L1;
- vu32 DHR8R1;
- vu32 DHR12R2;
- vu32 DHR12L2;
- vu32 DHR8R2;
- vu32 DHR12RD;
- vu32 DHR12LD;
- vu32 DHR8RD;
- vu32 DOR1;
- vu32 DOR2;
-} DAC_TypeDef;
-
-/*------------------------ Debug MCU -----------------------------------------*/
-typedef struct
-{
- vu32 IDCODE;
- vu32 CR;
-}DBGMCU_TypeDef;
-
-/*------------------------ DMA Controller ------------------------------------*/
-typedef struct
-{
- vu32 CCR;
- vu32 CNDTR;
- vu32 CPAR;
- vu32 CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- vu32 ISR;
- vu32 IFCR;
-} DMA_TypeDef;
-
-/*------------------------ External Interrupt/Event Controller ---------------*/
-typedef struct
-{
- vu32 IMR;
- vu32 EMR;
- vu32 RTSR;
- vu32 FTSR;
- vu32 SWIER;
- vu32 PR;
-} EXTI_TypeDef;
-
-/*------------------------ FLASH and Option Bytes Registers ------------------*/
-typedef struct
-{
- vu32 ACR;
- vu32 KEYR;
- vu32 OPTKEYR;
- vu32 SR;
- vu32 CR;
- vu32 AR;
- vu32 RESERVED;
- vu32 OBR;
- vu32 WRPR;
-} FLASH_TypeDef;
-
-typedef struct
-{
- vu16 RDP;
- vu16 USER;
- vu16 Data0;
- vu16 Data1;
- vu16 WRP0;
- vu16 WRP1;
- vu16 WRP2;
- vu16 WRP3;
-} OB_TypeDef;
-
-/*------------------------ Flexible Static Memory Controller -----------------*/
-typedef struct
-{
- vu32 BTCR[8];
-} FSMC_Bank1_TypeDef;
-
-typedef struct
-{
- vu32 BWTR[7];
-} FSMC_Bank1E_TypeDef;
-
-typedef struct
-{
- vu32 PCR2;
- vu32 SR2;
- vu32 PMEM2;
- vu32 PATT2;
- u32 RESERVED0;
- vu32 ECCR2;
-} FSMC_Bank2_TypeDef;
-
-typedef struct
-{
- vu32 PCR3;
- vu32 SR3;
- vu32 PMEM3;
- vu32 PATT3;
- u32 RESERVED0;
- vu32 ECCR3;
-} FSMC_Bank3_TypeDef;
-
-typedef struct
-{
- vu32 PCR4;
- vu32 SR4;
- vu32 PMEM4;
- vu32 PATT4;
- vu32 PIO4;
-} FSMC_Bank4_TypeDef;
-
-/*------------------------ General Purpose and Alternate Function IO ---------*/
-typedef struct
-{
- vu32 CRL;
- vu32 CRH;
- vu32 IDR;
- vu32 ODR;
- vu32 BSRR;
- vu32 BRR;
- vu32 LCKR;
-} GPIO_TypeDef;
-
-typedef struct
-{
- vu32 EVCR;
- vu32 MAPR;
- vu32 EXTICR[4];
-} AFIO_TypeDef;
-
-/*------------------------ Inter-integrated Circuit Interface ----------------*/
-typedef struct
-{
- vu16 CR1;
- u16 RESERVED0;
- vu16 CR2;
- u16 RESERVED1;
- vu16 OAR1;
- u16 RESERVED2;
- vu16 OAR2;
- u16 RESERVED3;
- vu16 DR;
- u16 RESERVED4;
- vu16 SR1;
- u16 RESERVED5;
- vu16 SR2;
- u16 RESERVED6;
- vu16 CCR;
- u16 RESERVED7;
- vu16 TRISE;
- u16 RESERVED8;
-} I2C_TypeDef;
-
-/*------------------------ Independent WATCHDOG ------------------------------*/
-typedef struct
-{
- vu32 KR;
- vu32 PR;
- vu32 RLR;
- vu32 SR;
-} IWDG_TypeDef;
-
-/*------------------------ Nested Vectored Interrupt Controller --------------*/
-typedef struct
-{
- vu32 ISER[2];
- u32 RESERVED0[30];
- vu32 ICER[2];
- u32 RSERVED1[30];
- vu32 ISPR[2];
- u32 RESERVED2[30];
- vu32 ICPR[2];
- u32 RESERVED3[30];
- vu32 IABR[2];
- u32 RESERVED4[62];
- vu32 IPR[15];
-} NVIC_TypeDef;
-
-typedef struct
-{
- vuc32 CPUID;
- vu32 ICSR;
- vu32 VTOR;
- vu32 AIRCR;
- vu32 SCR;
- vu32 CCR;
- vu32 SHPR[3];
- vu32 SHCSR;
- vu32 CFSR;
- vu32 HFSR;
- vu32 DFSR;
- vu32 MMFAR;
- vu32 BFAR;
- vu32 AFSR;
-} SCB_TypeDef;
-
-/*------------------------ Power Control -------------------------------------*/
-typedef struct
-{
- vu32 CR;
- vu32 CSR;
-} PWR_TypeDef;
-
-/*------------------------ Reset and Clock Control ---------------------------*/
-typedef struct
-{
- vu32 CR;
- vu32 CFGR;
- vu32 CIR;
- vu32 APB2RSTR;
- vu32 APB1RSTR;
- vu32 AHBENR;
- vu32 APB2ENR;
- vu32 APB1ENR;
- vu32 BDCR;
- vu32 CSR;
-} RCC_TypeDef;
-
-/*------------------------ Real-Time Clock -----------------------------------*/
-typedef struct
-{
- vu16 CRH;
- u16 RESERVED0;
- vu16 CRL;
- u16 RESERVED1;
- vu16 PRLH;
- u16 RESERVED2;
- vu16 PRLL;
- u16 RESERVED3;
- vu16 DIVH;
- u16 RESERVED4;
- vu16 DIVL;
- u16 RESERVED5;
- vu16 CNTH;
- u16 RESERVED6;
- vu16 CNTL;
- u16 RESERVED7;
- vu16 ALRH;
- u16 RESERVED8;
- vu16 ALRL;
- u16 RESERVED9;
-} RTC_TypeDef;
-
-/*------------------------ SD host Interface ---------------------------------*/
-typedef struct
-{
- vu32 POWER;
- vu32 CLKCR;
- vu32 ARG;
- vu32 CMD;
- vuc32 RESPCMD;
- vuc32 RESP1;
- vuc32 RESP2;
- vuc32 RESP3;
- vuc32 RESP4;
- vu32 DTIMER;
- vu32 DLEN;
- vu32 DCTRL;
- vuc32 DCOUNT;
- vuc32 STA;
- vu32 ICR;
- vu32 MASK;
- u32 RESERVED0[2];
- vuc32 FIFOCNT;
- u32 RESERVED1[13];
- vu32 FIFO;
-} SDIO_TypeDef;
-
-/*------------------------ Serial Peripheral Interface -----------------------*/
-typedef struct
-{
- vu16 CR1;
- u16 RESERVED0;
- vu16 CR2;
- u16 RESERVED1;
- vu16 SR;
- u16 RESERVED2;
- vu16 DR;
- u16 RESERVED3;
- vu16 CRCPR;
- u16 RESERVED4;
- vu16 RXCRCR;
- u16 RESERVED5;
- vu16 TXCRCR;
- u16 RESERVED6;
- vu16 I2SCFGR;
- u16 RESERVED7;
- vu16 I2SPR;
- u16 RESERVED8;
-} SPI_TypeDef;
-
-/*------------------------ SystemTick ----------------------------------------*/
-typedef struct
-{
- vu32 CTRL;
- vu32 LOAD;
- vu32 VAL;
- vuc32 CALIB;
-} SysTick_TypeDef;
-
-/*------------------------ TIM -----------------------------------------------*/
-typedef struct
-{
- vu16 CR1;
- u16 RESERVED0;
- vu16 CR2;
- u16 RESERVED1;
- vu16 SMCR;
- u16 RESERVED2;
- vu16 DIER;
- u16 RESERVED3;
- vu16 SR;
- u16 RESERVED4;
- vu16 EGR;
- u16 RESERVED5;
- vu16 CCMR1;
- u16 RESERVED6;
- vu16 CCMR2;
- u16 RESERVED7;
- vu16 CCER;
- u16 RESERVED8;
- vu16 CNT;
- u16 RESERVED9;
- vu16 PSC;
- u16 RESERVED10;
- vu16 ARR;
- u16 RESERVED11;
- vu16 RCR;
- u16 RESERVED12;
- vu16 CCR1;
- u16 RESERVED13;
- vu16 CCR2;
- u16 RESERVED14;
- vu16 CCR3;
- u16 RESERVED15;
- vu16 CCR4;
- u16 RESERVED16;
- vu16 BDTR;
- u16 RESERVED17;
- vu16 DCR;
- u16 RESERVED18;
- vu16 DMAR;
- u16 RESERVED19;
-} TIM_TypeDef;
-
-/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
-typedef struct
-{
- vu16 SR;
- u16 RESERVED0;
- vu16 DR;
- u16 RESERVED1;
- vu16 BRR;
- u16 RESERVED2;
- vu16 CR1;
- u16 RESERVED3;
- vu16 CR2;
- u16 RESERVED4;
- vu16 CR3;
- u16 RESERVED5;
- vu16 GTPR;
- u16 RESERVED6;
-} USART_TypeDef;
-
-/*------------------------ Window WATCHDOG -----------------------------------*/
-typedef struct
-{
- vu32 CR;
- vu32 CFR;
- vu32 SR;
-} WWDG_TypeDef;
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Peripheral and SRAM base address in the alias region */
-#define PERIPH_BB_BASE ((u32)0x42000000)
-#define SRAM_BB_BASE ((u32)0x22000000)
-
-/* Peripheral and SRAM base address in the bit-band region */
-#define SRAM_BASE ((u32)0x20000000)
-#define PERIPH_BASE ((u32)0x40000000)
-
-/* FSMC registers base address */
-#define FSMC_R_BASE ((u32)0xA0000000)
-
-/* Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
-
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
-
-/* Flash registers base address */
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
-/* Flash Option Bytes base address */
-#define OB_BASE ((u32)0x1FFFF800)
-
-/* FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((u32)0xE0042000)
-
-/* System Control Space memory map */
-#define SCS_BASE ((u32)0xE000E000)
-
-#define SysTick_BASE (SCS_BASE + 0x0010)
-#define NVIC_BASE (SCS_BASE + 0x0100)
-#define SCB_BASE (SCS_BASE + 0x0D00)
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-
-/*------------------------ Non Debug Mode ------------------------------------*/
-#ifndef DEBUG
-#ifdef _TIM2
- #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#endif /*_TIM2 */
-
-#ifdef _TIM3
- #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#endif /*_TIM3 */
-
-#ifdef _TIM4
- #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#endif /*_TIM4 */
-
-#ifdef _TIM5
- #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#endif /*_TIM5 */
-
-#ifdef _TIM6
- #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#endif /*_TIM6 */
-
-#ifdef _TIM7
- #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#endif /*_TIM7 */
-
-#ifdef _RTC
- #define RTC ((RTC_TypeDef *) RTC_BASE)
-#endif /*_RTC */
-
-#ifdef _WWDG
- #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#endif /*_WWDG */
-
-#ifdef _IWDG
- #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#endif /*_IWDG */
-
-#ifdef _SPI2
- #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#endif /*_SPI2 */
-
-#ifdef _SPI3
- #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#endif /*_SPI3 */
-
-#ifdef _USART2
- #define USART2 ((USART_TypeDef *) USART2_BASE)
-#endif /*_USART2 */
-
-#ifdef _USART3
- #define USART3 ((USART_TypeDef *) USART3_BASE)
-#endif /*_USART3 */
-
-#ifdef _UART4
- #define UART4 ((USART_TypeDef *) UART4_BASE)
-#endif /*_UART4 */
-
-#ifdef _UART5
- #define UART5 ((USART_TypeDef *) UART5_BASE)
-#endif /*_USART5 */
-
-#ifdef _I2C1
- #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#endif /*_I2C1 */
-
-#ifdef _I2C2
- #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#endif /*_I2C2 */
-
-#ifdef _CAN
- #define CAN ((CAN_TypeDef *) CAN_BASE)
-#endif /*_CAN */
-
-#ifdef _BKP
- #define BKP ((BKP_TypeDef *) BKP_BASE)
-#endif /*_BKP */
-
-#ifdef _PWR
- #define PWR ((PWR_TypeDef *) PWR_BASE)
-#endif /*_PWR */
-
-#ifdef _DAC
- #define DAC ((DAC_TypeDef *) DAC_BASE)
-#endif /*_DAC */
-
-#ifdef _AFIO
- #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#endif /*_AFIO */
-
-#ifdef _EXTI
- #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#endif /*_EXTI */
-
-#ifdef _GPIOA
- #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#endif /*_GPIOA */
-
-#ifdef _GPIOB
- #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#endif /*_GPIOB */
-
-#ifdef _GPIOC
- #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#endif /*_GPIOC */
-
-#ifdef _GPIOD
- #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#endif /*_GPIOD */
-
-#ifdef _GPIOE
- #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#endif /*_GPIOE */
-
-#ifdef _GPIOF
- #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#endif /*_GPIOF */
-
-#ifdef _GPIOG
- #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#endif /*_GPIOG */
-
-#ifdef _ADC1
- #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#endif /*_ADC1 */
-
-#ifdef _ADC2
- #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#endif /*_ADC2 */
-
-#ifdef _TIM1
- #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#endif /*_TIM1 */
-
-#ifdef _SPI1
- #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#endif /*_SPI1 */
-
-#ifdef _TIM8
- #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#endif /*_TIM8 */
-
-#ifdef _USART1
- #define USART1 ((USART_TypeDef *) USART1_BASE)
-#endif /*_USART1 */
-
-#ifdef _ADC3
- #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#endif /*_ADC3 */
-
-#ifdef _SDIO
- #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#endif /*_SDIO */
-
-#ifdef _DMA
- #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
- #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#endif /*_DMA */
-
-#ifdef _DMA1_Channel1
- #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#endif /*_DMA1_Channel1 */
-
-#ifdef _DMA1_Channel2
- #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#endif /*_DMA1_Channel2 */
-
-#ifdef _DMA1_Channel3
- #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#endif /*_DMA1_Channel3 */
-
-#ifdef _DMA1_Channel4
- #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#endif /*_DMA1_Channel4 */
-
-#ifdef _DMA1_Channel5
- #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#endif /*_DMA1_Channel5 */
-
-#ifdef _DMA1_Channel6
- #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#endif /*_DMA1_Channel6 */
-
-#ifdef _DMA1_Channel7
- #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#endif /*_DMA1_Channel7 */
-
-#ifdef _DMA2_Channel1
- #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#endif /*_DMA2_Channel1 */
-
-#ifdef _DMA2_Channel2
- #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#endif /*_DMA2_Channel2 */
-
-#ifdef _DMA2_Channel3
- #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#endif /*_DMA2_Channel3 */
-
-#ifdef _DMA2_Channel4
- #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#endif /*_DMA2_Channel4 */
-
-#ifdef _DMA2_Channel5
- #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#endif /*_DMA2_Channel5 */
-
-#ifdef _RCC
- #define RCC ((RCC_TypeDef *) RCC_BASE)
-#endif /*_RCC */
-
-#ifdef _CRC
- #define CRC ((CRC_TypeDef *) CRC_BASE)
-#endif /*_CRC */
-
-#ifdef _FLASH
- #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
- #define OB ((OB_TypeDef *) OB_BASE)
-#endif /*_FLASH */
-
-#ifdef _FSMC
- #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
- #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
- #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
- #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
- #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#endif /*_FSMC */
-
-#ifdef _DBGMCU
- #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#endif /*_DBGMCU */
-
-#ifdef _SysTick
- #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
-#endif /*_SysTick */
-
-#ifdef _NVIC
- #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
- #define SCB ((SCB_TypeDef *) SCB_BASE)
-#endif /*_NVIC */
-
-/*------------------------ Debug Mode ----------------------------------------*/
-#else /* DEBUG */
-#ifdef _TIM2
- EXT TIM_TypeDef *TIM2;
-#endif /*_TIM2 */
-
-#ifdef _TIM3
- EXT TIM_TypeDef *TIM3;
-#endif /*_TIM3 */
-
-#ifdef _TIM4
- EXT TIM_TypeDef *TIM4;
-#endif /*_TIM4 */
-
-#ifdef _TIM5
- EXT TIM_TypeDef *TIM5;
-#endif /*_TIM5 */
-
-#ifdef _TIM6
- EXT TIM_TypeDef *TIM6;
-#endif /*_TIM6 */
-
-#ifdef _TIM7
- EXT TIM_TypeDef *TIM7;
-#endif /*_TIM7 */
-
-#ifdef _RTC
- EXT RTC_TypeDef *RTC;
-#endif /*_RTC */
-
-#ifdef _WWDG
- EXT WWDG_TypeDef *WWDG;
-#endif /*_WWDG */
-
-#ifdef _IWDG
- EXT IWDG_TypeDef *IWDG;
-#endif /*_IWDG */
-
-#ifdef _SPI2
- EXT SPI_TypeDef *SPI2;
-#endif /*_SPI2 */
-
-#ifdef _SPI3
- EXT SPI_TypeDef *SPI3;
-#endif /*_SPI3 */
-
-#ifdef _USART2
- EXT USART_TypeDef *USART2;
-#endif /*_USART2 */
-
-#ifdef _USART3
- EXT USART_TypeDef *USART3;
-#endif /*_USART3 */
-
-#ifdef _UART4
- EXT USART_TypeDef *UART4;
-#endif /*_UART4 */
-
-#ifdef _UART5
- EXT USART_TypeDef *UART5;
-#endif /*_UART5 */
-
-#ifdef _I2C1
- EXT I2C_TypeDef *I2C1;
-#endif /*_I2C1 */
-
-#ifdef _I2C2
- EXT I2C_TypeDef *I2C2;
-#endif /*_I2C2 */
-
-#ifdef _CAN
- EXT CAN_TypeDef *CAN;
-#endif /*_CAN */
-
-#ifdef _BKP
- EXT BKP_TypeDef *BKP;
-#endif /*_BKP */
-
-#ifdef _PWR
- EXT PWR_TypeDef *PWR;
-#endif /*_PWR */
-
-#ifdef _DAC
- EXT DAC_TypeDef *DAC;
-#endif /*_DAC */
-
-#ifdef _AFIO
- EXT AFIO_TypeDef *AFIO;
-#endif /*_AFIO */
-
-#ifdef _EXTI
- EXT EXTI_TypeDef *EXTI;
-#endif /*_EXTI */
-
-#ifdef _GPIOA
- EXT GPIO_TypeDef *GPIOA;
-#endif /*_GPIOA */
-
-#ifdef _GPIOB
- EXT GPIO_TypeDef *GPIOB;
-#endif /*_GPIOB */
-
-#ifdef _GPIOC
- EXT GPIO_TypeDef *GPIOC;
-#endif /*_GPIOC */
-
-#ifdef _GPIOD
- EXT GPIO_TypeDef *GPIOD;
-#endif /*_GPIOD */
-
-#ifdef _GPIOE
- EXT GPIO_TypeDef *GPIOE;
-#endif /*_GPIOE */
-
-#ifdef _GPIOF
- EXT GPIO_TypeDef *GPIOF;
-#endif /*_GPIOF */
-
-#ifdef _GPIOG
- EXT GPIO_TypeDef *GPIOG;
-#endif /*_GPIOG */
-
-#ifdef _ADC1
- EXT ADC_TypeDef *ADC1;
-#endif /*_ADC1 */
-
-#ifdef _ADC2
- EXT ADC_TypeDef *ADC2;
-#endif /*_ADC2 */
-
-#ifdef _TIM1
- EXT TIM_TypeDef *TIM1;
-#endif /*_TIM1 */
-
-#ifdef _SPI1
- EXT SPI_TypeDef *SPI1;
-#endif /*_SPI1 */
-
-#ifdef _TIM8
- EXT TIM_TypeDef *TIM8;
-#endif /*_TIM8 */
-
-#ifdef _USART1
- EXT USART_TypeDef *USART1;
-#endif /*_USART1 */
-
-#ifdef _ADC3
- EXT ADC_TypeDef *ADC3;
-#endif /*_ADC3 */
-
-#ifdef _SDIO
- EXT SDIO_TypeDef *SDIO;
-#endif /*_SDIO */
-
-#ifdef _DMA
- EXT DMA_TypeDef *DMA1;
- EXT DMA_TypeDef *DMA2;
-#endif /*_DMA */
-
-#ifdef _DMA1_Channel1
- EXT DMA_Channel_TypeDef *DMA1_Channel1;
-#endif /*_DMA1_Channel1 */
-
-#ifdef _DMA1_Channel2
- EXT DMA_Channel_TypeDef *DMA1_Channel2;
-#endif /*_DMA1_Channel2 */
-
-#ifdef _DMA1_Channel3
- EXT DMA_Channel_TypeDef *DMA1_Channel3;
-#endif /*_DMA1_Channel3 */
-
-#ifdef _DMA1_Channel4
- EXT DMA_Channel_TypeDef *DMA1_Channel4;
-#endif /*_DMA1_Channel4 */
-
-#ifdef _DMA1_Channel5
- EXT DMA_Channel_TypeDef *DMA1_Channel5;
-#endif /*_DMA1_Channel5 */
-
-#ifdef _DMA1_Channel6
- EXT DMA_Channel_TypeDef *DMA1_Channel6;
-#endif /*_DMA1_Channel6 */
-
-#ifdef _DMA1_Channel7
- EXT DMA_Channel_TypeDef *DMA1_Channel7;
-#endif /*_DMA1_Channel7 */
-
-#ifdef _DMA2_Channel1
- EXT DMA_Channel_TypeDef *DMA2_Channel1;
-#endif /*_DMA2_Channel1 */
-
-#ifdef _DMA2_Channel2
- EXT DMA_Channel_TypeDef *DMA2_Channel2;
-#endif /*_DMA2_Channel2 */
-
-#ifdef _DMA2_Channel3
- EXT DMA_Channel_TypeDef *DMA2_Channel3;
-#endif /*_DMA2_Channel3 */
-
-#ifdef _DMA2_Channel4
- EXT DMA_Channel_TypeDef *DMA2_Channel4;
-#endif /*_DMA2_Channel4 */
-
-#ifdef _DMA2_Channel5
- EXT DMA_Channel_TypeDef *DMA2_Channel5;
-#endif /*_DMA2_Channel5 */
-
-#ifdef _RCC
- EXT RCC_TypeDef *RCC;
-#endif /*_RCC */
-
-#ifdef _CRC
- EXT CRC_TypeDef *CRC;
-#endif /*_CRC */
-
-#ifdef _FLASH
- EXT FLASH_TypeDef *FLASH;
- EXT OB_TypeDef *OB;
-#endif /*_FLASH */
-
-#ifdef _FSMC
- EXT FSMC_Bank1_TypeDef *FSMC_Bank1;
- EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E;
- EXT FSMC_Bank2_TypeDef *FSMC_Bank2;
- EXT FSMC_Bank3_TypeDef *FSMC_Bank3;
- EXT FSMC_Bank4_TypeDef *FSMC_Bank4;
-#endif /*_FSMC */
-
-#ifdef _DBGMCU
- EXT DBGMCU_TypeDef *DBGMCU;
-#endif /*_DBGMCU */
-
-#ifdef _SysTick
- EXT SysTick_TypeDef *SysTick;
-#endif /*_SysTick */
-
-#ifdef _NVIC
- EXT NVIC_TypeDef *NVIC;
- EXT SCB_TypeDef *SCB;
-#endif /*_NVIC */
-
-#endif /* DEBUG */
-
-/* Exported constants --------------------------------------------------------*/
-/******************************************************************************/
-/* */
-/* CRC calculation unit */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */
-
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */
-
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((u8)0x01) /* RESET bit */
-
-
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */
-#define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */
-#define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */
-#define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */
-#define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */
-#define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */
-#define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */
-
-/* PVD level configuration */
-#define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */
-
-#define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */
-
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */
-#define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */
-#define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */
-#define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */
-
-
-
-/******************************************************************************/
-/* */
-/* Backup registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for BKP_DR1 register ********************/
-#define BKP_DR1_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR2 register ********************/
-#define BKP_DR2_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR3 register ********************/
-#define BKP_DR3_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR4 register ********************/
-#define BKP_DR4_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR5 register ********************/
-#define BKP_DR5_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR6 register ********************/
-#define BKP_DR6_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR7 register ********************/
-#define BKP_DR7_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR8 register ********************/
-#define BKP_DR8_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR9 register ********************/
-#define BKP_DR9_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR10 register *******************/
-#define BKP_DR10_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR11 register *******************/
-#define BKP_DR11_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR12 register *******************/
-#define BKP_DR12_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR13 register *******************/
-#define BKP_DR13_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR14 register *******************/
-#define BKP_DR14_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR15 register *******************/
-#define BKP_DR15_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR16 register *******************/
-#define BKP_DR16_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR17 register *******************/
-#define BKP_DR17_D ((u16)0xFFFF) /* Backup data */
-
-
-/****************** Bit definition for BKP_DR18 register ********************/
-#define BKP_DR18_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR19 register *******************/
-#define BKP_DR19_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR20 register *******************/
-#define BKP_DR20_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR21 register *******************/
-#define BKP_DR21_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR22 register *******************/
-#define BKP_DR22_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR23 register *******************/
-#define BKP_DR23_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR24 register *******************/
-#define BKP_DR24_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR25 register *******************/
-#define BKP_DR25_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR26 register *******************/
-#define BKP_DR26_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR27 register *******************/
-#define BKP_DR27_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR28 register *******************/
-#define BKP_DR28_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR29 register *******************/
-#define BKP_DR29_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR30 register *******************/
-#define BKP_DR30_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR31 register *******************/
-#define BKP_DR31_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR32 register *******************/
-#define BKP_DR32_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR33 register *******************/
-#define BKP_DR33_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR34 register *******************/
-#define BKP_DR34_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR35 register *******************/
-#define BKP_DR35_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR36 register *******************/
-#define BKP_DR36_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR37 register *******************/
-#define BKP_DR37_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR38 register *******************/
-#define BKP_DR38_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR39 register *******************/
-#define BKP_DR39_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR40 register *******************/
-#define BKP_DR40_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR41 register *******************/
-#define BKP_DR41_D ((u16)0xFFFF) /* Backup data */
-
-
-/******************* Bit definition for BKP_DR42 register *******************/
-#define BKP_DR42_D ((u16)0xFFFF) /* Backup data */
-
-
-/****************** Bit definition for BKP_RTCCR register *******************/
-#define BKP_RTCCR_CAL ((u16)0x007F) /* Calibration value */
-#define BKP_RTCCR_CCO ((u16)0x0080) /* Calibration Clock Output */
-#define BKP_RTCCR_ASOE ((u16)0x0100) /* Alarm or Second Output Enable */
-#define BKP_RTCCR_ASOS ((u16)0x0200) /* Alarm or Second Output Selection */
-
-
-/******************** Bit definition for BKP_CR register ********************/
-#define BKP_CR_TPE ((u8)0x01) /* TAMPER pin enable */
-#define BKP_CR_TPAL ((u8)0x02) /* TAMPER pin active level */
-
-
-/******************* Bit definition for BKP_CSR register ********************/
-#define BKP_CSR_CTE ((u16)0x0001) /* Clear Tamper event */
-#define BKP_CSR_CTI ((u16)0x0002) /* Clear Tamper Interrupt */
-#define BKP_CSR_TPIE ((u16)0x0004) /* TAMPER Pin interrupt enable */
-#define BKP_CSR_TEF ((u16)0x0100) /* Tamper Event Flag */
-#define BKP_CSR_TIF ((u16)0x0200) /* Tamper Interrupt Flag */
-
-
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-
-
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((u32)0x00000001) /* Internal High Speed clock enable */
-#define RCC_CR_HSIRDY ((u32)0x00000002) /* Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM ((u32)0x000000F8) /* Internal High Speed clock trimming */
-#define RCC_CR_HSICAL ((u32)0x0000FF00) /* Internal High Speed clock Calibration */
-#define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */
-#define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((u32)0x00040000) /* External High Speed clock Bypass */
-#define RCC_CR_CSSON ((u32)0x00080000) /* Clock Security System enable */
-#define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */
-#define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */
-
-
-/******************* Bit definition for RCC_CFGR register *******************/
-#define RCC_CFGR_SW ((u32)0x00000003) /* SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((u32)0x00000001) /* Bit 0 */
-#define RCC_CFGR_SW_1 ((u32)0x00000002) /* Bit 1 */
-
-/* SW configuration */
-#define RCC_CFGR_SW_HSI ((u32)0x00000000) /* HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((u32)0x00000001) /* HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */
-
-#define RCC_CFGR_SWS ((u32)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((u32)0x00000004) /* Bit 0 */
-#define RCC_CFGR_SWS_1 ((u32)0x00000008) /* Bit 1 */
-
-/* SWS configuration */
-#define RCC_CFGR_SWS_HSI ((u32)0x00000000) /* HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */
-
-#define RCC_CFGR_HPRE ((u32)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((u32)0x00000010) /* Bit 0 */
-#define RCC_CFGR_HPRE_1 ((u32)0x00000020) /* Bit 1 */
-#define RCC_CFGR_HPRE_2 ((u32)0x00000040) /* Bit 2 */
-#define RCC_CFGR_HPRE_3 ((u32)0x00000080) /* Bit 3 */
-
-/* HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1 ((u32)0x00000000) /* SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((u32)0x00000080) /* SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((u32)0x00000090) /* SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((u32)0x000000A0) /* SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((u32)0x000000B0) /* SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((u32)0x000000C0) /* SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((u32)0x000000D0) /* SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((u32)0x000000E0) /* SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((u32)0x000000F0) /* SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1 ((u32)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((u32)0x00000100) /* Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((u32)0x00000200) /* Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((u32)0x00000400) /* Bit 2 */
-
-/* PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1 ((u32)0x00000000) /* HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((u32)0x00000500) /* HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((u32)0x00000600) /* HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((u32)0x00000700) /* HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2 ((u32)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((u32)0x00000800) /* Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((u32)0x00001000) /* Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((u32)0x00002000) /* Bit 2 */
-
-/* PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1 ((u32)0x00000000) /* HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((u32)0x00002000) /* HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((u32)0x00002800) /* HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((u32)0x00003000) /* HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((u32)0x00003800) /* HCLK divided by 16 */
-
-#define RCC_CFGR_ADCPRE ((u32)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
-#define RCC_CFGR_ADCPRE_0 ((u32)0x00004000) /* Bit 0 */
-#define RCC_CFGR_ADCPRE_1 ((u32)0x00008000) /* Bit 1 */
-
-/* ADCPPRE configuration */
-#define RCC_CFGR_ADCPRE_DIV2 ((u32)0x00000000) /* PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((u32)0x00004000) /* PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((u32)0x00008000) /* PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((u32)0x0000C000) /* PCLK2 divided by 8 */
-
-#define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */
-#define RCC_CFGR_PLLXTPRE ((u32)0x00020000) /* HSE divider for PLL entry */
-
-#define RCC_CFGR_PLLMULL ((u32)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0 ((u32)0x00040000) /* Bit 0 */
-#define RCC_CFGR_PLLMULL_1 ((u32)0x00080000) /* Bit 1 */
-#define RCC_CFGR_PLLMULL_2 ((u32)0x00100000) /* Bit 2 */
-#define RCC_CFGR_PLLMULL_3 ((u32)0x00200000) /* Bit 3 */
-
-/* PLLMUL configuration */
-#define RCC_CFGR_PLLMULL2 ((u32)0x00000000) /* PLL input clock*2 */
-#define RCC_CFGR_PLLMULL3 ((u32)0x00040000) /* PLL input clock*3 */
-#define RCC_CFGR_PLLMULL4 ((u32)0x00080000) /* PLL input clock*4 */
-#define RCC_CFGR_PLLMULL5 ((u32)0x000C0000) /* PLL input clock*5 */
-#define RCC_CFGR_PLLMULL6 ((u32)0x00100000) /* PLL input clock*6 */
-#define RCC_CFGR_PLLMULL7 ((u32)0x00140000) /* PLL input clock*7 */
-#define RCC_CFGR_PLLMULL8 ((u32)0x00180000) /* PLL input clock*8 */
-#define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */
-#define RCC_CFGR_PLLMULL10 ((u32)0x00200000) /* PLL input clock10 */
-#define RCC_CFGR_PLLMULL11 ((u32)0x00240000) /* PLL input clock*11 */
-#define RCC_CFGR_PLLMULL12 ((u32)0x00280000) /* PLL input clock*12 */
-#define RCC_CFGR_PLLMULL13 ((u32)0x002C0000) /* PLL input clock*13 */
-#define RCC_CFGR_PLLMULL14 ((u32)0x00300000) /* PLL input clock*14 */
-#define RCC_CFGR_PLLMULL15 ((u32)0x00340000) /* PLL input clock*15 */
-#define RCC_CFGR_PLLMULL16 ((u32)0x00380000) /* PLL input clock*16 */
-
-#define RCC_CFGR_USBPRE ((u32)0x00400000) /* USB prescaler */
-
-#define RCC_CFGR_MCO ((u32)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCO_0 ((u32)0x01000000) /* Bit 0 */
-#define RCC_CFGR_MCO_1 ((u32)0x02000000) /* Bit 1 */
-#define RCC_CFGR_MCO_2 ((u32)0x04000000) /* Bit 2 */
-
-/* MCO configuration */
-#define RCC_CFGR_MCO_NOCLOCK ((u32)0x00000000) /* No clock */
-#define RCC_CFGR_MCO_SYSCLK ((u32)0x04000000) /* System clock selected */
-#define RCC_CFGR_MCO_HSI ((u32)0x05000000) /* Internal 8 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE ((u32)0x06000000) /* External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL ((u32)0x07000000) /* PLL clock divided by 2 selected*/
-
-
-/******************* Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF ((u32)0x00000001) /* LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF ((u32)0x00000002) /* LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF ((u32)0x00000004) /* HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF ((u32)0x00000008) /* HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF ((u32)0x00000010) /* PLL Ready Interrupt flag */
-#define RCC_CIR_CSSF ((u32)0x00000080) /* Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE ((u32)0x00000100) /* LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE ((u32)0x00000200) /* LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE ((u32)0x00000400) /* HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE ((u32)0x00000800) /* HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE ((u32)0x00001000) /* PLL Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC ((u32)0x00010000) /* LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC ((u32)0x00020000) /* LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC ((u32)0x00040000) /* HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC ((u32)0x00080000) /* HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC ((u32)0x00100000) /* PLL Ready Interrupt Clear */
-#define RCC_CIR_CSSC ((u32)0x00800000) /* Clock Security System Interrupt Clear */
-
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_AFIORST ((u16)0x0001) /* Alternate Function I/O reset */
-#define RCC_APB2RSTR_IOPARST ((u16)0x0004) /* I/O port A reset */
-#define RCC_APB2RSTR_IOPBRST ((u16)0x0008) /* IO port B reset */
-#define RCC_APB2RSTR_IOPCRST ((u16)0x0010) /* IO port C reset */
-#define RCC_APB2RSTR_IOPDRST ((u16)0x0020) /* IO port D reset */
-#define RCC_APB2RSTR_IOPERST ((u16)0x0040) /* IO port E reset */
-#define RCC_APB2RSTR_IOPFRST ((u16)0x0080) /* IO port F reset */
-#define RCC_APB2RSTR_IOPGRST ((u16)0x0100) /* IO port G reset */
-#define RCC_APB2RSTR_ADC1RST ((u16)0x0200) /* ADC 1 interface reset */
-#define RCC_APB2RSTR_ADC2RST ((u16)0x0400) /* ADC 2 interface reset */
-#define RCC_APB2RSTR_TIM1RST ((u16)0x0800) /* TIM1 Timer reset */
-#define RCC_APB2RSTR_SPI1RST ((u16)0x1000) /* SPI 1 reset */
-#define RCC_APB2RSTR_TIM8RST ((u16)0x2000) /* TIM8 Timer reset */
-#define RCC_APB2RSTR_USART1RST ((u16)0x4000) /* USART1 reset */
-#define RCC_APB2RSTR_ADC3RST ((u16)0x8000) /* ADC3 interface reset */
-
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((u32)0x00000001) /* Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST ((u32)0x00000002) /* Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST ((u32)0x00000004) /* Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST ((u32)0x00000008) /* Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST ((u32)0x00000010) /* Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST ((u32)0x00000020) /* Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST ((u32)0x00000800) /* Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST ((u32)0x00004000) /* SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST ((u32)0x00008000) /* SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST ((u32)0x00020000) /* USART 2 reset */
-#define RCC_APB1RSTR_USART3RST ((u32)0x00040000) /* RUSART 3 reset */
-#define RCC_APB1RSTR_UART4RST ((u32)0x00080000) /* USART 4 reset */
-#define RCC_APB1RSTR_UART5RST ((u32)0x00100000) /* USART 5 reset */
-#define RCC_APB1RSTR_I2C1RST ((u32)0x00200000) /* I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST ((u32)0x00400000) /* I2C 2 reset */
-#define RCC_APB1RSTR_USBRST ((u32)0x00800000) /* USB reset */
-#define RCC_APB1RSTR_CANRST ((u32)0x02000000) /* CAN reset */
-#define RCC_APB1RSTR_BKPRST ((u32)0x08000000) /* Backup interface reset */
-#define RCC_APB1RSTR_PWRRST ((u32)0x10000000) /* Power interface reset */
-#define RCC_APB1RSTR_DACRST ((u32)0x20000000) /* DAC interface reset */
-
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN ((u16)0x0001) /* DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN ((u16)0x0002) /* DMA2 clock enable */
-#define RCC_AHBENR_SRAMEN ((u16)0x0004) /* SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN ((u16)0x0010) /* FLITF clock enable */
-#define RCC_AHBENR_CRCEN ((u16)0x0040) /* CRC clock enable */
-#define RCC_AHBENR_FSMCEN ((u16)0x0100) /* FSMC clock enable */
-#define RCC_AHBENR_SDIOEN ((u16)0x0400) /* SDIO clock enable */
-
-
-/****************** Bit definition for RCC_APB2ENR register *****************/
-#define RCC_APB2ENR_AFIOEN ((u16)0x0001) /* Alternate Function I/O clock enable */
-#define RCC_APB2ENR_IOPAEN ((u16)0x0004) /* I/O port A clock enable */
-#define RCC_APB2ENR_IOPBEN ((u16)0x0008) /* I/O port B clock enable */
-#define RCC_APB2ENR_IOPCEN ((u16)0x0010) /* I/O port C clock enable */
-#define RCC_APB2ENR_IOPDEN ((u16)0x0020) /* I/O port D clock enable */
-#define RCC_APB2ENR_IOPEEN ((u16)0x0040) /* I/O port E clock enable */
-#define RCC_APB2ENR_IOPFEN ((u16)0x0080) /* I/O port F clock enable */
-#define RCC_APB2ENR_IOPGEN ((u16)0x0100) /* I/O port G clock enable */
-#define RCC_APB2ENR_ADC1EN ((u16)0x0200) /* ADC 1 interface clock enable */
-#define RCC_APB2ENR_ADC2EN ((u16)0x0400) /* ADC 2 interface clock enable */
-#define RCC_APB2ENR_TIM1EN ((u16)0x0800) /* TIM1 Timer clock enable */
-#define RCC_APB2ENR_SPI1EN ((u16)0x1000) /* SPI 1 clock enable */
-#define RCC_APB2ENR_TIM8EN ((u16)0x2000) /* TIM8 Timer clock enable */
-#define RCC_APB2ENR_USART1EN ((u16)0x4000) /* USART1 clock enable */
-#define RCC_APB2ENR_ADC3EN ((u16)0x8000) /* DMA1 clock enable */
-
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((u32)0x00000001) /* Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN ((u32)0x00000002) /* Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN ((u32)0x00000004) /* Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN ((u32)0x00000008) /* Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN ((u32)0x00000010) /* Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN ((u32)0x00000020) /* Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN ((u32)0x00000800) /* Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((u32)0x00004000) /* SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN ((u32)0x00008000) /* SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN ((u32)0x00020000) /* USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN ((u32)0x00040000) /* USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN ((u32)0x00080000) /* USART 4 clock enable */
-#define RCC_APB1ENR_UART5EN ((u32)0x00100000) /* USART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN ((u32)0x00200000) /* I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((u32)0x00400000) /* I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN ((u32)0x00800000) /* USB clock enable */
-#define RCC_APB1ENR_CANEN ((u32)0x02000000) /* CAN clock enable */
-#define RCC_APB1ENR_BKPEN ((u32)0x08000000) /* Backup interface clock enable */
-#define RCC_APB1ENR_PWREN ((u32)0x10000000) /* Power interface clock enable */
-#define RCC_APB1ENR_DACEN ((u32)0x20000000) /* DAC interface clock enable */
-
-
-/******************* Bit definition for RCC_BDCR register *******************/
-#define RCC_BDCR_LSEON ((u32)0x00000001) /* External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY ((u32)0x00000002) /* External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP ((u32)0x00000004) /* External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_RTCSEL ((u32)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0 ((u32)0x00000100) /* Bit 0 */
-#define RCC_BDCR_RTCSEL_1 ((u32)0x00000200) /* Bit 1 */
-/* RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((u32)0x00000000) /* No clock */
-#define RCC_BDCR_RTCSEL_LSE ((u32)0x00000100) /* LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((u32)0x00000200) /* LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((u32)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */
-
-#define RCC_BDCR_RTCEN ((u32)0x00008000) /* RTC clock enable */
-#define RCC_BDCR_BDRST ((u32)0x00010000) /* Backup domain software reset */
-
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION ((u32)0x00000001) /* Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((u32)0x00000002) /* Internal Low Speed oscillator Ready */
-#define RCC_CSR_RMVF ((u32)0x01000000) /* Remove reset flag */
-#define RCC_CSR_PINRSTF ((u32)0x04000000) /* PIN reset flag */
-#define RCC_CSR_PORRSTF ((u32)0x08000000) /* POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((u32)0x10000000) /* Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((u32)0x20000000) /* Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((u32)0x40000000) /* Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((u32)0x80000000) /* Low-Power reset flag */
-
-
-
-/******************************************************************************/
-/* */
-/* General Purpose and Alternate Function IO */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for GPIO_CRL register *******************/
-#define GPIO_CRL_MODE ((u32)0x33333333) /* Port x mode bits */
-
-#define GPIO_CRL_MODE0 ((u32)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define GPIO_CRL_MODE0_0 ((u32)0x00000001) /* Bit 0 */
-#define GPIO_CRL_MODE0_1 ((u32)0x00000002) /* Bit 1 */
-
-#define GPIO_CRL_MODE1 ((u32)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define GPIO_CRL_MODE1_0 ((u32)0x00000010) /* Bit 0 */
-#define GPIO_CRL_MODE1_1 ((u32)0x00000020) /* Bit 1 */
-
-#define GPIO_CRL_MODE2 ((u32)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define GPIO_CRL_MODE2_0 ((u32)0x00000100) /* Bit 0 */
-#define GPIO_CRL_MODE2_1 ((u32)0x00000200) /* Bit 1 */
-
-#define GPIO_CRL_MODE3 ((u32)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define GPIO_CRL_MODE3_0 ((u32)0x00001000) /* Bit 0 */
-#define GPIO_CRL_MODE3_1 ((u32)0x00002000) /* Bit 1 */
-
-#define GPIO_CRL_MODE4 ((u32)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define GPIO_CRL_MODE4_0 ((u32)0x00010000) /* Bit 0 */
-#define GPIO_CRL_MODE4_1 ((u32)0x00020000) /* Bit 1 */
-
-#define GPIO_CRL_MODE5 ((u32)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define GPIO_CRL_MODE5_0 ((u32)0x00100000) /* Bit 0 */
-#define GPIO_CRL_MODE5_1 ((u32)0x00200000) /* Bit 1 */
-
-#define GPIO_CRL_MODE6 ((u32)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define GPIO_CRL_MODE6_0 ((u32)0x01000000) /* Bit 0 */
-#define GPIO_CRL_MODE6_1 ((u32)0x02000000) /* Bit 1 */
-
-#define GPIO_CRL_MODE7 ((u32)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define GPIO_CRL_MODE7_0 ((u32)0x10000000) /* Bit 0 */
-#define GPIO_CRL_MODE7_1 ((u32)0x20000000) /* Bit 1 */
-
-
-#define GPIO_CRL_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */
-
-#define GPIO_CRL_CNF0 ((u32)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define GPIO_CRL_CNF0_0 ((u32)0x00000004) /* Bit 0 */
-#define GPIO_CRL_CNF0_1 ((u32)0x00000008) /* Bit 1 */
-
-#define GPIO_CRL_CNF1 ((u32)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define GPIO_CRL_CNF1_0 ((u32)0x00000040) /* Bit 0 */
-#define GPIO_CRL_CNF1_1 ((u32)0x00000080) /* Bit 1 */
-
-#define GPIO_CRL_CNF2 ((u32)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define GPIO_CRL_CNF2_0 ((u32)0x00000400) /* Bit 0 */
-#define GPIO_CRL_CNF2_1 ((u32)0x00000800) /* Bit 1 */
-
-#define GPIO_CRL_CNF3 ((u32)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define GPIO_CRL_CNF3_0 ((u32)0x00004000) /* Bit 0 */
-#define GPIO_CRL_CNF3_1 ((u32)0x00008000) /* Bit 1 */
-
-#define GPIO_CRL_CNF4 ((u32)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define GPIO_CRL_CNF4_0 ((u32)0x00040000) /* Bit 0 */
-#define GPIO_CRL_CNF4_1 ((u32)0x00080000) /* Bit 1 */
-
-#define GPIO_CRL_CNF5 ((u32)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define GPIO_CRL_CNF5_0 ((u32)0x00400000) /* Bit 0 */
-#define GPIO_CRL_CNF5_1 ((u32)0x00800000) /* Bit 1 */
-
-#define GPIO_CRL_CNF6 ((u32)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define GPIO_CRL_CNF6_0 ((u32)0x04000000) /* Bit 0 */
-#define GPIO_CRL_CNF6_1 ((u32)0x08000000) /* Bit 1 */
-
-#define GPIO_CRL_CNF7 ((u32)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define GPIO_CRL_CNF7_0 ((u32)0x40000000) /* Bit 0 */
-#define GPIO_CRL_CNF7_1 ((u32)0x80000000) /* Bit 1 */
-
-
-/******************* Bit definition for GPIO_CRH register *******************/
-#define GPIO_CRH_MODE ((u32)0x33333333) /* Port x mode bits */
-
-#define GPIO_CRH_MODE8 ((u32)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define GPIO_CRH_MODE8_0 ((u32)0x00000001) /* Bit 0 */
-#define GPIO_CRH_MODE8_1 ((u32)0x00000002) /* Bit 1 */
-
-#define GPIO_CRH_MODE9 ((u32)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define GPIO_CRH_MODE9_0 ((u32)0x00000010) /* Bit 0 */
-#define GPIO_CRH_MODE9_1 ((u32)0x00000020) /* Bit 1 */
-
-#define GPIO_CRH_MODE10 ((u32)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define GPIO_CRH_MODE10_0 ((u32)0x00000100) /* Bit 0 */
-#define GPIO_CRH_MODE10_1 ((u32)0x00000200) /* Bit 1 */
-
-#define GPIO_CRH_MODE11 ((u32)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define GPIO_CRH_MODE11_0 ((u32)0x00001000) /* Bit 0 */
-#define GPIO_CRH_MODE11_1 ((u32)0x00002000) /* Bit 1 */
-
-#define GPIO_CRH_MODE12 ((u32)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define GPIO_CRH_MODE12_0 ((u32)0x00010000) /* Bit 0 */
-#define GPIO_CRH_MODE12_1 ((u32)0x00020000) /* Bit 1 */
-
-#define GPIO_CRH_MODE13 ((u32)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define GPIO_CRH_MODE13_0 ((u32)0x00100000) /* Bit 0 */
-#define GPIO_CRH_MODE13_1 ((u32)0x00200000) /* Bit 1 */
-
-#define GPIO_CRH_MODE14 ((u32)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define GPIO_CRH_MODE14_0 ((u32)0x01000000) /* Bit 0 */
-#define GPIO_CRH_MODE14_1 ((u32)0x02000000) /* Bit 1 */
-
-#define GPIO_CRH_MODE15 ((u32)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define GPIO_CRH_MODE15_0 ((u32)0x10000000) /* Bit 0 */
-#define GPIO_CRH_MODE15_1 ((u32)0x20000000) /* Bit 1 */
-
-
-#define GPIO_CRH_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */
-
-#define GPIO_CRH_CNF8 ((u32)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define GPIO_CRH_CNF8_0 ((u32)0x00000004) /* Bit 0 */
-#define GPIO_CRH_CNF8_1 ((u32)0x00000008) /* Bit 1 */
-
-#define GPIO_CRH_CNF9 ((u32)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define GPIO_CRH_CNF9_0 ((u32)0x00000040) /* Bit 0 */
-#define GPIO_CRH_CNF9_1 ((u32)0x00000080) /* Bit 1 */
-
-#define GPIO_CRH_CNF10 ((u32)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define GPIO_CRH_CNF10_0 ((u32)0x00000400) /* Bit 0 */
-#define GPIO_CRH_CNF10_1 ((u32)0x00000800) /* Bit 1 */
-
-#define GPIO_CRH_CNF11 ((u32)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define GPIO_CRH_CNF11_0 ((u32)0x00004000) /* Bit 0 */
-#define GPIO_CRH_CNF11_1 ((u32)0x00008000) /* Bit 1 */
-
-#define GPIO_CRH_CNF12 ((u32)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define GPIO_CRH_CNF12_0 ((u32)0x00040000) /* Bit 0 */
-#define GPIO_CRH_CNF12_1 ((u32)0x00080000) /* Bit 1 */
-
-#define GPIO_CRH_CNF13 ((u32)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define GPIO_CRH_CNF13_0 ((u32)0x00400000) /* Bit 0 */
-#define GPIO_CRH_CNF13_1 ((u32)0x00800000) /* Bit 1 */
-
-#define GPIO_CRH_CNF14 ((u32)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define GPIO_CRH_CNF14_0 ((u32)0x04000000) /* Bit 0 */
-#define GPIO_CRH_CNF14_1 ((u32)0x08000000) /* Bit 1 */
-
-#define GPIO_CRH_CNF15 ((u32)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define GPIO_CRH_CNF15_0 ((u32)0x40000000) /* Bit 0 */
-#define GPIO_CRH_CNF15_1 ((u32)0x80000000) /* Bit 1 */
-
-
-/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_IDR0 ((u16)0x0001) /* Port input data, bit 0 */
-#define GPIO_IDR_IDR1 ((u16)0x0002) /* Port input data, bit 1 */
-#define GPIO_IDR_IDR2 ((u16)0x0004) /* Port input data, bit 2 */
-#define GPIO_IDR_IDR3 ((u16)0x0008) /* Port input data, bit 3 */
-#define GPIO_IDR_IDR4 ((u16)0x0010) /* Port input data, bit 4 */
-#define GPIO_IDR_IDR5 ((u16)0x0020) /* Port input data, bit 5 */
-#define GPIO_IDR_IDR6 ((u16)0x0040) /* Port input data, bit 6 */
-#define GPIO_IDR_IDR7 ((u16)0x0080) /* Port input data, bit 7 */
-#define GPIO_IDR_IDR8 ((u16)0x0100) /* Port input data, bit 8 */
-#define GPIO_IDR_IDR9 ((u16)0x0200) /* Port input data, bit 9 */
-#define GPIO_IDR_IDR10 ((u16)0x0400) /* Port input data, bit 10 */
-#define GPIO_IDR_IDR11 ((u16)0x0800) /* Port input data, bit 11 */
-#define GPIO_IDR_IDR12 ((u16)0x1000) /* Port input data, bit 12 */
-#define GPIO_IDR_IDR13 ((u16)0x2000) /* Port input data, bit 13 */
-#define GPIO_IDR_IDR14 ((u16)0x4000) /* Port input data, bit 14 */
-#define GPIO_IDR_IDR15 ((u16)0x8000) /* Port input data, bit 15 */
-
-
-/******************* Bit definition for GPIO_ODR register *******************/
-#define GPIO_ODR_ODR0 ((u16)0x0001) /* Port output data, bit 0 */
-#define GPIO_ODR_ODR1 ((u16)0x0002) /* Port output data, bit 1 */
-#define GPIO_ODR_ODR2 ((u16)0x0004) /* Port output data, bit 2 */
-#define GPIO_ODR_ODR3 ((u16)0x0008) /* Port output data, bit 3 */
-#define GPIO_ODR_ODR4 ((u16)0x0010) /* Port output data, bit 4 */
-#define GPIO_ODR_ODR5 ((u16)0x0020) /* Port output data, bit 5 */
-#define GPIO_ODR_ODR6 ((u16)0x0040) /* Port output data, bit 6 */
-#define GPIO_ODR_ODR7 ((u16)0x0080) /* Port output data, bit 7 */
-#define GPIO_ODR_ODR8 ((u16)0x0100) /* Port output data, bit 8 */
-#define GPIO_ODR_ODR9 ((u16)0x0200) /* Port output data, bit 9 */
-#define GPIO_ODR_ODR10 ((u16)0x0400) /* Port output data, bit 10 */
-#define GPIO_ODR_ODR11 ((u16)0x0800) /* Port output data, bit 11 */
-#define GPIO_ODR_ODR12 ((u16)0x1000) /* Port output data, bit 12 */
-#define GPIO_ODR_ODR13 ((u16)0x2000) /* Port output data, bit 13 */
-#define GPIO_ODR_ODR14 ((u16)0x4000) /* Port output data, bit 14 */
-#define GPIO_ODR_ODR15 ((u16)0x8000) /* Port output data, bit 15 */
-
-
-/****************** Bit definition for GPIO_BSRR register *******************/
-#define GPIO_BSRR_BS0 ((u32)0x00000001) /* Port x Set bit 0 */
-#define GPIO_BSRR_BS1 ((u32)0x00000002) /* Port x Set bit 1 */
-#define GPIO_BSRR_BS2 ((u32)0x00000004) /* Port x Set bit 2 */
-#define GPIO_BSRR_BS3 ((u32)0x00000008) /* Port x Set bit 3 */
-#define GPIO_BSRR_BS4 ((u32)0x00000010) /* Port x Set bit 4 */
-#define GPIO_BSRR_BS5 ((u32)0x00000020) /* Port x Set bit 5 */
-#define GPIO_BSRR_BS6 ((u32)0x00000040) /* Port x Set bit 6 */
-#define GPIO_BSRR_BS7 ((u32)0x00000080) /* Port x Set bit 7 */
-#define GPIO_BSRR_BS8 ((u32)0x00000100) /* Port x Set bit 8 */
-#define GPIO_BSRR_BS9 ((u32)0x00000200) /* Port x Set bit 9 */
-#define GPIO_BSRR_BS10 ((u32)0x00000400) /* Port x Set bit 10 */
-#define GPIO_BSRR_BS11 ((u32)0x00000800) /* Port x Set bit 11 */
-#define GPIO_BSRR_BS12 ((u32)0x00001000) /* Port x Set bit 12 */
-#define GPIO_BSRR_BS13 ((u32)0x00002000) /* Port x Set bit 13 */
-#define GPIO_BSRR_BS14 ((u32)0x00004000) /* Port x Set bit 14 */
-#define GPIO_BSRR_BS15 ((u32)0x00008000) /* Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0 ((u32)0x00010000) /* Port x Reset bit 0 */
-#define GPIO_BSRR_BR1 ((u32)0x00020000) /* Port x Reset bit 1 */
-#define GPIO_BSRR_BR2 ((u32)0x00040000) /* Port x Reset bit 2 */
-#define GPIO_BSRR_BR3 ((u32)0x00080000) /* Port x Reset bit 3 */
-#define GPIO_BSRR_BR4 ((u32)0x00100000) /* Port x Reset bit 4 */
-#define GPIO_BSRR_BR5 ((u32)0x00200000) /* Port x Reset bit 5 */
-#define GPIO_BSRR_BR6 ((u32)0x00400000) /* Port x Reset bit 6 */
-#define GPIO_BSRR_BR7 ((u32)0x00800000) /* Port x Reset bit 7 */
-#define GPIO_BSRR_BR8 ((u32)0x01000000) /* Port x Reset bit 8 */
-#define GPIO_BSRR_BR9 ((u32)0x02000000) /* Port x Reset bit 9 */
-#define GPIO_BSRR_BR10 ((u32)0x04000000) /* Port x Reset bit 10 */
-#define GPIO_BSRR_BR11 ((u32)0x08000000) /* Port x Reset bit 11 */
-#define GPIO_BSRR_BR12 ((u32)0x10000000) /* Port x Reset bit 12 */
-#define GPIO_BSRR_BR13 ((u32)0x20000000) /* Port x Reset bit 13 */
-#define GPIO_BSRR_BR14 ((u32)0x40000000) /* Port x Reset bit 14 */
-#define GPIO_BSRR_BR15 ((u32)0x80000000) /* Port x Reset bit 15 */
-
-
-/******************* Bit definition for GPIO_BRR register *******************/
-#define GPIO_BRR_BR0 ((u16)0x0001) /* Port x Reset bit 0 */
-#define GPIO_BRR_BR1 ((u16)0x0002) /* Port x Reset bit 1 */
-#define GPIO_BRR_BR2 ((u16)0x0004) /* Port x Reset bit 2 */
-#define GPIO_BRR_BR3 ((u16)0x0008) /* Port x Reset bit 3 */
-#define GPIO_BRR_BR4 ((u16)0x0010) /* Port x Reset bit 4 */
-#define GPIO_BRR_BR5 ((u16)0x0020) /* Port x Reset bit 5 */
-#define GPIO_BRR_BR6 ((u16)0x0040) /* Port x Reset bit 6 */
-#define GPIO_BRR_BR7 ((u16)0x0080) /* Port x Reset bit 7 */
-#define GPIO_BRR_BR8 ((u16)0x0100) /* Port x Reset bit 8 */
-#define GPIO_BRR_BR9 ((u16)0x0200) /* Port x Reset bit 9 */
-#define GPIO_BRR_BR10 ((u16)0x0400) /* Port x Reset bit 10 */
-#define GPIO_BRR_BR11 ((u16)0x0800) /* Port x Reset bit 11 */
-#define GPIO_BRR_BR12 ((u16)0x1000) /* Port x Reset bit 12 */
-#define GPIO_BRR_BR13 ((u16)0x2000) /* Port x Reset bit 13 */
-#define GPIO_BRR_BR14 ((u16)0x4000) /* Port x Reset bit 14 */
-#define GPIO_BRR_BR15 ((u16)0x8000) /* Port x Reset bit 15 */
-
-
-/****************** Bit definition for GPIO_LCKR register *******************/
-#define GPIO_LCKR_LCK0 ((u32)0x00000001) /* Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1 ((u32)0x00000002) /* Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2 ((u32)0x00000004) /* Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3 ((u32)0x00000008) /* Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4 ((u32)0x00000010) /* Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5 ((u32)0x00000020) /* Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6 ((u32)0x00000040) /* Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7 ((u32)0x00000080) /* Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8 ((u32)0x00000100) /* Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9 ((u32)0x00000200) /* Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10 ((u32)0x00000400) /* Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11 ((u32)0x00000800) /* Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12 ((u32)0x00001000) /* Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13 ((u32)0x00002000) /* Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14 ((u32)0x00004000) /* Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15 ((u32)0x00008000) /* Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK ((u32)0x00010000) /* Lock key */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/****************** Bit definition for AFIO_EVCR register *******************/
-#define AFIO_EVCR_PIN ((u8)0x0F) /* PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0 ((u8)0x01) /* Bit 0 */
-#define AFIO_EVCR_PIN_1 ((u8)0x02) /* Bit 1 */
-#define AFIO_EVCR_PIN_2 ((u8)0x04) /* Bit 2 */
-#define AFIO_EVCR_PIN_3 ((u8)0x08) /* Bit 3 */
-
-/* PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((u8)0x00) /* Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1 ((u8)0x01) /* Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2 ((u8)0x02) /* Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3 ((u8)0x03) /* Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4 ((u8)0x04) /* Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5 ((u8)0x05) /* Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6 ((u8)0x06) /* Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7 ((u8)0x07) /* Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8 ((u8)0x08) /* Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9 ((u8)0x09) /* Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10 ((u8)0x0A) /* Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11 ((u8)0x0B) /* Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12 ((u8)0x0C) /* Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13 ((u8)0x0D) /* Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14 ((u8)0x0E) /* Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15 ((u8)0x0F) /* Pin 15 selected */
-
-#define AFIO_EVCR_PORT ((u8)0x70) /* PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0 ((u8)0x10) /* Bit 0 */
-#define AFIO_EVCR_PORT_1 ((u8)0x20) /* Bit 1 */
-#define AFIO_EVCR_PORT_2 ((u8)0x40) /* Bit 2 */
-
-/* PORT configuration */
-#define AFIO_EVCR_PORT_PA ((u8)0x00) /* Port A selected */
-#define AFIO_EVCR_PORT_PB ((u8)0x10) /* Port B selected */
-#define AFIO_EVCR_PORT_PC ((u8)0x20) /* Port C selected */
-#define AFIO_EVCR_PORT_PD ((u8)0x30) /* Port D selected */
-#define AFIO_EVCR_PORT_PE ((u8)0x40) /* Port E selected */
-
-#define AFIO_EVCR_EVOE ((u8)0x80) /* Event Output Enable */
-
-
-/****************** Bit definition for AFIO_MAPR register *******************/
-#define AFIO_MAPR_SPI1 _REMAP ((u32)0x00000001) /* SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP ((u32)0x00000002) /* I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP ((u32)0x00000004) /* USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP ((u32)0x00000008) /* USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP ((u32)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0 ((u32)0x00000010) /* Bit 0 */
-#define AFIO_MAPR_USART3_REMAP_1 ((u32)0x00000020) /* Bit 1 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((u32)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((u32)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP ((u32)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0 ((u32)0x00000040) /* Bit 0 */
-#define AFIO_MAPR_TIM1_REMAP_1 ((u32)0x00000080) /* Bit 1 */
-
-/* TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((u32)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((u32)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((u32)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP ((u32)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0 ((u32)0x00000100) /* Bit 0 */
-#define AFIO_MAPR_TIM2_REMAP_1 ((u32)0x00000200) /* Bit 1 */
-
-/* TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((u32)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((u32)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((u32)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP ((u32)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0 ((u32)0x00000400) /* Bit 0 */
-#define AFIO_MAPR_TIM3_REMAP_1 ((u32)0x00000800) /* Bit 1 */
-
-/* TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((u32)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((u32)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP ((u32)0x00001000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-
-#define AFIO_MAPR_CAN_REMAP ((u32)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0 ((u32)0x00002000) /* Bit 0 */
-#define AFIO_MAPR_CAN_REMAP_1 ((u32)0x00004000) /* Bit 1 */
-
-/* CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((u32)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2 ((u32)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3 ((u32)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP ((u32)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_MAPR_TIM5CH4_IREMAP ((u32)0x00010000) /* TIM5 Channel4 Internal Remap */
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((u32)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((u32)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((u32)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((u32)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
-
-#define AFIO_MAPR_SWJ_CFG ((u32)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0 ((u32)0x01000000) /* Bit 0 */
-#define AFIO_MAPR_SWJ_CFG_1 ((u32)0x02000000) /* Bit 1 */
-#define AFIO_MAPR_SWJ_CFG_2 ((u32)0x04000000) /* Bit 2 */
-
-/* SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG_RESET ((u32)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((u32)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((u32)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE ((u32)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
-
-
-/***************** Bit definition for AFIO_EXTICR1 register *****************/
-#define AFIO_EXTICR1_EXTI0 ((u16)0x000F) /* EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1 ((u16)0x00F0) /* EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2 ((u16)0x0F00) /* EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3 ((u16)0xF000) /* EXTI 3 configuration */
-
-/* EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((u16)0x0000) /* PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB ((u16)0x0001) /* PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC ((u16)0x0002) /* PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD ((u16)0x0003) /* PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE ((u16)0x0004) /* PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF ((u16)0x0005) /* PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG ((u16)0x0006) /* PG[0] pin */
-
-/* EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((u16)0x0000) /* PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB ((u16)0x0010) /* PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC ((u16)0x0020) /* PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD ((u16)0x0030) /* PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE ((u16)0x0040) /* PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF ((u16)0x0050) /* PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG ((u16)0x0060) /* PG[1] pin */
-
-/* EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((u16)0x0000) /* PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB ((u16)0x0100) /* PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC ((u16)0x0200) /* PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD ((u16)0x0300) /* PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE ((u16)0x0400) /* PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF ((u16)0x0500) /* PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG ((u16)0x0600) /* PG[2] pin */
-
-/* EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((u16)0x0000) /* PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB ((u16)0x1000) /* PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC ((u16)0x2000) /* PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD ((u16)0x3000) /* PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE ((u16)0x4000) /* PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF ((u16)0x5000) /* PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG ((u16)0x6000) /* PG[3] pin */
-
-
-/***************** Bit definition for AFIO_EXTICR2 register *****************/
-#define AFIO_EXTICR2_EXTI4 ((u16)0x000F) /* EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5 ((u16)0x00F0) /* EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6 ((u16)0x0F00) /* EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7 ((u16)0xF000) /* EXTI 7 configuration */
-
-/* EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((u16)0x0000) /* PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB ((u16)0x0001) /* PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC ((u16)0x0002) /* PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD ((u16)0x0003) /* PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE ((u16)0x0004) /* PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF ((u16)0x0005) /* PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG ((u16)0x0006) /* PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((u16)0x0000) /* PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB ((u16)0x0010) /* PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC ((u16)0x0020) /* PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD ((u16)0x0030) /* PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE ((u16)0x0040) /* PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF ((u16)0x0050) /* PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG ((u16)0x0060) /* PG[5] pin */
-
-/* EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((u16)0x0000) /* PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB ((u16)0x0100) /* PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC ((u16)0x0200) /* PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD ((u16)0x0300) /* PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE ((u16)0x0400) /* PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF ((u16)0x0500) /* PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG ((u16)0x0600) /* PG[6] pin */
-
-/* EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((u16)0x0000) /* PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB ((u16)0x1000) /* PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC ((u16)0x2000) /* PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD ((u16)0x3000) /* PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE ((u16)0x4000) /* PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF ((u16)0x5000) /* PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG ((u16)0x6000) /* PG[7] pin */
-
-
-/***************** Bit definition for AFIO_EXTICR3 register *****************/
-#define AFIO_EXTICR3_EXTI8 ((u16)0x000F) /* EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9 ((u16)0x00F0) /* EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10 ((u16)0x0F00) /* EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11 ((u16)0xF000) /* EXTI 11 configuration */
-
-/* EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((u16)0x0000) /* PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB ((u16)0x0001) /* PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC ((u16)0x0002) /* PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD ((u16)0x0003) /* PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE ((u16)0x0004) /* PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF ((u16)0x0005) /* PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG ((u16)0x0006) /* PG[8] pin */
-
-/* EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((u16)0x0000) /* PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB ((u16)0x0010) /* PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC ((u16)0x0020) /* PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD ((u16)0x0030) /* PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE ((u16)0x0040) /* PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF ((u16)0x0050) /* PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG ((u16)0x0060) /* PG[9] pin */
-
-/* EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((u16)0x0000) /* PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB ((u16)0x0100) /* PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC ((u16)0x0200) /* PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD ((u16)0x0300) /* PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE ((u16)0x0400) /* PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF ((u16)0x0500) /* PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG ((u16)0x0600) /* PG[10] pin */
-
-/* EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((u16)0x0000) /* PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB ((u16)0x1000) /* PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC ((u16)0x2000) /* PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD ((u16)0x3000) /* PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE ((u16)0x4000) /* PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF ((u16)0x5000) /* PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG ((u16)0x6000) /* PG[11] pin */
-
-
-/***************** Bit definition for AFIO_EXTICR4 register *****************/
-#define AFIO_EXTICR4_EXTI12 ((u16)0x000F) /* EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13 ((u16)0x00F0) /* EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14 ((u16)0x0F00) /* EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15 ((u16)0xF000) /* EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((u16)0x0000) /* PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB ((u16)0x0001) /* PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC ((u16)0x0002) /* PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD ((u16)0x0003) /* PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE ((u16)0x0004) /* PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF ((u16)0x0005) /* PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG ((u16)0x0006) /* PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((u16)0x0000) /* PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB ((u16)0x0010) /* PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC ((u16)0x0020) /* PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD ((u16)0x0030) /* PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE ((u16)0x0040) /* PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF ((u16)0x0050) /* PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG ((u16)0x0060) /* PG[13] pin */
-
-/* EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((u16)0x0000) /* PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB ((u16)0x0100) /* PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC ((u16)0x0200) /* PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD ((u16)0x0300) /* PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE ((u16)0x0400) /* PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF ((u16)0x0500) /* PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG ((u16)0x0600) /* PG[14] pin */
-
-/* EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((u16)0x0000) /* PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB ((u16)0x1000) /* PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC ((u16)0x2000) /* PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD ((u16)0x3000) /* PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE ((u16)0x4000) /* PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF ((u16)0x5000) /* PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG ((u16)0x6000) /* PG[15] pin */
-
-
-
-/******************************************************************************/
-/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */
-#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */
-#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */
-
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */
-
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */
-
-
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA ((u32)0xFFFFFFFF) /* Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 ((u32)0x00000001) /* bit 0 */
-#define NVIC_ISER_SETENA_1 ((u32)0x00000002) /* bit 1 */
-#define NVIC_ISER_SETENA_2 ((u32)0x00000004) /* bit 2 */
-#define NVIC_ISER_SETENA_3 ((u32)0x00000008) /* bit 3 */
-#define NVIC_ISER_SETENA_4 ((u32)0x00000010) /* bit 4 */
-#define NVIC_ISER_SETENA_5 ((u32)0x00000020) /* bit 5 */
-#define NVIC_ISER_SETENA_6 ((u32)0x00000040) /* bit 6 */
-#define NVIC_ISER_SETENA_7 ((u32)0x00000080) /* bit 7 */
-#define NVIC_ISER_SETENA_8 ((u32)0x00000100) /* bit 8 */
-#define NVIC_ISER_SETENA_9 ((u32)0x00000200) /* bit 9 */
-#define NVIC_ISER_SETENA_10 ((u32)0x00000400) /* bit 10 */
-#define NVIC_ISER_SETENA_11 ((u32)0x00000800) /* bit 11 */
-#define NVIC_ISER_SETENA_12 ((u32)0x00001000) /* bit 12 */
-#define NVIC_ISER_SETENA_13 ((u32)0x00002000) /* bit 13 */
-#define NVIC_ISER_SETENA_14 ((u32)0x00004000) /* bit 14 */
-#define NVIC_ISER_SETENA_15 ((u32)0x00008000) /* bit 15 */
-#define NVIC_ISER_SETENA_16 ((u32)0x00010000) /* bit 16 */
-#define NVIC_ISER_SETENA_17 ((u32)0x00020000) /* bit 17 */
-#define NVIC_ISER_SETENA_18 ((u32)0x00040000) /* bit 18 */
-#define NVIC_ISER_SETENA_19 ((u32)0x00080000) /* bit 19 */
-#define NVIC_ISER_SETENA_20 ((u32)0x00100000) /* bit 20 */
-#define NVIC_ISER_SETENA_21 ((u32)0x00200000) /* bit 21 */
-#define NVIC_ISER_SETENA_22 ((u32)0x00400000) /* bit 22 */
-#define NVIC_ISER_SETENA_23 ((u32)0x00800000) /* bit 23 */
-#define NVIC_ISER_SETENA_24 ((u32)0x01000000) /* bit 24 */
-#define NVIC_ISER_SETENA_25 ((u32)0x02000000) /* bit 25 */
-#define NVIC_ISER_SETENA_26 ((u32)0x04000000) /* bit 26 */
-#define NVIC_ISER_SETENA_27 ((u32)0x08000000) /* bit 27 */
-#define NVIC_ISER_SETENA_28 ((u32)0x10000000) /* bit 28 */
-#define NVIC_ISER_SETENA_29 ((u32)0x20000000) /* bit 29 */
-#define NVIC_ISER_SETENA_30 ((u32)0x40000000) /* bit 30 */
-#define NVIC_ISER_SETENA_31 ((u32)0x80000000) /* bit 31 */
-
-
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA ((u32)0xFFFFFFFF) /* Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 ((u32)0x00000001) /* bit 0 */
-#define NVIC_ICER_CLRENA_1 ((u32)0x00000002) /* bit 1 */
-#define NVIC_ICER_CLRENA_2 ((u32)0x00000004) /* bit 2 */
-#define NVIC_ICER_CLRENA_3 ((u32)0x00000008) /* bit 3 */
-#define NVIC_ICER_CLRENA_4 ((u32)0x00000010) /* bit 4 */
-#define NVIC_ICER_CLRENA_5 ((u32)0x00000020) /* bit 5 */
-#define NVIC_ICER_CLRENA_6 ((u32)0x00000040) /* bit 6 */
-#define NVIC_ICER_CLRENA_7 ((u32)0x00000080) /* bit 7 */
-#define NVIC_ICER_CLRENA_8 ((u32)0x00000100) /* bit 8 */
-#define NVIC_ICER_CLRENA_9 ((u32)0x00000200) /* bit 9 */
-#define NVIC_ICER_CLRENA_10 ((u32)0x00000400) /* bit 10 */
-#define NVIC_ICER_CLRENA_11 ((u32)0x00000800) /* bit 11 */
-#define NVIC_ICER_CLRENA_12 ((u32)0x00001000) /* bit 12 */
-#define NVIC_ICER_CLRENA_13 ((u32)0x00002000) /* bit 13 */
-#define NVIC_ICER_CLRENA_14 ((u32)0x00004000) /* bit 14 */
-#define NVIC_ICER_CLRENA_15 ((u32)0x00008000) /* bit 15 */
-#define NVIC_ICER_CLRENA_16 ((u32)0x00010000) /* bit 16 */
-#define NVIC_ICER_CLRENA_17 ((u32)0x00020000) /* bit 17 */
-#define NVIC_ICER_CLRENA_18 ((u32)0x00040000) /* bit 18 */
-#define NVIC_ICER_CLRENA_19 ((u32)0x00080000) /* bit 19 */
-#define NVIC_ICER_CLRENA_20 ((u32)0x00100000) /* bit 20 */
-#define NVIC_ICER_CLRENA_21 ((u32)0x00200000) /* bit 21 */
-#define NVIC_ICER_CLRENA_22 ((u32)0x00400000) /* bit 22 */
-#define NVIC_ICER_CLRENA_23 ((u32)0x00800000) /* bit 23 */
-#define NVIC_ICER_CLRENA_24 ((u32)0x01000000) /* bit 24 */
-#define NVIC_ICER_CLRENA_25 ((u32)0x02000000) /* bit 25 */
-#define NVIC_ICER_CLRENA_26 ((u32)0x04000000) /* bit 26 */
-#define NVIC_ICER_CLRENA_27 ((u32)0x08000000) /* bit 27 */
-#define NVIC_ICER_CLRENA_28 ((u32)0x10000000) /* bit 28 */
-#define NVIC_ICER_CLRENA_29 ((u32)0x20000000) /* bit 29 */
-#define NVIC_ICER_CLRENA_30 ((u32)0x40000000) /* bit 30 */
-#define NVIC_ICER_CLRENA_31 ((u32)0x80000000) /* bit 31 */
-
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND ((u32)0xFFFFFFFF) /* Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 ((u32)0x00000001) /* bit 0 */
-#define NVIC_ISPR_SETPEND_1 ((u32)0x00000002) /* bit 1 */
-#define NVIC_ISPR_SETPEND_2 ((u32)0x00000004) /* bit 2 */
-#define NVIC_ISPR_SETPEND_3 ((u32)0x00000008) /* bit 3 */
-#define NVIC_ISPR_SETPEND_4 ((u32)0x00000010) /* bit 4 */
-#define NVIC_ISPR_SETPEND_5 ((u32)0x00000020) /* bit 5 */
-#define NVIC_ISPR_SETPEND_6 ((u32)0x00000040) /* bit 6 */
-#define NVIC_ISPR_SETPEND_7 ((u32)0x00000080) /* bit 7 */
-#define NVIC_ISPR_SETPEND_8 ((u32)0x00000100) /* bit 8 */
-#define NVIC_ISPR_SETPEND_9 ((u32)0x00000200) /* bit 9 */
-#define NVIC_ISPR_SETPEND_10 ((u32)0x00000400) /* bit 10 */
-#define NVIC_ISPR_SETPEND_11 ((u32)0x00000800) /* bit 11 */
-#define NVIC_ISPR_SETPEND_12 ((u32)0x00001000) /* bit 12 */
-#define NVIC_ISPR_SETPEND_13 ((u32)0x00002000) /* bit 13 */
-#define NVIC_ISPR_SETPEND_14 ((u32)0x00004000) /* bit 14 */
-#define NVIC_ISPR_SETPEND_15 ((u32)0x00008000) /* bit 15 */
-#define NVIC_ISPR_SETPEND_16 ((u32)0x00010000) /* bit 16 */
-#define NVIC_ISPR_SETPEND_17 ((u32)0x00020000) /* bit 17 */
-#define NVIC_ISPR_SETPEND_18 ((u32)0x00040000) /* bit 18 */
-#define NVIC_ISPR_SETPEND_19 ((u32)0x00080000) /* bit 19 */
-#define NVIC_ISPR_SETPEND_20 ((u32)0x00100000) /* bit 20 */
-#define NVIC_ISPR_SETPEND_21 ((u32)0x00200000) /* bit 21 */
-#define NVIC_ISPR_SETPEND_22 ((u32)0x00400000) /* bit 22 */
-#define NVIC_ISPR_SETPEND_23 ((u32)0x00800000) /* bit 23 */
-#define NVIC_ISPR_SETPEND_24 ((u32)0x01000000) /* bit 24 */
-#define NVIC_ISPR_SETPEND_25 ((u32)0x02000000) /* bit 25 */
-#define NVIC_ISPR_SETPEND_26 ((u32)0x04000000) /* bit 26 */
-#define NVIC_ISPR_SETPEND_27 ((u32)0x08000000) /* bit 27 */
-#define NVIC_ISPR_SETPEND_28 ((u32)0x10000000) /* bit 28 */
-#define NVIC_ISPR_SETPEND_29 ((u32)0x20000000) /* bit 29 */
-#define NVIC_ISPR_SETPEND_30 ((u32)0x40000000) /* bit 30 */
-#define NVIC_ISPR_SETPEND_31 ((u32)0x80000000) /* bit 31 */
-
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND ((u32)0xFFFFFFFF) /* Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 ((u32)0x00000001) /* bit 0 */
-#define NVIC_ICPR_CLRPEND_1 ((u32)0x00000002) /* bit 1 */
-#define NVIC_ICPR_CLRPEND_2 ((u32)0x00000004) /* bit 2 */
-#define NVIC_ICPR_CLRPEND_3 ((u32)0x00000008) /* bit 3 */
-#define NVIC_ICPR_CLRPEND_4 ((u32)0x00000010) /* bit 4 */
-#define NVIC_ICPR_CLRPEND_5 ((u32)0x00000020) /* bit 5 */
-#define NVIC_ICPR_CLRPEND_6 ((u32)0x00000040) /* bit 6 */
-#define NVIC_ICPR_CLRPEND_7 ((u32)0x00000080) /* bit 7 */
-#define NVIC_ICPR_CLRPEND_8 ((u32)0x00000100) /* bit 8 */
-#define NVIC_ICPR_CLRPEND_9 ((u32)0x00000200) /* bit 9 */
-#define NVIC_ICPR_CLRPEND_10 ((u32)0x00000400) /* bit 10 */
-#define NVIC_ICPR_CLRPEND_11 ((u32)0x00000800) /* bit 11 */
-#define NVIC_ICPR_CLRPEND_12 ((u32)0x00001000) /* bit 12 */
-#define NVIC_ICPR_CLRPEND_13 ((u32)0x00002000) /* bit 13 */
-#define NVIC_ICPR_CLRPEND_14 ((u32)0x00004000) /* bit 14 */
-#define NVIC_ICPR_CLRPEND_15 ((u32)0x00008000) /* bit 15 */
-#define NVIC_ICPR_CLRPEND_16 ((u32)0x00010000) /* bit 16 */
-#define NVIC_ICPR_CLRPEND_17 ((u32)0x00020000) /* bit 17 */
-#define NVIC_ICPR_CLRPEND_18 ((u32)0x00040000) /* bit 18 */
-#define NVIC_ICPR_CLRPEND_19 ((u32)0x00080000) /* bit 19 */
-#define NVIC_ICPR_CLRPEND_20 ((u32)0x00100000) /* bit 20 */
-#define NVIC_ICPR_CLRPEND_21 ((u32)0x00200000) /* bit 21 */
-#define NVIC_ICPR_CLRPEND_22 ((u32)0x00400000) /* bit 22 */
-#define NVIC_ICPR_CLRPEND_23 ((u32)0x00800000) /* bit 23 */
-#define NVIC_ICPR_CLRPEND_24 ((u32)0x01000000) /* bit 24 */
-#define NVIC_ICPR_CLRPEND_25 ((u32)0x02000000) /* bit 25 */
-#define NVIC_ICPR_CLRPEND_26 ((u32)0x04000000) /* bit 26 */
-#define NVIC_ICPR_CLRPEND_27 ((u32)0x08000000) /* bit 27 */
-#define NVIC_ICPR_CLRPEND_28 ((u32)0x10000000) /* bit 28 */
-#define NVIC_ICPR_CLRPEND_29 ((u32)0x20000000) /* bit 29 */
-#define NVIC_ICPR_CLRPEND_30 ((u32)0x40000000) /* bit 30 */
-#define NVIC_ICPR_CLRPEND_31 ((u32)0x80000000) /* bit 31 */
-
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE ((u32)0xFFFFFFFF) /* Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 ((u32)0x00000001) /* bit 0 */
-#define NVIC_IABR_ACTIVE_1 ((u32)0x00000002) /* bit 1 */
-#define NVIC_IABR_ACTIVE_2 ((u32)0x00000004) /* bit 2 */
-#define NVIC_IABR_ACTIVE_3 ((u32)0x00000008) /* bit 3 */
-#define NVIC_IABR_ACTIVE_4 ((u32)0x00000010) /* bit 4 */
-#define NVIC_IABR_ACTIVE_5 ((u32)0x00000020) /* bit 5 */
-#define NVIC_IABR_ACTIVE_6 ((u32)0x00000040) /* bit 6 */
-#define NVIC_IABR_ACTIVE_7 ((u32)0x00000080) /* bit 7 */
-#define NVIC_IABR_ACTIVE_8 ((u32)0x00000100) /* bit 8 */
-#define NVIC_IABR_ACTIVE_9 ((u32)0x00000200) /* bit 9 */
-#define NVIC_IABR_ACTIVE_10 ((u32)0x00000400) /* bit 10 */
-#define NVIC_IABR_ACTIVE_11 ((u32)0x00000800) /* bit 11 */
-#define NVIC_IABR_ACTIVE_12 ((u32)0x00001000) /* bit 12 */
-#define NVIC_IABR_ACTIVE_13 ((u32)0x00002000) /* bit 13 */
-#define NVIC_IABR_ACTIVE_14 ((u32)0x00004000) /* bit 14 */
-#define NVIC_IABR_ACTIVE_15 ((u32)0x00008000) /* bit 15 */
-#define NVIC_IABR_ACTIVE_16 ((u32)0x00010000) /* bit 16 */
-#define NVIC_IABR_ACTIVE_17 ((u32)0x00020000) /* bit 17 */
-#define NVIC_IABR_ACTIVE_18 ((u32)0x00040000) /* bit 18 */
-#define NVIC_IABR_ACTIVE_19 ((u32)0x00080000) /* bit 19 */
-#define NVIC_IABR_ACTIVE_20 ((u32)0x00100000) /* bit 20 */
-#define NVIC_IABR_ACTIVE_21 ((u32)0x00200000) /* bit 21 */
-#define NVIC_IABR_ACTIVE_22 ((u32)0x00400000) /* bit 22 */
-#define NVIC_IABR_ACTIVE_23 ((u32)0x00800000) /* bit 23 */
-#define NVIC_IABR_ACTIVE_24 ((u32)0x01000000) /* bit 24 */
-#define NVIC_IABR_ACTIVE_25 ((u32)0x02000000) /* bit 25 */
-#define NVIC_IABR_ACTIVE_26 ((u32)0x04000000) /* bit 26 */
-#define NVIC_IABR_ACTIVE_27 ((u32)0x08000000) /* bit 27 */
-#define NVIC_IABR_ACTIVE_28 ((u32)0x10000000) /* bit 28 */
-#define NVIC_IABR_ACTIVE_29 ((u32)0x20000000) /* bit 29 */
-#define NVIC_IABR_ACTIVE_30 ((u32)0x40000000) /* bit 30 */
-#define NVIC_IABR_ACTIVE_31 ((u32)0x80000000) /* bit 31 */
-
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((u32)0x000000FF) /* Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((u32)0x0000FF00) /* Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((u32)0x00FF0000) /* Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((u32)0xFF000000) /* Priority of interrupt 3 */
-
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((u32)0x000000FF) /* Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((u32)0x0000FF00) /* Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((u32)0x00FF0000) /* Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((u32)0xFF000000) /* Priority of interrupt 7 */
-
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((u32)0x000000FF) /* Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((u32)0x0000FF00) /* Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((u32)0x00FF0000) /* Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((u32)0xFF000000) /* Priority of interrupt 11 */
-
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((u32)0x000000FF) /* Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((u32)0x0000FF00) /* Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((u32)0x00FF0000) /* Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((u32)0xFF000000) /* Priority of interrupt 15 */
-
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((u32)0x000000FF) /* Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((u32)0x0000FF00) /* Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((u32)0x00FF0000) /* Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((u32)0xFF000000) /* Priority of interrupt 19 */
-
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((u32)0x000000FF) /* Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((u32)0x0000FF00) /* Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((u32)0x00FF0000) /* Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((u32)0xFF000000) /* Priority of interrupt 23 */
-
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((u32)0x000000FF) /* Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((u32)0x0000FF00) /* Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((u32)0x00FF0000) /* Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((u32)0xFF000000) /* Priority of interrupt 27 */
-
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((u32)0x000000FF) /* Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((u32)0x0000FF00) /* Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((u32)0x00FF0000) /* Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((u32)0xFF000000) /* Priority of interrupt 31 */
-
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((u32)0x0000000F) /* Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((u32)0x0000FFF0) /* Number of processor within family */
-#define SCB_CPUID_Constant ((u32)0x000F0000) /* Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((u32)0x00F00000) /* Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((u32)0xFF000000) /* Implementer code. ARM is 0x41 */
-
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((u32)0x000001FF) /* Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((u32)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((u32)0x003FF000) /* Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((u32)0x00400000) /* Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((u32)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((u32)0x02000000) /* Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((u32)0x04000000) /* Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((u32)0x08000000) /* Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((u32)0x10000000) /* Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((u32)0x80000000) /* Set pending NMI bit */
-
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((u32)0x1FFFFF80) /* Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((u32)0x20000000) /* Table base in code(0) or RAM(1) */
-
-
-/****************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((u32)0x00000001) /* System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((u32)0x00000002) /* Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((u32)0x00000004) /* Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((u32)0x00000700) /* PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((u32)0x00000100) /* Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((u32)0x00000200) /* Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((u32)0x00000400) /* Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((u32)0x00000000) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((u32)0x00000100) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((u32)0x00000200) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((u32)0x00000300) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((u32)0x00000400) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((u32)0x00000500) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((u8)0x02) /* Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((u8)0x04) /* Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((u8)0x10) /* Wake up from WFE */
-
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((u16)0x0001) /* Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((u16)0x0002) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((u16)0x0008) /* Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((u16)0x0010) /* Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((u16)0x0100) /* Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((u16)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N ((u32)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1 ((u32)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2 ((u32)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3 ((u32)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((u32)0x00000001) /* MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((u32)0x00000002) /* BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((u32)0x00000008) /* UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((u32)0x00000080) /* SVCall is active */
-#define SCB_SHCSR_MONITORACT ((u32)0x00000100) /* Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((u32)0x00000400) /* PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((u32)0x00000800) /* SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((u32)0x00001000) /* Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((u32)0x00002000) /* MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((u32)0x00004000) /* Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((u32)0x00008000) /* SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((u32)0x00010000) /* MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((u32)0x00020000) /* Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((u32)0x00040000) /* UsageFault enable */
-
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/* MFSR */
-#define SCB_CFSR_IACCVIOL ((u32)0x00000001) /* Instruction access violation */
-#define SCB_CFSR_DACCVIOL ((u32)0x00000002) /* Data access violation */
-#define SCB_CFSR_MUNSTKERR ((u32)0x00000008) /* Unstacking error */
-#define SCB_CFSR_MSTKERR ((u32)0x00000010) /* Stacking error */
-#define SCB_CFSR_MMARVALID ((u32)0x00000080) /* Memory Manage Address Register address valid flag */
-/* BFSR */
-#define SCB_CFSR_IBUSERR ((u32)0x00000100) /* Instruction bus error flag */
-#define SCB_CFSR_PRECISERR ((u32)0x00000200) /* Precise data bus error */
-#define SCB_CFSR_IMPRECISERR ((u32)0x00000400) /* Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR ((u32)0x00000800) /* Unstacking error */
-#define SCB_CFSR_STKERR ((u32)0x00001000) /* Stacking error */
-#define SCB_CFSR_BFARVALID ((u32)0x00008000) /* Bus Fault Address Register address valid flag */
-/* UFSR */
-#define SCB_CFSR_UNDEFINSTR ((u32)0x00010000) /* The processor attempt to excecute an undefined instruction */
-#define SCB_CFSR_INVSTATE ((u32)0x00020000) /* Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC ((u32)0x00040000) /* Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP ((u32)0x00080000) /* Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED ((u32)0x01000000) /* Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO ((u32)0x02000000) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((u32)0x00000002) /* Fault occures because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((u32)0x40000000) /* Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((u32)0x80000000) /* Fault related to debug */
-
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((u8)0x01) /* Halt request flag */
-#define SCB_DFSR_BKPT ((u8)0x02) /* BKPT flag */
-#define SCB_DFSR_DWTTRAP ((u8)0x04) /* Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((u8)0x08) /* Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((u8)0x10) /* External debug request flag */
-
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS ((u32)0xFFFFFFFF) /* Mem Manage fault address field */
-
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS ((u32)0xFFFFFFFF) /* Bus fault address field */
-
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF ((u32)0xFFFFFFFF) /* Implementation defined */
-
-
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((u32)0x00000001) /* Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((u32)0x00000002) /* Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((u32)0x00000004) /* Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((u32)0x00000008) /* Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((u32)0x00000010) /* Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((u32)0x00000020) /* Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((u32)0x00000040) /* Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((u32)0x00000080) /* Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((u32)0x00000100) /* Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((u32)0x00000200) /* Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((u32)0x00000400) /* Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((u32)0x00000800) /* Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((u32)0x00001000) /* Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((u32)0x00002000) /* Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((u32)0x00004000) /* Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((u32)0x00008000) /* Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((u32)0x00010000) /* Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((u32)0x00020000) /* Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((u32)0x00040000) /* Interrupt Mask on line 18 */
-
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0 ((u32)0x00000001) /* Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((u32)0x00000002) /* Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((u32)0x00000004) /* Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((u32)0x00000008) /* Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((u32)0x00000010) /* Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((u32)0x00000020) /* Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((u32)0x00000040) /* Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((u32)0x00000080) /* Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((u32)0x00000100) /* Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((u32)0x00000200) /* Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((u32)0x00000400) /* Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((u32)0x00000800) /* Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((u32)0x00001000) /* Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((u32)0x00002000) /* Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((u32)0x00004000) /* Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((u32)0x00008000) /* Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((u32)0x00010000) /* Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((u32)0x00020000) /* Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((u32)0x00040000) /* Event Mask on line 18 */
-
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0 ((u32)0x00000001) /* Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((u32)0x00000002) /* Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((u32)0x00000004) /* Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((u32)0x00000008) /* Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((u32)0x00000010) /* Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((u32)0x00000020) /* Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((u32)0x00000040) /* Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((u32)0x00000080) /* Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((u32)0x00000100) /* Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((u32)0x00000200) /* Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((u32)0x00000400) /* Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((u32)0x00000800) /* Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((u32)0x00001000) /* Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((u32)0x00002000) /* Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((u32)0x00004000) /* Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((u32)0x00008000) /* Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((u32)0x00010000) /* Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((u32)0x00020000) /* Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((u32)0x00040000) /* Rising trigger event configuration bit of line 18 */
-
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((u32)0x00000001) /* Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((u32)0x00000002) /* Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((u32)0x00000004) /* Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((u32)0x00000008) /* Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((u32)0x00000010) /* Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((u32)0x00000020) /* Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((u32)0x00000040) /* Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((u32)0x00000080) /* Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((u32)0x00000100) /* Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((u32)0x00000200) /* Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((u32)0x00000400) /* Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((u32)0x00000800) /* Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((u32)0x00001000) /* Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((u32)0x00002000) /* Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((u32)0x00004000) /* Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((u32)0x00008000) /* Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((u32)0x00010000) /* Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((u32)0x00020000) /* Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((u32)0x00040000) /* Falling trigger event configuration bit of line 18 */
-
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0 ((u32)0x00000001) /* Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((u32)0x00000002) /* Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((u32)0x00000004) /* Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((u32)0x00000008) /* Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((u32)0x00000010) /* Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((u32)0x00000020) /* Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((u32)0x00000040) /* Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((u32)0x00000080) /* Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((u32)0x00000100) /* Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((u32)0x00000200) /* Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((u32)0x00000400) /* Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((u32)0x00000800) /* Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((u32)0x00001000) /* Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((u32)0x00002000) /* Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((u32)0x00004000) /* Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((u32)0x00008000) /* Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((u32)0x00010000) /* Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((u32)0x00020000) /* Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((u32)0x00040000) /* Software Interrupt on line 18 */
-
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0 ((u32)0x00000001) /* Pending bit 0 */
-#define EXTI_PR_PR1 ((u32)0x00000002) /* Pending bit 1 */
-#define EXTI_PR_PR2 ((u32)0x00000004) /* Pending bit 2 */
-#define EXTI_PR_PR3 ((u32)0x00000008) /* Pending bit 3 */
-#define EXTI_PR_PR4 ((u32)0x00000010) /* Pending bit 4 */
-#define EXTI_PR_PR5 ((u32)0x00000020) /* Pending bit 5 */
-#define EXTI_PR_PR6 ((u32)0x00000040) /* Pending bit 6 */
-#define EXTI_PR_PR7 ((u32)0x00000080) /* Pending bit 7 */
-#define EXTI_PR_PR8 ((u32)0x00000100) /* Pending bit 8 */
-#define EXTI_PR_PR9 ((u32)0x00000200) /* Pending bit 9 */
-#define EXTI_PR_PR10 ((u32)0x00000400) /* Pending bit 10 */
-#define EXTI_PR_PR11 ((u32)0x00000800) /* Pending bit 11 */
-#define EXTI_PR_PR12 ((u32)0x00001000) /* Pending bit 12 */
-#define EXTI_PR_PR13 ((u32)0x00002000) /* Pending bit 13 */
-#define EXTI_PR_PR14 ((u32)0x00004000) /* Pending bit 14 */
-#define EXTI_PR_PR15 ((u32)0x00008000) /* Pending bit 15 */
-#define EXTI_PR_PR16 ((u32)0x00010000) /* Pending bit 16 */
-#define EXTI_PR_PR17 ((u32)0x00020000) /* Pending bit 17 */
-#define EXTI_PR_PR18 ((u32)0x00040000) /* Trigger request occurred on the external interrupt line 18 */
-
-
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((u32)0x00000001) /* Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((u32)0x00000010) /* Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((u32)0x00000100) /* Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((u32)0x00001000) /* Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((u32)0x00010000) /* Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((u32)0x00100000) /* Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7 ((u32)0x01000000) /* Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error flag */
-
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((u32)0x00000001) /* Channel 1 Global interrupt clearr */
-#define DMA_IFCR_CTCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((u32)0x00000010) /* Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((u32)0x00000100) /* Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((u32)0x00001000) /* Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((u32)0x00010000) /* Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((u32)0x00100000) /* Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7 ((u32)0x01000000) /* Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error clear */
-
-
-/******************* Bit definition for DMA_CCR1 register *******************/
-#define DMA_CCR1_EN ((u16)0x0001) /* Channel enable*/
-#define DMA_CCR1_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CCR1_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR1_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR1_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR1_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR1_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR1_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR1_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR1_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR1_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR1_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR1_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR1_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR1_PL ((u16)0x3000) /* PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR1_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR1_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR1_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
-
-
-/******************* Bit definition for DMA_CCR2 register *******************/
-#define DMA_CCR2_EN ((u16)0x0001) /* Channel enable */
-#define DMA_CCR2_TCIE ((u16)0x0002) /* ransfer complete interrupt enable */
-#define DMA_CCR2_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR2_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR2_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR2_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR2_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR2_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR2_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR2_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR2_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR2_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR2_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR2_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR2_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR2_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR2_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR2_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
-
-
-/******************* Bit definition for DMA_CCR3 register *******************/
-#define DMA_CCR3_EN ((u16)0x0001) /* Channel enable */
-#define DMA_CCR3_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CCR3_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR3_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR3_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR3_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR3_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR3_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR3_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR3_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR3_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR3_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR3_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR3_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR3_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR3_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR3_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR3_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
-
-
-/******************* Bit definition for DMA_CCR4 register *******************/
-#define DMA_CCR4_EN ((u16)0x0001) /* Channel enable */
-#define DMA_CCR4_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CCR4_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR4_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR4_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR4_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR4_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR4_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR4_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR4_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR4_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR4_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR4_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR4_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR4_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR4_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR4_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR4_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
-
-
-/****************** Bit definition for DMA_CCR5 register *******************/
-#define DMA_CCR5_EN ((u16)0x0001) /* Channel enable */
-#define DMA_CCR5_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CCR5_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR5_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR5_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR5_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR5_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR5_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR5_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR5_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR5_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR5_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR5_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR5_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR5_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR5_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR5_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR5_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */
-
-
-/******************* Bit definition for DMA_CCR6 register *******************/
-#define DMA_CCR6_EN ((u16)0x0001) /* Channel enable */
-#define DMA_CCR6_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CCR6_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR6_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR6_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR6_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR6_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR6_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR6_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR6_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR6_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR6_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR6_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR6_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR6_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR6_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR6_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR6_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
-
-
-/******************* Bit definition for DMA_CCR7 register *******************/
-#define DMA_CCR7_EN ((u16)0x0001) /* Channel enable */
-#define DMA_CCR7_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CCR7_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CCR7_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
-#define DMA_CCR7_DIR ((u16)0x0010) /* Data transfer direction */
-#define DMA_CCR7_CIRC ((u16)0x0020) /* Circular mode */
-#define DMA_CCR7_PINC ((u16)0x0040) /* Peripheral increment mode */
-#define DMA_CCR7_MINC ((u16)0x0080) /* Memory increment mode */
-
-#define DMA_CCR7_PSIZE , ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR7_PSIZE_0 ((u16)0x0100) /* Bit 0 */
-#define DMA_CCR7_PSIZE_1 ((u16)0x0200) /* Bit 1 */
-
-#define DMA_CCR7_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR7_MSIZE_0 ((u16)0x0400) /* Bit 0 */
-#define DMA_CCR7_MSIZE_1 ((u16)0x0800) /* Bit 1 */
-
-#define DMA_CCR7_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CCR7_PL_0 ((u16)0x1000) /* Bit 0 */
-#define DMA_CCR7_PL_1 ((u16)0x2000) /* Bit 1 */
-
-#define DMA_CCR7_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */
-
-
-/****************** Bit definition for DMA_CNDTR1 register ******************/
-#define DMA_CNDTR1_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CNDTR2 register ******************/
-#define DMA_CNDTR2_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CNDTR3 register ******************/
-#define DMA_CNDTR3_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CNDTR4 register ******************/
-#define DMA_CNDTR4_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CNDTR5 register ******************/
-#define DMA_CNDTR5_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CNDTR6 register ******************/
-#define DMA_CNDTR6_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CNDTR7 register ******************/
-#define DMA_CNDTR7_NDT ((u16)0xFFFF) /* Number of data to Transfer */
-
-
-/****************** Bit definition for DMA_CPAR1 register *******************/
-#define DMA_CPAR1_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR2 register *******************/
-#define DMA_CPAR2_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR3 register *******************/
-#define DMA_CPAR3_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR4 register *******************/
-#define DMA_CPAR4_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR5 register *******************/
-#define DMA_CPAR5_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR6 register *******************/
-#define DMA_CPAR6_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CPAR7 register *******************/
-#define DMA_CPAR7_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
-
-
-/****************** Bit definition for DMA_CMAR1 register *******************/
-#define DMA_CMAR1_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR2 register *******************/
-#define DMA_CMAR2_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR3 register *******************/
-#define DMA_CMAR3_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR4 register *******************/
-#define DMA_CMAR4_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR5 register *******************/
-#define DMA_CMAR5_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR6 register *******************/
-#define DMA_CMAR6_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-/****************** Bit definition for DMA_CMAR7 register *******************/
-#define DMA_CMAR7_MA ((u32)0xFFFFFFFF) /* Memory Address */
-
-
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD ((u8)0x01) /* Analog watchdog flag */
-#define ADC_SR_EOC ((u8)0x02) /* End of conversion */
-#define ADC_SR_JEOC ((u8)0x04) /* Injected channel end of conversion */
-#define ADC_SR_JSTRT ((u8)0x08) /* Injected channel Start flag */
-#define ADC_SR_STRT ((u8)0x10) /* Regular channel Start flag */
-
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH ((u32)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_CR1_AWDCH_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_CR1_AWDCH_2 ((u32)0x00000004) /* Bit 2 */
-#define ADC_CR1_AWDCH_3 ((u32)0x00000008) /* Bit 3 */
-#define ADC_CR1_AWDCH_4 ((u32)0x00000010) /* Bit 4 */
-
-#define ADC_CR1_EOCIE ((u32)0x00000020) /* Interrupt enable for EOC */
-#define ADC_CR1_AWDIE ((u32)0x00000040) /* AAnalog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE ((u32)0x00000080) /* Interrupt enable for injected channels */
-#define ADC_CR1_SCAN ((u32)0x00000100) /* Scan mode */
-#define ADC_CR1_AWDSGL ((u32)0x00000200) /* Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO ((u32)0x00000400) /* Automatic injected group conversion */
-#define ADC_CR1_DISCEN ((u32)0x00000800) /* Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN ((u32)0x00001000) /* Discontinuous mode on injected channels */
-
-#define ADC_CR1_DISCNUM ((u32)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0 ((u32)0x00002000) /* Bit 0 */
-#define ADC_CR1_DISCNUM_1 ((u32)0x00004000) /* Bit 1 */
-#define ADC_CR1_DISCNUM_2 ((u32)0x00008000) /* Bit 2 */
-
-#define ADC_CR1_DUALMOD ((u32)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
-#define ADC_CR1_DUALMOD_0 ((u32)0x00010000) /* Bit 0 */
-#define ADC_CR1_DUALMOD_1 ((u32)0x00020000) /* Bit 1 */
-#define ADC_CR1_DUALMOD_2 ((u32)0x00040000) /* Bit 2 */
-#define ADC_CR1_DUALMOD_3 ((u32)0x00080000) /* Bit 3 */
-
-#define ADC_CR1_JAWDEN ((u32)0x00400000) /* Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN ((u32)0x00800000) /* Analog watchdog enable on regular channels */
-
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON ((u32)0x00000001) /* A/D Converter ON / OFF */
-#define ADC_CR2_CONT ((u32)0x00000002) /* Continuous Conversion */
-#define ADC_CR2_CAL ((u32)0x00000004) /* A/D Calibration */
-#define ADC_CR2_RSTCAL ((u32)0x00000008) /* Reset Calibration */
-#define ADC_CR2_DMA ((u32)0x00000100) /* Direct Memory access mode */
-#define ADC_CR2_ALIGN ((u32)0x00000800) /* Data Alignment */
-
-#define ADC_CR2_JEXTSEL ((u32)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0 ((u32)0x00001000) /* Bit 0 */
-#define ADC_CR2_JEXTSEL_1 ((u32)0x00002000) /* Bit 1 */
-#define ADC_CR2_JEXTSEL_2 ((u32)0x00004000) /* Bit 2 */
-
-#define ADC_CR2_JEXTTRIG ((u32)0x00008000) /* External Trigger Conversion mode for injected channels */
-
-#define ADC_CR2_EXTSEL ((u32)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0 ((u32)0x00020000) /* Bit 0 */
-#define ADC_CR2_EXTSEL_1 ((u32)0x00040000) /* Bit 1 */
-#define ADC_CR2_EXTSEL_2 ((u32)0x00080000) /* Bit 2 */
-
-#define ADC_CR2_EXTTRIG ((u32)0x00100000) /* External Trigger Conversion mode for regular channels */
-#define ADC_CR2_JSWSTART ((u32)0x00200000) /* Start Conversion of injected channels */
-#define ADC_CR2_SWSTART ((u32)0x00400000) /* Start Conversion of regular channels */
-#define ADC_CR2_TSVREFE ((u32)0x00800000) /* Temperature Sensor and VREFINT Enable */
-
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10 ((u32)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR1_SMP10_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_SMPR1_SMP10_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_SMPR1_SMP10_2 ((u32)0x00000004) /* Bit 2 */
-
-#define ADC_SMPR1_SMP11 ((u32)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR1_SMP11_0 ((u32)0x00000008) /* Bit 0 */
-#define ADC_SMPR1_SMP11_1 ((u32)0x00000010) /* Bit 1 */
-#define ADC_SMPR1_SMP11_2 ((u32)0x00000020) /* Bit 2 */
-
-#define ADC_SMPR1_SMP12 ((u32)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR1_SMP12_0 ((u32)0x00000040) /* Bit 0 */
-#define ADC_SMPR1_SMP12_1 ((u32)0x00000080) /* Bit 1 */
-#define ADC_SMPR1_SMP12_2 ((u32)0x00000100) /* Bit 2 */
-
-#define ADC_SMPR1_SMP13 ((u32)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR1_SMP13_0 ((u32)0x00000200) /* Bit 0 */
-#define ADC_SMPR1_SMP13_1 ((u32)0x00000400) /* Bit 1 */
-#define ADC_SMPR1_SMP13_2 ((u32)0x00000800) /* Bit 2 */
-
-#define ADC_SMPR1_SMP14 ((u32)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR1_SMP14_0 ((u32)0x00001000) /* Bit 0 */
-#define ADC_SMPR1_SMP14_1 ((u32)0x00002000) /* Bit 1 */
-#define ADC_SMPR1_SMP14_2 ((u32)0x00004000) /* Bit 2 */
-
-#define ADC_SMPR1_SMP15 ((u32)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMPR1_SMP15_0 ((u32)0x00008000) /* Bit 0 */
-#define ADC_SMPR1_SMP15_1 ((u32)0x00010000) /* Bit 1 */
-#define ADC_SMPR1_SMP15_2 ((u32)0x00020000) /* Bit 2 */
-
-#define ADC_SMPR1_SMP16 ((u32)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR1_SMP16_0 ((u32)0x00040000) /* Bit 0 */
-#define ADC_SMPR1_SMP16_1 ((u32)0x00080000) /* Bit 1 */
-#define ADC_SMPR1_SMP16_2 ((u32)0x00100000) /* Bit 2 */
-
-#define ADC_SMPR1_SMP17 ((u32)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR1_SMP17_0 ((u32)0x00200000) /* Bit 0 */
-#define ADC_SMPR1_SMP17_1 ((u32)0x00400000) /* Bit 1 */
-#define ADC_SMPR1_SMP17_2 ((u32)0x00800000) /* Bit 2 */
-
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0 ((u32)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR2_SMP0_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_SMPR2_SMP0_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_SMPR2_SMP0_2 ((u32)0x00000004) /* Bit 2 */
-
-#define ADC_SMPR2_SMP1 ((u32)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR2_SMP1_0 ((u32)0x00000008) /* Bit 0 */
-#define ADC_SMPR2_SMP1_1 ((u32)0x00000010) /* Bit 1 */
-#define ADC_SMPR2_SMP1_2 ((u32)0x00000020) /* Bit 2 */
-
-#define ADC_SMPR2_SMP2 ((u32)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR2_SMP2_0 ((u32)0x00000040) /* Bit 0 */
-#define ADC_SMPR2_SMP2_1 ((u32)0x00000080) /* Bit 1 */
-#define ADC_SMPR2_SMP2_2 ((u32)0x00000100) /* Bit 2 */
-
-#define ADC_SMPR2_SMP3 ((u32)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR2_SMP3_0 ((u32)0x00000200) /* Bit 0 */
-#define ADC_SMPR2_SMP3_1 ((u32)0x00000400) /* Bit 1 */
-#define ADC_SMPR2_SMP3_2 ((u32)0x00000800) /* Bit 2 */
-
-#define ADC_SMPR2_SMP4 ((u32)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR2_SMP4_0 ((u32)0x00001000) /* Bit 0 */
-#define ADC_SMPR2_SMP4_1 ((u32)0x00002000) /* Bit 1 */
-#define ADC_SMPR2_SMP4_2 ((u32)0x00004000) /* Bit 2 */
-
-#define ADC_SMPR2_SMP5 ((u32)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP5_0 ((u32)0x00008000) /* Bit 0 */
-#define ADC_SMPR2_SMP5_1 ((u32)0x00010000) /* Bit 1 */
-#define ADC_SMPR2_SMP5_2 ((u32)0x00020000) /* Bit 2 */
-
-#define ADC_SMPR2_SMP6 ((u32)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR2_SMP6_0 ((u32)0x00040000) /* Bit 0 */
-#define ADC_SMPR2_SMP6_1 ((u32)0x00080000) /* Bit 1 */
-#define ADC_SMPR2_SMP6_2 ((u32)0x00100000) /* Bit 2 */
-
-#define ADC_SMPR2_SMP7 ((u32)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR2_SMP7_0 ((u32)0x00200000) /* Bit 0 */
-#define ADC_SMPR2_SMP7_1 ((u32)0x00400000) /* Bit 1 */
-#define ADC_SMPR2_SMP7_2 ((u32)0x00800000) /* Bit 2 */
-
-#define ADC_SMPR2_SMP8 ((u32)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR2_SMP8_0 ((u32)0x01000000) /* Bit 0 */
-#define ADC_SMPR2_SMP8_1 ((u32)0x02000000) /* Bit 1 */
-#define ADC_SMPR2_SMP8_2 ((u32)0x04000000) /* Bit 2 */
-
-#define ADC_SMPR2_SMP9 ((u32)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR2_SMP9_0 ((u32)0x08000000) /* Bit 0 */
-#define ADC_SMPR2_SMP9_1 ((u32)0x10000000) /* Bit 1 */
-#define ADC_SMPR2_SMP9_2 ((u32)0x20000000) /* Bit 2 */
-
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((u16)0x0FFF) /* Data offset for injected channel 1 */
-
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((u16)0x0FFF) /* Data offset for injected channel 2 */
-
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((u16)0x0FFF) /* Data offset for injected channel 3 */
-
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((u16)0x0FFF) /* Data offset for injected channel 4 */
-
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((u16)0x0FFF) /* Analog watchdog high threshold */
-
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((u16)0x0FFF) /* Analog watchdog low threshold */
-
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13 ((u32)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR1_SQ13_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_SQR1_SQ13_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_SQR1_SQ13_2 ((u32)0x00000004) /* Bit 2 */
-#define ADC_SQR1_SQ13_3 ((u32)0x00000008) /* Bit 3 */
-#define ADC_SQR1_SQ13_4 ((u32)0x00000010) /* Bit 4 */
-
-#define ADC_SQR1_SQ14 ((u32)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR1_SQ14_0 ((u32)0x00000020) /* Bit 0 */
-#define ADC_SQR1_SQ14_1 ((u32)0x00000040) /* Bit 1 */
-#define ADC_SQR1_SQ14_2 ((u32)0x00000080) /* Bit 2 */
-#define ADC_SQR1_SQ14_3 ((u32)0x00000100) /* Bit 3 */
-#define ADC_SQR1_SQ14_4 ((u32)0x00000200) /* Bit 4 */
-
-#define ADC_SQR1_SQ15 ((u32)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR1_SQ15_0 ((u32)0x00000400) /* Bit 0 */
-#define ADC_SQR1_SQ15_1 ((u32)0x00000800) /* Bit 1 */
-#define ADC_SQR1_SQ15_2 ((u32)0x00001000) /* Bit 2 */
-#define ADC_SQR1_SQ15_3 ((u32)0x00002000) /* Bit 3 */
-#define ADC_SQR1_SQ15_4 ((u32)0x00004000) /* Bit 4 */
-
-#define ADC_SQR1_SQ16 ((u32)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR1_SQ16_0 ((u32)0x00008000) /* Bit 0 */
-#define ADC_SQR1_SQ16_1 ((u32)0x00010000) /* Bit 1 */
-#define ADC_SQR1_SQ16_2 ((u32)0x00020000) /* Bit 2 */
-#define ADC_SQR1_SQ16_3 ((u32)0x00040000) /* Bit 3 */
-#define ADC_SQR1_SQ16_4 ((u32)0x00080000) /* Bit 4 */
-
-#define ADC_SQR1_L ((u32)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0 ((u32)0x00100000) /* Bit 0 */
-#define ADC_SQR1_L_1 ((u32)0x00200000) /* Bit 1 */
-#define ADC_SQR1_L_2 ((u32)0x00400000) /* Bit 2 */
-#define ADC_SQR1_L_3 ((u32)0x00800000) /* Bit 3 */
-
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7 ((u32)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR2_SQ7_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_SQR2_SQ7_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_SQR2_SQ7_2 ((u32)0x00000004) /* Bit 2 */
-#define ADC_SQR2_SQ7_3 ((u32)0x00000008) /* Bit 3 */
-#define ADC_SQR2_SQ7_4 ((u32)0x00000010) /* Bit 4 */
-
-#define ADC_SQR2_SQ8 ((u32)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR2_SQ8_0 ((u32)0x00000020) /* Bit 0 */
-#define ADC_SQR2_SQ8_1 ((u32)0x00000040) /* Bit 1 */
-#define ADC_SQR2_SQ8_2 ((u32)0x00000080) /* Bit 2 */
-#define ADC_SQR2_SQ8_3 ((u32)0x00000100) /* Bit 3 */
-#define ADC_SQR2_SQ8_4 ((u32)0x00000200) /* Bit 4 */
-
-#define ADC_SQR2_SQ9 ((u32)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR2_SQ9_0 ((u32)0x00000400) /* Bit 0 */
-#define ADC_SQR2_SQ9_1 ((u32)0x00000800) /* Bit 1 */
-#define ADC_SQR2_SQ9_2 ((u32)0x00001000) /* Bit 2 */
-#define ADC_SQR2_SQ9_3 ((u32)0x00002000) /* Bit 3 */
-#define ADC_SQR2_SQ9_4 ((u32)0x00004000) /* Bit 4 */
-
-#define ADC_SQR2_SQ10 ((u32)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR2_SQ10_0 ((u32)0x00008000) /* Bit 0 */
-#define ADC_SQR2_SQ10_1 ((u32)0x00010000) /* Bit 1 */
-#define ADC_SQR2_SQ10_2 ((u32)0x00020000) /* Bit 2 */
-#define ADC_SQR2_SQ10_3 ((u32)0x00040000) /* Bit 3 */
-#define ADC_SQR2_SQ10_4 ((u32)0x00080000) /* Bit 4 */
-
-#define ADC_SQR2_SQ11 ((u32)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR2_SQ11_0 ((u32)0x00100000) /* Bit 0 */
-#define ADC_SQR2_SQ11_1 ((u32)0x00200000) /* Bit 1 */
-#define ADC_SQR2_SQ11_2 ((u32)0x00400000) /* Bit 2 */
-#define ADC_SQR2_SQ11_3 ((u32)0x00800000) /* Bit 3 */
-#define ADC_SQR2_SQ11_4 ((u32)0x01000000) /* Bit 4 */
-
-#define ADC_SQR2_SQ12 ((u32)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR2_SQ12_0 ((u32)0x02000000) /* Bit 0 */
-#define ADC_SQR2_SQ12_1 ((u32)0x04000000) /* Bit 1 */
-#define ADC_SQR2_SQ12_2 ((u32)0x08000000) /* Bit 2 */
-#define ADC_SQR2_SQ12_3 ((u32)0x10000000) /* Bit 3 */
-#define ADC_SQR2_SQ12_4 ((u32)0x20000000) /* Bit 4 */
-
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1 ((u32)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR3_SQ1_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_SQR3_SQ1_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_SQR3_SQ1_2 ((u32)0x00000004) /* Bit 2 */
-#define ADC_SQR3_SQ1_3 ((u32)0x00000008) /* Bit 3 */
-#define ADC_SQR3_SQ1_4 ((u32)0x00000010) /* Bit 4 */
-
-#define ADC_SQR3_SQ2 ((u32)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR3_SQ2_0 ((u32)0x00000020) /* Bit 0 */
-#define ADC_SQR3_SQ2_1 ((u32)0x00000040) /* Bit 1 */
-#define ADC_SQR3_SQ2_2 ((u32)0x00000080) /* Bit 2 */
-#define ADC_SQR3_SQ2_3 ((u32)0x00000100) /* Bit 3 */
-#define ADC_SQR3_SQ2_4 ((u32)0x00000200) /* Bit 4 */
-
-#define ADC_SQR3_SQ3 ((u32)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR3_SQ3_0 ((u32)0x00000400) /* Bit 0 */
-#define ADC_SQR3_SQ3_1 ((u32)0x00000800) /* Bit 1 */
-#define ADC_SQR3_SQ3_2 ((u32)0x00001000) /* Bit 2 */
-#define ADC_SQR3_SQ3_3 ((u32)0x00002000) /* Bit 3 */
-#define ADC_SQR3_SQ3_4 ((u32)0x00004000) /* Bit 4 */
-
-#define ADC_SQR3_SQ4 ((u32)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR3_SQ4_0 ((u32)0x00008000) /* Bit 0 */
-#define ADC_SQR3_SQ4_1 ((u32)0x00010000) /* Bit 1 */
-#define ADC_SQR3_SQ4_2 ((u32)0x00020000) /* Bit 2 */
-#define ADC_SQR3_SQ4_3 ((u32)0x00040000) /* Bit 3 */
-#define ADC_SQR3_SQ4_4 ((u32)0x00080000) /* Bit 4 */
-
-#define ADC_SQR3_SQ5 ((u32)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR3_SQ5_0 ((u32)0x00100000) /* Bit 0 */
-#define ADC_SQR3_SQ5_1 ((u32)0x00200000) /* Bit 1 */
-#define ADC_SQR3_SQ5_2 ((u32)0x00400000) /* Bit 2 */
-#define ADC_SQR3_SQ5_3 ((u32)0x00800000) /* Bit 3 */
-#define ADC_SQR3_SQ5_4 ((u32)0x01000000) /* Bit 4 */
-
-#define ADC_SQR3_SQ6 ((u32)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR3_SQ6_0 ((u32)0x02000000) /* Bit 0 */
-#define ADC_SQR3_SQ6_1 ((u32)0x04000000) /* Bit 1 */
-#define ADC_SQR3_SQ6_2 ((u32)0x08000000) /* Bit 2 */
-#define ADC_SQR3_SQ6_3 ((u32)0x10000000) /* Bit 3 */
-#define ADC_SQR3_SQ6_4 ((u32)0x20000000) /* Bit 4 */
-
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1 ((u32)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQR_JSQ1_0 ((u32)0x00000001) /* Bit 0 */
-#define ADC_JSQR_JSQ1_1 ((u32)0x00000002) /* Bit 1 */
-#define ADC_JSQR_JSQ1_2 ((u32)0x00000004) /* Bit 2 */
-#define ADC_JSQR_JSQ1_3 ((u32)0x00000008) /* Bit 3 */
-#define ADC_JSQR_JSQ1_4 ((u32)0x00000010) /* Bit 4 */
-
-#define ADC_JSQR_JSQ2 ((u32)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0 ((u32)0x00000020) /* Bit 0 */
-#define ADC_JSQR_JSQ2_1 ((u32)0x00000040) /* Bit 1 */
-#define ADC_JSQR_JSQ2_2 ((u32)0x00000080) /* Bit 2 */
-#define ADC_JSQR_JSQ2_3 ((u32)0x00000100) /* Bit 3 */
-#define ADC_JSQR_JSQ2_4 ((u32)0x00000200) /* Bit 4 */
-
-#define ADC_JSQR_JSQ3 ((u32)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0 ((u32)0x00000400) /* Bit 0 */
-#define ADC_JSQR_JSQ3_1 ((u32)0x00000800) /* Bit 1 */
-#define ADC_JSQR_JSQ3_2 ((u32)0x00001000) /* Bit 2 */
-#define ADC_JSQR_JSQ3_3 ((u32)0x00002000) /* Bit 3 */
-#define ADC_JSQR_JSQ3_4 ((u32)0x00004000) /* Bit 4 */
-
-#define ADC_JSQR_JSQ4 ((u32)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0 ((u32)0x00008000) /* Bit 0 */
-#define ADC_JSQR_JSQ4_1 ((u32)0x00010000) /* Bit 1 */
-#define ADC_JSQR_JSQ4_2 ((u32)0x00020000) /* Bit 2 */
-#define ADC_JSQR_JSQ4_3 ((u32)0x00040000) /* Bit 3 */
-#define ADC_JSQR_JSQ4_4 ((u32)0x00080000) /* Bit 4 */
-
-#define ADC_JSQR_JL ((u32)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0 ((u32)0x00100000) /* Bit 0 */
-#define ADC_JSQR_JL_1 ((u32)0x00200000) /* Bit 1 */
-
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA ((u16)0xFFFF) /* Injected data */
-
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA ((u16)0xFFFF) /* Injected data */
-
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA ((u16)0xFFFF) /* Injected data */
-
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA ((u16)0xFFFF) /* Injected data */
-
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((u32)0x0000FFFF) /* Regular data */
-#define ADC_DR_ADC2DATA ((u32)0xFFFF0000) /* ADC2 data */
-
-
-
-/******************************************************************************/
-/* */
-/* Digital to Analog Converter */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((u32)0x00000001) /* DAC channel1 enable */
-#define DAC_CR_BOFF1 ((u32)0x00000002) /* DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((u32)0x00000004) /* DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((u32)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((u32)0x00000008) /* Bit 0 */
-#define DAC_CR_TSEL1_1 ((u32)0x00000010) /* Bit 1 */
-#define DAC_CR_TSEL1_2 ((u32)0x00000020) /* Bit 2 */
-
-#define DAC_CR_WAVE1 ((u32)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((u32)0x00000040) /* Bit 0 */
-#define DAC_CR_WAVE1_1 ((u32)0x00000080) /* Bit 1 */
-
-#define DAC_CR_MAMP1 ((u32)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((u32)0x00000100) /* Bit 0 */
-#define DAC_CR_MAMP1_1 ((u32)0x00000200) /* Bit 1 */
-#define DAC_CR_MAMP1_2 ((u32)0x00000400) /* Bit 2 */
-#define DAC_CR_MAMP1_3 ((u32)0x00000800) /* Bit 3 */
-
-#define DAC_CR_DMAEN1 ((u32)0x00001000) /* DAC channel1 DMA enable */
-#define DAC_CR_EN2 ((u32)0x00010000) /* DAC channel2 enable */
-#define DAC_CR_BOFF2 ((u32)0x00020000) /* DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((u32)0x00040000) /* DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((u32)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((u32)0x00080000) /* Bit 0 */
-#define DAC_CR_TSEL2_1 ((u32)0x00100000) /* Bit 1 */
-#define DAC_CR_TSEL2_2 ((u32)0x00200000) /* Bit 2 */
-
-#define DAC_CR_WAVE2 ((u32)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((u32)0x00400000) /* Bit 0 */
-#define DAC_CR_WAVE2_1 ((u32)0x00800000) /* Bit 1 */
-
-#define DAC_CR_MAMP2 ((u32)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((u32)0x01000000) /* Bit 0 */
-#define DAC_CR_MAMP2_1 ((u32)0x02000000) /* Bit 1 */
-#define DAC_CR_MAMP2_2 ((u32)0x04000000) /* Bit 2 */
-#define DAC_CR_MAMP2_3 ((u32)0x08000000) /* Bit 3 */
-
-#define DAC_CR_DMAEN2 ((u32)0x10000000) /* DAC channel2 DMA enabled */
-
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((u8)0x01) /* DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((u8)0x02) /* DAC channel2 software trigger */
-
-
-/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((u16)0x0FFF) /* DAC channel1 12-bit Right aligned data */
-
-
-/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((u16)0xFFF0) /* DAC channel1 12-bit Left aligned data */
-
-
-/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((u8)0xFF) /* DAC channel1 8-bit Right aligned data */
-
-
-/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((u16)0x0FFF) /* DAC channel2 12-bit Right aligned data */
-
-
-/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((u16)0xFFF0) /* DAC channel2 12-bit Left aligned data */
-
-
-/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((u8)0xFF) /* DAC channel2 8-bit Right aligned data */
-
-
-/***************** Bit definition for DAC_DHR12RD register ******************/
-#define DAC_DHR12RD_DACC1DHR ((u32)0x00000FFF) /* DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((u32)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */
-
-
-/***************** Bit definition for DAC_DHR12LD register ******************/
-#define DAC_DHR12LD_DACC1DHR ((u32)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((u32)0xFFF00000) /* DAC channel2 12-bit Left aligned data */
-
-
-/****************** Bit definition for DAC_DHR8RD register ******************/
-#define DAC_DHR8RD_DACC1DHR ((u16)0x00FF) /* DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((u16)0xFF00) /* DAC channel2 8-bit Right aligned data */
-
-
-/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((u16)0x0FFF) /* DAC channel1 data output */
-
-
-/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((u16)0x0FFF) /* DAC channel2 data output */
-
-
-
-/******************************************************************************/
-/* */
-/* TIM */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((u16)0x0001) /* Counter enable */
-#define TIM_CR1_UDIS ((u16)0x0002) /* Update disable */
-#define TIM_CR1_URS ((u16)0x0004) /* Update request source */
-#define TIM_CR1_OPM ((u16)0x0008) /* One pulse mode */
-#define TIM_CR1_DIR ((u16)0x0010) /* Direction */
-
-#define TIM_CR1_CMS ((u16)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((u16)0x0020) /* Bit 0 */
-#define TIM_CR1_CMS_1 ((u16)0x0040) /* Bit 1 */
-
-#define TIM_CR1_ARPE ((u16)0x0080) /* Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((u16)0x0300) /* CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((u16)0x0100) /* Bit 0 */
-#define TIM_CR1_CKD_1 ((u16)0x0200) /* Bit 1 */
-
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((u16)0x0001) /* Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((u16)0x0004) /* Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((u16)0x0008) /* Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((u16)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((u16)0x0010) /* Bit 0 */
-#define TIM_CR2_MMS_1 ((u16)0x0020) /* Bit 1 */
-#define TIM_CR2_MMS_2 ((u16)0x0040) /* Bit 2 */
-
-#define TIM_CR2_TI1S ((u16)0x0080) /* TI1 Selection */
-#define TIM_CR2_OIS1 ((u16)0x0100) /* Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((u16)0x0200) /* Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((u16)0x0400) /* Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((u16)0x0800) /* Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((u16)0x1000) /* Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((u16)0x2000) /* Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((u16)0x4000) /* Output Idle state 4 (OC4 output) */
-
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((u16)0x0007) /* SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((u16)0x0001) /* Bit 0 */
-#define TIM_SMCR_SMS_1 ((u16)0x0002) /* Bit 1 */
-#define TIM_SMCR_SMS_2 ((u16)0x0004) /* Bit 2 */
-
-#define TIM_SMCR_TS ((u16)0x0070) /* TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((u16)0x0010) /* Bit 0 */
-#define TIM_SMCR_TS_1 ((u16)0x0020) /* Bit 1 */
-#define TIM_SMCR_TS_2 ((u16)0x0040) /* Bit 2 */
-
-#define TIM_SMCR_MSM ((u16)0x0080) /* Master/slave mode */
-
-#define TIM_SMCR_ETF ((u16)0x0F00) /* ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((u16)0x0100) /* Bit 0 */
-#define TIM_SMCR_ETF_1 ((u16)0x0200) /* Bit 1 */
-#define TIM_SMCR_ETF_2 ((u16)0x0400) /* Bit 2 */
-#define TIM_SMCR_ETF_3 ((u16)0x0800) /* Bit 3 */
-
-#define TIM_SMCR_ETPS ((u16)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((u16)0x1000) /* Bit 0 */
-#define TIM_SMCR_ETPS_1 ((u16)0x2000) /* Bit 1 */
-
-#define TIM_SMCR_ECE ((u16)0x4000) /* External clock enable */
-#define TIM_SMCR_ETP ((u16)0x8000) /* External trigger polarity */
-
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((u16)0x0001) /* Update interrupt enable */
-#define TIM_DIER_CC1IE ((u16)0x0002) /* Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((u16)0x0004) /* Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((u16)0x0008) /* Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((u16)0x0010) /* Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((u16)0x0020) /* COM interrupt enable */
-#define TIM_DIER_TIE ((u16)0x0040) /* Trigger interrupt enable */
-#define TIM_DIER_BIE ((u16)0x0080) /* Break interrupt enable */
-#define TIM_DIER_UDE ((u16)0x0100) /* Update DMA request enable */
-#define TIM_DIER_CC1DE ((u16)0x0200) /* Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((u16)0x0400) /* Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((u16)0x0800) /* Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((u16)0x1000) /* Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((u16)0x2000) /* COM DMA request enable */
-#define TIM_DIER_TDE ((u16)0x4000) /* Trigger DMA request enable */
-
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((u16)0x0001) /* Update interrupt Flag */
-#define TIM_SR_CC1IF ((u16)0x0002) /* Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((u16)0x0004) /* Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((u16)0x0008) /* Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((u16)0x0010) /* Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((u16)0x0020) /* COM interrupt Flag */
-#define TIM_SR_TIF ((u16)0x0040) /* Trigger interrupt Flag */
-#define TIM_SR_BIF ((u16)0x0080) /* Break interrupt Flag */
-#define TIM_SR_CC1OF ((u16)0x0200) /* Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((u16)0x0400) /* Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((u16)0x0800) /* Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((u16)0x1000) /* Capture/Compare 4 Overcapture Flag */
-
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((u8)0x01) /* Update Generation */
-#define TIM_EGR_CC1G ((u8)0x02) /* Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((u8)0x04) /* Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((u8)0x08) /* Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((u8)0x10) /* Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((u8)0x20) /* Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((u8)0x40) /* Trigger Generation */
-#define TIM_EGR_BG ((u8)0x80) /* Break Generation */
-
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((u16)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((u16)0x0001) /* Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((u16)0x0002) /* Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((u16)0x0004) /* Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((u16)0x0008) /* Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((u16)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((u16)0x0010) /* Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((u16)0x0020) /* Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((u16)0x0040) /* Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((u16)0x0080) /* Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((u16)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((u16)0x0100) /* Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((u16)0x0200) /* Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((u16)0x0400) /* Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((u16)0x0800) /* Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((u16)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((u16)0x1000) /* Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((u16)0x2000) /* Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((u16)0x4000) /* Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((u16)0x8000) /* Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((u16)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((u16)0x0004) /* Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((u16)0x0008) /* Bit 1 */
-
-#define TIM_CCMR1_IC1F ((u16)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((u16)0x0010) /* Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((u16)0x0020) /* Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((u16)0x0040) /* Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((u16)0x0080) /* Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((u16)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((u16)0x0400) /* Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((u16)0x0800) /* Bit 1 */
-
-#define TIM_CCMR1_IC2F ((u16)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((u16)0x1000) /* Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((u16)0x2000) /* Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((u16)0x4000) /* Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((u16)0x8000) /* Bit 3 */
-
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((u16)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((u16)0x0001) /* Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((u16)0x0002) /* Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((u16)0x0004) /* Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((u16)0x0008) /* Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((u16)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((u16)0x0010) /* Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((u16)0x0020) /* Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((u16)0x0040) /* Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((u16)0x0080) /* Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((u16)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((u16)0x0100) /* Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((u16)0x0200) /* Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((u16)0x0400) /* Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((u16)0x0800) /* Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((u16)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((u16)0x1000) /* Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((u16)0x2000) /* Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((u16)0x4000) /* Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((u16)0x8000) /* Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((u16)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((u16)0x0004) /* Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((u16)0x0008) /* Bit 1 */
-
-#define TIM_CCMR2_IC3F ((u16)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((u16)0x0010) /* Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((u16)0x0020) /* Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((u16)0x0040) /* Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((u16)0x0080) /* Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((u16)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((u16)0x0400) /* Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((u16)0x0800) /* Bit 1 */
-
-#define TIM_CCMR2_IC4F ((u16)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((u16)0x1000) /* Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((u16)0x2000) /* Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((u16)0x4000) /* Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((u16)0x8000) /* Bit 3 */
-
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((u16)0x0001) /* Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((u16)0x0002) /* Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((u16)0x0004) /* Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((u16)0x0008) /* Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((u16)0x0010) /* Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((u16)0x0020) /* Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((u16)0x0040) /* Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((u16)0x0080) /* Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((u16)0x0100) /* Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((u16)0x0200) /* Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((u16)0x0400) /* Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((u16)0x0800) /* Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((u16)0x1000) /* Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((u16)0x2000) /* Capture/Compare 4 output Polarity */
-
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((u16)0xFFFF) /* Counter Value */
-
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((u16)0xFFFF) /* Prescaler Value */
-
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((u16)0xFFFF) /* actual auto-reload Value */
-
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((u8)0xFF) /* Repetition Counter Value */
-
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((u16)0xFFFF) /* Capture/Compare 1 Value */
-
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((u16)0xFFFF) /* Capture/Compare 2 Value */
-
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((u16)0xFFFF) /* Capture/Compare 3 Value */
-
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((u16)0xFFFF) /* Capture/Compare 4 Value */
-
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((u16)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((u16)0x0001) /* Bit 0 */
-#define TIM_BDTR_DTG_1 ((u16)0x0002) /* Bit 1 */
-#define TIM_BDTR_DTG_2 ((u16)0x0004) /* Bit 2 */
-#define TIM_BDTR_DTG_3 ((u16)0x0008) /* Bit 3 */
-#define TIM_BDTR_DTG_4 ((u16)0x0010) /* Bit 4 */
-#define TIM_BDTR_DTG_5 ((u16)0x0020) /* Bit 5 */
-#define TIM_BDTR_DTG_6 ((u16)0x0040) /* Bit 6 */
-#define TIM_BDTR_DTG_7 ((u16)0x0080) /* Bit 7 */
-
-#define TIM_BDTR_LOCK ((u16)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((u16)0x0100) /* Bit 0 */
-#define TIM_BDTR_LOCK_1 ((u16)0x0200) /* Bit 1 */
-
-#define TIM_BDTR_OSSI ((u16)0x0400) /* Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((u16)0x0800) /* Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((u16)0x1000) /* Break enable */
-#define TIM_BDTR_BKP ((u16)0x2000) /* Break Polarity */
-#define TIM_BDTR_AOE ((u16)0x4000) /* Automatic Output enable */
-#define TIM_BDTR_MOE ((u16)0x8000) /* Main Output enable */
-
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((u16)0x001F) /* DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((u16)0x0001) /* Bit 0 */
-#define TIM_DCR_DBA_1 ((u16)0x0002) /* Bit 1 */
-#define TIM_DCR_DBA_2 ((u16)0x0004) /* Bit 2 */
-#define TIM_DCR_DBA_3 ((u16)0x0008) /* Bit 3 */
-#define TIM_DCR_DBA_4 ((u16)0x0010) /* Bit 4 */
-
-#define TIM_DCR_DBL ((u16)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((u16)0x0100) /* Bit 0 */
-#define TIM_DCR_DBL_1 ((u16)0x0200) /* Bit 1 */
-#define TIM_DCR_DBL_2 ((u16)0x0400) /* Bit 2 */
-#define TIM_DCR_DBL_3 ((u16)0x0800) /* Bit 3 */
-#define TIM_DCR_DBL_4 ((u16)0x1000) /* Bit 4 */
-
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((u16)0xFFFF) /* DMA register for burst accesses */
-
-
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for RTC_CRH register ********************/
-#define RTC_CRH_SECIE ((u8)0x01) /* Second Interrupt Enable */
-#define RTC_CRH_ALRIE ((u8)0x02) /* Alarm Interrupt Enable */
-#define RTC_CRH_OWIE ((u8)0x04) /* OverfloW Interrupt Enable */
-
-
-/******************* Bit definition for RTC_CRL register ********************/
-#define RTC_CRL_SECF ((u8)0x01) /* Second Flag */
-#define RTC_CRL_ALRF ((u8)0x02) /* Alarm Flag */
-#define RTC_CRL_OWF ((u8)0x04) /* OverfloW Flag */
-#define RTC_CRL_RSF ((u8)0x08) /* Registers Synchronized Flag */
-#define RTC_CRL_CNF ((u8)0x10) /* Configuration Flag */
-#define RTC_CRL_RTOFF ((u8)0x20) /* RTC operation OFF */
-
-
-/******************* Bit definition for RTC_PRLH register *******************/
-#define RTC_PRLH_PRL ((u16)0x000F) /* RTC Prescaler Reload Value High */
-
-
-/******************* Bit definition for RTC_PRLL register *******************/
-#define RTC_PRLL_PRL ((u16)0xFFFF) /* RTC Prescaler Reload Value Low */
-
-
-/******************* Bit definition for RTC_DIVH register *******************/
-#define RTC_DIVH_RTC_DIV ((u16)0x000F) /* RTC Clock Divider High */
-
-
-/******************* Bit definition for RTC_DIVL register *******************/
-#define RTC_DIVL_RTC_DIV ((u16)0xFFFF) /* RTC Clock Divider Low */
-
-
-/******************* Bit definition for RTC_CNTH register *******************/
-#define RTC_CNTH_RTC_CNT ((u16)0xFFFF) /* RTC Counter High */
-
-
-/******************* Bit definition for RTC_CNTL register *******************/
-#define RTC_CNTL_RTC_CNT ((u16)0xFFFF) /* RTC Counter Low */
-
-
-/******************* Bit definition for RTC_ALRH register *******************/
-#define RTC_ALRH_RTC_ALR ((u16)0xFFFF) /* RTC Alarm High */
-
-
-/******************* Bit definition for RTC_ALRL register *******************/
-#define RTC_ALRL_RTC_ALR ((u16)0xFFFF) /* RTC Alarm Low */
-
-
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((u16)0xFFFF) /* Key value (write only, read 0000h) */
-
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((u8)0x07) /* PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((u8)0x01) /* Bit 0 */
-#define IWDG_PR_PR_1 ((u8)0x02) /* Bit 1 */
-#define IWDG_PR_PR_2 ((u8)0x04) /* Bit 2 */
-
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((u16)0x0FFF) /* Watchdog counter reload value */
-
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((u8)0x01) /* Watchdog prescaler value update */
-#define IWDG_SR_RVU ((u8)0x02) /* Watchdog counter reload value update */
-
-
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((u8)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((u8)0x01) /* Bit 0 */
-#define WWDG_CR_T1 ((u8)0x02) /* Bit 1 */
-#define WWDG_CR_T2 ((u8)0x04) /* Bit 2 */
-#define WWDG_CR_T3 ((u8)0x08) /* Bit 3 */
-#define WWDG_CR_T4 ((u8)0x10) /* Bit 4 */
-#define WWDG_CR_T5 ((u8)0x20) /* Bit 5 */
-#define WWDG_CR_T6 ((u8)0x40) /* Bit 6 */
-
-#define WWDG_CR_WDGA ((u8)0x80) /* Activation bit */
-
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((u16)0x007F) /* W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((u16)0x0001) /* Bit 0 */
-#define WWDG_CFR_W1 ((u16)0x0002) /* Bit 1 */
-#define WWDG_CFR_W2 ((u16)0x0004) /* Bit 2 */
-#define WWDG_CFR_W3 ((u16)0x0008) /* Bit 3 */
-#define WWDG_CFR_W4 ((u16)0x0010) /* Bit 4 */
-#define WWDG_CFR_W5 ((u16)0x0020) /* Bit 5 */
-#define WWDG_CFR_W6 ((u16)0x0040) /* Bit 6 */
-
-#define WWDG_CFR_WDGTB ((u16)0x0180) /* WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((u16)0x0080) /* Bit 0 */
-#define WWDG_CFR_WDGTB1 ((u16)0x0100) /* Bit 1 */
-
-#define WWDG_CFR_EWI ((u16)0x0200) /* Early Wakeup Interrupt */
-
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((u8)0x01) /* Early Wakeup Interrupt Flag */
-
-
-
-/******************************************************************************/
-/* */
-/* Flexible Static Memory Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for FSMC_BCR1 register *******************/
-#define FSMC_BCR1_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
-#define FSMC_BCR1_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
-
-#define FSMC_BCR1_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR1_MTYP_0 ((u32)0x00000004) /* Bit 0 */
-#define FSMC_BCR1_MTYP_1 ((u32)0x00000008) /* Bit 1 */
-
-#define FSMC_BCR1_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR1_MWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BCR1_MWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_BCR1_FACCEN ((u32)0x00000040) /* Flash access enable */
-#define FSMC_BCR1_BURSTEN ((u32)0x00000100) /* Burst enable bit */
-#define FSMC_BCR1_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */
-#define FSMC_BCR1_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
-#define FSMC_BCR1_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
-#define FSMC_BCR1_WREN ((u32)0x00001000) /* Write enable bit */
-#define FSMC_BCR1_WAITEN ((u32)0x00002000) /* Wait enable bit */
-#define FSMC_BCR1_EXTMOD ((u32)0x00004000) /* Extended mode enable */
-#define FSMC_BCR1_CBURSTRW ((u32)0x00080000) /* Write burst enable */
-
-
-/****************** Bit definition for FSMC_BCR2 register *******************/
-#define FSMC_BCR2_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
-#define FSMC_BCR2_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
-
-#define FSMC_BCR2_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR2_MTYP_0 ((u32)0x00000004) /* Bit 0 */
-#define FSMC_BCR2_MTYP_1 ((u32)0x00000008) /* Bit 1 */
-
-#define FSMC_BCR2_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR2_MWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BCR2_MWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_BCR2_FACCEN ((u32)0x00000040) /* Flash access enable */
-#define FSMC_BCR2_BURSTEN ((u32)0x00000100) /* Burst enable bit */
-#define FSMC_BCR2_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */
-#define FSMC_BCR2_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
-#define FSMC_BCR2_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
-#define FSMC_BCR2_WREN ((u32)0x00001000) /* Write enable bit */
-#define FSMC_BCR2_WAITEN ((u32)0x00002000) /* Wait enable bit */
-#define FSMC_BCR2_EXTMOD ((u32)0x00004000) /* Extended mode enable */
-#define FSMC_BCR2_CBURSTRW ((u32)0x00080000) /* Write burst enable */
-
-
-/****************** Bit definition for FSMC_BCR3 register *******************/
-#define FSMC_BCR3_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
-#define FSMC_BCR3_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
-
-#define FSMC_BCR3_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR3_MTYP_0 ((u32)0x00000004) /* Bit 0 */
-#define FSMC_BCR3_MTYP_1 ((u32)0x00000008) /* Bit 1 */
-
-#define FSMC_BCR3_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR3_MWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BCR3_MWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_BCR3_FACCEN ((u32)0x00000040) /* Flash access enable */
-#define FSMC_BCR3_BURSTEN ((u32)0x00000100) /* Burst enable bit */
-#define FSMC_BCR3_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit. */
-#define FSMC_BCR3_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
-#define FSMC_BCR3_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
-#define FSMC_BCR3_WREN ((u32)0x00001000) /* Write enable bit */
-#define FSMC_BCR3_WAITEN ((u32)0x00002000) /* Wait enable bit */
-#define FSMC_BCR3_EXTMOD ((u32)0x00004000) /* Extended mode enable */
-#define FSMC_BCR3_CBURSTRW ((u32)0x00080000) /* Write burst enable */
-
-
-/****************** Bit definition for FSMC_BCR4 register *******************/
-#define FSMC_BCR4_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
-#define FSMC_BCR4_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
-
-#define FSMC_BCR4_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
-#define FSMC_BCR4_MTYP_0 ((u32)0x00000004) /* Bit 0 */
-#define FSMC_BCR4_MTYP_1 ((u32)0x00000008) /* Bit 1 */
-
-#define FSMC_BCR4_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR4_MWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BCR4_MWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_BCR4_FACCEN ((u32)0x00000040) /* Flash access enable */
-#define FSMC_BCR4_BURSTEN ((u32)0x00000100) /* Burst enable bit */
-#define FSMC_BCR4_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */
-#define FSMC_BCR4_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
-#define FSMC_BCR4_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
-#define FSMC_BCR4_WREN ((u32)0x00001000) /* Write enable bit */
-#define FSMC_BCR4_WAITEN ((u32)0x00002000) /* Wait enable bit */
-#define FSMC_BCR4_EXTMOD ((u32)0x00004000) /* Extended mode enable */
-#define FSMC_BCR4_CBURSTRW ((u32)0x00080000) /* Write burst enable */
-
-
-/****************** Bit definition for FSMC_BTR1 register ******************/
-#define FSMC_BTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_BTR2 register *******************/
-#define FSMC_BTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/******************* Bit definition for FSMC_BTR3 register *******************/
-#define FSMC_BTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_BTR4 register *******************/
-#define FSMC_BTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_BWTR1 register ******************/
-#define FSMC_BWTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BWTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BWTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BWTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BWTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BWTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BWTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BWTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BWTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BWTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BWTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BWTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BWTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BWTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BWTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BWTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BWTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BWTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BWTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BWTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BWTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BWTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BWTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BWTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BWTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BWTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_BWTR2 register ******************/
-#define FSMC_BWTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BWTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BWTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BWTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BWTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BWTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BWTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BWTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BWTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BWTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BWTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BWTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BWTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BWTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BWTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BWTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BWTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BWTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1*/
-#define FSMC_BWTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BWTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BWTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BWTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BWTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BWTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BWTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BWTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_BWTR3 register ******************/
-#define FSMC_BWTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BWTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BWTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BWTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BWTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BWTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BWTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BWTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BWTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BWTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BWTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BWTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BWTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BWTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BWTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BWTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BWTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BWTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BWTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BWTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BWTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BWTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BWTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BWTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BWTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BWTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_BWTR4 register ******************/
-#define FSMC_BWTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_BWTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_BWTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_BWTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
-
-#define FSMC_BWTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_BWTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
-#define FSMC_BWTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
-#define FSMC_BWTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
-
-#define FSMC_BWTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_BWTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_BWTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_BWTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */
-
-#define FSMC_BWTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_BWTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_BWTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_BWTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
-
-#define FSMC_BWTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BWTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
-#define FSMC_BWTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
-#define FSMC_BWTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
-#define FSMC_BWTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
-
-#define FSMC_BWTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
-#define FSMC_BWTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_BWTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_BWTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_BWTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
-
-#define FSMC_BWTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
-#define FSMC_BWTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
-
-
-/****************** Bit definition for FSMC_PCR2 register *******************/
-#define FSMC_PCR2_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */
-#define FSMC_PCR2_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR2_PTYP ((u32)0x00000008) /* Memory type */
-
-#define FSMC_PCR2_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR2_PWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_PCR2_PWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_PCR2_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */
-#define FSMC_PCR2_ADLOW ((u32)0x00000100) /* Address low bit delivery */
-
-#define FSMC_PCR2_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR2_TCLR_0 ((u32)0x00000200) /* Bit 0 */
-#define FSMC_PCR2_TCLR_1 ((u32)0x00000400) /* Bit 1 */
-#define FSMC_PCR2_TCLR_2 ((u32)0x00000800) /* Bit 2 */
-#define FSMC_PCR2_TCLR_3 ((u32)0x00001000) /* Bit 3 */
-
-#define FSMC_PCR2_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR2_TAR_0 ((u32)0x00002000) /* Bit 0 */
-#define FSMC_PCR2_TAR_1 ((u32)0x00004000) /* Bit 1 */
-#define FSMC_PCR2_TAR_2 ((u32)0x00008000) /* Bit 2 */
-#define FSMC_PCR2_TAR_3 ((u32)0x00010000) /* Bit 3 */
-
-#define FSMC_PCR2_ECCPS ((u32)0x000E0000) /* ECCPS[1:0] bits (ECC page size) */
-#define FSMC_PCR2_ECCPS_0 ((u32)0x00020000) /* Bit 0 */
-#define FSMC_PCR2_ECCPS_1 ((u32)0x00040000) /* Bit 1 */
-#define FSMC_PCR2_ECCPS_2 ((u32)0x00080000) /* Bit 2 */
-
-
-/****************** Bit definition for FSMC_PCR3 register *******************/
-#define FSMC_PCR3_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */
-#define FSMC_PCR3_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR3_PTYP ((u32)0x00000008) /* Memory type */
-
-#define FSMC_PCR3_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR3_PWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_PCR3_PWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_PCR3_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */
-#define FSMC_PCR3_ADLOW ((u32)0x00000100) /* Address low bit delivery */
-
-#define FSMC_PCR3_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR3_TCLR_0 ((u32)0x00000200) /* Bit 0 */
-#define FSMC_PCR3_TCLR_1 ((u32)0x00000400) /* Bit 1 */
-#define FSMC_PCR3_TCLR_2 ((u32)0x00000800) /* Bit 2 */
-#define FSMC_PCR3_TCLR_3 ((u32)0x00001000) /* Bit 3 */
-
-#define FSMC_PCR3_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR3_TAR_0 ((u32)0x00002000) /* Bit 0 */
-#define FSMC_PCR3_TAR_1 ((u32)0x00004000) /* Bit 1 */
-#define FSMC_PCR3_TAR_2 ((u32)0x00008000) /* Bit 2 */
-#define FSMC_PCR3_TAR_3 ((u32)0x00010000) /* Bit 3 */
-
-#define FSMC_PCR3_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR3_ECCPS_0 ((u32)0x00020000) /* Bit 0 */
-#define FSMC_PCR3_ECCPS_1 ((u32)0x00040000) /* Bit 1 */
-#define FSMC_PCR3_ECCPS_2 ((u32)0x00080000) /* Bit 2 */
-
-
-/****************** Bit definition for FSMC_PCR4 register *******************/
-#define FSMC_PCR4_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */
-#define FSMC_PCR4_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR4_PTYP ((u32)0x00000008) /* Memory type */
-
-#define FSMC_PCR4_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR4_PWID_0 ((u32)0x00000010) /* Bit 0 */
-#define FSMC_PCR4_PWID_1 ((u32)0x00000020) /* Bit 1 */
-
-#define FSMC_PCR4_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */
-#define FSMC_PCR4_ADLOW ((u32)0x00000100) /* Address low bit delivery */
-
-#define FSMC_PCR4_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR4_TCLR_0 ((u32)0x00000200) /* Bit 0 */
-#define FSMC_PCR4_TCLR_1 ((u32)0x00000400) /* Bit 1 */
-#define FSMC_PCR4_TCLR_2 ((u32)0x00000800) /* Bit 2 */
-#define FSMC_PCR4_TCLR_3 ((u32)0x00001000) /* Bit 3 */
-
-#define FSMC_PCR4_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR4_TAR_0 ((u32)0x00002000) /* Bit 0 */
-#define FSMC_PCR4_TAR_1 ((u32)0x00004000) /* Bit 1 */
-#define FSMC_PCR4_TAR_2 ((u32)0x00008000) /* Bit 2 */
-#define FSMC_PCR4_TAR_3 ((u32)0x00010000) /* Bit 3 */
-
-#define FSMC_PCR4_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR4_ECCPS_0 ((u32)0x00020000) /* Bit 0 */
-#define FSMC_PCR4_ECCPS_1 ((u32)0x00040000) /* Bit 1 */
-#define FSMC_PCR4_ECCPS_2 ((u32)0x00080000) /* Bit 2 */
-
-
-/******************* Bit definition for FSMC_SR2 register *******************/
-#define FSMC_SR2_IRS ((u8)0x01) /* Interrupt Rising Edge status */
-#define FSMC_SR2_ILS ((u8)0x02) /* Interrupt Level status */
-#define FSMC_SR2_IFS ((u8)0x04) /* Interrupt Falling Edge status */
-#define FSMC_SR2_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR2_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */
-#define FSMC_SR2_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR2_FEMPT ((u8)0x40) /* FIFO empty */
-
-
-/******************* Bit definition for FSMC_SR3 register *******************/
-#define FSMC_SR3_IRS ((u8)0x01) /* Interrupt Rising Edge status */
-#define FSMC_SR3_ILS ((u8)0x02) /* Interrupt Level status */
-#define FSMC_SR3_IFS ((u8)0x04) /* Interrupt Falling Edge status */
-#define FSMC_SR3_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR3_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */
-#define FSMC_SR3_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR3_FEMPT ((u8)0x40) /* FIFO empty */
-
-
-/******************* Bit definition for FSMC_SR4 register *******************/
-#define FSMC_SR4_IRS ((u8)0x01) /* Interrupt Rising Edge status */
-#define FSMC_SR4_ILS ((u8)0x02) /* Interrupt Level status */
-#define FSMC_SR4_IFS ((u8)0x04) /* Interrupt Falling Edge status */
-#define FSMC_SR4_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR4_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */
-#define FSMC_SR4_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR4_FEMPT ((u8)0x40) /* FIFO empty */
-
-
-/****************** Bit definition for FSMC_PMEM2 register ******************/
-#define FSMC_PMEM2_MEMSET2 ((u32)0x000000FF) /* MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define FSMC_PMEM2_MEMSET2_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PMEM2_MEMSET2_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PMEM2_MEMSET2_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PMEM2_MEMSET2_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PMEM2_MEMSET2_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PMEM2_MEMSET2_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PMEM2_MEMSET2_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PMEM2_MEMSET2_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PMEM2_MEMWAIT2 ((u32)0x0000FF00) /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define FSMC_PMEM2_MEMWAIT2_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PMEM2_MEMWAIT2_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PMEM2_MEMWAIT2_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PMEM2_MEMWAIT2_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PMEM2_MEMWAIT2_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PMEM2_MEMWAIT2_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PMEM2_MEMWAIT2_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PMEM2_MEMWAIT2_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PMEM2_MEMHOLD2 ((u32)0x00FF0000) /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define FSMC_PMEM2_MEMHOLD2_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PMEM2_MEMHOLD2_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PMEM2_MEMHOLD2_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PMEM2_MEMHOLD2_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PMEM2_MEMHOLD2_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PMEM2_MEMHOLD2_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PMEM2_MEMHOLD2_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PMEM2_MEMHOLD2_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PMEM2_MEMHIZ2 ((u32)0xFF000000) /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define FSMC_PMEM2_MEMHIZ2_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PMEM2_MEMHIZ2_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PMEM2_MEMHIZ2_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PMEM2_MEMHIZ2_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PMEM2_MEMHIZ2_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PMEM2_MEMHIZ2_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PMEM2_MEMHIZ2_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PMEM2_MEMHIZ2_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_PMEM3 register ******************/
-#define FSMC_PMEM3_MEMSET3 ((u32)0x000000FF) /* MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define FSMC_PMEM3_MEMSET3_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PMEM3_MEMSET3_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PMEM3_MEMSET3_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PMEM3_MEMSET3_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PMEM3_MEMSET3_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PMEM3_MEMSET3_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PMEM3_MEMSET3_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PMEM3_MEMSET3_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PMEM3_MEMWAIT3 ((u32)0x0000FF00) /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define FSMC_PMEM3_MEMWAIT3_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PMEM3_MEMWAIT3_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PMEM3_MEMWAIT3_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PMEM3_MEMWAIT3_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PMEM3_MEMWAIT3_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PMEM3_MEMWAIT3_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PMEM3_MEMWAIT3_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PMEM3_MEMWAIT3_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PMEM3_MEMHOLD3 ((u32)0x00FF0000) /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define FSMC_PMEM3_MEMHOLD3_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PMEM3_MEMHOLD3_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PMEM3_MEMHOLD3_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PMEM3_MEMHOLD3_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PMEM3_MEMHOLD3_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PMEM3_MEMHOLD3_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PMEM3_MEMHOLD3_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PMEM3_MEMHOLD3_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PMEM3_MEMHIZ3 ((u32)0xFF000000) /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define FSMC_PMEM3_MEMHIZ3_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PMEM3_MEMHIZ3_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PMEM3_MEMHIZ3_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PMEM3_MEMHIZ3_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PMEM3_MEMHIZ3_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PMEM3_MEMHIZ3_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PMEM3_MEMHIZ3_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PMEM3_MEMHIZ3_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_PMEM4 register ******************/
-#define FSMC_PMEM4_MEMSET4 ((u32)0x000000FF) /* MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define FSMC_PMEM4_MEMSET4_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PMEM4_MEMSET4_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PMEM4_MEMSET4_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PMEM4_MEMSET4_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PMEM4_MEMSET4_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PMEM4_MEMSET4_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PMEM4_MEMSET4_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PMEM4_MEMSET4_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PMEM4_MEMWAIT4 ((u32)0x0000FF00) /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define FSMC_PMEM4_MEMWAIT4_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PMEM4_MEMWAIT4_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PMEM4_MEMWAIT4_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PMEM4_MEMWAIT4_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PMEM4_MEMWAIT4_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PMEM4_MEMWAIT4_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PMEM4_MEMWAIT4_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PMEM4_MEMWAIT4_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PMEM4_MEMHOLD4 ((u32)0x00FF0000) /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define FSMC_PMEM4_MEMHOLD4_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PMEM4_MEMHOLD4_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PMEM4_MEMHOLD4_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PMEM4_MEMHOLD4_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PMEM4_MEMHOLD4_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PMEM4_MEMHOLD4_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PMEM4_MEMHOLD4_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PMEM4_MEMHOLD4_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PMEM4_MEMHIZ4 ((u32)0xFF000000) /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define FSMC_PMEM4_MEMHIZ4_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PMEM4_MEMHIZ4_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PMEM4_MEMHIZ4_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PMEM4_MEMHIZ4_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PMEM4_MEMHIZ4_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PMEM4_MEMHIZ4_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PMEM4_MEMHIZ4_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PMEM4_MEMHIZ4_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_PATT2 register ******************/
-#define FSMC_PATT2_ATTSET2 ((u32)0x000000FF) /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define FSMC_PATT2_ATTSET2_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PATT2_ATTSET2_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PATT2_ATTSET2_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PATT2_ATTSET2_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PATT2_ATTSET2_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PATT2_ATTSET2_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PATT2_ATTSET2_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PATT2_ATTSET2_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PATT2_ATTWAIT2 ((u32)0x0000FF00) /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define FSMC_PATT2_ATTWAIT2_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PATT2_ATTWAIT2_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PATT2_ATTWAIT2_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PATT2_ATTWAIT2_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PATT2_ATTWAIT2_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PATT2_ATTWAIT2_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PATT2_ATTWAIT2_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PATT2_ATTWAIT2_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PATT2_ATTHOLD2 ((u32)0x00FF0000) /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define FSMC_PATT2_ATTHOLD2_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PATT2_ATTHOLD2_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PATT2_ATTHOLD2_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PATT2_ATTHOLD2_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PATT2_ATTHOLD2_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PATT2_ATTHOLD2_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PATT2_ATTHOLD2_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PATT2_ATTHOLD2_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PATT2_ATTHIZ2 ((u32)0xFF000000) /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define FSMC_PATT2_ATTHIZ2_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PATT2_ATTHIZ2_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PATT2_ATTHIZ2_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PATT2_ATTHIZ2_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PATT2_ATTHIZ2_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PATT2_ATTHIZ2_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PATT2_ATTHIZ2_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PATT2_ATTHIZ2_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_PATT3 register ******************/
-#define FSMC_PATT3_ATTSET3 ((u32)0x000000FF) /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define FSMC_PATT3_ATTSET3_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PATT3_ATTSET3_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PATT3_ATTSET3_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PATT3_ATTSET3_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PATT3_ATTSET3_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PATT3_ATTSET3_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PATT3_ATTSET3_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PATT3_ATTSET3_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PATT3_ATTWAIT3 ((u32)0x0000FF00) /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define FSMC_PATT3_ATTWAIT3_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PATT3_ATTWAIT3_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PATT3_ATTWAIT3_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PATT3_ATTWAIT3_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PATT3_ATTWAIT3_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PATT3_ATTWAIT3_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PATT3_ATTWAIT3_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PATT3_ATTWAIT3_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PATT3_ATTHOLD3 ((u32)0x00FF0000) /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define FSMC_PATT3_ATTHOLD3_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PATT3_ATTHOLD3_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PATT3_ATTHOLD3_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PATT3_ATTHOLD3_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PATT3_ATTHOLD3_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PATT3_ATTHOLD3_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PATT3_ATTHOLD3_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PATT3_ATTHOLD3_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PATT3_ATTHIZ3 ((u32)0xFF000000) /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define FSMC_PATT3_ATTHIZ3_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PATT3_ATTHIZ3_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PATT3_ATTHIZ3_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PATT3_ATTHIZ3_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PATT3_ATTHIZ3_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PATT3_ATTHIZ3_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PATT3_ATTHIZ3_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PATT3_ATTHIZ3_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_PATT4 register ******************/
-#define FSMC_PATT4_ATTSET4 ((u32)0x000000FF) /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define FSMC_PATT4_ATTSET4_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PATT4_ATTSET4_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PATT4_ATTSET4_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PATT4_ATTSET4_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PATT4_ATTSET4_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PATT4_ATTSET4_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PATT4_ATTSET4_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PATT4_ATTSET4_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PATT4_ATTWAIT4 ((u32)0x0000FF00) /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define FSMC_PATT4_ATTWAIT4_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PATT4_ATTWAIT4_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PATT4_ATTWAIT4_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PATT4_ATTWAIT4_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PATT4_ATTWAIT4_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PATT4_ATTWAIT4_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PATT4_ATTWAIT4_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PATT4_ATTWAIT4_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PATT4_ATTHOLD4 ((u32)0x00FF0000) /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define FSMC_PATT4_ATTHOLD4_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PATT4_ATTHOLD4_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PATT4_ATTHOLD4_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PATT4_ATTHOLD4_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PATT4_ATTHOLD4_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PATT4_ATTHOLD4_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PATT4_ATTHOLD4_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PATT4_ATTHOLD4_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PATT4_ATTHIZ4 ((u32)0xFF000000) /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define FSMC_PATT4_ATTHIZ4_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PATT4_ATTHIZ4_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PATT4_ATTHIZ4_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PATT4_ATTHIZ4_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PATT4_ATTHIZ4_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PATT4_ATTHIZ4_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PATT4_ATTHIZ4_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PATT4_ATTHIZ4_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_PIO4 register *******************/
-#define FSMC_PIO4_IOSET4 ((u32)0x000000FF) /* IOSET4[7:0] bits (I/O 4 setup time) */
-#define FSMC_PIO4_IOSET4_0 ((u32)0x00000001) /* Bit 0 */
-#define FSMC_PIO4_IOSET4_1 ((u32)0x00000002) /* Bit 1 */
-#define FSMC_PIO4_IOSET4_2 ((u32)0x00000004) /* Bit 2 */
-#define FSMC_PIO4_IOSET4_3 ((u32)0x00000008) /* Bit 3 */
-#define FSMC_PIO4_IOSET4_4 ((u32)0x00000010) /* Bit 4 */
-#define FSMC_PIO4_IOSET4_5 ((u32)0x00000020) /* Bit 5 */
-#define FSMC_PIO4_IOSET4_6 ((u32)0x00000040) /* Bit 6 */
-#define FSMC_PIO4_IOSET4_7 ((u32)0x00000080) /* Bit 7 */
-
-#define FSMC_PIO4_IOWAIT4 ((u32)0x0000FF00) /* IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define FSMC_PIO4_IOWAIT4_0 ((u32)0x00000100) /* Bit 0 */
-#define FSMC_PIO4_IOWAIT4_1 ((u32)0x00000200) /* Bit 1 */
-#define FSMC_PIO4_IOWAIT4_2 ((u32)0x00000400) /* Bit 2 */
-#define FSMC_PIO4_IOWAIT4_3 ((u32)0x00000800) /* Bit 3 */
-#define FSMC_PIO4_IOWAIT4_4 ((u32)0x00001000) /* Bit 4 */
-#define FSMC_PIO4_IOWAIT4_5 ((u32)0x00002000) /* Bit 5 */
-#define FSMC_PIO4_IOWAIT4_6 ((u32)0x00004000) /* Bit 6 */
-#define FSMC_PIO4_IOWAIT4_7 ((u32)0x00008000) /* Bit 7 */
-
-#define FSMC_PIO4_IOHOLD4 ((u32)0x00FF0000) /* IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define FSMC_PIO4_IOHOLD4_0 ((u32)0x00010000) /* Bit 0 */
-#define FSMC_PIO4_IOHOLD4_1 ((u32)0x00020000) /* Bit 1 */
-#define FSMC_PIO4_IOHOLD4_2 ((u32)0x00040000) /* Bit 2 */
-#define FSMC_PIO4_IOHOLD4_3 ((u32)0x00080000) /* Bit 3 */
-#define FSMC_PIO4_IOHOLD4_4 ((u32)0x00100000) /* Bit 4 */
-#define FSMC_PIO4_IOHOLD4_5 ((u32)0x00200000) /* Bit 5 */
-#define FSMC_PIO4_IOHOLD4_6 ((u32)0x00400000) /* Bit 6 */
-#define FSMC_PIO4_IOHOLD4_7 ((u32)0x00800000) /* Bit 7 */
-
-#define FSMC_PIO4_IOHIZ4 ((u32)0xFF000000) /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define FSMC_PIO4_IOHIZ4_0 ((u32)0x01000000) /* Bit 0 */
-#define FSMC_PIO4_IOHIZ4_1 ((u32)0x02000000) /* Bit 1 */
-#define FSMC_PIO4_IOHIZ4_2 ((u32)0x04000000) /* Bit 2 */
-#define FSMC_PIO4_IOHIZ4_3 ((u32)0x08000000) /* Bit 3 */
-#define FSMC_PIO4_IOHIZ4_4 ((u32)0x10000000) /* Bit 4 */
-#define FSMC_PIO4_IOHIZ4_5 ((u32)0x20000000) /* Bit 5 */
-#define FSMC_PIO4_IOHIZ4_6 ((u32)0x40000000) /* Bit 6 */
-#define FSMC_PIO4_IOHIZ4_7 ((u32)0x80000000) /* Bit 7 */
-
-
-/****************** Bit definition for FSMC_ECCR2 register ******************/
-#define FSMC_ECCR2_ECC2 ((u32)0xFFFFFFFF) /* ECC result */
-
-/****************** Bit definition for FSMC_ECCR3 register ******************/
-#define FSMC_ECCR3_ECC3 ((u32)0xFFFFFFFF) /* ECC result */
-
-
-
-/******************************************************************************/
-/* */
-/* SD host Interface */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL ((u8)0x03) /* PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 ((u8)0x01) /* Bit 0 */
-#define SDIO_POWER_PWRCTRL_1 ((u8)0x02) /* Bit 1 */
-
-
-/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV ((u16)0x00FF) /* Clock divide factor */
-#define SDIO_CLKCR_CLKEN ((u16)0x0100) /* Clock enable bit */
-#define SDIO_CLKCR_PWRSAV ((u16)0x0200) /* Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS ((u16)0x0400) /* Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS ((u16)0x1800) /* WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 ((u16)0x0800) /* Bit 0 */
-#define SDIO_CLKCR_WIDBUS_1 ((u16)0x1000) /* Bit 1 */
-
-#define SDIO_CLKCR_NEGEDGE ((u16)0x2000) /* SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN ((u16)0x4000) /* HW Flow Control enable */
-
-
-/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG ((u32)0xFFFFFFFF) /* Command argument */
-
-
-/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX ((u16)0x003F) /* Command Index */
-
-#define SDIO_CMD_WAITRESP ((u16)0x00C0) /* WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 ((u16)0x0040) /* Bit 0 */
-#define SDIO_CMD_WAITRESP_1 ((u16)0x0080) /* Bit 1 */
-
-#define SDIO_CMD_WAITINT ((u16)0x0100) /* CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND ((u16)0x0200) /* CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN ((u16)0x0400) /* Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND ((u16)0x0800) /* SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL ((u16)0x1000) /* Enable CMD completion */
-#define SDIO_CMD_NIEN ((u16)0x2000) /* Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD ((u16)0x4000) /* CE-ATA command */
-
-
-/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD ((u8)0x3F) /* Response command index */
-
-
-/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0 ((u32)0xFFFFFFFF) /* Card Status */
-
-
-/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1 ((u32)0xFFFFFFFF) /* Card Status */
-
-
-/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2 ((u32)0xFFFFFFFF) /* Card Status */
-
-
-/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3 ((u32)0xFFFFFFFF) /* Card Status */
-
-
-/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4 ((u32)0xFFFFFFFF) /* Card Status */
-
-
-/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME ((u32)0xFFFFFFFF) /* Data timeout period. */
-
-
-/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH ((u32)0x01FFFFFF) /* Data length value */
-
-
-/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN ((u16)0x0001) /* Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR ((u16)0x0002) /* Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE ((u16)0x0004) /* Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN ((u16)0x0008) /* DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE ((u16)0x00F0) /* DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((u16)0x0010) /* Bit 0 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((u16)0x0020) /* Bit 1 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((u16)0x0040) /* Bit 2 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((u16)0x0080) /* Bit 3 */
-
-#define SDIO_DCTRL_RWSTART ((u16)0x0100) /* Read wait start */
-#define SDIO_DCTRL_RWSTOP ((u16)0x0200) /* Read wait stop */
-#define SDIO_DCTRL_RWMOD ((u16)0x0400) /* Read wait mode */
-#define SDIO_DCTRL_SDIOEN ((u16)0x0800) /* SD I/O enable functions */
-
-
-/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT ((u32)0x01FFFFFF) /* Data count value */
-
-
-/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL ((u32)0x00000001) /* Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL ((u32)0x00000002) /* Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT ((u32)0x00000004) /* Command response timeout */
-#define SDIO_STA_DTIMEOUT ((u32)0x00000008) /* Data timeout */
-#define SDIO_STA_TXUNDERR ((u32)0x00000010) /* Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR ((u32)0x00000020) /* Received FIFO overrun error */
-#define SDIO_STA_CMDREND ((u32)0x00000040) /* Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT ((u32)0x00000080) /* Command sent (no response required) */
-#define SDIO_STA_DATAEND ((u32)0x00000100) /* Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR ((u32)0x00000200) /* Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND ((u32)0x00000400) /* Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT ((u32)0x00000800) /* Command transfer in progress */
-#define SDIO_STA_TXACT ((u32)0x00001000) /* Data transmit in progress */
-#define SDIO_STA_RXACT ((u32)0x00002000) /* Data receive in progress */
-#define SDIO_STA_TXFIFOHE ((u32)0x00004000) /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF ((u32)0x00008000) /* Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF ((u32)0x00010000) /* Transmit FIFO full */
-#define SDIO_STA_RXFIFOF ((u32)0x00020000) /* Receive FIFO full */
-#define SDIO_STA_TXFIFOE ((u32)0x00040000) /* Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE ((u32)0x00080000) /* Receive FIFO empty */
-#define SDIO_STA_TXDAVL ((u32)0x00100000) /* Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL ((u32)0x00200000) /* Data available in receive FIFO */
-#define SDIO_STA_SDIOIT ((u32)0x00400000) /* SDIO interrupt received */
-#define SDIO_STA_CEATAEND ((u32)0x00800000) /* CE-ATA command completion signal received for CMD61 */
-
-
-/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC ((u32)0x00000001) /* CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC ((u32)0x00000002) /* DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC ((u32)0x00000004) /* CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC ((u32)0x00000008) /* DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC ((u32)0x00000010) /* TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC ((u32)0x00000020) /* RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC ((u32)0x00000040) /* CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC ((u32)0x00000080) /* CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC ((u32)0x00000100) /* DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC ((u32)0x00000200) /* STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC ((u32)0x00000400) /* DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC ((u32)0x00400000) /* SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC ((u32)0x00800000) /* CEATAEND flag clear bit */
-
-
-/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE ((u32)0x00000001) /* Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE ((u32)0x00000002) /* Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE ((u32)0x00000004) /* Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE ((u32)0x00000008) /* Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE ((u32)0x00000010) /* Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE ((u32)0x00000020) /* Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE ((u32)0x00000040) /* Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE ((u32)0x00000080) /* Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE ((u32)0x00000100) /* Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE ((u32)0x00000200) /* Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE ((u32)0x00000400) /* Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE ((u32)0x00000800) /* CCommand Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE ((u32)0x00001000) /* Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE ((u32)0x00002000) /* Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE ((u32)0x00004000) /* Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE ((u32)0x00008000) /* Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE ((u32)0x00010000) /* Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE ((u32)0x00020000) /* Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE ((u32)0x00040000) /* Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE ((u32)0x00080000) /* Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE ((u32)0x00100000) /* Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE ((u32)0x00200000) /* Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE ((u32)0x00400000) /* SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE ((u32)0x00800000) /* CE-ATA command completion signal received Interrupt Enable */
-
-
-/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT ((u32)0x00FFFFFF) /* Remaining number of words to be written to or read from the FIFO */
-
-
-/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA ((u32)0xFFFFFFFF) /* Receive and transmit FIFO data */
-
-
-
-/******************************************************************************/
-/* */
-/* USB */
-/* */
-/******************************************************************************/
-
-/* Endpoint-specific registers */
-/******************* Bit definition for USB_EP0R register *******************/
-#define USB_EP0R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP0R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP0R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP0R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP0R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP0R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP0R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP0R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP0R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP1R register *******************/
-#define USB_EP1R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP1R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP1R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP1R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP1R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP1R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP1R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP1R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP1R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP2R register *******************/
-#define USB_EP2R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP2R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP2R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP2R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP2R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP2R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP2R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP2R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP2R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP3R register *******************/
-#define USB_EP3R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP3R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP3R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP3R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP3R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP3R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP3R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP3R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP3R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP4R register *******************/
-#define USB_EP4R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP4R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP4R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP4R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP4R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP4R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP4R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP4R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP4R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP5R register *******************/
-#define USB_EP5R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP5R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP5R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP5R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP5R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP5R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP5R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP5R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP5R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP6R register *******************/
-#define USB_EP6R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP6R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP6R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP6R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP6R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP6R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP6R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP6R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP6R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/******************* Bit definition for USB_EP7R register *******************/
-#define USB_EP7R_EA ((u16)0x000F) /* Endpoint Address */
-
-#define USB_EP7R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
-#define USB_EP7R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
-
-#define USB_EP7R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
-#define USB_EP7R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
-
-#define USB_EP7R_SETUP ((u16)0x0800) /* Setup transaction completed */
-
-#define USB_EP7R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
-#define USB_EP7R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
-
-#define USB_EP7R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
-
-
-/* Common registers */
-/******************* Bit definition for USB_CNTR register *******************/
-#define USB_CNTR_FRES ((u16)0x0001) /* Force USB Reset */
-#define USB_CNTR_PDWN ((u16)0x0002) /* Power down */
-#define USB_CNTR_LP_MODE ((u16)0x0004) /* Low-power mode */
-#define USB_CNTR_FSUSP ((u16)0x0008) /* Force suspend */
-#define USB_CNTR_RESUME ((u16)0x0010) /* Resume request */
-#define USB_CNTR_ESOFM ((u16)0x0100) /* Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM ((u16)0x0200) /* Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM ((u16)0x0400) /* RESET Interrupt Mask */
-#define USB_CNTR_SUSPM ((u16)0x0800) /* Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM ((u16)0x1000) /* Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM ((u16)0x2000) /* Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM ((u16)0x4000) /* Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM ((u16)0x8000) /* Correct Transfer Interrupt Mask */
-
-
-/******************* Bit definition for USB_ISTR register *******************/
-#define USB_ISTR_EP_ID ((u16)0x000F) /* Endpoint Identifier */
-#define USB_ISTR_DIR ((u16)0x0010) /* Direction of transaction */
-#define USB_ISTR_ESOF ((u16)0x0100) /* Expected Start Of Frame */
-#define USB_ISTR_SOF ((u16)0x0200) /* Start Of Frame */
-#define USB_ISTR_RESET ((u16)0x0400) /* USB RESET request */
-#define USB_ISTR_SUSP ((u16)0x0800) /* Suspend mode request */
-#define USB_ISTR_WKUP ((u16)0x1000) /* Wake up */
-#define USB_ISTR_ERR ((u16)0x2000) /* Error */
-#define USB_ISTR_PMAOVR ((u16)0x4000) /* Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR ((u16)0x8000) /* Correct Transfer */
-
-
-/******************* Bit definition for USB_FNR register ********************/
-#define USB_FNR_FN ((u16)0x07FF) /* Frame Number */
-#define USB_FNR_LSOF ((u16)0x1800) /* Lost SOF */
-#define USB_FNR_LCK ((u16)0x2000) /* Locked */
-#define USB_FNR_RXDM ((u16)0x4000) /* Receive Data - Line Status */
-#define USB_FNR_RXDP ((u16)0x8000) /* Receive Data + Line Status */
-
-
-/****************** Bit definition for USB_DADDR register *******************/
-#define USB_DADDR_ADD ((u8)0x7F) /* ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0 ((u8)0x01) /* Bit 0 */
-#define USB_DADDR_ADD1 ((u8)0x02) /* Bit 1 */
-#define USB_DADDR_ADD2 ((u8)0x04) /* Bit 2 */
-#define USB_DADDR_ADD3 ((u8)0x08) /* Bit 3 */
-#define USB_DADDR_ADD4 ((u8)0x10) /* Bit 4 */
-#define USB_DADDR_ADD5 ((u8)0x20) /* Bit 5 */
-#define USB_DADDR_ADD6 ((u8)0x40) /* Bit 6 */
-
-#define USB_DADDR_EF ((u8)0x80) /* Enable Function */
-
-
-/****************** Bit definition for USB_BTABLE register ******************/
-#define USB_BTABLE_BTABLE ((u16)0xFFF8) /* Buffer Table */
-
-
-/* Buffer descriptor table */
-/***************** Bit definition for USB_ADDR0_TX register *****************/
-#define USB_ADDR0_TX_ADDR0_TX ((u16)0xFFFE) /* Transmission Buffer Address 0 */
-
-
-/***************** Bit definition for USB_ADDR1_TX register *****************/
-#define USB_ADDR1_TX_ADDR1_TX ((u16)0xFFFE) /* Transmission Buffer Address 1 */
-
-
-/***************** Bit definition for USB_ADDR2_TX register *****************/
-#define USB_ADDR2_TX_ADDR2_TX ((u16)0xFFFE) /* Transmission Buffer Address 2 */
-
-
-/***************** Bit definition for USB_ADDR3_TX register *****************/
-#define USB_ADDR3_TX_ADDR3_TX ((u16)0xFFFE) /* Transmission Buffer Address 3 */
-
-
-/***************** Bit definition for USB_ADDR4_TX register *****************/
-#define USB_ADDR4_TX_ADDR4_TX ((u16)0xFFFE) /* Transmission Buffer Address 4 */
-
-
-/***************** Bit definition for USB_ADDR5_TX register *****************/
-#define USB_ADDR5_TX_ADDR5_TX ((u16)0xFFFE) /* Transmission Buffer Address 5 */
-
-
-/***************** Bit definition for USB_ADDR6_TX register *****************/
-#define USB_ADDR6_TX_ADDR6_TX ((u16)0xFFFE) /* Transmission Buffer Address 6 */
-
-
-/***************** Bit definition for USB_ADDR7_TX register *****************/
-#define USB_ADDR7_TX_ADDR7_TX ((u16)0xFFFE) /* Transmission Buffer Address 7 */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/***************** Bit definition for USB_COUNT0_TX register ****************/
-#define USB_COUNT0_TX_COUNT0_TX ((u16)0x03FF) /* Transmission Byte Count 0 */
-
-
-/***************** Bit definition for USB_COUNT1_TX register ****************/
-#define USB_COUNT1_TX_COUNT1_TX ((u16)0x03FF) /* Transmission Byte Count 1 */
-
-
-/***************** Bit definition for USB_COUNT2_TX register ****************/
-#define USB_COUNT2_TX_COUNT2_TX ((u16)0x03FF) /* Transmission Byte Count 2 */
-
-
-/***************** Bit definition for USB_COUNT3_TX register ****************/
-#define USB_COUNT3_TX_COUNT3_TX ((u16)0x03FF) /* Transmission Byte Count 3 */
-
-
-/***************** Bit definition for USB_COUNT4_TX register ****************/
-#define USB_COUNT4_TX_COUNT4_TX ((u16)0x03FF) /* Transmission Byte Count 4 */
-
-/***************** Bit definition for USB_COUNT5_TX register ****************/
-#define USB_COUNT5_TX_COUNT5_TX ((u16)0x03FF) /* Transmission Byte Count 5 */
-
-
-/***************** Bit definition for USB_COUNT6_TX register ****************/
-#define USB_COUNT6_TX_COUNT6_TX ((u16)0x03FF) /* Transmission Byte Count 6 */
-
-
-/***************** Bit definition for USB_COUNT7_TX register ****************/
-#define USB_COUNT7_TX_COUNT7_TX ((u16)0x03FF) /* Transmission Byte Count 7 */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 0 (low) */
-
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 0 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 1 (low) */
-
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 1 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 2 (low) */
-
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 2 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((u16)0x000003FF) /* Transmission Byte Count 3 (low) */
-
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((u16)0x03FF0000) /* Transmission Byte Count 3 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 4 (low) */
-
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 4 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 5 (low) */
-
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 5 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 6 (low) */
-
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 6 (high) */
-
-
-
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 7 (low) */
-
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 7 (high) */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/***************** Bit definition for USB_ADDR0_RX register *****************/
-#define USB_ADDR0_RX_ADDR0_RX ((u16)0xFFFE) /* Reception Buffer Address 0 */
-
-
-/***************** Bit definition for USB_ADDR1_RX register *****************/
-#define USB_ADDR1_RX_ADDR1_RX ((u16)0xFFFE) /* Reception Buffer Address 1 */
-
-
-/***************** Bit definition for USB_ADDR2_RX register *****************/
-#define USB_ADDR2_RX_ADDR2_RX ((u16)0xFFFE) /* Reception Buffer Address 2 */
-
-
-/***************** Bit definition for USB_ADDR3_RX register *****************/
-#define USB_ADDR3_RX_ADDR3_RX ((u16)0xFFFE) /* Reception Buffer Address 3 */
-
-
-/***************** Bit definition for USB_ADDR4_RX register *****************/
-#define USB_ADDR4_RX_ADDR4_RX ((u16)0xFFFE) /* Reception Buffer Address 4 */
-
-
-/***************** Bit definition for USB_ADDR5_RX register *****************/
-#define USB_ADDR5_RX_ADDR5_RX ((u16)0xFFFE) /* Reception Buffer Address 5 */
-
-
-/***************** Bit definition for USB_ADDR6_RX register *****************/
-#define USB_ADDR6_RX_ADDR6_RX ((u16)0xFFFE) /* Reception Buffer Address 6 */
-
-
-/***************** Bit definition for USB_ADDR7_RX register *****************/
-#define USB_ADDR7_RX_ADDR7_RX ((u16)0xFFFE) /* Reception Buffer Address 7 */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/***************** Bit definition for USB_COUNT0_RX register ****************/
-#define USB_COUNT0_RX_COUNT0_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT0_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT0_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT0_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT0_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT0_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/***************** Bit definition for USB_COUNT1_RX register ****************/
-#define USB_COUNT1_RX_COUNT1_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT1_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT1_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT1_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT1_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT1_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/***************** Bit definition for USB_COUNT2_RX register ****************/
-#define USB_COUNT2_RX_COUNT2_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT2_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT2_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT2_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT2_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT2_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/***************** Bit definition for USB_COUNT3_RX register ****************/
-#define USB_COUNT3_RX_COUNT3_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT3_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT3_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT3_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT3_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT3_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/***************** Bit definition for USB_COUNT4_RX register ****************/
-#define USB_COUNT4_RX_COUNT4_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT4_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT4_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT4_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT4_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT4_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/***************** Bit definition for USB_COUNT5_RX register ****************/
-#define USB_COUNT5_RX_COUNT5_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT5_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT5_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT5_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT5_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT5_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-/***************** Bit definition for USB_COUNT6_RX register ****************/
-#define USB_COUNT6_RX_COUNT6_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT6_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT6_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT6_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT6_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT6_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/***************** Bit definition for USB_COUNT7_RX register ****************/
-#define USB_COUNT7_RX_COUNT7_RX ((u16)0x03FF) /* Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
-#define USB_COUNT7_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
-#define USB_COUNT7_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
-#define USB_COUNT7_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
-#define USB_COUNT7_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
-
-#define USB_COUNT7_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
-
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
-
-
-
-/******************************************************************************/
-/* */
-/* Controller Area Network */
-/* */
-/******************************************************************************/
-
-/* CAN control and status registers */
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ ((u16)0x0001) /* Initialization Request */
-#define CAN_MCR_SLEEP ((u16)0x0002) /* Sleep Mode Request */
-#define CAN_MCR_TXFP ((u16)0x0004) /* Transmit FIFO Priority */
-#define CAN_MCR_RFLM ((u16)0x0008) /* Receive FIFO Locked Mode */
-#define CAN_MCR_NART ((u16)0x0010) /* No Automatic Retransmission */
-#define CAN_MCR_AWUM ((u16)0x0020) /* Automatic Wakeup Mode */
-#define CAN_MCR_ABOM ((u16)0x0040) /* Automatic Bus-Off Management */
-#define CAN_MCR_TTCM ((u16)0x0080) /* Time Triggered Communication Mode */
-#define CAN_MCR_RESET ((u16)0x8000) /* bxCAN software master reset */
-
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK ((u16)0x0001) /* Initialization Acknowledge */
-#define CAN_MSR_SLAK ((u16)0x0002) /* Sleep Acknowledge */
-#define CAN_MSR_ERRI ((u16)0x0004) /* Error Interrupt */
-#define CAN_MSR_WKUI ((u16)0x0008) /* Wakeup Interrupt */
-#define CAN_MSR_SLAKI ((u16)0x0010) /* Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM ((u16)0x0100) /* Transmit Mode */
-#define CAN_MSR_RXM ((u16)0x0200) /* Receive Mode */
-#define CAN_MSR_SAMP ((u16)0x0400) /* Last Sample Point */
-#define CAN_MSR_RX ((u16)0x0800) /* CAN Rx Signal */
-
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0 ((u32)0x00000004) /* Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0 ((u32)0x00000008) /* Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1 ((u32)0x00000400) /* Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1 ((u32)0x00000800) /* Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2 ((u32)0x00040000) /* Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2 ((u32)0x00080000) /* Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE ((u32)0x03000000) /* Mailbox Code */
-
-#define CAN_TSR_TME ((u32)0x1C000000) /* TME[2:0] bits */
-#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW ((u32)0xE0000000) /* LOW[2:0] bits */
-#define CAN_TSR_LOW0 ((u32)0x20000000) /* Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1 ((u32)0x40000000) /* Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2 ((u32)0x80000000) /* Lowest Priority Flag for Mailbox 2 */
-
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0 ((u8)0x03) /* FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0 ((u8)0x08) /* FIFO 0 Full */
-#define CAN_RF0R_FOVR0 ((u8)0x10) /* FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0 ((u8)0x20) /* Release FIFO 0 Output Mailbox */
-
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1 ((u8)0x03) /* FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1 ((u8)0x08) /* FIFO 1 Full */
-#define CAN_RF1R_FOVR1 ((u8)0x10) /* FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1 ((u8)0x20) /* Release FIFO 1 Output Mailbox */
-
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE ((u32)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0 ((u32)0x00000002) /* FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0 ((u32)0x00000004) /* FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0 ((u32)0x00000008) /* FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1 ((u32)0x00000010) /* FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1 ((u32)0x00000020) /* FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1 ((u32)0x00000040) /* FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE ((u32)0x00000100) /* Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE ((u32)0x00000200) /* Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE ((u32)0x00000400) /* Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE ((u32)0x00000800) /* Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE ((u32)0x00008000) /* Error Interrupt Enable */
-#define CAN_IER_WKUIE ((u32)0x00010000) /* Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE ((u32)0x00020000) /* Sleep Interrupt Enable */
-
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF ((u32)0x00000001) /* Error Warning Flag */
-#define CAN_ESR_EPVF ((u32)0x00000002) /* Error Passive Flag */
-#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-Off Flag */
-
-#define CAN_ESR_LEC ((u32)0x00000070) /* LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 ((u32)0x00000010) /* Bit 0 */
-#define CAN_ESR_LEC_1 ((u32)0x00000020) /* Bit 1 */
-#define CAN_ESR_LEC_2 ((u32)0x00000040) /* Bit 2 */
-
-#define CAN_ESR_TEC ((u32)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC ((u32)0xFF000000) /* Receive Error Counter */
-
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP ((u32)0x000003FF) /* Baud Rate Prescaler */
-#define CAN_BTR_TS1 ((u32)0x000F0000) /* Time Segment 1 */
-#define CAN_BTR_TS2 ((u32)0x00700000) /* Time Segment 2 */
-#define CAN_BTR_SJW ((u32)0x03000000) /* Resynchronization Jump Width */
-#define CAN_BTR_LBKM ((u32)0x40000000) /* Loop Back Mode (Debug) */
-#define CAN_BTR_SILM ((u32)0x80000000) /* Silent Mode */
-
-
-/* Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */
-#define CAN_TI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */
-#define CAN_TI0R_IDE ((u32)0x00000004) /* Identifier Extension */
-#define CAN_TI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */
-#define CAN_TI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
-
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC ((u32)0x0000000F) /* Data Length Code */
-#define CAN_TDT0R_TGT ((u32)0x00000100) /* Transmit Global Time */
-#define CAN_TDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
-
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
-#define CAN_TDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
-#define CAN_TDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
-#define CAN_TDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
-
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
-#define CAN_TDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
-#define CAN_TDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
-#define CAN_TDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
-
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */
-#define CAN_TI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */
-#define CAN_TI1R_IDE ((u32)0x00000004) /* Identifier Extension */
-#define CAN_TI1R_EXID ((u32)0x001FFFF8) /* Extended Identifier */
-#define CAN_TI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
-
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC ((u32)0x0000000F) /* Data Length Code */
-#define CAN_TDT1R_TGT ((u32)0x00000100) /* Transmit Global Time */
-#define CAN_TDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
-
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
-#define CAN_TDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
-#define CAN_TDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
-#define CAN_TDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
-
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
-#define CAN_TDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
-#define CAN_TDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
-#define CAN_TDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
-
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */
-#define CAN_TI2R_RTR ((u32)0x00000002) /* Remote Transmission Request */
-#define CAN_TI2R_IDE ((u32)0x00000004) /* Identifier Extension */
-#define CAN_TI2R_EXID ((u32)0x001FFFF8) /* Extended identifier */
-#define CAN_TI2R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
-
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC ((u32)0x0000000F) /* Data Length Code */
-#define CAN_TDT2R_TGT ((u32)0x00000100) /* Transmit Global Time */
-#define CAN_TDT2R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
-
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
-#define CAN_TDL2R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
-#define CAN_TDL2R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
-#define CAN_TDL2R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
-
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
-#define CAN_TDH2R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
-#define CAN_TDH2R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
-#define CAN_TDH2R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
-
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */
-#define CAN_RI0R_IDE ((u32)0x00000004) /* Identifier Extension */
-#define CAN_RI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */
-#define CAN_RI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
-
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC ((u32)0x0000000F) /* Data Length Code */
-#define CAN_RDT0R_FMI ((u32)0x0000FF00) /* Filter Match Index */
-#define CAN_RDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
-
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
-#define CAN_RDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
-#define CAN_RDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
-#define CAN_RDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
-
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
-#define CAN_RDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
-#define CAN_RDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
-#define CAN_RDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
-
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */
-#define CAN_RI1R_IDE ((u32)0x00000004) /* Identifier Extension */
-#define CAN_RI1R_EXID ((u32)0x001FFFF8) /* Extended identifier */
-#define CAN_RI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
-
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC ((u32)0x0000000F) /* Data Length Code */
-#define CAN_RDT1R_FMI ((u32)0x0000FF00) /* Filter Match Index */
-#define CAN_RDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
-
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
-#define CAN_RDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
-#define CAN_RDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
-#define CAN_RDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
-
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
-#define CAN_RDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
-#define CAN_RDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
-#define CAN_RDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
-
-/* CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT ((u8)0x01) /* Filter Init Mode */
-
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((u16)0x3FFF) /* Filter Mode */
-#define CAN_FM1R_FBM0 ((u16)0x0001) /* Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((u16)0x0002) /* Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((u16)0x0004) /* Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((u16)0x0008) /* Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((u16)0x0010) /* Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((u16)0x0020) /* Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((u16)0x0040) /* Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((u16)0x0080) /* Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((u16)0x0100) /* Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((u16)0x0200) /* Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((u16)0x0400) /* Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((u16)0x0800) /* Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((u16)0x1000) /* Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((u16)0x2000) /* Filter Init Mode bit 13 */
-
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((u16)0x3FFF) /* Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((u16)0x0001) /* Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((u16)0x0002) /* Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((u16)0x0004) /* Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((u16)0x0008) /* Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((u16)0x0010) /* Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((u16)0x0020) /* Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((u16)0x0040) /* Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((u16)0x0080) /* Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((u16)0x0100) /* Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((u16)0x0200) /* Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((u16)0x0400) /* Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((u16)0x0800) /* Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((u16)0x1000) /* Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((u16)0x2000) /* Filter Scale Configuration bit 13 */
-
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((u16)0x3FFF) /* Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((u16)0x0001) /* Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((u16)0x0002) /* Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((u16)0x0004) /* Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((u16)0x0008) /* Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((u16)0x0010) /* Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((u16)0x0020) /* Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((u16)0x0040) /* Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((u16)0x0080) /* Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((u16)0x0100) /* Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((u16)0x0200) /* Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((u16)0x0400) /* Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((u16)0x0800) /* Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((u16)0x1000) /* Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((u16)0x2000) /* Filter FIFO Assignment for Filter 13 */
-
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((u16)0x3FFF) /* Filter Active */
-#define CAN_FA1R_FACT0 ((u16)0x0001) /* Filter 0 Active */
-#define CAN_FA1R_FACT1 ((u16)0x0002) /* Filter 1 Active */
-#define CAN_FA1R_FACT2 ((u16)0x0004) /* Filter 2 Active */
-#define CAN_FA1R_FACT3 ((u16)0x0008) /* Filter 3 Active */
-#define CAN_FA1R_FACT4 ((u16)0x0010) /* Filter 4 Active */
-#define CAN_FA1R_FACT5 ((u16)0x0020) /* Filter 5 Active */
-#define CAN_FA1R_FACT6 ((u16)0x0040) /* Filter 6 Active */
-#define CAN_FA1R_FACT7 ((u16)0x0080) /* Filter 7 Active */
-#define CAN_FA1R_FACT8 ((u16)0x0100) /* Filter 8 Active */
-#define CAN_FA1R_FACT9 ((u16)0x0200) /* Filter 9 Active */
-#define CAN_FA1R_FACT10 ((u16)0x0400) /* Filter 10 Active */
-#define CAN_FA1R_FACT11 ((u16)0x0800) /* Filter 11 Active */
-#define CAN_FA1R_FACT12 ((u16)0x1000) /* Filter 12 Active */
-#define CAN_FA1R_FACT13 ((u16)0x2000) /* Filter 13 Active */
-
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F0R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F0R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F0R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F0R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F0R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F0R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F0R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F0R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F0R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F0R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F0R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F0R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F0R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F0R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F0R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F0R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F0R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F0R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F0R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F0R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F0R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F0R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F0R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F0R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F0R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F0R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F0R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F0R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F0R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F0R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F0R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F1R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F1R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F1R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F1R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F1R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F1R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F1R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F1R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F1R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F1R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F1R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F1R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F1R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F1R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F1R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F1R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F1R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F1R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F1R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F1R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F1R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F1R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F1R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F1R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F1R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F1R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F1R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F1R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F1R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F1R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F1R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F2R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F2R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F2R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F2R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F2R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F2R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F2R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F2R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F2R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F2R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F2R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F2R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F2R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F2R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F2R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F2R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F2R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F2R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F2R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F2R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F2R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F2R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F2R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F2R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F2R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F2R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F2R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F2R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F2R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F2R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F2R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F3R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F3R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F3R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F3R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F3R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F3R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F3R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F3R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F3R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F3R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F3R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F3R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F3R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F3R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F3R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F3R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F3R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F3R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F3R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F3R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F3R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F3R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F3R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F3R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F3R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F3R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F3R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F3R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F3R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F3R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F3R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F4R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F4R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F4R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F4R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F4R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F4R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F4R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F4R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F4R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F4R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F4R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F4R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F4R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F4R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F4R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F4R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F4R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F4R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F4R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F4R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F4R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F4R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F4R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F4R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F4R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F4R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F4R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F4R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F4R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F4R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F4R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F5R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F5R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F5R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F5R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F5R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F5R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F5R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F5R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F5R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F5R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F5R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F5R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F5R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F5R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F5R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F5R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F5R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F5R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F5R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F5R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F5R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F5R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F5R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F5R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F5R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F5R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F5R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F5R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F5R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F5R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F5R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F6R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F6R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F6R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F6R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F6R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F6R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F6R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F6R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F6R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F6R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F6R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F6R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F6R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F6R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F6R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F6R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F6R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F6R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F6R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F6R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F6R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F6R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F6R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F6R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F6R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F6R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F6R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F6R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F6R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F6R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F6R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F7R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F7R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F7R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F7R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F7R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F7R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F7R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F7R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F7R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F7R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F7R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F7R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F7R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F7R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F7R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F7R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F7R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F7R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F7R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F7R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F7R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F7R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F7R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F7R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F7R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F7R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F7R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F7R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F7R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F7R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F7R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F8R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F8R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F8R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F8R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F8R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F8R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F8R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F8R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F8R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F8R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F8R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F8R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F8R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F8R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F8R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F8R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F8R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F8R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F8R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F8R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F8R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F8R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F8R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F8R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F8R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F8R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F8R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F8R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F8R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F8R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F8R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F9R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F9R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F9R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F9R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F9R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F9R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F9R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F9R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F9R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F9R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F9R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F9R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F9R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F9R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F9R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F9R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F9R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F9R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F9R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F9R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F9R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F9R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F9R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F9R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F9R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F9R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F9R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F9R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F9R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F9R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F9R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F10R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F10R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F10R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F10R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F10R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F10R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F10R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F10R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F10R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F10R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F10R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F10R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F10R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F10R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F10R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F10R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F10R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F10R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F10R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F10R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F10R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F10R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F10R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F10R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F10R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F10R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F10R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F10R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F10R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F10R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F10R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F11R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F11R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F11R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F11R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F11R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F11R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F11R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F11R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F11R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F11R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F11R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F11R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F11R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F11R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F11R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F11R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F11R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F11R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F11R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F11R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F11R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F11R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F11R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F11R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F11R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F11R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F11R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F11R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F11R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F11R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F11R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F12R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F12R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F12R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F12R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F12R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F12R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F12R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F12R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F12R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F12R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F12R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F12R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F12R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F12R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F12R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F12R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F12R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F12R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F12R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F12R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F12R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F12R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F12R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F12R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F12R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F12R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F12R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F12R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F12R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F12R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F12R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F13R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F13R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F13R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F13R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F13R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F13R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F13R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F13R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F13R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F13R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F13R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F13R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F13R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F13R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F13R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F13R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F13R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F13R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F13R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F13R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F13R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F13R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F13R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F13R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F13R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F13R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F13R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F13R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F13R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F13R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F13R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F0R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F0R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F0R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F0R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F0R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F0R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F0R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F0R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F0R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F0R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F0R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F0R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F0R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F0R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F0R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F0R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F0R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F0R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F0R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F0R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F0R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F0R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F0R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F0R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F0R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F0R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F0R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F0R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F0R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F0R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F0R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F1R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F1R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F1R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F1R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F1R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F1R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F1R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F1R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F1R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F1R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F1R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F1R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F1R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F1R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F1R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F1R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F1R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F1R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F1R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F1R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F1R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F1R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F1R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F1R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F1R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F1R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F1R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F1R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F1R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F1R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F1R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F2R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F2R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F2R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F2R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F2R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F2R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F2R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F2R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F2R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F2R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F2R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F2R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F2R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F2R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F2R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F2R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F2R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F2R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F2R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F2R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F2R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F2R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F2R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F2R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F2R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F2R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F2R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F2R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F2R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F2R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F2R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F3R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F3R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F3R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F3R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F3R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F3R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F3R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F3R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F3R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F3R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F3R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F3R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F3R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F3R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F3R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F3R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F3R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F3R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F3R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F3R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F3R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F3R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F3R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F3R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F3R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F3R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F3R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F3R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F3R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F3R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F3R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F4R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F4R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F4R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F4R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F4R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F4R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F4R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F4R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F4R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F4R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F4R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F4R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F4R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F4R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F4R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F4R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F4R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F4R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F4R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F4R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F4R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F4R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F4R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F4R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F4R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F4R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F4R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F4R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F4R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F4R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F4R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F5R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F5R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F5R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F5R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F5R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F5R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F5R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F5R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F5R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F5R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F5R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F5R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F5R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F5R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F5R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F5R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F5R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F5R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F5R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F5R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F5R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F5R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F5R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F5R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F5R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F5R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F5R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F5R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F5R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F5R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F5R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F6R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F6R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F6R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F6R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F6R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F6R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F6R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F6R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F6R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F6R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F6R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F6R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F6R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F6R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F6R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F6R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F6R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F6R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F6R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F6R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F6R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F6R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F6R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F6R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F6R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F6R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F6R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F6R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F6R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F6R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F6R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F7R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F7R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F7R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F7R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F7R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F7R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F7R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F7R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F7R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F7R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F7R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F7R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F7R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F7R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F7R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F7R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F7R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F7R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F7R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F7R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F7R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F7R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F7R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F7R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F7R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F7R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F7R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F7R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F7R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F7R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F7R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F8R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F8R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F8R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F8R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F8R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F8R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F8R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F8R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F8R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F8R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F8R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F8R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F8R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F8R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F8R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F8R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F8R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F8R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F8R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F8R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F8R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F8R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F8R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F8R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F8R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F8R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F8R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F8R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F8R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F8R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F8R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F9R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F9R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F9R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F9R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F9R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F9R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F9R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F9R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F9R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F9R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F9R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F9R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F9R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F9R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F9R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F9R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F9R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F9R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F9R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F9R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F9R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F9R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F9R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F9R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F9R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F9R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F9R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F9R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F9R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F9R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F9R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F10R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F10R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F10R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F10R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F10R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F10R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F10R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F10R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F10R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F10R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F10R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F10R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F10R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F10R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F10R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F10R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F10R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F10R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F10R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F10R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F10R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F10R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F10R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F10R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F10R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F10R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F10R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F10R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F10R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F10R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F10R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F11R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F11R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F11R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F11R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F11R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F11R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F11R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F11R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F11R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F11R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F11R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F11R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F11R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F11R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F11R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F11R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F11R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F11R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F11R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F11R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F11R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F11R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F11R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F11R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F11R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F11R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F11R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F11R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F11R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F11R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F11R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F12R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F12R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F12R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F12R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F12R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F12R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F12R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F12R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F12R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F12R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F12R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F12R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F12R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F12R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F12R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F12R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F12R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F12R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F12R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F12R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F12R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F12R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F12R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F12R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F12R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F12R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F12R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F12R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F12R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F12R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F12R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
-#define CAN_F13R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
-#define CAN_F13R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
-#define CAN_F13R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
-#define CAN_F13R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
-#define CAN_F13R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
-#define CAN_F13R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
-#define CAN_F13R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
-#define CAN_F13R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
-#define CAN_F13R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
-#define CAN_F13R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
-#define CAN_F13R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
-#define CAN_F13R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
-#define CAN_F13R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
-#define CAN_F13R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
-#define CAN_F13R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
-#define CAN_F13R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
-#define CAN_F13R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
-#define CAN_F13R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
-#define CAN_F13R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
-#define CAN_F13R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
-#define CAN_F13R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
-#define CAN_F13R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
-#define CAN_F13R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
-#define CAN_F13R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
-#define CAN_F13R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
-#define CAN_F13R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
-#define CAN_F13R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
-#define CAN_F13R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
-#define CAN_F13R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
-#define CAN_F13R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
-#define CAN_F13R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
-
-
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((u16)0x0001) /* Clock Phase */
-#define SPI_CR1_CPOL ((u16)0x0002) /* Clock Polarity */
-#define SPI_CR1_MSTR ((u16)0x0004) /* Master Selection */
-
-#define SPI_CR1_BR ((u16)0x0038) /* BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((u16)0x0008) /* Bit 0 */
-#define SPI_CR1_BR_1 ((u16)0x0010) /* Bit 1 */
-#define SPI_CR1_BR_2 ((u16)0x0020) /* Bit 2 */
-
-#define SPI_CR1_SPE ((u16)0x0040) /* SPI Enable */
-#define SPI_CR1_LSBFIRST ((u16)0x0080) /* Frame Format */
-#define SPI_CR1_SSI ((u16)0x0100) /* Internal slave select */
-#define SPI_CR1_SSM ((u16)0x0200) /* Software slave management */
-#define SPI_CR1_RXONLY ((u16)0x0400) /* Receive only */
-#define SPI_CR1_DFF ((u16)0x0800) /* Data Frame Format */
-#define SPI_CR1_CRCNEXT ((u16)0x1000) /* Transmit CRC next */
-#define SPI_CR1_CRCEN ((u16)0x2000) /* Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((u16)0x4000) /* Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((u16)0x8000) /* Bidirectional data mode enable */
-
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((u8)0x01) /* Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((u8)0x02) /* Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((u8)0x04) /* SS Output Enable */
-#define SPI_CR2_ERRIE ((u8)0x20) /* Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((u8)0x40) /* RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((u8)0x80) /* Tx buffer Empty Interrupt Enable */
-
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((u8)0x01) /* Receive buffer Not Empty */
-#define SPI_SR_TXE ((u8)0x02) /* Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((u8)0x04) /* Channel side */
-#define SPI_SR_UDR ((u8)0x08) /* Underrun flag */
-#define SPI_SR_CRCERR ((u8)0x10) /* CRC Error flag */
-#define SPI_SR_MODF ((u8)0x20) /* Mode fault */
-#define SPI_SR_OVR ((u8)0x40) /* Overrun flag */
-#define SPI_SR_BSY ((u8)0x80) /* Busy flag */
-
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((u16)0xFFFF) /* Data Register */
-
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((u16)0xFFFF) /* CRC polynomial register */
-
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((u16)0xFFFF) /* Rx CRC Register */
-
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((u16)0xFFFF) /* Tx CRC Register */
-
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((u16)0x0001) /* Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN ((u16)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((u16)0x0002) /* Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((u16)0x0004) /* Bit 1 */
-
-#define SPI_I2SCFGR_CKPOL ((u16)0x0008) /* steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD ((u16)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((u16)0x0010) /* Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((u16)0x0020) /* Bit 1 */
-
-#define SPI_I2SCFGR_PCMSYNC ((u16)0x0080) /* PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG ((u16)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((u16)0x0100) /* Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((u16)0x0200) /* Bit 1 */
-
-#define SPI_I2SCFGR_I2SE ((u16)0x0400) /* I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((u16)0x0800) /* I2S mode selection */
-
-
-/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((u16)0x00FF) /* I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((u16)0x0100) /* Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((u16)0x0200) /* Master Clock Output Enable */
-
-
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE ((u16)0x0001) /* Peripheral Enable */
-#define I2C_CR1_SMBUS ((u16)0x0002) /* SMBus Mode */
-#define I2C_CR1_SMBTYPE ((u16)0x0008) /* SMBus Type */
-#define I2C_CR1_ENARP ((u16)0x0010) /* ARP Enable */
-#define I2C_CR1_ENPEC ((u16)0x0020) /* PEC Enable */
-#define I2C_CR1_ENGC ((u16)0x0040) /* General Call Enable */
-#define I2C_CR1_NOSTRETCH ((u16)0x0080) /* Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START ((u16)0x0100) /* Start Generation */
-#define I2C_CR1_STOP ((u16)0x0200) /* Stop Generation */
-#define I2C_CR1_ACK ((u16)0x0400) /* Acknowledge Enable */
-#define I2C_CR1_POS ((u16)0x0800) /* Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC ((u16)0x1000) /* Packet Error Checking */
-#define I2C_CR1_ALERT ((u16)0x2000) /* SMBus Alert */
-#define I2C_CR1_SWRST ((u16)0x8000) /* Software Reset */
-
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ ((u16)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 ((u16)0x0001) /* Bit 0 */
-#define I2C_CR2_FREQ_1 ((u16)0x0002) /* Bit 1 */
-#define I2C_CR2_FREQ_2 ((u16)0x0004) /* Bit 2 */
-#define I2C_CR2_FREQ_3 ((u16)0x0008) /* Bit 3 */
-#define I2C_CR2_FREQ_4 ((u16)0x0010) /* Bit 4 */
-#define I2C_CR2_FREQ_5 ((u16)0x0020) /* Bit 5 */
-
-#define I2C_CR2_ITERREN ((u16)0x0100) /* Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN ((u16)0x0200) /* Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN ((u16)0x0400) /* Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN ((u16)0x0800) /* DMA Requests Enable */
-#define I2C_CR2_LAST ((u16)0x1000) /* DMA Last Transfer */
-
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((u16)0x00FE) /* Interface Address */
-#define I2C_OAR1_ADD8_9 ((u16)0x0300) /* Interface Address */
-
-#define I2C_OAR1_ADD0 ((u16)0x0001) /* Bit 0 */
-#define I2C_OAR1_ADD1 ((u16)0x0002) /* Bit 1 */
-#define I2C_OAR1_ADD2 ((u16)0x0004) /* Bit 2 */
-#define I2C_OAR1_ADD3 ((u16)0x0008) /* Bit 3 */
-#define I2C_OAR1_ADD4 ((u16)0x0010) /* Bit 4 */
-#define I2C_OAR1_ADD5 ((u16)0x0020) /* Bit 5 */
-#define I2C_OAR1_ADD6 ((u16)0x0040) /* Bit 6 */
-#define I2C_OAR1_ADD7 ((u16)0x0080) /* Bit 7 */
-#define I2C_OAR1_ADD8 ((u16)0x0100) /* Bit 8 */
-#define I2C_OAR1_ADD9 ((u16)0x0200) /* Bit 9 */
-
-#define I2C_OAR1_ADDMODE ((u16)0x8000) /* Addressing Mode (Slave mode) */
-
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL ((u8)0x01) /* Dual addressing mode enable */
-#define I2C_OAR2_ADD2 ((u8)0xFE) /* Interface address */
-
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR ((u8)0xFF) /* 8-bit Data Register */
-
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB ((u16)0x0001) /* Start Bit (Master mode) */
-#define I2C_SR1_ADDR ((u16)0x0002) /* Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF ((u16)0x0004) /* Byte Transfer Finished */
-#define I2C_SR1_ADD10 ((u16)0x0008) /* 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF ((u16)0x0010) /* Stop detection (Slave mode) */
-#define I2C_SR1_RXNE ((u16)0x0040) /* Data Register not Empty (receivers) */
-#define I2C_SR1_TXE ((u16)0x0080) /* Data Register Empty (transmitters) */
-#define I2C_SR1_BERR ((u16)0x0100) /* Bus Error */
-#define I2C_SR1_ARLO ((u16)0x0200) /* Arbitration Lost (master mode) */
-#define I2C_SR1_AF ((u16)0x0400) /* Acknowledge Failure */
-#define I2C_SR1_OVR ((u16)0x0800) /* Overrun/Underrun */
-#define I2C_SR1_PECERR ((u16)0x1000) /* PEC Error in reception */
-#define I2C_SR1_TIMEOUT ((u16)0x4000) /* Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT ((u16)0x8000) /* SMBus Alert */
-
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL ((u16)0x0001) /* Master/Slave */
-#define I2C_SR2_BUSY ((u16)0x0002) /* Bus Busy */
-#define I2C_SR2_TRA ((u16)0x0004) /* Transmitter/Receiver */
-#define I2C_SR2_GENCALL ((u16)0x0010) /* General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT ((u16)0x0020) /* SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST ((u16)0x0040) /* SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF ((u16)0x0080) /* Dual Flag (Slave mode) */
-#define I2C_SR2_PEC ((u16)0xFF00) /* Packet Error Checking Register */
-
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR ((u16)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY ((u16)0x4000) /* Fast Mode Duty Cycle */
-#define I2C_CCR_FS ((u16)0x8000) /* I2C Master Mode Selection */
-
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE ((u8)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE ((u16)0x0001) /* Parity Error */
-#define USART_SR_FE ((u16)0x0002) /* Framing Error */
-#define USART_SR_NE ((u16)0x0004) /* Noise Error Flag */
-#define USART_SR_ORE ((u16)0x0008) /* OverRun Error */
-#define USART_SR_IDLE ((u16)0x0010) /* IDLE line detected */
-#define USART_SR_RXNE ((u16)0x0020) /* Read Data Register Not Empty */
-#define USART_SR_TC ((u16)0x0040) /* Transmission Complete */
-#define USART_SR_TXE ((u16)0x0080) /* Transmit Data Register Empty */
-#define USART_SR_LBD ((u16)0x0100) /* LIN Break Detection Flag */
-#define USART_SR_CTS ((u16)0x0200) /* CTS Flag */
-
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR ((u16)0x01FF) /* Data value */
-
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction ((u16)0x000F) /* Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa ((u16)0xFFF0) /* Mantissa of USARTDIV */
-
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK ((u16)0x0001) /* Send Break */
-#define USART_CR1_RWU ((u16)0x0002) /* Receiver wakeup */
-#define USART_CR1_RE ((u16)0x0004) /* Receiver Enable */
-#define USART_CR1_TE ((u16)0x0008) /* Transmitter Enable */
-#define USART_CR1_IDLEIE ((u16)0x0010) /* IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((u16)0x0020) /* RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((u16)0x0040) /* Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((u16)0x0080) /* PE Interrupt Enable */
-#define USART_CR1_PEIE ((u16)0x0100) /* PE Interrupt Enable */
-#define USART_CR1_PS ((u16)0x0200) /* Parity Selection */
-#define USART_CR1_PCE ((u16)0x0400) /* Parity Control Enable */
-#define USART_CR1_WAKE ((u16)0x0800) /* Wakeup method */
-#define USART_CR1_M ((u16)0x1000) /* Word length */
-#define USART_CR1_UE ((u16)0x2000) /* USART Enable */
-
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD ((u16)0x000F) /* Address of the USART node */
-#define USART_CR2_LBDL ((u16)0x0020) /* LIN Break Detection Length */
-#define USART_CR2_LBDIE ((u16)0x0040) /* LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((u16)0x0100) /* Last Bit Clock pulse */
-#define USART_CR2_CPHA ((u16)0x0200) /* Clock Phase */
-#define USART_CR2_CPOL ((u16)0x0400) /* Clock Polarity */
-#define USART_CR2_CLKEN ((u16)0x0800) /* Clock Enable */
-
-#define USART_CR2_STOP ((u16)0x3000) /* STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((u16)0x1000) /* Bit 0 */
-#define USART_CR2_STOP_1 ((u16)0x2000) /* Bit 1 */
-
-#define USART_CR2_LINEN ((u16)0x4000) /* LIN mode enable */
-
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((u16)0x0001) /* Error Interrupt Enable */
-#define USART_CR3_IREN ((u16)0x0002) /* IrDA mode Enable */
-#define USART_CR3_IRLP ((u16)0x0004) /* IrDA Low-Power */
-#define USART_CR3_HDSEL ((u16)0x0008) /* Half-Duplex Selection */
-#define USART_CR3_NACK ((u16)0x0010) /* Smartcard NACK enable */
-#define USART_CR3_SCEN ((u16)0x0020) /* Smartcard mode enable */
-#define USART_CR3_DMAR ((u16)0x0040) /* DMA Enable Receiver */
-#define USART_CR3_DMAT ((u16)0x0080) /* DMA Enable Transmitter */
-#define USART_CR3_RTSE ((u16)0x0100) /* RTS Enable */
-#define USART_CR3_CTSE ((u16)0x0200) /* CTS Enable */
-#define USART_CR3_CTSIE ((u16)0x0400) /* CTS Interrupt Enable */
-
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((u16)0x00FF) /* PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 ((u16)0x0001) /* Bit 0 */
-#define USART_GTPR_PSC_1 ((u16)0x0002) /* Bit 1 */
-#define USART_GTPR_PSC_2 ((u16)0x0004) /* Bit 2 */
-#define USART_GTPR_PSC_3 ((u16)0x0008) /* Bit 3 */
-#define USART_GTPR_PSC_4 ((u16)0x0010) /* Bit 4 */
-#define USART_GTPR_PSC_5 ((u16)0x0020) /* Bit 5 */
-#define USART_GTPR_PSC_6 ((u16)0x0040) /* Bit 6 */
-#define USART_GTPR_PSC_7 ((u16)0x0080) /* Bit 7 */
-
-#define USART_GTPR_GT ((u16)0xFF00) /* Guard time value */
-
-
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((u32)0x00000FFF) /* Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((u32)0xFFFF0000) /* REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((u32)0x00010000) /* Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((u32)0x00020000) /* Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((u32)0x00040000) /* Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((u32)0x00080000) /* Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((u32)0x00100000) /* Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((u32)0x00200000) /* Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((u32)0x00400000) /* Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((u32)0x00800000) /* Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((u32)0x01000000) /* Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((u32)0x02000000) /* Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((u32)0x04000000) /* Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((u32)0x08000000) /* Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((u32)0x10000000) /* Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((u32)0x20000000) /* Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((u32)0x40000000) /* Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((u32)0x80000000) /* Bit 15 */
-
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_SLEEP ((u32)0x00000001) /* Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((u32)0x00000002) /* Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((u32)0x00000004) /* Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN ((u32)0x00000020) /* Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE ((u32)0x000000C0) /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0 ((u32)0x00000040) /* Bit 0 */
-#define DBGMCU_CR_TRACE_MODE_1 ((u32)0x00000080) /* Bit 1 */
-
-#define DBGMCU_CR_DBG_IWDG_STOP ((u32)0x00000100) /* Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_WWDG_STOP ((u32)0x00000200) /* Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM1_STOP ((u32)0x00000400) /* TIM1 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM2_STOP ((u32)0x00000800) /* TIM2 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM3_STOP ((u32)0x00001000) /* TIM3 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM4_STOP ((u32)0x00002000) /* TIM4 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN_STOP ((u32)0x00004000) /* Debug CAN stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) /* SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) /* SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM5_STOP ((u32)0x00020000) /* TIM5 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM6_STOP ((u32)0x00040000) /* TIM6 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM7_STOP ((u32)0x00080000) /* TIM7 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM8_STOP ((u32)0x00100000) /* TIM8 counter stopped when core is halted */
-
-
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((u8)0x07) /* LATENCY[2:0] bits (Latency) */
-#define FLASH_ACR_LATENCY_0 ((u8)0x01) /* Bit 0 */
-#define FLASH_ACR_LATENCY_1 ((u8)0x02) /* Bit 1 */
-#define FLASH_ACR_LATENCY_2 ((u8)0x04) /* Bit 2 */
-
-#define FLASH_ACR_HLFCYA ((u8)0x08) /* Flash Half Cycle Access Enable */
-#define FLASH_ACR_PRFTBE ((u8)0x10) /* Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS ((u8)0x20) /* Prefetch Buffer Status */
-
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR ((u32)0xFFFFFFFF) /* FPEC Key */
-
-
-/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR ((u32)0xFFFFFFFF) /* Option Byte Key */
-
-
-/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((u8)0x01) /* Busy */
-#define FLASH_SR_PGERR ((u8)0x04) /* Programming Error */
-#define FLASH_SR_WRPRTERR ((u8)0x10) /* Write Protection Error */
-#define FLASH_SR_EOP ((u8)0x20) /* End of operation */
-
-
-/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG ((u16)0x0001) /* Programming */
-#define FLASH_CR_PER ((u16)0x0002) /* Page Erase */
-#define FLASH_CR_MER ((u16)0x0004) /* Mass Erase */
-#define FLASH_CR_OPTPG ((u16)0x0010) /* Option Byte Programming */
-#define FLASH_CR_OPTER ((u16)0x0020) /* Option Byte Erase */
-#define FLASH_CR_STRT ((u16)0x0040) /* Start */
-#define FLASH_CR_LOCK ((u16)0x0080) /* Lock */
-#define FLASH_CR_OPTWRE ((u16)0x0200) /* Option Bytes Write Enable */
-#define FLASH_CR_ERRIE ((u16)0x0400) /* Error Interrupt Enable */
-#define FLASH_CR_EOPIE ((u16)0x1000) /* End of operation interrupt enable */
-
-
-/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR ((u32)0xFFFFFFFF) /* Flash Address */
-
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR ((u16)0x0001) /* Option Byte Error */
-#define FLASH_OBR_RDPRT ((u16)0x0002) /* Read protection */
-
-#define FLASH_OBR_USER ((u16)0x03FC) /* User Option Bytes */
-#define FLASH_OBR_WDG_SW ((u16)0x0004) /* WDG_SW */
-#define FLASH_OBR_nRST_STOP ((u16)0x0008) /* nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((u16)0x0010) /* nRST_STDBY */
-#define FLASH_OBR_Notused ((u16)0x03E0) /* Not used */
-
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((u32)0xFFFFFFFF) /* Write Protect */
-
-
-/*----------------------------------------------------------------------------*/
-
-
-/****************** Bit definition for FLASH_RDP register *******************/
-#define FLASH_RDP_RDP ((u32)0x000000FF) /* Read protection option byte */
-#define FLASH_RDP_nRDP ((u32)0x0000FF00) /* Read protection complemented option byte */
-
-
-/****************** Bit definition for FLASH_USER register ******************/
-#define FLASH_USER_USER ((u32)0x00FF0000) /* User option byte */
-#define FLASH_USER_nUSER ((u32)0xFF000000) /* User complemented option byte */
-
-
-/****************** Bit definition for FLASH_Data0 register *****************/
-#define FLASH_Data0_Data0 ((u32)0x000000FF) /* User data storage option byte */
-#define FLASH_Data0_nData0 ((u32)0x0000FF00) /* User data storage complemented option byte */
-
-
-/****************** Bit definition for FLASH_Data1 register *****************/
-#define FLASH_Data1_Data1 ((u32)0x00FF0000) /* User data storage option byte */
-#define FLASH_Data1_nData1 ((u32)0xFF000000) /* User data storage complemented option byte */
-
-
-/****************** Bit definition for FLASH_WRP0 register ******************/
-#define FLASH_WRP0_WRP0 ((u32)0x000000FF) /* Flash memory write protection option bytes */
-#define FLASH_WRP0_nWRP0 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */
-
-
-/****************** Bit definition for FLASH_WRP1 register ******************/
-#define FLASH_WRP1_WRP1 ((u32)0x00FF0000) /* Flash memory write protection option bytes */
-#define FLASH_WRP1_nWRP1 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */
-
-
-/****************** Bit definition for FLASH_WRP2 register ******************/
-#define FLASH_WRP2_WRP2 ((u32)0x000000FF) /* Flash memory write protection option bytes */
-#define FLASH_WRP2_nWRP2 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */
-
-
-/****************** Bit definition for FLASH_WRP3 register ******************/
-#define FLASH_WRP3_WRP3 ((u32)0x00FF0000) /* Flash memory write protection option bytes */
-#define FLASH_WRP3_nWRP3 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */
-
-
-/* Exported macro ------------------------------------------------------------*/
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = 0x0)
-
-#define WRITE_REG(REG, VAL) ((REG) = VAL)
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __STM32F10x_MAP_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_nvic.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_nvic.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_nvic.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,287 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_nvic.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* NVIC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_NVIC_H
-#define __STM32F10x_NVIC_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* NVIC Init Structure definition */
-typedef struct
-{
- u8 NVIC_IRQChannel;
- u8 NVIC_IRQChannelPreemptionPriority;
- u8 NVIC_IRQChannelSubPriority;
- FunctionalState NVIC_IRQChannelCmd;
-} NVIC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/* IRQ Channels --------------------------------------------------------------*/
-#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
-#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
-#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
-#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
-#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
-#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
-#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
-#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
-#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
-#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
-#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
-#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
-#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
-#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
-#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
-#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
-#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
-#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
-#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
-#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
-#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
-#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
-#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
-#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
-#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
-#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
-#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
-#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
-#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
-#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
-#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
-#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
-#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
-#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
-#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
-#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
-#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
-#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
-#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
-#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
-#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
-#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
-#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
-#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
-#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
-#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
-#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
-#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
-#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
-#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
-#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
-#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
-#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
-#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
-#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
-#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
-#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
-#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
-#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
-#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
-
-
-#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
- ((CHANNEL) == PVD_IRQChannel) || \
- ((CHANNEL) == TAMPER_IRQChannel) || \
- ((CHANNEL) == RTC_IRQChannel) || \
- ((CHANNEL) == FLASH_IRQChannel) || \
- ((CHANNEL) == RCC_IRQChannel) || \
- ((CHANNEL) == EXTI0_IRQChannel) || \
- ((CHANNEL) == EXTI1_IRQChannel) || \
- ((CHANNEL) == EXTI2_IRQChannel) || \
- ((CHANNEL) == EXTI3_IRQChannel) || \
- ((CHANNEL) == EXTI4_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel1_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel2_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel3_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel4_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel5_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel6_IRQChannel) || \
- ((CHANNEL) == DMA1_Channel7_IRQChannel) || \
- ((CHANNEL) == ADC1_2_IRQChannel) || \
- ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
- ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
- ((CHANNEL) == CAN_RX1_IRQChannel) || \
- ((CHANNEL) == CAN_SCE_IRQChannel) || \
- ((CHANNEL) == EXTI9_5_IRQChannel) || \
- ((CHANNEL) == TIM1_BRK_IRQChannel) || \
- ((CHANNEL) == TIM1_UP_IRQChannel) || \
- ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
- ((CHANNEL) == TIM1_CC_IRQChannel) || \
- ((CHANNEL) == TIM2_IRQChannel) || \
- ((CHANNEL) == TIM3_IRQChannel) || \
- ((CHANNEL) == TIM4_IRQChannel) || \
- ((CHANNEL) == I2C1_EV_IRQChannel) || \
- ((CHANNEL) == I2C1_ER_IRQChannel) || \
- ((CHANNEL) == I2C2_EV_IRQChannel) || \
- ((CHANNEL) == I2C2_ER_IRQChannel) || \
- ((CHANNEL) == SPI1_IRQChannel) || \
- ((CHANNEL) == SPI2_IRQChannel) || \
- ((CHANNEL) == USART1_IRQChannel) || \
- ((CHANNEL) == USART2_IRQChannel) || \
- ((CHANNEL) == USART3_IRQChannel) || \
- ((CHANNEL) == EXTI15_10_IRQChannel) || \
- ((CHANNEL) == RTCAlarm_IRQChannel) || \
- ((CHANNEL) == USBWakeUp_IRQChannel) || \
- ((CHANNEL) == TIM8_BRK_IRQChannel) || \
- ((CHANNEL) == TIM8_UP_IRQChannel) || \
- ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
- ((CHANNEL) == TIM8_CC_IRQChannel) || \
- ((CHANNEL) == ADC3_IRQChannel) || \
- ((CHANNEL) == FSMC_IRQChannel) || \
- ((CHANNEL) == SDIO_IRQChannel) || \
- ((CHANNEL) == TIM5_IRQChannel) || \
- ((CHANNEL) == SPI3_IRQChannel) || \
- ((CHANNEL) == UART4_IRQChannel) || \
- ((CHANNEL) == UART5_IRQChannel) || \
- ((CHANNEL) == TIM6_IRQChannel) || \
- ((CHANNEL) == TIM7_IRQChannel) || \
- ((CHANNEL) == DMA2_Channel1_IRQChannel) || \
- ((CHANNEL) == DMA2_Channel2_IRQChannel) || \
- ((CHANNEL) == DMA2_Channel3_IRQChannel) || \
- ((CHANNEL) == DMA2_Channel4_5_IRQChannel))
-
-
-/* System Handlers -----------------------------------------------------------*/
-#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
-#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
-#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
-#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
-#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
-#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
-#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
-#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
-#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
-
-#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
- ((HANDLER) == SystemHandler_BusFault) || \
- ((HANDLER) == SystemHandler_UsageFault))
-
-#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
- ((HANDLER) == SystemHandler_BusFault) || \
- ((HANDLER) == SystemHandler_UsageFault) || \
- ((HANDLER) == SystemHandler_SVCall) || \
- ((HANDLER) == SystemHandler_DebugMonitor) || \
- ((HANDLER) == SystemHandler_PSV) || \
- ((HANDLER) == SystemHandler_SysTick))
-
-#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
- ((HANDLER) == SystemHandler_BusFault) || \
- ((HANDLER) == SystemHandler_SVCall))
-
-#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
- ((HANDLER) == SystemHandler_PSV) || \
- ((HANDLER) == SystemHandler_SysTick))
-
-#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
- ((HANDLER) == SystemHandler_SysTick))
-
-#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
- ((HANDLER) == SystemHandler_BusFault) || \
- ((HANDLER) == SystemHandler_UsageFault) || \
- ((HANDLER) == SystemHandler_SVCall) || \
- ((HANDLER) == SystemHandler_DebugMonitor) || \
- ((HANDLER) == SystemHandler_PSV) || \
- ((HANDLER) == SystemHandler_SysTick))
-
-#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
- ((HANDLER) == SystemHandler_MemoryManage) || \
- ((HANDLER) == SystemHandler_BusFault) || \
- ((HANDLER) == SystemHandler_UsageFault) || \
- ((HANDLER) == SystemHandler_DebugMonitor))
-
-#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
- ((HANDLER) == SystemHandler_BusFault))
-
-
-/* Vector Table Base ---------------------------------------------------------*/
-#define NVIC_VectTab_RAM ((u32)0x20000000)
-#define NVIC_VectTab_FLASH ((u32)0x08000000)
-
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
- ((VECTTAB) == NVIC_VectTab_FLASH))
-
-/* System Low Power ----------------------------------------------------------*/
-#define NVIC_LP_SEVONPEND ((u8)0x10)
-#define NVIC_LP_SLEEPDEEP ((u8)0x04)
-#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
-
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-
-/* Preemption Priority Group -------------------------------------------------*/
-#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
- 0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
- ((GROUP) == NVIC_PriorityGroup_1) || \
- ((GROUP) == NVIC_PriorityGroup_2) || \
- ((GROUP) == NVIC_PriorityGroup_3) || \
- ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
-#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void NVIC_DeInit(void);
-void NVIC_SCBDeInit(void);
-void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SETPRIMASK(void);
-void NVIC_RESETPRIMASK(void);
-void NVIC_SETFAULTMASK(void);
-void NVIC_RESETFAULTMASK(void);
-void NVIC_BASEPRICONFIG(u32 NewPriority);
-u32 NVIC_GetBASEPRI(void);
-u16 NVIC_GetCurrentPendingIRQChannel(void);
-ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
-void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
-void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
-u16 NVIC_GetCurrentActiveHandler(void);
-ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
-u32 NVIC_GetCPUID(void);
-void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
-void NVIC_GenerateSystemReset(void);
-void NVIC_GenerateCoreReset(void);
-void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
-void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
-void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
- u8 SystemHandlerSubPriority);
-ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
-void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
-void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
-ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
-u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
-u32 NVIC_GetFaultAddress(u32 SystemHandler);
-
-#endif /* __STM32F10x_NVIC_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_pwr.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_pwr.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_pwr.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,77 +1,155 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_pwr.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* PWR firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_PWR_H
#define __STM32F10x_PWR_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* PVD detection level */
-#define PWR_PVDLevel_2V2 ((u32)0x00000000)
-#define PWR_PVDLevel_2V3 ((u32)0x00000020)
-#define PWR_PVDLevel_2V4 ((u32)0x00000040)
-#define PWR_PVDLevel_2V5 ((u32)0x00000060)
-#define PWR_PVDLevel_2V6 ((u32)0x00000080)
-#define PWR_PVDLevel_2V7 ((u32)0x000000A0)
-#define PWR_PVDLevel_2V8 ((u32)0x000000C0)
-#define PWR_PVDLevel_2V9 ((u32)0x000000E0)
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+ * @}
+ */
-/* Regulator state is STOP mode */
-#define PWR_Regulator_ON ((u32)0x00000000)
-#define PWR_Regulator_LowPower ((u32)0x00000001)
+/** @defgroup Regulator_state_is_STOP_mode
+ * @{
+ */
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
-/* STOP mode entry */
-#define PWR_STOPEntry_WFI ((u8)0x01)
-#define PWR_STOPEntry_WFE ((u8)0x02)
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-/* PWR Flag */
-#define PWR_FLAG_WU ((u32)0x00000001)
-#define PWR_FLAG_SB ((u32)0x00000002)
-#define PWR_FLAG_PVDO ((u32)0x00000004)
+/**
+ * @}
+ */
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU ((uint32_t)0x00000001)
+#define PWR_FLAG_SB ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO))
+
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions
+ * @{
+ */
+
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
-void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
-void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
-FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
-void PWR_ClearFlag(u32 PWR_FLAG);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_PWR_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rcc.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rcc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rcc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,288 +1,700 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_rcc.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* RCC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the RCC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
#define __STM32F10x_RCC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Types
+ * @{
+ */
+
typedef struct
{
- u32 SYSCLK_Frequency;
- u32 HCLK_Frequency;
- u32 PCLK1_Frequency;
- u32 PCLK2_Frequency;
- u32 ADCCLK_Frequency;
+ uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* HSE configuration */
-#define RCC_HSE_OFF ((u32)0x00000000)
-#define RCC_HSE_ON ((u32)0x00010000)
-#define RCC_HSE_Bypass ((u32)0x00040000)
+/**
+ * @}
+ */
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint32_t)0x00000000)
+#define RCC_HSE_ON ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
-/* PLL entry clock source */
-#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
-#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
-#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
+/**
+ * @}
+ */
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+/** @defgroup PLL_entry_clock_source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
+
+#ifndef STM32F10X_CL
+ #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
+ #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
((SOURCE) == RCC_PLLSource_HSE_Div2))
+#else
+ #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+#endif /* STM32F10X_CL */
-/* PLL multiplication factor */
-#define RCC_PLLMul_2 ((u32)0x00000000)
-#define RCC_PLLMul_3 ((u32)0x00040000)
-#define RCC_PLLMul_4 ((u32)0x00080000)
-#define RCC_PLLMul_5 ((u32)0x000C0000)
-#define RCC_PLLMul_6 ((u32)0x00100000)
-#define RCC_PLLMul_7 ((u32)0x00140000)
-#define RCC_PLLMul_8 ((u32)0x00180000)
-#define RCC_PLLMul_9 ((u32)0x001C0000)
-#define RCC_PLLMul_10 ((u32)0x00200000)
-#define RCC_PLLMul_11 ((u32)0x00240000)
-#define RCC_PLLMul_12 ((u32)0x00280000)
-#define RCC_PLLMul_13 ((u32)0x002C0000)
-#define RCC_PLLMul_14 ((u32)0x00300000)
-#define RCC_PLLMul_15 ((u32)0x00340000)
-#define RCC_PLLMul_16 ((u32)0x00380000)
+/**
+ * @}
+ */
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
- ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
- ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
- ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
- ((MUL) == RCC_PLLMul_16))
+/** @defgroup PLL_multiplication_factor
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define RCC_PLLMul_2 ((uint32_t)0x00000000)
+ #define RCC_PLLMul_3 ((uint32_t)0x00040000)
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_10 ((uint32_t)0x00200000)
+ #define RCC_PLLMul_11 ((uint32_t)0x00240000)
+ #define RCC_PLLMul_12 ((uint32_t)0x00280000)
+ #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
+ #define RCC_PLLMul_14 ((uint32_t)0x00300000)
+ #define RCC_PLLMul_15 ((uint32_t)0x00340000)
+ #define RCC_PLLMul_16 ((uint32_t)0x00380000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
-/* System clock source */
-#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
-#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
+#else
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_6_5))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+#ifdef STM32F10X_CL
+/** @defgroup PREDIV1_division_factor
+ * @{
+ */
+ #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
+ #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
+ #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
+ #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
+ #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
+ #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
+ #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
+ #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
+ #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
+ #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
+ #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
+ #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
+ #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
+ #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
+ #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
+
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup PREDIV1_clock_source
+ * @{
+ */
+/* PREDIV1 clock source (only for STM32 connectivity line devices) */
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
+ ((SOURCE) == RCC_PREDIV1_Source_PLL2))
+/**
+ * @}
+ */
+
+
+/** @defgroup PREDIV2_division_factor
+ * @{
+ */
+
+ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
+ #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
+ #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
+ #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
+ #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
+ #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
+ #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
+ #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
+ #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
+ #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
+ #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
+ #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
+ #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
+ #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
+ #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
+
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
+ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
+ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
+ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
+ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
+ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
+ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
+ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL2_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
+ #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
+ #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
+ #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
+ #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
+ #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
+ #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
+ #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
+ #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
+
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
+ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
+ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
+ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
+ ((MUL) == RCC_PLL2Mul_20))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL3_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
+ #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
+ #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
+ #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
+ #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
+ #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
+ #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
+ #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
+ #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
+
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
+ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
+ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
+ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
+ ((MUL) == RCC_PLL3Mul_20))
+/**
+ * @}
+ */
+
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
-/* AHB clock source */
-#define RCC_SYSCLK_Div1 ((u32)0x00000000)
-#define RCC_SYSCLK_Div2 ((u32)0x00000080)
-#define RCC_SYSCLK_Div4 ((u32)0x00000090)
-#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
-#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
-#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
-#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
-#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
-#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
+/** @defgroup AHB_clock_source
+ * @{
+ */
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
-/* APB1/APB2 clock source */
-#define RCC_HCLK_Div1 ((u32)0x00000000)
-#define RCC_HCLK_Div2 ((u32)0x00000400)
-#define RCC_HCLK_Div4 ((u32)0x00000500)
-#define RCC_HCLK_Div8 ((u32)0x00000600)
-#define RCC_HCLK_Div16 ((u32)0x00000700)
+/** @defgroup APB1_APB2_clock_source
+ * @{
+ */
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
-/* RCC Interrupt source */
-#define RCC_IT_LSIRDY ((u8)0x01)
-#define RCC_IT_LSERDY ((u8)0x02)
-#define RCC_IT_HSIRDY ((u8)0x04)
-#define RCC_IT_HSERDY ((u8)0x08)
-#define RCC_IT_PLLRDY ((u8)0x10)
-#define RCC_IT_CSS ((u8)0x80)
+/** @defgroup RCC_Interrupt_source
+ * @{
+ */
-#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
-/* USB clock source */
-#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
-#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
+#ifndef STM32F10X_CL
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+#else
+ #define RCC_IT_PLL2RDY ((uint8_t)0x20)
+ #define RCC_IT_PLL3RDY ((uint8_t)0x40)
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+#endif /* STM32F10X_CL */
-#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+
+/**
+ * @}
+ */
+
+#ifndef STM32F10X_CL
+/** @defgroup USB_Device_clock_source
+ * @{
+ */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+#else
+/** @defgroup USB_OTG_FS_clock_source
+ * @{
+ */
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
-/* ADC clock source */
-#define RCC_PCLK2_Div2 ((u32)0x00000000)
-#define RCC_PCLK2_Div4 ((u32)0x00004000)
-#define RCC_PCLK2_Div6 ((u32)0x00008000)
-#define RCC_PCLK2_Div8 ((u32)0x0000C000)
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
+ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+#ifdef STM32F10X_CL
+/** @defgroup I2S2_clock_source
+ * @{
+ */
+ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+
+/** @defgroup I2S3_clock_source
+ * @{
+ */
+ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+ * @}
+ */
-/* LSE configuration */
-#define RCC_LSE_OFF ((u8)0x00)
-#define RCC_LSE_ON ((u8)0x01)
-#define RCC_LSE_Bypass ((u8)0x04)
+/** @defgroup LSE_configuration
+ * @{
+ */
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_Bypass ((uint8_t)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
-/* RTC clock source */
-#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
-#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
-#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
+/** @defgroup RTC_clock_source
+ * @{
+ */
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+ * @}
+ */
-/* AHB peripheral */
-#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)
-#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)
-#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
-#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
-#define RCC_AHBPeriph_CRC ((u32)0x00000040)
-#define RCC_AHBPeriph_FSMC ((u32)0x00000100)
-#define RCC_AHBPeriph_SDIO ((u32)0x00000400)
+/** @defgroup AHB_peripheral
+ * @{
+ */
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
-/* APB2 peripheral */
-#define RCC_APB2Periph_AFIO ((u32)0x00000001)
-#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
-#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
-#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
-#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
-#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
-#define RCC_APB2Periph_GPIOF ((u32)0x00000080)
-#define RCC_APB2Periph_GPIOG ((u32)0x00000100)
-#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
-#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
-#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
-#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
-#define RCC_APB2Periph_TIM8 ((u32)0x00002000)
-#define RCC_APB2Periph_USART1 ((u32)0x00004000)
-#define RCC_APB2Periph_ADC3 ((u32)0x00008000)
-#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
-/* APB1 peripheral */
-#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
-#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
-#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
-#define RCC_APB1Periph_TIM5 ((u32)0x00000008)
-#define RCC_APB1Periph_TIM6 ((u32)0x00000010)
-#define RCC_APB1Periph_TIM7 ((u32)0x00000020)
-#define RCC_APB1Periph_WWDG ((u32)0x00000800)
-#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
-#define RCC_APB1Periph_SPI3 ((u32)0x00008000)
-#define RCC_APB1Periph_USART2 ((u32)0x00020000)
-#define RCC_APB1Periph_USART3 ((u32)0x00040000)
-#define RCC_APB1Periph_UART4 ((u32)0x00080000)
-#define RCC_APB1Periph_UART5 ((u32)0x00100000)
-#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
-#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
-#define RCC_APB1Periph_USB ((u32)0x00800000)
-#define RCC_APB1Periph_CAN ((u32)0x02000000)
-#define RCC_APB1Periph_BKP ((u32)0x08000000)
-#define RCC_APB1Periph_PWR ((u32)0x10000000)
-#define RCC_APB1Periph_DAC ((u32)0x20000000)
-#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)
+/** @defgroup APB1_peripheral
+ * @{
+ */
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00))
-/* Clock source to output on MCO pin */
-#define RCC_MCO_NoClock ((u8)0x00)
-#define RCC_MCO_SYSCLK ((u8)0x04)
-#define RCC_MCO_HSI ((u8)0x05)
-#define RCC_MCO_HSE ((u8)0x06)
-#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
+/**
+ * @}
+ */
-#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
- ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
- ((MCO) == RCC_MCO_PLLCLK_Div2))
+/** @defgroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
-/* RCC Flag */
-#define RCC_FLAG_HSIRDY ((u8)0x21)
-#define RCC_FLAG_HSERDY ((u8)0x31)
-#define RCC_FLAG_PLLRDY ((u8)0x39)
-#define RCC_FLAG_LSERDY ((u8)0x41)
-#define RCC_FLAG_LSIRDY ((u8)0x61)
-#define RCC_FLAG_PINRST ((u8)0x7A)
-#define RCC_FLAG_PORRST ((u8)0x7B)
-#define RCC_FLAG_SFTRST ((u8)0x7C)
-#define RCC_FLAG_IWDGRST ((u8)0x7D)
-#define RCC_FLAG_WWDGRST ((u8)0x7E)
-#define RCC_FLAG_LPWRRST ((u8)0x7F)
+#define RCC_MCO_NoClock ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
- ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
- ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
- ((FLAG) == RCC_FLAG_LPWRRST))
+#ifndef STM32F10X_CL
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2))
+#else
+ #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
+ #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
+ #define RCC_MCO_XT1 ((uint8_t)0x0A)
+ #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
+ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
+ ((MCO) == RCC_MCO_PLL3CLK))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#else
+ #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
+ #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#endif /* STM32F10X_CL */
+
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions
+ * @{
+ */
+
void RCC_DeInit(void);
-void RCC_HSEConfig(u32 RCC_HSE);
+void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
-void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
-void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
-u8 RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(u32 RCC_SYSCLK);
-void RCC_PCLK1Config(u32 RCC_HCLK);
-void RCC_PCLK2Config(u32 RCC_HCLK);
-void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
-void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
-void RCC_ADCCLKConfig(u32 RCC_PCLK2);
-void RCC_LSEConfig(u8 RCC_LSE);
+
+#ifdef STM32F10X_CL
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+ void RCC_PLL2Cmd(FunctionalState NewState);
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+ void RCC_PLL3Cmd(FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
+#ifndef STM32F10X_CL
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+#else
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+
+#ifdef STM32F10X_CL
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
-void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCOConfig(u8 RCC_MCO);
-FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(u8 RCC_IT);
-void RCC_ClearITPendingBit(u8 RCC_IT);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_RCC_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rtc.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rtc.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_rtc.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,70 +1,134 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_rtc.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* RTC firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RTC_H
#define __STM32F10x_RTC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* RTC interrupts define -----------------------------------------------------*/
-#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */
-#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */
-#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
-#define IS_RTC_IT(IT) ((((IT) & (u16)0xFFF8) == 0x00) && ((IT) != 0x00))
+/** @addtogroup RTC
+ * @{
+ */
+/** @defgroup RTC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RTC_interrupts_define
+ * @{
+ */
+
+#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
+#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
+#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
((IT) == RTC_IT_SEC))
-
-/* RTC interrupts flags ------------------------------------------------------*/
-#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */
-#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */
-#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */
-#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */
-#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */
+/**
+ * @}
+ */
-#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+/** @defgroup RTC_interrupts_flags
+ * @{
+ */
+#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
+#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
+#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
-#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions
+ * @{
+ */
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
-u32 RTC_GetCounter(void);
-void RTC_SetCounter(u32 CounterValue);
-void RTC_SetPrescaler(u32 PrescalerValue);
-void RTC_SetAlarm(u32 AlarmValue);
-u32 RTC_GetDivider(void);
+uint32_t RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
-FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
-void RTC_ClearFlag(u16 RTC_FLAG);
-ITStatus RTC_GetITStatus(u16 RTC_IT);
-void RTC_ClearITPendingBit(u16 RTC_IT);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_RTC_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_sdio.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_sdio.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_sdio.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,181 +1,316 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_sdio.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* SDIO firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the SDIO firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SDIO_H
#define __STM32F10x_SDIO_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_Exported_Types
+ * @{
+ */
+
typedef struct
{
- u8 SDIO_ClockDiv;
- u32 SDIO_ClockEdge;
- u32 SDIO_ClockBypass;
- u32 SDIO_ClockPowerSave;
- u32 SDIO_BusWide;
- u32 SDIO_HardwareFlowControl;
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between 0x00 and 0xFF. */
+
} SDIO_InitTypeDef;
typedef struct
{
- u32 SDIO_Argument;
- u32 SDIO_CmdIndex;
- u32 SDIO_Response;
- u32 SDIO_Wait;
- u32 SDIO_CPSM;
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register */
+
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitTypeDef;
typedef struct
{
- u32 SDIO_DataTimeOut;
- u32 SDIO_DataLength;
- u32 SDIO_DataBlockSize;
- u32 SDIO_TransferDir;
- u32 SDIO_TransferMode;
- u32 SDIO_DPSM;
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-/* SDIO Clock Edge -----------------------------------------------------------*/
-#define SDIO_ClockEdge_Rising ((u32)0x00000000)
-#define SDIO_ClockEdge_Falling ((u32)0x00002000)
+/**
+ * @}
+ */
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
-/* SDIO Clock Bypass ----------------------------------------------------------*/
-#define SDIO_ClockBypass_Disable ((u32)0x00000000)
-#define SDIO_ClockBypass_Enable ((u32)0x00000400)
+/**
+ * @}
+ */
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
- ((BYPASS) == SDIO_ClockBypass_Enable))
+ ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+ * @}
+ */
-/* SDIO Clock Power Save ----------------------------------------------------*/
-#define SDIO_ClockPowerSave_Disable ((u32)0x00000000)
-#define SDIO_ClockPowerSave_Enable ((u32)0x00000200)
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+ * @}
+ */
-/* SDIO Bus Wide -------------------------------------------------------------*/
-#define SDIO_BusWide_1b ((u32)0x00000000)
-#define SDIO_BusWide_4b ((u32)0x00000800)
-#define SDIO_BusWide_8b ((u32)0x00001000)
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
-
-/* SDIO Hardware Flow Control -----------------------------------------------*/
-#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000)
-#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
-
-/* SDIO Power State ----------------------------------------------------------*/
-#define SDIO_PowerState_OFF ((u32)0x00000000)
-#define SDIO_PowerState_ON ((u32)0x00000003)
+/**
+ * @}
+ */
+/** @defgroup SDIO_Power_State
+ * @{
+ */
+
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+ * @}
+ */
-/* SDIO Interrupt soucres ----------------------------------------------------*/
-#define SDIO_IT_CCRCFAIL ((u32)0x00000001)
-#define SDIO_IT_DCRCFAIL ((u32)0x00000002)
-#define SDIO_IT_CTIMEOUT ((u32)0x00000004)
-#define SDIO_IT_DTIMEOUT ((u32)0x00000008)
-#define SDIO_IT_TXUNDERR ((u32)0x00000010)
-#define SDIO_IT_RXOVERR ((u32)0x00000020)
-#define SDIO_IT_CMDREND ((u32)0x00000040)
-#define SDIO_IT_CMDSENT ((u32)0x00000080)
-#define SDIO_IT_DATAEND ((u32)0x00000100)
-#define SDIO_IT_STBITERR ((u32)0x00000200)
-#define SDIO_IT_DBCKEND ((u32)0x00000400)
-#define SDIO_IT_CMDACT ((u32)0x00000800)
-#define SDIO_IT_TXACT ((u32)0x00001000)
-#define SDIO_IT_RXACT ((u32)0x00002000)
-#define SDIO_IT_TXFIFOHE ((u32)0x00004000)
-#define SDIO_IT_RXFIFOHF ((u32)0x00008000)
-#define SDIO_IT_TXFIFOF ((u32)0x00010000)
-#define SDIO_IT_RXFIFOF ((u32)0x00020000)
-#define SDIO_IT_TXFIFOE ((u32)0x00040000)
-#define SDIO_IT_RXFIFOE ((u32)0x00080000)
-#define SDIO_IT_TXDAVL ((u32)0x00100000)
-#define SDIO_IT_RXDAVL ((u32)0x00200000)
-#define SDIO_IT_SDIOIT ((u32)0x00400000)
-#define SDIO_IT_CEATAEND ((u32)0x00800000)
-#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00))
+/** @defgroup SDIO_Interrupt_soucres
+ * @{
+ */
-/* SDIO Command Index -------------------------------------------------------*/
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
-/* SDIO Response Type --------------------------------------------------------*/
-#define SDIO_Response_No ((u32)0x00000000)
-#define SDIO_Response_Short ((u32)0x00000040)
-#define SDIO_Response_Long ((u32)0x000000C0)
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+#define SDIO_Response_No ((uint32_t)0x00000000)
+#define SDIO_Response_Short ((uint32_t)0x00000040)
+#define SDIO_Response_Long ((uint32_t)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
+/**
+ * @}
+ */
-/* SDIO Wait Interrupt State -------------------------------------------------*/
-#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */
-#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */
-#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
+/**
+ * @}
+ */
-/* SDIO CPSM State -----------------------------------------------------------*/
-#define SDIO_CPSM_Disable ((u32)0x00000000)
-#define SDIO_CPSM_Enable ((u32)0x00000400)
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+ * @}
+ */
-/* SDIO Response Registers ---------------------------------------------------*/
-#define SDIO_RESP1 ((u32)0x00000000)
-#define SDIO_RESP2 ((u32)0x00000004)
-#define SDIO_RESP3 ((u32)0x00000008)
-#define SDIO_RESP4 ((u32)0x0000000C)
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
-/* SDIO Data Length ----------------------------------------------------------*/
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
-/* SDIO Data Block Size ------------------------------------------------------*/
-#define SDIO_DataBlockSize_1b ((u32)0x00000000)
-#define SDIO_DataBlockSize_2b ((u32)0x00000010)
-#define SDIO_DataBlockSize_4b ((u32)0x00000020)
-#define SDIO_DataBlockSize_8b ((u32)0x00000030)
-#define SDIO_DataBlockSize_16b ((u32)0x00000040)
-#define SDIO_DataBlockSize_32b ((u32)0x00000050)
-#define SDIO_DataBlockSize_64b ((u32)0x00000060)
-#define SDIO_DataBlockSize_128b ((u32)0x00000070)
-#define SDIO_DataBlockSize_256b ((u32)0x00000080)
-#define SDIO_DataBlockSize_512b ((u32)0x00000090)
-#define SDIO_DataBlockSize_1024b ((u32)0x000000A0)
-#define SDIO_DataBlockSize_2048b ((u32)0x000000B0)
-#define SDIO_DataBlockSize_4096b ((u32)0x000000C0)
-#define SDIO_DataBlockSize_8192b ((u32)0x000000D0)
-#define SDIO_DataBlockSize_16384b ((u32)0x000000E0)
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
@@ -191,53 +326,73 @@
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
+/**
+ * @}
+ */
-/* SDIO Transfer Direction ---------------------------------------------------*/
-#define SDIO_TransferDir_ToCard ((u32)0x00000000)
-#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
- ((DIR) == SDIO_TransferDir_ToSDIO))
+ ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+ * @}
+ */
-/* SDIO Transfer Type --------------------------------------------------------*/
-#define SDIO_TransferMode_Block ((u32)0x00000000)
-#define SDIO_TransferMode_Stream ((u32)0x00000004)
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
- ((MODE) == SDIO_TransferMode_Block))
+ ((MODE) == SDIO_TransferMode_Block))
+/**
+ * @}
+ */
-/* SDIO DPSM State -----------------------------------------------------------*/
-#define SDIO_DPSM_Disable ((u32)0x00000000)
-#define SDIO_DPSM_Enable ((u32)0x00000001)
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+ * @}
+ */
-/* SDIO Flags ----------------------------------------------------------------*/
-#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
-#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
-#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
-#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
-#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
-#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
-#define SDIO_FLAG_CMDREND ((u32)0x00000040)
-#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
-#define SDIO_FLAG_DATAEND ((u32)0x00000100)
-#define SDIO_FLAG_STBITERR ((u32)0x00000200)
-#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
-#define SDIO_FLAG_CMDACT ((u32)0x00000800)
-#define SDIO_FLAG_TXACT ((u32)0x00001000)
-#define SDIO_FLAG_RXACT ((u32)0x00002000)
-#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
-#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
-#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
-#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
-#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
-#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
-#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
-#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
-#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
-#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
+/** @defgroup SDIO_Flags
+ * @{
+ */
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
@@ -263,7 +418,7 @@
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00))
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
@@ -290,48 +445,86 @@
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00))
-
-/* SDIO Read Wait Mode -------------------------------------------------------*/
-#define SDIO_ReadWaitMode_CLK ((u32)0x00000000)
-#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001)
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
- ((MODE) == SDIO_ReadWaitMode_DATA2))
+ ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Functions
+ * @{
+ */
+
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
-void SDIO_SetPowerState(u32 SDIO_PowerState);
-u32 SDIO_GetPowerState(void);
-void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
void SDIO_DMACmd(FunctionalState NewState);
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
-u8 SDIO_GetCommandResponse(void);
-u32 SDIO_GetResponse(u32 SDIO_RESP);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-u32 SDIO_GetDataCounter(void);
-u32 SDIO_ReadData(void);
-void SDIO_WriteData(u32 Data);
-u32 SDIO_GetFIFOCount(void);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
-void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
-FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
-void SDIO_ClearFlag(u32 SDIO_FLAG);
-ITStatus SDIO_GetITStatus(u32 SDIO_IT);
-void SDIO_ClearITPendingBit(u32 SDIO_IT);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_SDIO_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_spi.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_spi.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_spi.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,117 +1,213 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_spi.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* SPI firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the SPI firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SPI_H
#define __STM32F10x_SPI_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* SPI Init structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
typedef struct
{
- u16 SPI_Direction;
- u16 SPI_Mode;
- u16 SPI_DataSize;
- u16 SPI_CPOL;
- u16 SPI_CPHA;
- u16 SPI_NSS;
- u16 SPI_BaudRatePrescaler;
- u16 SPI_FirstBit;
- u16 SPI_CRCPolynomial;
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be any combination of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be any combination of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be any combination of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be any combination of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be any combination of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be any combination of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be any combination of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be any combination of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
-/* I2S Init structure definition */
+/**
+ * @brief I2S Init structure definition
+ */
+
typedef struct
{
- u16 I2S_Mode;
- u16 I2S_Standard;
- u16 I2S_DataFormat;
- u16 I2S_MCLKOutput;
- u16 I2S_AudioFreq;
- u16 I2S_CPOL;
+
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be any combination of @ref I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be any combination of @ref I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be any combination of @ref I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be any combination of @ref I2S_MCLK_Output */
+
+ uint16_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be any combination of @ref I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be any combination of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/**
+ * @}
+ */
-#define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \
- ((*(u32*)&(PERIPH)) == SPI2_BASE) || \
- ((*(u32*)&(PERIPH)) == SPI3_BASE))
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
-#define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \
- ((*(u32*)&(PERIPH)) == SPI3_BASE))
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
-/* SPI data direction mode */
-#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)
-#define SPI_Direction_1Line_Rx ((u16)0x8000)
-#define SPI_Direction_1Line_Tx ((u16)0xC000)
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
-/* SPI master/slave mode */
-#define SPI_Mode_Master ((u16)0x0104)
-#define SPI_Mode_Slave ((u16)0x0000)
+/** @defgroup SPI_mode
+ * @{
+ */
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
-/* SPI data size */
-#define SPI_DataSize_16b ((u16)0x0800)
-#define SPI_DataSize_8b ((u16)0x0000)
+/** @defgroup SPI_data_size
+ * @{
+ */
+#define SPI_DataSize_16b ((uint16_t)0x0800)
+#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
+/**
+ * @}
+ */
-/* SPI Clock Polarity */
-#define SPI_CPOL_Low ((u16)0x0000)
-#define SPI_CPOL_High ((u16)0x0002)
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
-/* SPI Clock Phase */
-#define SPI_CPHA_1Edge ((u16)0x0000)
-#define SPI_CPHA_2Edge ((u16)0x0001)
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
-/* SPI Slave Select management */
-#define SPI_NSS_Soft ((u16)0x0200)
-#define SPI_NSS_Hard ((u16)0x0000)
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
-/* SPI BaudRate Prescaler */
-#define SPI_BaudRatePrescaler_2 ((u16)0x0000)
-#define SPI_BaudRatePrescaler_4 ((u16)0x0008)
-#define SPI_BaudRatePrescaler_8 ((u16)0x0010)
-#define SPI_BaudRatePrescaler_16 ((u16)0x0018)
-#define SPI_BaudRatePrescaler_32 ((u16)0x0020)
-#define SPI_BaudRatePrescaler_64 ((u16)0x0028)
-#define SPI_BaudRatePrescaler_128 ((u16)0x0030)
-#define SPI_BaudRatePrescaler_256 ((u16)0x0038)
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
@@ -120,146 +216,236 @@
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
-/* SPI MSB/LSB transmission */
-#define SPI_FirstBit_MSB ((u16)0x0000)
-#define SPI_FirstBit_LSB ((u16)0x0080)
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
-/* I2S Mode */
-#define I2S_Mode_SlaveTx ((u16)0x0000)
-#define I2S_Mode_SlaveRx ((u16)0x0100)
-#define I2S_Mode_MasterTx ((u16)0x0200)
-#define I2S_Mode_MasterRx ((u16)0x0300)
+/** @defgroup I2S_Mode
+ * @{
+ */
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx) || \
((MODE) == I2S_Mode_MasterRx) )
+/**
+ * @}
+ */
-/* I2S Standard */
-#define I2S_Standard_Phillips ((u16)0x0000)
-#define I2S_Standard_MSB ((u16)0x0010)
-#define I2S_Standard_LSB ((u16)0x0020)
-#define I2S_Standard_PCMShort ((u16)0x0030)
-#define I2S_Standard_PCMLong ((u16)0x00B0)
+/** @defgroup I2S_Standard
+ * @{
+ */
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
-/* I2S Data Format */
-#define I2S_DataFormat_16b ((u16)0x0000)
-#define I2S_DataFormat_16bextended ((u16)0x0001)
-#define I2S_DataFormat_24b ((u16)0x0003)
-#define I2S_DataFormat_32b ((u16)0x0005)
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
-/* I2S MCLK Output */
-#define I2S_MCLKOutput_Enable ((u16)0x0200)
-#define I2S_MCLKOutput_Disable ((u16)0x0000)
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
-/* I2S Audio Frequency */
-#define I2S_AudioFreq_48k ((u16)48000)
-#define I2S_AudioFreq_44k ((u16)44100)
-#define I2S_AudioFreq_22k ((u16)22050)
-#define I2S_AudioFreq_16k ((u16)16000)
-#define I2S_AudioFreq_8k ((u16)8000)
-#define I2S_AudioFreq_Default ((u16)2)
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
-#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
+#define I2S_AudioFreq_96k ((uint16_t)96000)
+#define I2S_AudioFreq_48k ((uint16_t)48000)
+#define I2S_AudioFreq_44k ((uint16_t)44100)
+#define I2S_AudioFreq_32k ((uint16_t)32000)
+#define I2S_AudioFreq_22k ((uint16_t)22050)
+#define I2S_AudioFreq_16k ((uint16_t)16000)
+#define I2S_AudioFreq_11k ((uint16_t)11025)
+#define I2S_AudioFreq_8k ((uint16_t)8000)
+#define I2S_AudioFreq_Default ((uint16_t)2)
+#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \
+ ((FREQ) == I2S_AudioFreq_48k) || \
((FREQ) == I2S_AudioFreq_44k) || \
+ ((FREQ) == I2S_AudioFreq_32k) || \
((FREQ) == I2S_AudioFreq_22k) || \
((FREQ) == I2S_AudioFreq_16k) || \
+ ((FREQ) == I2S_AudioFreq_11k) || \
((FREQ) == I2S_AudioFreq_8k) || \
((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
-/* I2S Clock Polarity */
-#define I2S_CPOL_Low ((u16)0x0000)
-#define I2S_CPOL_High ((u16)0x0008)
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
-/* SPI_I2S DMA transfer requests */
-#define SPI_I2S_DMAReq_Tx ((u16)0x0002)
-#define SPI_I2S_DMAReq_Rx ((u16)0x0001)
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
-/* SPI NSS internal software mangement */
-#define SPI_NSSInternalSoft_Set ((u16)0x0100)
-#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)
+/** @defgroup SPI_NSS_internal_software_mangement
+ * @{
+ */
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
-/* SPI CRC Transmit/Receive */
-#define SPI_CRC_Tx ((u8)0x00)
-#define SPI_CRC_Rx ((u8)0x01)
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
-/* SPI direction transmit/receive */
-#define SPI_Direction_Rx ((u16)0xBFFF)
-#define SPI_Direction_Tx ((u16)0x4000)
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
-/* SPI_I2S interrupts definition */
-#define SPI_I2S_IT_TXE ((u8)0x71)
-#define SPI_I2S_IT_RXNE ((u8)0x60)
-#define SPI_I2S_IT_ERR ((u8)0x50)
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
-
-#define SPI_I2S_IT_OVR ((u8)0x56)
-#define SPI_IT_MODF ((u8)0x55)
-#define SPI_IT_CRCERR ((u8)0x54)
-#define I2S_IT_UDR ((u8)0x53)
-
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_IT_CRCERR ((uint8_t)0x54)
+#define I2S_IT_UDR ((uint8_t)0x53)
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+ * @}
+ */
-/* SPI_I2S flags definition */
-#define SPI_I2S_FLAG_RXNE ((u16)0x0001)
-#define SPI_I2S_FLAG_TXE ((u16)0x0002)
-#define I2S_FLAG_CHSIDE ((u16)0x0004)
-#define I2S_FLAG_UDR ((u16)0x0008)
-#define SPI_FLAG_CRCERR ((u16)0x0010)
-#define SPI_FLAG_MODF ((u16)0x0020)
-#define SPI_I2S_FLAG_OVR ((u16)0x0040)
-#define SPI_I2S_FLAG_BSY ((u16)0x0080)
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+ * @}
+ */
-/* SPI CRC polynomial --------------------------------------------------------*/
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions
+ * @{
+ */
+
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
@@ -267,23 +453,38 @@
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState);
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data);
-u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);
-u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /*__STM32F10x_SPI_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_systick.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_systick.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_systick.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,64 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_systick.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* SysTick firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_SYSTICK_H
-#define __STM32F10x_SYSTICK_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* SysTick clock source */
-#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((u32)0x00000004)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-
-/* SysTick counter state */
-#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)
-#define SysTick_Counter_Enable ((u32)0x00000001)
-#define SysTick_Counter_Clear ((u32)0x00000000)
-
-#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \
- ((COUNTER) == SysTick_Counter_Enable) || \
- ((COUNTER) == SysTick_Counter_Clear))
-
-/* SysTick Flag */
-#define SysTick_FLAG_COUNT ((u32)0x00000010)
-#define SysTick_FLAG_SKEW ((u32)0x0000001E)
-#define SysTick_FLAG_NOREF ((u32)0x0000001F)
-
-#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \
- ((FLAG) == SysTick_FLAG_SKEW) || \
- ((FLAG) == SysTick_FLAG_NOREF))
-
-#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF))
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
-void SysTick_SetReload(u32 Reload);
-void SysTick_CounterCmd(u32 SysTick_Counter);
-void SysTick_ITConfig(FunctionalState NewState);
-u32 SysTick_GetCounter(void);
-FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
-
-#endif /* __STM32F10x_SYSTICK_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_tim.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_tim.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_tim.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,109 +1,208 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_tim.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* TIM firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TIM_H
#define __STM32F10x_TIM_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
-/* TIM Time Base Init structure definition */
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This sturcture is used with all TIMx except for TIM6 and TIM7.
+ */
+
typedef struct
{
- u16 TIM_Prescaler;
- u16 TIM_CounterMode;
- u16 TIM_Period;
- u16 TIM_ClockDivision;
- u8 TIM_RepetitionCounter;
-} TIM_TimeBaseInitTypeDef;
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
-/* TIM Output Compare Init structure definition */
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
typedef struct
{
- u16 TIM_OCMode;
- u16 TIM_OutputState;
- u16 TIM_OutputNState;
- u16 TIM_Pulse;
- u16 TIM_OCPolarity;
- u16 TIM_OCNPolarity;
- u16 TIM_OCIdleState;
- u16 TIM_OCNIdleState;
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
} TIM_OCInitTypeDef;
-/* TIM Input Capture Init structure definition */
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
typedef struct
{
- u16 TIM_Channel;
- u16 TIM_ICPolarity;
- u16 TIM_ICSelection;
- u16 TIM_ICPrescaler;
- u16 TIM_ICFilter;
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
} TIM_ICInitTypeDef;
-/* BDTR structure definition */
+/**
+ * @brief BDTR structure definition
+ * @note This sturcture is used only with TIM1 and TIM8.
+ */
+
typedef struct
{
- u16 TIM_OSSRState;
- u16 TIM_OSSIState;
- u16 TIM_LOCKLevel;
- u16 TIM_DeadTime;
- u16 TIM_Break;
- u16 TIM_BreakPolarity;
- u16 TIM_AutomaticOutput;
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BDTRInitTypeDef;
-/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
-#define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM2_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM4_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM5_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM6_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM7_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM8_BASE))
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8))
-#define IS_TIM_18_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM8_BASE))
+#define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8))
-#define IS_TIM_123458_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM2_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM4_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM5_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM8_BASE))
+#define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8))
+/**
+ * @}
+ */
-/* TIM Output Compare and PWM modes -----------------------------------------*/
-#define TIM_OCMode_Timing ((u16)0x0000)
-#define TIM_OCMode_Active ((u16)0x0010)
-#define TIM_OCMode_Inactive ((u16)0x0020)
-#define TIM_OCMode_Toggle ((u16)0x0030)
-#define TIM_OCMode_PWM1 ((u16)0x0060)
-#define TIM_OCMode_PWM2 ((u16)0x0070)
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
((MODE) == TIM_OCMode_Active) || \
((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2))
-
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
((MODE) == TIM_OCMode_Active) || \
((MODE) == TIM_OCMode_Inactive) || \
@@ -112,200 +211,305 @@
((MODE) == TIM_OCMode_PWM2) || \
((MODE) == TIM_ForcedAction_Active) || \
((MODE) == TIM_ForcedAction_InActive))
-/* TIM One Pulse Mode -------------------------------------------------------*/
-#define TIM_OPMode_Single ((u16)0x0008)
-#define TIM_OPMode_Repetitive ((u16)0x0000)
+/**
+ * @}
+ */
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
-/* TIM Channel -------------------------------------------------------------*/
-#define TIM_Channel_1 ((u16)0x0000)
-#define TIM_Channel_2 ((u16)0x0004)
-#define TIM_Channel_3 ((u16)0x0008)
-#define TIM_Channel_4 ((u16)0x000C)
+/** @defgroup TIM_Channel
+ * @{
+ */
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4))
-
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2))
-
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3))
-/* TIM Clock Division CKD --------------------------------------------------*/
-#define TIM_CKD_DIV1 ((u16)0x0000)
-#define TIM_CKD_DIV2 ((u16)0x0100)
-#define TIM_CKD_DIV4 ((u16)0x0200)
+/**
+ * @}
+ */
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
((DIV) == TIM_CKD_DIV2) || \
((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
-/* TIM Counter Mode --------------------------------------------------------*/
-#define TIM_CounterMode_Up ((u16)0x0000)
-#define TIM_CounterMode_Down ((u16)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
((MODE) == TIM_CounterMode_Down) || \
((MODE) == TIM_CounterMode_CenterAligned1) || \
((MODE) == TIM_CounterMode_CenterAligned2) || \
((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
-/* TIM Output Compare Polarity ---------------------------------------------*/
-#define TIM_OCPolarity_High ((u16)0x0000)
-#define TIM_OCPolarity_Low ((u16)0x0002)
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
-/* TIM Output Compare N Polarity -------------------------------------------*/
-#define TIM_OCNPolarity_High ((u16)0x0000)
-#define TIM_OCNPolarity_Low ((u16)0x0008)
-
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
((POLARITY) == TIM_OCNPolarity_Low))
+/**
+ * @}
+ */
-/* TIM Output Compare states -----------------------------------------------*/
-#define TIM_OutputState_Disable ((u16)0x0000)
-#define TIM_OutputState_Enable ((u16)0x0001)
+/** @defgroup TIM_Output_Compare_state
+ * @{
+ */
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
-/* TIM Output Compare N States ---------------------------------------------*/
-#define TIM_OutputNState_Disable ((u16)0x0000)
-#define TIM_OutputNState_Enable ((u16)0x0004)
+/** @defgroup TIM_Output_Compare_N_state
+ * @{
+ */
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
((STATE) == TIM_OutputNState_Enable))
+/**
+ * @}
+ */
-/* TIM Capture Compare States -----------------------------------------------*/
-#define TIM_CCx_Enable ((u16)0x0001)
-#define TIM_CCx_Disable ((u16)0x0000)
+/** @defgroup TIM_Capture_Compare_state
+ * @{
+ */
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
-/* TIM Capture Compare N States --------------------------------------------*/
-#define TIM_CCxN_Enable ((u16)0x0004)
-#define TIM_CCxN_Disable ((u16)0x0000)
+/** @defgroup TIM_Capture_Compare_N_state
+ * @{
+ */
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
((CCXN) == TIM_CCxN_Disable))
+/**
+ * @}
+ */
-/* Break Input enable/disable -----------------------------------------------*/
-#define TIM_Break_Enable ((u16)0x1000)
-#define TIM_Break_Disable ((u16)0x0000)
+/** @defgroup Break_Input_enable_disable
+ * @{
+ */
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
((STATE) == TIM_Break_Disable))
+/**
+ * @}
+ */
-/* Break Polarity -----------------------------------------------------------*/
-#define TIM_BreakPolarity_Low ((u16)0x0000)
-#define TIM_BreakPolarity_High ((u16)0x2000)
+/** @defgroup Break_Polarity
+ * @{
+ */
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
((POLARITY) == TIM_BreakPolarity_High))
+/**
+ * @}
+ */
-/* TIM AOE Bit Set/Reset ---------------------------------------------------*/
-#define TIM_AutomaticOutput_Enable ((u16)0x4000)
-#define TIM_AutomaticOutput_Disable ((u16)0x0000)
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
((STATE) == TIM_AutomaticOutput_Disable))
-/* Lock levels --------------------------------------------------------------*/
-#define TIM_LOCKLevel_OFF ((u16)0x0000)
-#define TIM_LOCKLevel_1 ((u16)0x0100)
-#define TIM_LOCKLevel_2 ((u16)0x0200)
-#define TIM_LOCKLevel_3 ((u16)0x0300)
+/**
+ * @}
+ */
+/** @defgroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
((LEVEL) == TIM_LOCKLevel_1) || \
((LEVEL) == TIM_LOCKLevel_2) || \
((LEVEL) == TIM_LOCKLevel_3))
+/**
+ * @}
+ */
-/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
-#define TIM_OSSIState_Enable ((u16)0x0400)
-#define TIM_OSSIState_Disable ((u16)0x0000)
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
((STATE) == TIM_OSSIState_Disable))
+/**
+ * @}
+ */
-/* OSSR: Off-State Selection for Run mode states ----------------------------*/
-#define TIM_OSSRState_Enable ((u16)0x0800)
-#define TIM_OSSRState_Disable ((u16)0x0000)
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
((STATE) == TIM_OSSRState_Disable))
+/**
+ * @}
+ */
-/* TIM Output Compare Idle State -------------------------------------------*/
-#define TIM_OCIdleState_Set ((u16)0x0100)
-#define TIM_OCIdleState_Reset ((u16)0x0000)
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
((STATE) == TIM_OCIdleState_Reset))
+/**
+ * @}
+ */
-/* TIM Output Compare N Idle State -----------------------------------------*/
-#define TIM_OCNIdleState_Set ((u16)0x0200)
-#define TIM_OCNIdleState_Reset ((u16)0x0000)
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
((STATE) == TIM_OCNIdleState_Reset))
+/**
+ * @}
+ */
-/* TIM Input Capture Polarity ----------------------------------------------*/
-#define TIM_ICPolarity_Rising ((u16)0x0000)
-#define TIM_ICPolarity_Falling ((u16)0x0002)
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
((POLARITY) == TIM_ICPolarity_Falling))
+/**
+ * @}
+ */
-/* TIM Input Capture Selection ---------------------------------------------*/
-#define TIM_ICSelection_DirectTI ((u16)0x0001)
-#define TIM_ICSelection_IndirectTI ((u16)0x0002)
-#define TIM_ICSelection_TRC ((u16)0x0003)
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
((SELECTION) == TIM_ICSelection_IndirectTI) || \
((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
-/* TIM Input Capture Prescaler ---------------------------------------------*/
-#define TIM_ICPSC_DIV1 ((u16)0x0000)
-#define TIM_ICPSC_DIV2 ((u16)0x0004)
-#define TIM_ICPSC_DIV4 ((u16)0x0008)
-#define TIM_ICPSC_DIV8 ((u16)0x000C)
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
((PRESCALER) == TIM_ICPSC_DIV2) || \
((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
-/* TIM interrupt sources ---------------------------------------------------*/
-#define TIM_IT_Update ((u16)0x0001)
-#define TIM_IT_CC1 ((u16)0x0002)
-#define TIM_IT_CC2 ((u16)0x0004)
-#define TIM_IT_CC3 ((u16)0x0008)
-#define TIM_IT_CC4 ((u16)0x0010)
-#define TIM_IT_COM ((u16)0x0020)
-#define TIM_IT_Trigger ((u16)0x0040)
-#define TIM_IT_Break ((u16)0x0080)
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
-#define IS_TIM_IT(IT) ((((IT) & (u16)0xFF00) == 0x0000) && ((IT) != 0x0000))
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
- (((TIM_IT) & (u16)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
- (((TIM_IT) & (u16)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
- (((TIM_IT) & (u16)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
-
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
@@ -314,28 +518,33 @@
((IT) == TIM_IT_COM) || \
((IT) == TIM_IT_Trigger) || \
((IT) == TIM_IT_Break))
+/**
+ * @}
+ */
-/* TIM DMA Base address ----------------------------------------------------*/
-#define TIM_DMABase_CR1 ((u16)0x0000)
-#define TIM_DMABase_CR2 ((u16)0x0001)
-#define TIM_DMABase_SMCR ((u16)0x0002)
-#define TIM_DMABase_DIER ((u16)0x0003)
-#define TIM_DMABase_SR ((u16)0x0004)
-#define TIM_DMABase_EGR ((u16)0x0005)
-#define TIM_DMABase_CCMR1 ((u16)0x0006)
-#define TIM_DMABase_CCMR2 ((u16)0x0007)
-#define TIM_DMABase_CCER ((u16)0x0008)
-#define TIM_DMABase_CNT ((u16)0x0009)
-#define TIM_DMABase_PSC ((u16)0x000A)
-#define TIM_DMABase_ARR ((u16)0x000B)
-#define TIM_DMABase_RCR ((u16)0x000C)
-#define TIM_DMABase_CCR1 ((u16)0x000D)
-#define TIM_DMABase_CCR2 ((u16)0x000E)
-#define TIM_DMABase_CCR3 ((u16)0x000F)
-#define TIM_DMABase_CCR4 ((u16)0x0010)
-#define TIM_DMABase_BDTR ((u16)0x0011)
-#define TIM_DMABase_DCR ((u16)0x0012)
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
((BASE) == TIM_DMABase_CR2) || \
((BASE) == TIM_DMABase_SMCR) || \
@@ -355,27 +564,32 @@
((BASE) == TIM_DMABase_CCR4) || \
((BASE) == TIM_DMABase_BDTR) || \
((BASE) == TIM_DMABase_DCR))
+/**
+ * @}
+ */
-/* TIM DMA Burst Length ----------------------------------------------------*/
-#define TIM_DMABurstLength_1Byte ((u16)0x0000)
-#define TIM_DMABurstLength_2Bytes ((u16)0x0100)
-#define TIM_DMABurstLength_3Bytes ((u16)0x0200)
-#define TIM_DMABurstLength_4Bytes ((u16)0x0300)
-#define TIM_DMABurstLength_5Bytes ((u16)0x0400)
-#define TIM_DMABurstLength_6Bytes ((u16)0x0500)
-#define TIM_DMABurstLength_7Bytes ((u16)0x0600)
-#define TIM_DMABurstLength_8Bytes ((u16)0x0700)
-#define TIM_DMABurstLength_9Bytes ((u16)0x0800)
-#define TIM_DMABurstLength_10Bytes ((u16)0x0900)
-#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
-#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
-#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
-#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
-#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
-#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
-#define TIM_DMABurstLength_17Bytes ((u16)0x1000)
-#define TIM_DMABurstLength_18Bytes ((u16)0x1100)
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
((LENGTH) == TIM_DMABurstLength_2Bytes) || \
((LENGTH) == TIM_DMABurstLength_3Bytes) || \
@@ -394,47 +608,55 @@
((LENGTH) == TIM_DMABurstLength_16Bytes) || \
((LENGTH) == TIM_DMABurstLength_17Bytes) || \
((LENGTH) == TIM_DMABurstLength_18Bytes))
+/**
+ * @}
+ */
-/* TIM DMA sources ---------------------------------------------------------*/
-#define TIM_DMA_Update ((u16)0x0100)
-#define TIM_DMA_CC1 ((u16)0x0200)
-#define TIM_DMA_CC2 ((u16)0x0400)
-#define TIM_DMA_CC3 ((u16)0x0800)
-#define TIM_DMA_CC4 ((u16)0x1000)
-#define TIM_DMA_COM ((u16)0x2000)
-#define TIM_DMA_Trigger ((u16)0x4000)
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
- (((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
- (((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
- (((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
+/**
+ * @}
+ */
-/* TIM External Trigger Prescaler ------------------------------------------*/
-#define TIM_ExtTRGPSC_OFF ((u16)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
-/* TIM Internal Trigger Selection ------------------------------------------*/
-#define TIM_TS_ITR0 ((u16)0x0000)
-#define TIM_TS_ITR1 ((u16)0x0010)
-#define TIM_TS_ITR2 ((u16)0x0020)
-#define TIM_TS_ITR3 ((u16)0x0030)
-#define TIM_TS_TI1F_ED ((u16)0x0040)
-#define TIM_TS_TI1FP1 ((u16)0x0050)
-#define TIM_TS_TI2FP2 ((u16)0x0060)
-#define TIM_TS_ETRF ((u16)0x0070)
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
@@ -443,109 +665,159 @@
((SELECTION) == TIM_TS_TI1FP1) || \
((SELECTION) == TIM_TS_TI2FP2) || \
((SELECTION) == TIM_TS_ETRF))
-
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
-/* TIM TIx External Clock Source -------------------------------------------*/
-#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+ * @}
+ */
-/* TIM External Trigger Polarity -------------------------------------------*/
-#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
-
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
-/* TIM Prescaler Reload Mode -----------------------------------------------*/
-#define TIM_PSCReloadMode_Update ((u16)0x0000)
-#define TIM_PSCReloadMode_Immediate ((u16)0x0001)
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
-/* TIM Forced Action -------------------------------------------------------*/
-#define TIM_ForcedAction_Active ((u16)0x0050)
-#define TIM_ForcedAction_InActive ((u16)0x0040)
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
-/* TIM Encoder Mode --------------------------------------------------------*/
-#define TIM_EncoderMode_TI1 ((u16)0x0001)
-#define TIM_EncoderMode_TI2 ((u16)0x0002)
-#define TIM_EncoderMode_TI12 ((u16)0x0003)
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
((MODE) == TIM_EncoderMode_TI2) || \
((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
-/* TIM Event Source --------------------------------------------------------*/
-#define TIM_EventSource_Update ((u16)0x0001)
-#define TIM_EventSource_CC1 ((u16)0x0002)
-#define TIM_EventSource_CC2 ((u16)0x0004)
-#define TIM_EventSource_CC3 ((u16)0x0008)
-#define TIM_EventSource_CC4 ((u16)0x0010)
-#define TIM_EventSource_COM ((u16)0x0020)
-#define TIM_EventSource_Trigger ((u16)0x0040)
-#define TIM_EventSource_Break ((u16)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+/** @defgroup TIM_Event_Source
+ * @{
+ */
-#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
- (((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
- (((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
- (((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-/* TIM Update Source --------------------------------------------------------*/
-#define TIM_UpdateSource_Global ((u16)0x0000)
-#define TIM_UpdateSource_Regular ((u16)0x0001)
+/**
+ * @}
+ */
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
-/* TIM Ouput Compare Preload State ------------------------------------------*/
-#define TIM_OCPreload_Enable ((u16)0x0008)
-#define TIM_OCPreload_Disable ((u16)0x0000)
+/** @defgroup TIM_Ouput_Compare_Preload_State
+ * @{
+ */
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
-/* TIM Ouput Compare Fast State ---------------------------------------------*/
-#define TIM_OCFast_Enable ((u16)0x0004)
-#define TIM_OCFast_Disable ((u16)0x0000)
+/** @defgroup TIM_Ouput_Compare_Fast_State
+ * @{
+ */
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
((STATE) == TIM_OCFast_Disable))
-/* TIM Ouput Compare Clear State --------------------------------------------*/
-#define TIM_OCClear_Enable ((u16)0x0080)
-#define TIM_OCClear_Disable ((u16)0x0000)
+/**
+ * @}
+ */
+/** @defgroup TIM_Ouput_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
-/* TIM Trigger Output Source ------------------------------------------------*/
-#define TIM_TRGOSource_Reset ((u16)0x0000)
-#define TIM_TRGOSource_Enable ((u16)0x0010)
-#define TIM_TRGOSource_Update ((u16)0x0020)
-#define TIM_TRGOSource_OC1 ((u16)0x0030)
-#define TIM_TRGOSource_OC1Ref ((u16)0x0040)
-#define TIM_TRGOSource_OC2Ref ((u16)0x0050)
-#define TIM_TRGOSource_OC3Ref ((u16)0x0060)
-#define TIM_TRGOSource_OC4Ref ((u16)0x0070)
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
((SOURCE) == TIM_TRGOSource_Enable) || \
((SOURCE) == TIM_TRGOSource_Update) || \
@@ -554,75 +826,54 @@
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+ * @}
+ */
-#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_Reset)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_Enable)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_Update)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_OC1)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\
- ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
- (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
- ((TRGO) == TIM_TRGOSource_OC4Ref)))
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
-/* TIM Slave Mode ----------------------------------------------------------*/
-#define TIM_SlaveMode_Reset ((u16)0x0004)
-#define TIM_SlaveMode_Gated ((u16)0x0005)
-#define TIM_SlaveMode_Trigger ((u16)0x0006)
-#define TIM_SlaveMode_External1 ((u16)0x0007)
-
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
((MODE) == TIM_SlaveMode_Gated) || \
((MODE) == TIM_SlaveMode_Trigger) || \
((MODE) == TIM_SlaveMode_External1))
+/**
+ * @}
+ */
-/* TIM Master Slave Mode ---------------------------------------------------*/
-#define TIM_MasterSlaveMode_Enable ((u16)0x0080)
-#define TIM_MasterSlaveMode_Disable ((u16)0x0000)
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
-/* TIM Flags ---------------------------------------------------------------*/
-#define TIM_FLAG_Update ((u16)0x0001)
-#define TIM_FLAG_CC1 ((u16)0x0002)
-#define TIM_FLAG_CC2 ((u16)0x0004)
-#define TIM_FLAG_CC3 ((u16)0x0008)
-#define TIM_FLAG_CC4 ((u16)0x0010)
-#define TIM_FLAG_COM ((u16)0x0020)
-#define TIM_FLAG_Trigger ((u16)0x0040)
-#define TIM_FLAG_Break ((u16)0x0080)
-#define TIM_FLAG_CC1OF ((u16)0x0200)
-#define TIM_FLAG_CC2OF ((u16)0x0400)
-#define TIM_FLAG_CC3OF ((u16)0x0800)
-#define TIM_FLAG_CC4OF ((u16)0x1000)
+/** @defgroup TIM_Flags
+ * @{
+ */
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_COM ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_Break ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
((FLAG) == TIM_FLAG_CC1) || \
((FLAG) == TIM_FLAG_CC2) || \
@@ -635,43 +886,47 @@
((FLAG) == TIM_FLAG_CC2OF) || \
((FLAG) == TIM_FLAG_CC3OF) || \
((FLAG) == TIM_FLAG_CC4OF))
+
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
-#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
- (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
- (((TIM_FLAG) & (u16)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
- (((TIM_FLAG) & (u16)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
- (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
- (((TIM_FLAG) & (u16)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
-#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) ||\
- ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
- ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
- (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\
- ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \
- ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\
- ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) ||\
- ((*(u32*)&(PERIPH))==TIM1_BASE)|| ((*(u32*)&(PERIPH))==TIM8_BASE) || \
- ((*(u32*)&(PERIPH))==TIM7_BASE) || ((*(u32*)&(PERIPH))==TIM6_BASE)) && \
- (((TIM_FLAG) == TIM_FLAG_Update))) ||\
- ((((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) &&\
- (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\
- ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
- ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
- ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
- (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\
- ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
-
-/* TIM Input Capture Filer Value ---------------------------------------------*/
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
-/* TIM External Trigger Filter -----------------------------------------------*/
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions
+ * @{
+ */
+
void TIM_DeInit(TIM_TypeDef* TIMx);
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
@@ -687,92 +942,99 @@
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
- u16 TIM_ICPolarity, u16 ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
- u16 ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
- u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
- u16 ExtTRGFilter);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
- u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
-u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
-u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
-u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
-u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
-u16 TIM_GetCounter(TIM_TypeDef* TIMx);
-u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
-
-#endif /*__STM32F10x_TIM_H */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+#ifdef __cplusplus
+}
+#endif
+#endif /*__STM32F10x_TIM_H */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
-
-
-
-
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_type.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_type.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_type.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,80 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_type.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the common data types used for the
-* STM32F10x firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_TYPE_H
-#define __STM32F10x_TYPE_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-typedef signed long s32;
-typedef signed short s16;
-typedef signed char s8;
-
-typedef signed long const sc32; /* Read Only */
-typedef signed short const sc16; /* Read Only */
-typedef signed char const sc8; /* Read Only */
-
-typedef volatile signed long vs32;
-typedef volatile signed short vs16;
-typedef volatile signed char vs8;
-
-typedef volatile signed long const vsc32; /* Read Only */
-typedef volatile signed short const vsc16; /* Read Only */
-typedef volatile signed char const vsc8; /* Read Only */
-
-typedef unsigned long u32;
-typedef unsigned short u16;
-typedef unsigned char u8;
-
-typedef unsigned long const uc32; /* Read Only */
-typedef unsigned short const uc16; /* Read Only */
-typedef unsigned char const uc8; /* Read Only */
-
-typedef volatile unsigned long vu32;
-typedef volatile unsigned short vu16;
-typedef volatile unsigned char vu8;
-
-typedef volatile unsigned long const vuc32; /* Read Only */
-typedef volatile unsigned short const vuc16; /* Read Only */
-typedef volatile unsigned char const vuc8; /* Read Only */
-
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-#define U8_MAX ((u8)255)
-#define S8_MAX ((s8)127)
-#define S8_MIN ((s8)-128)
-#define U16_MAX ((u16)65535u)
-#define S16_MAX ((s16)32767)
-#define S16_MIN ((s16)-32768)
-#define U32_MAX ((u32)4294967295uL)
-#define S32_MAX ((s32)2147483647)
-#define S32_MIN ((s32)-2147483648)
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __STM32F10x_TYPE_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_usart.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_usart.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_usart.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,253 +1,409 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_usart.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* USART firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_USART_H
#define __STM32F10x_USART_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* USART Init Structure definition */
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+
typedef struct
{
- u32 USART_BaudRate;
- u16 USART_WordLength;
- u16 USART_StopBits;
- u16 USART_Parity;
- u16 USART_Mode;
- u16 USART_HardwareFlowControl;
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
-/* USART Clock Init Structure definition */
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
typedef struct
{
- u16 USART_Clock;
- u16 USART_CPOL;
- u16 USART_CPHA;
- u16 USART_LastBit;
+
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
-/* Exported constants --------------------------------------------------------*/
-#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
- ((*(u32*)&(PERIPH)) == USART2_BASE) || \
- ((*(u32*)&(PERIPH)) == USART3_BASE) || \
- ((*(u32*)&(PERIPH)) == UART4_BASE) || \
- ((*(u32*)&(PERIPH)) == UART5_BASE))
+/**
+ * @}
+ */
-#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
- ((*(u32*)&(PERIPH)) == USART2_BASE) || \
- ((*(u32*)&(PERIPH)) == USART3_BASE))
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4) || \
+ ((PERIPH) == UART5))
-#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
- ((*(u32*)&(PERIPH)) == USART2_BASE) || \
- ((*(u32*)&(PERIPH)) == USART3_BASE) || \
- ((*(u32*)&(PERIPH)) == UART4_BASE))
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3))
-/* USART Word Length ---------------------------------------------------------*/
-#define USART_WordLength_8b ((u16)0x0000)
-#define USART_WordLength_9b ((u16)0x1000)
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint16_t)0x0000)
+#define USART_WordLength_9b ((uint16_t)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
+/**
+ * @}
+ */
-/* USART Stop Bits -----------------------------------------------------------*/
-#define USART_StopBits_1 ((u16)0x0000)
-#define USART_StopBits_0_5 ((u16)0x1000)
-#define USART_StopBits_2 ((u16)0x2000)
-#define USART_StopBits_1_5 ((u16)0x3000)
-
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint16_t)0x0000)
+#define USART_StopBits_0_5 ((uint16_t)0x1000)
+#define USART_StopBits_2 ((uint16_t)0x2000)
+#define USART_StopBits_1_5 ((uint16_t)0x3000)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_0_5) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
-/* USART Parity --------------------------------------------------------------*/
-#define USART_Parity_No ((u16)0x0000)
-#define USART_Parity_Even ((u16)0x0400)
-#define USART_Parity_Odd ((u16)0x0600)
+/**
+ * @}
+ */
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint16_t)0x0000)
+#define USART_Parity_Even ((uint16_t)0x0400)
+#define USART_Parity_Odd ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
-/* USART Mode ----------------------------------------------------------------*/
-#define USART_Mode_Rx ((u16)0x0004)
-#define USART_Mode_Tx ((u16)0x0008)
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx ((uint16_t)0x0004)
+#define USART_Mode_Tx ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
-#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00))
-
-/* USART Hardware Flow Control -----------------------------------------------*/
-#define USART_HardwareFlowControl_None ((u16)0x0000)
-#define USART_HardwareFlowControl_RTS ((u16)0x0100)
-#define USART_HardwareFlowControl_CTS ((u16)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)
-
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
-#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
- ((*(u32*)&(PERIPH)) != UART5_BASE)) \
- || ((HFC) == USART_HardwareFlowControl_None))
-
-/* USART Clock ---------------------------------------------------------------*/
-#define USART_Clock_Disable ((u16)0x0000)
-#define USART_Clock_Enable ((u16)0x0800)
-
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_Clock_Disable ((uint16_t)0x0000)
+#define USART_Clock_Enable ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
-/* USART Clock Polarity ------------------------------------------------------*/
-#define USART_CPOL_Low ((u16)0x0000)
-#define USART_CPOL_High ((u16)0x0400)
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint16_t)0x0000)
+#define USART_CPOL_High ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/* USART Clock Phase ---------------------------------------------------------*/
-#define USART_CPHA_1Edge ((u16)0x0000)
-#define USART_CPHA_2Edge ((u16)0x0200)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint16_t)0x0000)
+#define USART_CPHA_2Edge ((uint16_t)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-/* USART Last Bit ------------------------------------------------------------*/
-#define USART_LastBit_Disable ((u16)0x0000)
-#define USART_LastBit_Enable ((u16)0x0100)
+/**
+ * @}
+ */
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint16_t)0x0000)
+#define USART_LastBit_Enable ((uint16_t)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
-/* USART Interrupt definition ------------------------------------------------*/
-#define USART_IT_PE ((u16)0x0028)
-#define USART_IT_TXE ((u16)0x0727)
-#define USART_IT_TC ((u16)0x0626)
-#define USART_IT_RXNE ((u16)0x0525)
-#define USART_IT_IDLE ((u16)0x0424)
-#define USART_IT_LBD ((u16)0x0846)
-#define USART_IT_CTS ((u16)0x096A)
-#define USART_IT_ERR ((u16)0x0060)
-#define USART_IT_ORE ((u16)0x0360)
-#define USART_IT_NE ((u16)0x0260)
-#define USART_IT_FE ((u16)0x0160)
-
+/** @defgroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_LBD ((uint16_t)0x0846)
+#define USART_IT_CTS ((uint16_t)0x096A)
+#define USART_IT_ERR ((uint16_t)0x0060)
+#define USART_IT_ORE ((uint16_t)0x0360)
+#define USART_IT_NE ((uint16_t)0x0260)
+#define USART_IT_FE ((uint16_t)0x0160)
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+ * @}
+ */
-#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
- ((*(u32*)&(PERIPH)) != UART5_BASE)) \
- || ((USART_IT) != USART_IT_CTS))
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
-/* USART DMA Requests --------------------------------------------------------*/
-#define USART_DMAReq_Tx ((u16)0x0080)
-#define USART_DMAReq_Rx ((u16)0x0040)
+#define USART_DMAReq_Tx ((uint16_t)0x0080)
+#define USART_DMAReq_Rx ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00))
+/**
+ * @}
+ */
-/* USART WakeUp methods ------------------------------------------------------*/
-#define USART_WakeUp_IdleLine ((u16)0x0000)
-#define USART_WakeUp_AddressMark ((u16)0x0800)
+/** @defgroup USART_WakeUp_methods
+ * @{
+ */
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
-/* USART LIN Break Detection Length ------------------------------------------*/
-#define USART_LINBreakDetectLength_10b ((u16)0x0000)
-#define USART_LINBreakDetectLength_11b ((u16)0x0020)
-
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
-/* USART IrDA Low Power ------------------------------------------------------*/
-#define USART_IrDAMode_LowPower ((u16)0x0004)
-#define USART_IrDAMode_Normal ((u16)0x0000)
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
-/* USART Flags ---------------------------------------------------------------*/
-#define USART_FLAG_CTS ((u16)0x0200)
-#define USART_FLAG_LBD ((u16)0x0100)
-#define USART_FLAG_TXE ((u16)0x0080)
-#define USART_FLAG_TC ((u16)0x0040)
-#define USART_FLAG_RXNE ((u16)0x0020)
-#define USART_FLAG_IDLE ((u16)0x0010)
-#define USART_FLAG_ORE ((u16)0x0008)
-#define USART_FLAG_NE ((u16)0x0004)
-#define USART_FLAG_FE ((u16)0x0002)
-#define USART_FLAG_PE ((u16)0x0001)
+/** @defgroup USART_Flags
+ * @{
+ */
+#define USART_FLAG_CTS ((uint16_t)0x0200)
+#define USART_FLAG_LBD ((uint16_t)0x0100)
+#define USART_FLAG_TXE ((uint16_t)0x0080)
+#define USART_FLAG_TC ((uint16_t)0x0040)
+#define USART_FLAG_RXNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLE ((uint16_t)0x0010)
+#define USART_FLAG_ORE ((uint16_t)0x0008)
+#define USART_FLAG_NE ((uint16_t)0x0004)
+#define USART_FLAG_FE ((uint16_t)0x0002)
+#define USART_FLAG_PE ((uint16_t)0x0001)
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00))
-
-#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\
- ((*(u32*)&(PERIPH)) != UART5_BASE)) \
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+ ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_FLAG) != USART_FLAG_CTS))
-
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions
+ * @{
+ */
+
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
-void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
-void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendData(USART_TypeDef* USARTx, u16 Data);
-u16 USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
-void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
-void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_USART_H */
+/**
+ * @}
+ */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_wwdg.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_wwdg.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/inc/stm32f10x_wwdg.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,54 +1,114 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_wwdg.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains all the functions prototypes for the
-* WWDG firmware library.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains all the functions prototypes for the WWDG firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_WWDG_H
#define __STM32F10x_WWDG_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
+#include "stm32f10x.h"
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* WWDG Prescaler */
-#define WWDG_Prescaler_1 ((u32)0x00000000)
-#define WWDG_Prescaler_2 ((u32)0x00000080)
-#define WWDG_Prescaler_4 ((u32)0x00000100)
-#define WWDG_Prescaler_8 ((u32)0x00000180)
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
-
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions
+ * @{
+ */
+
void WWDG_DeInit(void);
-void WWDG_SetPrescaler(u32 WWDG_Prescaler);
-void WWDG_SetWindowValue(u8 WindowValue);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
-void WWDG_SetCounter(u8 Counter);
-void WWDG_Enable(u8 Counter);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __STM32F10x_WWDG_H */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Added: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/misc.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/misc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/misc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file misc.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @defgroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Property changes on: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/misc.c
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_adc.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_adc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_adc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,1402 +1,1306 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_adc.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the ADC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_adc.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ADC DISCNUM mask */
-#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF)
-
-/* ADC DISCEN mask */
-#define CR1_DISCEN_Set ((u32)0x00000800)
-#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF)
-
-/* ADC JAUTO mask */
-#define CR1_JAUTO_Set ((u32)0x00000400)
-#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF)
-
-/* ADC JDISCEN mask */
-#define CR1_JDISCEN_Set ((u32)0x00001000)
-#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF)
-
-/* ADC AWDCH mask */
-#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CR1_AWDMode_Reset ((u32)0xFF3FFDFF)
-
-/* CR1 register Mask */
-#define CR1_CLEAR_Mask ((u32)0xFFF0FEFF)
-
-/* ADC ADON mask */
-#define CR2_ADON_Set ((u32)0x00000001)
-#define CR2_ADON_Reset ((u32)0xFFFFFFFE)
-
-/* ADC DMA mask */
-#define CR2_DMA_Set ((u32)0x00000100)
-#define CR2_DMA_Reset ((u32)0xFFFFFEFF)
-
-/* ADC RSTCAL mask */
-#define CR2_RSTCAL_Set ((u32)0x00000008)
-
-/* ADC CAL mask */
-#define CR2_CAL_Set ((u32)0x00000004)
-
-/* ADC SWSTART mask */
-#define CR2_SWSTART_Set ((u32)0x00400000)
-
-/* ADC EXTTRIG mask */
-#define CR2_EXTTRIG_Set ((u32)0x00100000)
-#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF)
-
-/* ADC Software start mask */
-#define CR2_EXTTRIG_SWSTART_Set ((u32)0x00500000)
-#define CR2_EXTTRIG_SWSTART_Reset ((u32)0xFFAFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF)
-
-/* ADC JEXTTRIG mask */
-#define CR2_JEXTTRIG_Set ((u32)0x00008000)
-#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF)
-
-/* ADC JSWSTART mask */
-#define CR2_JSWSTART_Set ((u32)0x00200000)
-
-/* ADC injected software start mask */
-#define CR2_JEXTTRIG_JSWSTART_Set ((u32)0x00208000)
-#define CR2_JEXTTRIG_JSWSTART_Reset ((u32)0xFFDF7FFF)
-
-/* ADC TSPD mask */
-#define CR2_TSVREFE_Set ((u32)0x00800000)
-#define CR2_TSVREFE_Reset ((u32)0xFF7FFFFF)
-
-/* CR2 register Mask */
-#define CR2_CLEAR_Mask ((u32)0xFFF1F7FD)
-
-/* ADC SQx mask */
-#define SQR3_SQ_Set ((u32)0x0000001F)
-#define SQR2_SQ_Set ((u32)0x0000001F)
-#define SQR1_SQ_Set ((u32)0x0000001F)
-
-/* SQR1 register Mask */
-#define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define JSQR_JSQ_Set ((u32)0x0000001F)
-
-/* ADC JL mask */
-#define JSQR_JL_Set ((u32)0x00300000)
-#define JSQR_JL_Reset ((u32)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SMPR1_SMP_Set ((u32)0x00000007)
-#define SMPR2_SMP_Set ((u32)0x00000007)
-
-/* ADC JDRx registers offset */
-#define JDR_Offset ((u8)0x28)
-
-/* ADC1 DR register base address */
-#define DR_ADDRESS ((u32)0x4001244C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : ADC_DeInit
-* Description : Deinitializes the ADCx peripheral registers to their default
-* reset values.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_DeInit(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- switch (*(u32*)&ADCx)
- {
- case ADC1_BASE:
- /* Enable ADC1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
- /* Release ADC1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
- break;
-
- case ADC2_BASE:
- /* Enable ADC2 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
- /* Release ADC2 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
- break;
-
- case ADC3_BASE:
- /* Enable ADC3 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
- /* Release ADC3 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_Init
-* Description : Initializes the ADCx peripheral according to the specified parameters
-* in the ADC_InitStruct.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that
-* contains the configuration information for the specified
-* ADC peripheral.
-* Output : None
-* Return : None
-******************************************************************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- u32 tmpreg1 = 0;
- u8 tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
-
- /*---------------------------- ADCx CR1 Configuration -----------------*/
- /* Get the ADCx CR1 value */
- tmpreg1 = ADCx->CR1;
- /* Clear DUALMOD and SCAN bits */
- tmpreg1 &= CR1_CLEAR_Mask;
- /* Configure ADCx: Dual mode and scan conversion mode */
- /* Set DUALMOD bits according to ADC_Mode value */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
- /* Write to ADCx CR1 */
- ADCx->CR1 = tmpreg1;
-
- /*---------------------------- ADCx CR2 Configuration -----------------*/
- /* Get the ADCx CR2 value */
- tmpreg1 = ADCx->CR2;
- /* Clear CONT, ALIGN and EXTSEL bits */
- tmpreg1 &= CR2_CLEAR_Mask;
- /* Configure ADCx: external trigger event and continuous conversion mode */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
- ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
- /* Write to ADCx CR2 */
- ADCx->CR2 = tmpreg1;
-
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
- /* Clear L bits */
- tmpreg1 &= SQR1_CLEAR_Mask;
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfChannel value */
- tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
- tmpreg1 |= ((u32)tmpreg2 << 20);
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-}
-
-/*******************************************************************************
-* Function Name : ADC_StructInit
-* Description : Fills each ADC_InitStruct member with its default value.
-* Input : ADC_InitStruct : pointer to an ADC_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Reset ADC init structure parameters values */
- /* Initialize the ADC_Mode member */
- ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
-
- /* initialize the ADC_ScanConvMode member */
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_NbrOfChannel member */
- ADC_InitStruct->ADC_NbrOfChannel = 1;
-}
-
-/*******************************************************************************
-* Function Name : ADC_Cmd
-* Description : Enables or disables the specified ADC peripheral.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the ADCx peripheral. This parameter
-* can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ADON bit to wake up the ADC from power down mode */
- ADCx->CR2 |= CR2_ADON_Set;
- }
- else
- {
- /* Disable the selected ADC peripheral */
- ADCx->CR2 &= CR2_ADON_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_DMACmd
-* Description : Enables or disables the specified ADC DMA request.
-* Input : - ADCx: where x can be 1 or 3 to select the ADC peripheral.
-* Note: ADC2 hasn't a DMA capability.
-* - NewState: new state of the selected ADC DMA transfer.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_DMA_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CR2 |= CR2_DMA_Set;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CR2 &= CR2_DMA_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_ITConfig
-* Description : Enables or disables the specified ADC interrupts.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_IT: specifies the ADC interrupt sources to be enabled
-* or disabled.
-* This parameter can be any combination of the following values:
-* - ADC_IT_EOC: End of conversion interrupt mask
-* - ADC_IT_AWD: Analog watchdog interrupt mask
-* - ADC_IT_JEOC: End of injected conversion interrupt mask
-* - NewState: new state of the specified ADC interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState)
-{
- u8 itmask = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = (u8)ADC_IT;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->CR1 |= itmask;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->CR1 &= (~(u32)itmask);
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_ResetCalibration
-* Description : Resets the selected ADC calibration registers.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ResetCalibration(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Resets the selected ADC calibartion registers */
- ADCx->CR2 |= CR2_RSTCAL_Set;
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetResetCalibrationStatus
-* Description : Gets the selected ADC reset calibration registers status.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : The new state of ADC reset calibration registers (SET or RESET).
-*******************************************************************************/
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of RSTCAL bit */
- if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u32)RESET)
- {
- /* RSTCAL bit is set */
- bitstatus = SET;
- }
- else
- {
- /* RSTCAL bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the RSTCAL bit status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : ADC_StartCalibration
-* Description : Starts the selected ADC calibration process.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_StartCalibration(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Enable the selected ADC calibration process */
- ADCx->CR2 |= CR2_CAL_Set;
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetCalibrationStatus
-* Description : Gets the selected ADC calibration status.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : The new state of ADC calibration (SET or RESET).
-*******************************************************************************/
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of CAL bit */
- if ((ADCx->CR2 & CR2_CAL_Set) != (u32)RESET)
- {
- /* CAL bit is set: calibration on going */
- bitstatus = SET;
- }
- else
- {
- /* CAL bit is reset: end of calibration */
- bitstatus = RESET;
- }
-
- /* Return the CAL bit status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : ADC_SoftwareStartConvCmd
-* Description : Enables or disables the selected ADC software start conversion .
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC software start conversion.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC conversion on external event and start the selected
- ADC conversion */
- ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
- }
- else
- {
- /* Disable the selected ADC conversion on external event and stop the selected
- ADC conversion */
- ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetSoftwareStartConvStatus
-* Description : Gets the selected ADC Software start conversion Status.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : The new state of ADC software start conversion (SET or RESET).
-*******************************************************************************/
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of SWSTART bit */
- if ((ADCx->CR2 & CR2_SWSTART_Set) != (u32)RESET)
- {
- /* SWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* SWSTART bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the SWSTART bit status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : ADC_DiscModeChannelCountConfig
-* Description : Configures the discontinuous mode for the selected ADC regular
-* group channel.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - Number: specifies the discontinuous mode regular channel
-* count value. This number must be between 1 and 8.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
-{
- u32 tmpreg1 = 0;
- u32 tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
-
- /* Get the old register value */
- tmpreg1 = ADCx->CR1;
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= CR1_DISCNUM_Reset;
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 13;
- /* Store the new register value */
- ADCx->CR1 = tmpreg1;
-}
-
-/*******************************************************************************
-* Function Name : ADC_DiscModeCmd
-* Description : Enables or disables the discontinuous mode on regular group
-* channel for the specified ADC
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC discontinuous mode
-* on regular group channel.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CR1 |= CR1_DISCEN_Set;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CR1 &= CR1_DISCEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_RegularChannelConfig
-* Description : Configures for the selected ADC regular channel its corresponding
-* rank in the sequencer and its sample time.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_Channel: the ADC channel to configure.
-* This parameter can be one of the following values:
-* - ADC_Channel_0: ADC Channel0 selected
-* - ADC_Channel_1: ADC Channel1 selected
-* - ADC_Channel_2: ADC Channel2 selected
-* - ADC_Channel_3: ADC Channel3 selected
-* - ADC_Channel_4: ADC Channel4 selected
-* - ADC_Channel_5: ADC Channel5 selected
-* - ADC_Channel_6: ADC Channel6 selected
-* - ADC_Channel_7: ADC Channel7 selected
-* - ADC_Channel_8: ADC Channel8 selected
-* - ADC_Channel_9: ADC Channel9 selected
-* - ADC_Channel_10: ADC Channel10 selected
-* - ADC_Channel_11: ADC Channel11 selected
-* - ADC_Channel_12: ADC Channel12 selected
-* - ADC_Channel_13: ADC Channel13 selected
-* - ADC_Channel_14: ADC Channel14 selected
-* - ADC_Channel_15: ADC Channel15 selected
-* - ADC_Channel_16: ADC Channel16 selected
-* - ADC_Channel_17: ADC Channel17 selected
-* - Rank: The rank in the regular group sequencer. This parameter
-* must be between 1 to 16.
-* - ADC_SampleTime: The sample time value to be set for the
-* selected channel.
-* This parameter can be one of the following values:
-* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
-* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
-* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
-* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
-* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
-* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
-* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
-* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
-{
- u32 tmpreg1 = 0, tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_REGULAR_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
- /* Set the discontinuous mode channel count */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the discontinuous mode channel count */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* For Rank 1 to 6 */
- if (Rank < 7)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
- /* Calculate the mask to clear */
- tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- /* For Rank 7 to 12 */
- else if (Rank < 13)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
- /* Calculate the mask to clear */
- tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 13 to 16 */
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
- /* Calculate the mask to clear */
- tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_ExternalTrigConvCmd
-* Description : Enables or disables the ADCx conversion through external trigger.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC external trigger
-* start of conversion.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC conversion on external event */
- ADCx->CR2 |= CR2_EXTTRIG_Set;
- }
- else
- {
- /* Disable the selected ADC conversion on external event */
- ADCx->CR2 &= CR2_EXTTRIG_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetConversionValue
-* Description : Returns the last ADCx conversion result data for regular channel.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : The Data conversion value.
-*******************************************************************************/
-u16 ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (u16) ADCx->DR;
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetDualModeConversionValue
-* Description : Returns the last ADC1 and ADC2 conversion result data in dual mode.
-* Output : None
-* Return : The Data conversion value.
-*******************************************************************************/
-u32 ADC_GetDualModeConversionValue(void)
-{
- /* Return the dual mode conversion value */
- return (*(vu32 *) DR_ADDRESS);
-}
-
-/*******************************************************************************
-* Function Name : ADC_AutoInjectedConvCmd
-* Description : Enables or disables the selected ADC automatic injected group
-* conversion after regular one.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC auto injected
-* conversion
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CR1 |= CR1_JAUTO_Set;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CR1 &= CR1_JAUTO_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_InjectedDiscModeCmd
-* Description : Enables or disables the discontinuous mode for injected group
-* channel for the specified ADC
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC discontinuous mode
-* on injected group channel.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CR1 |= CR1_JDISCEN_Set;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CR1 &= CR1_JDISCEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_ExternalTrigInjectedConvConfig
-* Description : Configures the ADCx external trigger for injected channels conversion.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_ExternalTrigInjecConv: specifies the ADC trigger to
-* start injected conversion.
-* This parameter can be one of the following values:
-* - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event
-* selected (for ADC1, ADC2 and ADC3)
-* - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture
-* compare4 selected (for ADC1, ADC2 and ADC3)
-* - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event
-* selected (for ADC1 and ADC2)
-* - ADC_External TrigInjecConv_T2_CC1: Timer2 capture
-* compare1 selected (for ADC1 and ADC2)
-* - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture
-* compare4 selected (for ADC1 and ADC2)
-* - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event
-* selected (for ADC1 and ADC2)
-* - ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External
-* interrupt line 15 or Timer8 capture compare4 event selected
-* (for ADC1 and ADC2)
-* - ADC_External TrigInjecConv_T4_CC3: Timer4 capture
-* compare3 selected (for ADC3 only)
-* - ADC_External TrigInjecConv_T8_CC2: Timer8 capture
-* compare2 selected (for ADC3 only)
-* - ADC_External TrigInjecConv_T8_CC4: Timer8 capture
-* compare4 selected (for ADC3 only)
-* - ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event
-* selected (for ADC3 only)
-* - ADC_External TrigInjecConv_T5_CC4: Timer5 capture
-* compare4 selected (for ADC3 only)
-* - ADC_ExternalTrigInjecConv_None: Injected conversion
-* started by software and not by external trigger (for
-* ADC1, ADC2 and ADC3)
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
-
- /* Get the old register value */
- tmpreg = ADCx->CR2;
- /* Clear the old external event selection for injected group */
- tmpreg &= CR2_JEXTSEL_Reset;
- /* Set the external event selection for injected group */
- tmpreg |= ADC_ExternalTrigInjecConv;
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : ADC_ExternalTrigInjectedConvCmd
-* Description : Enables or disables the ADCx injected channels conversion
-* through external trigger
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC external trigger
-* start of injected conversion.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC external event selection for injected group */
- ADCx->CR2 |= CR2_JEXTTRIG_Set;
- }
- else
- {
- /* Disable the selected ADC external event selection for injected group */
- ADCx->CR2 &= CR2_JEXTTRIG_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_SoftwareStartInjectedConvCmd
-* Description : Enables or disables the selected ADC start of the injected
-* channels conversion.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - NewState: new state of the selected ADC software start
-* injected conversion.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC conversion for injected group on external event and start the selected
- ADC injected conversion */
- ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
- }
- else
- {
- /* Disable the selected ADC conversion on external event for injected group and stop the selected
- ADC injected conversion */
- ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetSoftwareStartInjectedConvCmdStatus
-* Description : Gets the selected ADC Software start injected conversion Status.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* Output : None
-* Return : The new state of ADC software start injected conversion (SET or RESET).
-*******************************************************************************/
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of JSWSTART bit */
- if ((ADCx->CR2 & CR2_JSWSTART_Set) != (u32)RESET)
- {
- /* JSWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JSWSTART bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the JSWSTART bit status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : ADC_InjectedChannelConfig
-* Description : Configures for the selected ADC injected channel its corresponding
-* rank in the sequencer and its sample time.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_Channel: the ADC channel to configure.
-* This parameter can be one of the following values:
-* - ADC_Channel_0: ADC Channel0 selected
-* - ADC_Channel_1: ADC Channel1 selected
-* - ADC_Channel_2: ADC Channel2 selected
-* - ADC_Channel_3: ADC Channel3 selected
-* - ADC_Channel_4: ADC Channel4 selected
-* - ADC_Channel_5: ADC Channel5 selected
-* - ADC_Channel_6: ADC Channel6 selected
-* - ADC_Channel_7: ADC Channel7 selected
-* - ADC_Channel_8: ADC Channel8 selected
-* - ADC_Channel_9: ADC Channel9 selected
-* - ADC_Channel_10: ADC Channel10 selected
-* - ADC_Channel_11: ADC Channel11 selected
-* - ADC_Channel_12: ADC Channel12 selected
-* - ADC_Channel_13: ADC Channel13 selected
-* - ADC_Channel_14: ADC Channel14 selected
-* - ADC_Channel_15: ADC Channel15 selected
-* - ADC_Channel_16: ADC Channel16 selected
-* - ADC_Channel_17: ADC Channel17 selected
-* - Rank: The rank in the injected group sequencer. This parameter
-* must be between 1 to 4.
-* - ADC_SampleTime: The sample time value to be set for the
-* selected channel.
-* This parameter can be one of the following values:
-* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
-* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
-* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
-* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
-* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
-* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
-* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
-* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
-{
- u32 tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_INJECTED_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10));
- /* Set the discontinuous mode channel count */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the discontinuous mode channel count */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
-
- /* Rank configuration */
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Get JL value: Number = JL+1 */
- tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = JSQR_JSQ_Set << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
- /* Clear the old JSQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = (u32)ADC_Channel << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
- /* Set the JSQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/*******************************************************************************
-* Function Name : ADC_InjectedSequencerLengthConfig
-* Description : Configures the sequencer length for injected channels
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - Length: The sequencer length.
-* This parameter must be a number between 1 to 4.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length)
-{
- u32 tmpreg1 = 0;
- u32 tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_LENGTH(Length));
-
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Clear the old injected sequnence lenght JL bits */
- tmpreg1 &= JSQR_JL_Reset;
- /* Set the injected sequnence lenght JL bits */
- tmpreg2 = Length - 1;
- tmpreg1 |= tmpreg2 << 20;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/*******************************************************************************
-* Function Name : ADC_SetInjectedOffset
-* Description : Set the injected channels conversion value offset
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_InjectedChannel: the ADC injected channel to set its
-* offset.
-* This parameter can be one of the following values:
-* - ADC_InjectedChannel_1: Injected Channel1 selected
-* - ADC_InjectedChannel_2: Injected Channel2 selected
-* - ADC_InjectedChannel_3: Injected Channel3 selected
-* - ADC_InjectedChannel_4: Injected Channel4 selected
-* - Offset: the offset value for the selected ADC injected channel
-* This parameter must be a 12bit value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- /* Set the selected injected channel data offset */
- *((vu32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetInjectedConversionValue
-* Description : Returns the ADC injected channel conversion result
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_InjectedChannel: the converted ADC injected channel.
-* This parameter can be one of the following values:
-* - ADC_InjectedChannel_1: Injected Channel1 selected
-* - ADC_InjectedChannel_2: Injected Channel2 selected
-* - ADC_InjectedChannel_3: Injected Channel3 selected
-* - ADC_InjectedChannel_4: Injected Channel4 selected
-* Output : None
-* Return : The Data conversion value.
-*******************************************************************************/
-u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
-
- /* Returns the selected injected channel conversion data value */
- return (u16) (*(vu32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
-}
-
-/*******************************************************************************
-* Function Name : ADC_AnalogWatchdogCmd
-* Description : Enables or disables the analog watchdog on single/all regular
-* or injected channels
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_AnalogWatchdog: the ADC analog watchdog configuration.
-* This parameter can be one of the following values:
-* - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on
-* a single regular channel
-* - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on
-* a single injected channel
-* - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog
-* watchdog on a single regular or injected channel
-* - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on
-* all regular channel
-* - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on
-* all injected channel
-* - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog
-* on all regular and injected channels
-* - ADC_AnalogWatchdog_None: No channel guarded by the
-* analog watchdog
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
- /* Clear AWDEN, AWDENJ and AWDSGL bits */
- tmpreg &= CR1_AWDMode_Reset;
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : ADC_AnalogWatchdogThresholdsConfig
-* Description : Configures the high and low thresholds of the analog watchdog.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - HighThreshold: the ADC analog watchdog High threshold value.
-* This parameter must be a 12bit value.
-* - LowThreshold: the ADC analog watchdog Low threshold value.
-* This parameter must be a 12bit value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold,
- u16 LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high threshold */
- ADCx->HTR = HighThreshold;
- /* Set the ADCx low threshold */
- ADCx->LTR = LowThreshold;
-}
-
-/*******************************************************************************
-* Function Name : ADC_AnalogWatchdogSingleChannelConfig
-* Description : Configures the analog watchdog guarded single channel
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_Channel: the ADC channel to configure for the analog
-* watchdog.
-* This parameter can be one of the following values:
-* - ADC_Channel_0: ADC Channel0 selected
-* - ADC_Channel_1: ADC Channel1 selected
-* - ADC_Channel_2: ADC Channel2 selected
-* - ADC_Channel_3: ADC Channel3 selected
-* - ADC_Channel_4: ADC Channel4 selected
-* - ADC_Channel_5: ADC Channel5 selected
-* - ADC_Channel_6: ADC Channel6 selected
-* - ADC_Channel_7: ADC Channel7 selected
-* - ADC_Channel_8: ADC Channel8 selected
-* - ADC_Channel_9: ADC Channel9 selected
-* - ADC_Channel_10: ADC Channel10 selected
-* - ADC_Channel_11: ADC Channel11 selected
-* - ADC_Channel_12: ADC Channel12 selected
-* - ADC_Channel_13: ADC Channel13 selected
-* - ADC_Channel_14: ADC Channel14 selected
-* - ADC_Channel_15: ADC Channel15 selected
-* - ADC_Channel_16: ADC Channel16 selected
-* - ADC_Channel_17: ADC Channel17 selected
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= CR1_AWDCH_Reset;
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_Channel;
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : ADC_TempSensorVrefintCmd
-* Description : Enables or disables the temperature sensor and Vrefint channel.
-* Input : - NewState: new state of the temperature sensor.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC1->CR2 |= CR2_TSVREFE_Set;
- }
- else
- {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC1->CR2 &= CR2_TSVREFE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetFlagStatus
-* Description : Checks whether the specified ADC flag is set or not.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - ADC_FLAG_AWD: Analog watchdog flag
-* - ADC_FLAG_EOC: End of conversion flag
-* - ADC_FLAG_JEOC: End of injected group conversion flag
-* - ADC_FLAG_JSTRT: Start of injected group conversion flag
-* - ADC_FLAG_STRT: Start of regular group conversion flag
-* Output : None
-* Return : The new state of ADC_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- /* Check the status of the specified ADC flag */
- if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : ADC_ClearFlag
-* Description : Clears the ADCx's pending flags.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_FLAG: specifies the flag to clear.
-* This parameter can be any combination of the following values:
-* - ADC_FLAG_AWD: Analog watchdog flag
-* - ADC_FLAG_EOC: End of conversion flag
-* - ADC_FLAG_JEOC: End of injected group conversion flag
-* - ADC_FLAG_JSTRT: Start of injected group conversion flag
-* - ADC_FLAG_STRT: Start of regular group conversion flag
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->SR = ~(u32)ADC_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : ADC_GetITStatus
-* Description : Checks whether the specified ADC interrupt has occurred or not.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_IT: specifies the ADC interrupt source to check.
-* This parameter can be one of the following values:
-* - ADC_IT_EOC: End of conversion interrupt mask
-* - ADC_IT_AWD: Analog watchdog interrupt mask
-* - ADC_IT_JEOC: End of injected conversion interrupt mask
-* Output : None
-* Return : The new state of ADC_IT (SET or RESET).
-*******************************************************************************/
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)
-{
- ITStatus bitstatus = RESET;
- u32 itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = ADC_IT >> 8;
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
-
- /* Check the status of the specified ADC interrupt */
- if (((ADCx->SR & itmask) != (u32)RESET) && enablestatus)
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : ADC_ClearITPendingBit
-* Description : Clears the ADCx's interrupt pending bits.
-* Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
-* - ADC_IT: specifies the ADC interrupt pending bit to clear.
-* This parameter can be any combination of the following values:
-* - ADC_IT_EOC: End of conversion interrupt mask
-* - ADC_IT_AWD: Analog watchdog interrupt mask
-* - ADC_IT_JEOC: End of injected conversion interrupt mask
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT)
-{
- u8 itmask = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = (u8)(ADC_IT >> 8);
-
- /* Clear the selected ADC interrupt pending bits */
- ADCx->SR = ~(u32)itmask;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the ADC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @defgroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set ((uint32_t)0x00000001)
+#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set ((uint32_t)0x00000100)
+#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set ((uint32_t)0x00300000)
+#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS ((uint32_t)0x4001244C)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ if (ADCx == ADC1)
+ {
+ /* Enable ADC1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+ }
+ else if (ADCx == ADC2)
+ {
+ /* Enable ADC2 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+ /* Release ADC2 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+ }
+ else
+ {
+ if (ADCx == ADC3)
+ {
+ /* Enable ADC3 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+ /* Release ADC3 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+ * the configuration information for the specified ADC peripheral.
+ * @retval None
+ */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+ /*---------------------------- ADCx CR1 Configuration -----------------*/
+ /* Get the ADCx CR1 value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CR1_CLEAR_Mask;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to ADC_Mode value */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+ /* Write to ADCx CR1 */
+ ADCx->CR1 = tmpreg1;
+
+ /*---------------------------- ADCx CR2 Configuration -----------------*/
+ /* Get the ADCx CR2 value */
+ tmpreg1 = ADCx->CR2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CR2_CLEAR_Mask;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to ADC_DataAlign value */
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+ /* Set CONT bit according to ADC_ContinuousConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+ /* Write to ADCx CR2 */
+ ADCx->CR2 = tmpreg1;
+
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+ /* Clear L bits */
+ tmpreg1 &= SQR1_CLEAR_Mask;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfChannel value */
+ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* Initialize the ADC_Mode member */
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+ /* initialize the ADC_ScanConvMode member */
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+ /* Initialize the ADC_ContinuousConvMode member */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+ /* Initialize the ADC_ExternalTrigConv member */
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+ /* Initialize the ADC_DataAlign member */
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+ /* Initialize the ADC_NbrOfChannel member */
+ ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ADON bit to wake up the ADC from power down mode */
+ ADCx->CR2 |= CR2_ADON_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CR2 &= CR2_ADON_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.
+ * Note: ADC2 hasn't a DMA capability.
+ * @param NewState: new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CR2 |= CR2_DMA_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CR2 &= CR2_DMA_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @param NewState: new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CR1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CR1 &= (~(uint32_t)itmask);
+ }
+}
+
+/**
+ * @brief Resets the selected ADC calibration registers.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Resets the selected ADC calibartion registers */
+ ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC reset calibration registers status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC reset calibration registers (SET or RESET).
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of RSTCAL bit */
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+ {
+ /* RSTCAL bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* RSTCAL bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the RSTCAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Enable the selected ADC calibration process */
+ ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of SWSTART bit */
+ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+ {
+ /* SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Number: specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ * @retval None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CR1 |= CR1_DISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CR1 &= CR1_DISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_REGULAR_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CR2 |= CR2_EXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t) ADCx->DR;
+}
+
+/**
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ * @retval The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+ /* Return the dual mode conversion value */
+ return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CR1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CR1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CR1 |= CR1_JDISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CR1 &= CR1_JDISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+ /* Clear the old external event selection for injected group */
+ tmpreg &= CR2_JEXTSEL_Reset;
+ /* Set the external event selection for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of JSWSTART bit */
+ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+ {
+ /* JSWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JSWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JSWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_INJECTED_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Get JL value: Number = JL+1 */
+ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Length: The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ * @retval None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Clear the old injected sequnence lenght JL bits */
+ tmpreg1 &= JSQR_JL_Reset;
+ /* Set the injected sequnence lenght JL bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @param Offset: the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDR_Offset;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+ * @retval None
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpreg &= CR1_AWDMode_Reset;
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+ uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->HTR = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->LTR = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= CR1_AWDCH_Reset;
+ /* Set the Analog watchdog channel */
+ tmpreg |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param NewState: new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 |= CR2_TSVREFE_Set;
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 &= CR2_TSVREFE_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval None
+ */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval The new state of ADC_IT (SET or RESET).
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx’s interrupt pending bits.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval None
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_bkp.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_bkp.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_bkp.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,272 +1,311 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_bkp.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the BKP firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ BKP registers bit address in the alias region ----------- */
-#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-/* Alias word address of TPAL bit */
-#define CR_OFFSET (BKP_OFFSET + 0x30)
-#define TPAL_BitNumber 0x01
-#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
-
-/* Alias word address of TPE bit */
-#define TPE_BitNumber 0x00
-#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of TPIE bit */
-#define CSR_OFFSET (BKP_OFFSET + 0x34)
-#define TPIE_BitNumber 0x02
-#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
-
-/* Alias word address of TIF bit */
-#define TIF_BitNumber 0x09
-#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
-
-/* Alias word address of TEF bit */
-#define TEF_BitNumber 0x08
-#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
-
-
-/* ---------------------- BKP registers bit mask ------------------------ */
-/* RTCCR register bit mask */
-#define RTCCR_CAL_Mask ((u16)0xFF80)
-#define RTCCR_Mask ((u16)0xFC7F)
-
-/* CSR register bit mask */
-#define CSR_CTE_Set ((u16)0x0001)
-#define CSR_CTI_Set ((u16)0x0002)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : BKP_DeInit
-* Description : Deinitializes the BKP peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_DeInit(void)
-{
- RCC_BackupResetCmd(ENABLE);
- RCC_BackupResetCmd(DISABLE);
-}
-
-/*******************************************************************************
-* Function Name : BKP_TamperPinLevelConfig
-* Description : Configures the Tamper Pin active level.
-* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level.
-* This parameter can be one of the following values:
-* - BKP_TamperPinLevel_High: Tamper pin active on high level
-* - BKP_TamperPinLevel_Low: Tamper pin active on low level
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)
-{
- /* Check the parameters */
- assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
-
- *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
-}
-
-/*******************************************************************************
-* Function Name : BKP_TamperPinCmd
-* Description : Enables or disables the Tamper Pin activation.
-* Input : - NewState: new state of the Tamper Pin activation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_TamperPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CR_TPE_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : BKP_ITConfig
-* Description : Enables or disables the Tamper Pin Interrupt.
-* Input : - NewState: new state of the Tamper Pin Interrupt.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CSR_TPIE_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : BKP_RTCOutputConfig
-* Description : Select the RTC output source to output on the Tamper pin.
-* Input : - BKP_RTCOutputSource: specifies the RTC output source.
-* This parameter can be one of the following values:
-* - BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
-* - BKP_RTCOutputSource_CalibClock: output the RTC clock
-* with frequency divided by 64 on the Tamper pin.
-* - BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse
-* signal on the Tamper pin.
-* - BKP_RTCOutputSource_Second: output the RTC Second pulse
-* signal on the Tamper pin.
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource)
-{
- u16 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
-
- tmpreg = BKP->RTCCR;
-
- /* Clear CCO, ASOE and ASOS bits */
- tmpreg &= RTCCR_Mask;
-
- /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
- tmpreg |= BKP_RTCOutputSource;
-
- /* Store the new value */
- BKP->RTCCR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : BKP_SetRTCCalibrationValue
-* Description : Sets RTC Clock Calibration value.
-* Input : - CalibrationValue: specifies the RTC Clock Calibration value.
-* This parameter must be a number between 0 and 0x7F.
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_SetRTCCalibrationValue(u8 CalibrationValue)
-{
- u16 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
-
- tmpreg = BKP->RTCCR;
-
- /* Clear CAL[6:0] bits */
- tmpreg &= RTCCR_CAL_Mask;
-
- /* Set CAL[6:0] bits according to CalibrationValue value */
- tmpreg |= CalibrationValue;
-
- /* Store the new value */
- BKP->RTCCR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : BKP_WriteBackupRegister
-* Description : Writes user data to the specified Data Backup Register.
-* Input : - BKP_DR: specifies the Data Backup Register.
-* This parameter can be BKP_DRx where x:[1, 42]
-* - Data: data to write
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)
-{
- /* Check the parameters */
- assert_param(IS_BKP_DR(BKP_DR));
-
- *(vu16 *) (BKP_BASE + BKP_DR) = Data;
-}
-
-/*******************************************************************************
-* Function Name : BKP_ReadBackupRegister
-* Description : Reads data from the specified Data Backup Register.
-* Input : - BKP_DR: specifies the Data Backup Register.
-* This parameter can be BKP_DRx where x:[1, 42]
-* Output : None
-* Return : The content of the specified Data Backup Register
-*******************************************************************************/
-u16 BKP_ReadBackupRegister(u16 BKP_DR)
-{
- /* Check the parameters */
- assert_param(IS_BKP_DR(BKP_DR));
-
- return (*(vu16 *) (BKP_BASE + BKP_DR));
-}
-
-/*******************************************************************************
-* Function Name : BKP_GetFlagStatus
-* Description : Checks whether the Tamper Pin Event flag is set or not.
-* Input : None
-* Output : None
-* Return : The new state of the Tamper Pin Event flag (SET or RESET).
-*******************************************************************************/
-FlagStatus BKP_GetFlagStatus(void)
-{
- return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
-}
-
-/*******************************************************************************
-* Function Name : BKP_ClearFlag
-* Description : Clears Tamper Pin Event pending flag.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_ClearFlag(void)
-{
- /* Set CTE bit to clear Tamper Pin Event flag */
- BKP->CSR |= CSR_CTE_Set;
-}
-
-/*******************************************************************************
-* Function Name : BKP_GetITStatus
-* Description : Checks whether the Tamper Pin Interrupt has occurred or not.
-* Input : None
-* Output : None
-* Return : The new state of the Tamper Pin Interrupt (SET or RESET).
-*******************************************************************************/
-ITStatus BKP_GetITStatus(void)
-{
- return (ITStatus)(*(vu32 *) CSR_TIF_BB);
-}
-
-/*******************************************************************************
-* Function Name : BKP_ClearITPendingBit
-* Description : Clears Tamper Pin Interrupt pending bit.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void BKP_ClearITPendingBit(void)
-{
- /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
- BKP->CSR |= CSR_CTI_Set;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the BKP firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup BKP
+ * @brief BKP driver modules
+ * @{
+ */
+
+/** @defgroup BKP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Defines
+ * @{
+ */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
+
+/* --- CR Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CR_OFFSET (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber 0x01
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber 0x00
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber 0x02
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber 0x09
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber 0x08
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCR_CAL_Mask ((uint16_t)0xFF80)
+#define RTCCR_Mask ((uint16_t)0xFC7F)
+
+/* CSR register bit mask */
+#define CSR_CTE_Set ((uint16_t)0x0001)
+#define CSR_CTI_Set ((uint16_t)0x0002)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup BKP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void BKP_DeInit(void)
+{
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+ * @brief Configures the Tamper Pin active level.
+ * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ * This parameter can be one of the following values:
+ * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+ * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+ * @retval None
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+ /* Check the parameters */
+ assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+ *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin activation.
+ * @param NewState: new state of the Tamper Pin activation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin Interrupt.
+ * @param NewState: new state of the Tamper Pin Interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Select the RTC output source to output on the Tamper pin.
+ * @param BKP_RTCOutputSource: specifies the RTC output source.
+ * This parameter can be one of the following values:
+ * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+ * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+ * divided by 64 on the Tamper pin.
+ * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+ * the Tamper pin.
+ * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+ * the Tamper pin.
+ * @retval None
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
+ tmpreg = BKP->RTCCR;
+ /* Clear CCO, ASOE and ASOS bits */
+ tmpreg &= RTCCR_Mask;
+
+ /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+ tmpreg |= BKP_RTCOutputSource;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Sets RTC Clock Calibration value.
+ * @param CalibrationValue: specifies the RTC Clock Calibration value.
+ * This parameter must be a number between 0 and 0x7F.
+ * @retval None
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+ tmpreg = BKP->RTCCR;
+ /* Clear CAL[6:0] bits */
+ tmpreg &= RTCCR_CAL_Mask;
+ /* Set CAL[6:0] bits according to CalibrationValue value */
+ tmpreg |= CalibrationValue;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Writes user data to the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @param Data: data to write
+ * @retval None
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Reads data from the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @retval The content of the specified Data Backup Register
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Event flag is set or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+ return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Event pending flag.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearFlag(void)
+{
+ /* Set CTE bit to clear Tamper Pin Event flag */
+ BKP->CSR |= CSR_CTE_Set;
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+ */
+ITStatus BKP_GetITStatus(void)
+{
+ return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Interrupt pending bit.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearITPendingBit(void)
+{
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+ BKP->CSR |= CSR_CTI_Set;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_can.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_can.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_can.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,907 +1,990 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_can.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the CAN firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_can.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-
-/* Private define ------------------------------------------------------------*/
-/* CAN Master Control Register bits */
-#define MCR_INRQ ((u32)0x00000001) /* Initialization request */
-#define MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */
-#define MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */
-#define MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */
-#define MCR_NART ((u32)0x00000010) /* No automatic retransmission */
-#define MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */
-#define MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */
-#define MCR_TTCM ((u32)0x00000080) /* time triggered communication */
-
-/* CAN Master Status Register bits */
-#define MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */
-#define MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */
-#define MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */
-
-/* CAN Transmit Status Register bits */
-#define TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */
-#define TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */
-#define TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */
-#define TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */
-#define TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */
-#define TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */
-#define TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */
-#define TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */
-#define TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */
-#define TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */
-#define TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */
-#define TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */
-
-/* CAN Receive FIFO 0 Register bits */
-#define RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */
-#define RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */
-#define RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */
-
-/* CAN Receive FIFO 1 Register bits */
-#define RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */
-#define RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */
-#define RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */
-
-/* CAN Error Status Register bits */
-#define ESR_EWGF ((u32)0x00000001) /* Error warning flag */
-#define ESR_EPVF ((u32)0x00000002) /* Error passive flag */
-#define ESR_BOFF ((u32)0x00000004) /* Bus-off flag */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((u32)0x00000001) /* Filter init mode */
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
-
-/* Private functions ---------------------------------------------------------*/
-/*******************************************************************************
-* Function Name : CAN_DeInit
-* Description : Deinitializes the CAN peripheral registers to their default
-* reset values.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_DeInit(void)
-{
- /* Enable CAN reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
- /* Release CAN from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
-}
-
-/*******************************************************************************
-* Function Name : CAN_Init
-* Description : Initializes the CAN peripheral according to the specified
-* parameters in the CAN_InitStruct.
-* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
- contains the configuration information for the CAN peripheral.
-* Output : None.
-* Return : Constant indicates initialization succeed which will be
-* CANINITFAILED or CANINITOK.
-*******************************************************************************/
-u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
-{
- u8 InitStatus = 0;
- u16 WaitAck = 0;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* Request initialisation */
- CAN->MCR = MCR_INRQ;
-
- /* ...and check acknowledged */
- if ((CAN->MSR & MSR_INAK) == 0)
- {
- InitStatus = CANINITFAILED;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CAN->MCR |= MCR_TTCM;
- }
- else
- {
- CAN->MCR &= ~MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CAN->MCR |= MCR_ABOM;
- }
- else
- {
- CAN->MCR &= ~MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CAN->MCR |= MCR_AWUM;
- }
- else
- {
- CAN->MCR &= ~MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CAN->MCR |= MCR_NART;
- }
- else
- {
- CAN->MCR &= ~MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CAN->MCR |= MCR_RFLM;
- }
- else
- {
- CAN->MCR &= ~MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CAN->MCR |= MCR_TXFP;
- }
- else
- {
- CAN->MCR &= ~MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |
- ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |
- ((u32)CAN_InitStruct->CAN_Prescaler - 1);
-
- InitStatus = CANINITOK;
-
- /* Request leave initialisation */
- CAN->MCR &= ~MCR_INRQ;
-
- /* Wait the acknowledge */
- for(WaitAck = 0x400; WaitAck > 0x0; WaitAck--)
- {
- }
-
- /* ...and check acknowledged */
- if ((CAN->MSR & MSR_INAK) == MSR_INAK)
- {
- InitStatus = CANINITFAILED;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-/*******************************************************************************
-* Function Name : CAN_FilterInit
-* Description : Initializes the CAN peripheral according to the specified
-* parameters in the CAN_FilterInitStruct.
-* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
-* structure that contains the configuration information.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- u16 FilterNumber_BitPos = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- FilterNumber_BitPos =
- (u16)(((u16)0x0001) << ((u16)CAN_FilterInitStruct->CAN_FilterNumber));
-
- /* Initialisation mode for the filter */
- CAN->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN->FA1R &= ~(u32)FilterNumber_BitPos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN->FS1R &= ~(u32)FilterNumber_BitPos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN->FS1R |= FilterNumber_BitPos;
-
- /* 32-bit identifier or First 32-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* 32-bit mask or Second 32-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow);
-
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN->FM1R &= ~(u32)FilterNumber_BitPos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN->FM1R |= (u32)FilterNumber_BitPos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN->FFA1R &= ~(u32)FilterNumber_BitPos;
- }
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN->FFA1R |= (u32)FilterNumber_BitPos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN->FA1R |= FilterNumber_BitPos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN->FMR &= ~FMR_FINIT;
-}
-
-/*******************************************************************************
-* Function Name : CAN_StructInit
-* Description : Fills each CAN_InitStruct member with its default value.
-* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
-* will be initialized.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
-
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
-
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
-
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
-
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
-
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
-
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
-
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/*******************************************************************************
-* Function Name : CAN_ITConfig
-* Description : Enables or disables the specified CAN interrupts.
-* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or
-* disabled.
-* This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,
-* CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,
-* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
-* CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or
-* CAN_IT_SLK.
-* - NewState: new state of the CAN interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ITConfig(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CAN interrupt */
- CAN->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CAN interrupt */
- CAN->IER &= ~CAN_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : CAN_Transmit
-* Description : Initiates the transmission of a message.
-* Input : TxMessage: pointer to a structure which contains CAN Id, CAN
-* DLC and CAN datas.
-* Output : None.
-* Return : The number of the mailbox that is used for transmission
-* or CAN_NO_MB if there is no empty mailbox.
-*******************************************************************************/
-u8 CAN_Transmit(CanTxMsg* TxMessage)
-{
- u8 TransmitMailbox = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- assert_param(IS_CAN_EXTID(TxMessage->StdId));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CAN->TSR&TSR_TME0) == TSR_TME0)
- {
- TransmitMailbox = 0;
- }
- else if ((CAN->TSR&TSR_TME1) == TSR_TME1)
- {
- TransmitMailbox = 1;
- }
- else if ((CAN->TSR&TSR_TME2) == TSR_TME2)
- {
- TransmitMailbox = 2;
- }
- else
- {
- TransmitMailbox = CAN_NO_MB;
- }
-
- if (TransmitMailbox != CAN_NO_MB)
- {
- /* Set up the Id */
- CAN->sTxMailBox[TransmitMailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_ID_STD)
- {
- TxMessage->StdId &= (u32)0x000007FF;
- TxMessage->StdId = TxMessage->StdId << 21;
-
- CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->IDE |
- TxMessage->RTR);
- }
- else
- {
- TxMessage->ExtId &= (u32)0x1FFFFFFF;
- TxMessage->ExtId <<= 3;
-
- CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->ExtId | TxMessage->IDE |
- TxMessage->RTR);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= (u8)0x0000000F;
- CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0;
- CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) |
- ((u32)TxMessage->Data[2] << 16) |
- ((u32)TxMessage->Data[1] << 8) |
- ((u32)TxMessage->Data[0]));
- CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) |
- ((u32)TxMessage->Data[6] << 16) |
- ((u32)TxMessage->Data[5] << 8) |
- ((u32)TxMessage->Data[4]));
-
- /* Request transmission */
- CAN->sTxMailBox[TransmitMailbox].TIR |= TMIDxR_TXRQ;
- }
-
- return TransmitMailbox;
-}
-
-/*******************************************************************************
-* Function Name : CAN_TransmitStatus
-* Description : Checks the transmission of a message.
-* Input : TransmitMailbox: the number of the mailbox that is used for
-* transmission.
-* Output : None.
-* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED
-* in an other case.
-*******************************************************************************/
-u8 CAN_TransmitStatus(u8 TransmitMailbox)
-{
- /* RQCP, TXOK and TME bits */
- u8 State = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
-
- switch (TransmitMailbox)
- {
- case (0): State |= (u8)((CAN->TSR & TSR_RQCP0) << 2);
- State |= (u8)((CAN->TSR & TSR_TXOK0) >> 0);
- State |= (u8)((CAN->TSR & TSR_TME0) >> 26);
- break;
- case (1): State |= (u8)((CAN->TSR & TSR_RQCP1) >> 6);
- State |= (u8)((CAN->TSR & TSR_TXOK1) >> 8);
- State |= (u8)((CAN->TSR & TSR_TME1) >> 27);
- break;
- case (2): State |= (u8)((CAN->TSR & TSR_RQCP2) >> 14);
- State |= (u8)((CAN->TSR & TSR_TXOK2) >> 16);
- State |= (u8)((CAN->TSR & TSR_TME2) >> 28);
- break;
- default:
- State = CANTXFAILED;
- break;
- }
-
- switch (State)
- {
- /* transmit pending */
- case (0x0): State = CANTXPENDING;
- break;
- /* transmit failed */
- case (0x5): State = CANTXFAILED;
- break;
- /* transmit succedeed */
- case (0x7): State = CANTXOK;
- break;
- default:
- State = CANTXFAILED;
- break;
- }
-
- return State;
-}
-
-/*******************************************************************************
-* Function Name : CAN_CancelTransmit
-* Description : Cancels a transmit request.
-* Input : Mailbox number.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_CancelTransmit(u8 Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
-
- /* abort transmission */
- switch (Mailbox)
- {
- case (0): CAN->TSR |= TSR_ABRQ0;
- break;
- case (1): CAN->TSR |= TSR_ABRQ1;
- break;
- case (2): CAN->TSR |= TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : CAN_FIFORelease
-* Description : Releases a FIFO.
-* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_FIFORelease(u8 FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CAN->RF0R = RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CAN->RF1R = RF1R_RFOM1;
- }
-}
-
-/*******************************************************************************
-* Function Name : CAN_MessagePending
-* Description : Returns the number of pending messages.
-* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-* Output : None.
-* Return : NbMessage which is the number of pending message.
-*******************************************************************************/
-u8 CAN_MessagePending(u8 FIFONumber)
-{
- u8 MessagePending=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- if (FIFONumber == CAN_FIFO0)
- {
- MessagePending = (u8)(CAN->RF0R&(u32)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- MessagePending = (u8)(CAN->RF1R&(u32)0x03);
- }
- else
- {
- MessagePending = 0;
- }
- return MessagePending;
-}
-
-/*******************************************************************************
-* Function Name : CAN_Receive
-* Description : Receives a message.
-* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-* Output : RxMessage: pointer to a structure which contains CAN Id,
-* CAN DLC, CAN datas and FMI number.
-* Return : None.
-*******************************************************************************/
-void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Get the Id */
- RxMessage->IDE = (u8)0x04 & CAN->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_ID_STD)
- {
- RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (u32)0x1FFFFFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (u8)0x02 & CAN->sFIFOMailBox[FIFONumber].RIR;
-
- /* Get the DLC */
- RxMessage->DLC = (u8)0x0F & CAN->sFIFOMailBox[FIFONumber].RDTR;
-
- /* Get the FMI */
- RxMessage->FMI = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8);
-
- /* Get the data field */
- RxMessage->Data[0] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24);
-
- RxMessage->Data[4] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24);
-
- /* Release the FIFO */
- CAN_FIFORelease(FIFONumber);
-}
-
-/*******************************************************************************
-* Function Name : CAN_Sleep
-* Description : Enters the low power mode.
-* Input : None.
-* Output : None.
-* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
-*******************************************************************************/
-u8 CAN_Sleep(void)
-{
- u8 SleepStatus = 0;
-
- /* Sleep mode entering request */
- CAN->MCR |= MCR_SLEEP;
- SleepStatus = CANSLEEPOK;
-
- /* Sleep mode status */
- if ((CAN->MCR&MCR_SLEEP) == 0)
- {
- /* Sleep mode not entered */
- SleepStatus = CANSLEEPFAILED;
- }
-
- /* At this step, sleep mode status */
- return SleepStatus;
-}
-
-/*******************************************************************************
-* Function Name : CAN_WakeUp
-* Description : Wakes the CAN up.
-* Input : None.
-* Output : None.
-* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other
-* case.
-*******************************************************************************/
-u8 CAN_WakeUp(void)
-{
- u8 WakeUpStatus = 0;
-
- /* Wake up request */
- CAN->MCR &= ~MCR_SLEEP;
- WakeUpStatus = CANWAKEUPFAILED;
-
- /* Sleep mode status */
- if ((CAN->MCR&MCR_SLEEP) == 0)
- {
- /* Sleep mode exited */
- WakeUpStatus = CANWAKEUPOK;
- }
-
- /* At this step, sleep mode status */
- return WakeUpStatus;
-}
-
-/*******************************************************************************
-* Function Name : CAN_GetFlagStatus
-* Description : Checks whether the specified CAN flag is set or not.
-* Input : CAN_FLAG: specifies the flag to check.
-* This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or
-* CAN_FLAG_BOF.
-* Output : None.
-* Return : The new state of CAN_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_FLAG(CAN_FLAG));
-
- /* Check the status of the specified CAN flag */
- if ((CAN->ESR & CAN_FLAG) != (u32)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : CAN_ClearFlag
-* Description : Clears the CAN's pending flags.
-* Input : CAN_FLAG: specifies the flag to clear.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_ClearFlag(u32 CAN_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FLAG(CAN_FLAG));
-
- /* Clear the selected CAN flags */
- CAN->ESR &= ~CAN_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : CAN_GetITStatus
-* Description : Checks whether the specified CAN interrupt has occurred or
-* not.
-* Input : CAN_IT: specifies the CAN interrupt source to check.
-* This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,
-* CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,
-* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
-* CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.
-* Output : None.
-* Return : The new state of CAN_IT (SET or RESET).
-*******************************************************************************/
-ITStatus CAN_GetITStatus(u32 CAN_IT)
-{
- ITStatus pendingbitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ITStatus(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_RQCP0:
- pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP0);
- break;
- case CAN_IT_RQCP1:
- pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP1);
- break;
- case CAN_IT_RQCP2:
- pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP2);
- break;
- case CAN_IT_FF0:
- pendingbitstatus = CheckITStatus(CAN->RF0R, RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- pendingbitstatus = CheckITStatus(CAN->RF0R, RF0R_FOVR0);
- break;
- case CAN_IT_FF1:
- pendingbitstatus = CheckITStatus(CAN->RF1R, RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- pendingbitstatus = CheckITStatus(CAN->RF1R, RF1R_FOVR1);
- break;
- case CAN_IT_EWG:
- pendingbitstatus = CheckITStatus(CAN->ESR, ESR_EWGF);
- break;
- case CAN_IT_EPV:
- pendingbitstatus = CheckITStatus(CAN->ESR, ESR_EPVF);
- break;
- case CAN_IT_BOF:
- pendingbitstatus = CheckITStatus(CAN->ESR, ESR_BOFF);
- break;
- case CAN_IT_SLK:
- pendingbitstatus = CheckITStatus(CAN->MSR, MSR_SLAKI);
- break;
- case CAN_IT_WKU:
- pendingbitstatus = CheckITStatus(CAN->MSR, MSR_WKUI);
- break;
-
- default :
- pendingbitstatus = RESET;
- break;
- }
-
- /* Return the CAN_IT status */
- return pendingbitstatus;
-}
-
-/*******************************************************************************
-* Function Name : CAN_ClearITPendingBit
-* Description : Clears the CAN's interrupt pending bits.
-* Input : CAN_IT: specifies the interrupt pending bit to clear.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-void CAN_ClearITPendingBit(u32 CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ITStatus(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_RQCP0:
- CAN->TSR = TSR_RQCP0; /* rc_w1*/
- break;
- case CAN_IT_RQCP1:
- CAN->TSR = TSR_RQCP1; /* rc_w1*/
- break;
- case CAN_IT_RQCP2:
- CAN->TSR = TSR_RQCP2; /* rc_w1*/
- break;
- case CAN_IT_FF0:
- CAN->RF0R = RF0R_FULL0; /* rc_w1*/
- break;
- case CAN_IT_FOV0:
- CAN->RF0R = RF0R_FOVR0; /* rc_w1*/
- break;
- case CAN_IT_FF1:
- CAN->RF1R = RF1R_FULL1; /* rc_w1*/
- break;
- case CAN_IT_FOV1:
- CAN->RF1R = RF1R_FOVR1; /* rc_w1*/
- break;
- case CAN_IT_EWG:
- CAN->ESR &= ~ ESR_EWGF; /* rw */
- break;
- case CAN_IT_EPV:
- CAN->ESR &= ~ ESR_EPVF; /* rw */
- break;
- case CAN_IT_BOF:
- CAN->ESR &= ~ ESR_BOFF; /* rw */
- break;
- case CAN_IT_WKU:
- CAN->MSR = MSR_WKUI; /* rc_w1*/
- break;
- case CAN_IT_SLK:
- CAN->MSR = MSR_SLAKI; /* rc_w1*/
- break;
- default :
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : CheckITStatus
-* Description : Checks whether the CAN interrupt has occurred or not.
-* Input : CAN_Reg: specifies the CAN interrupt register to check.
-* It_Bit: specifies the interrupt source bit to check.
-* Output : None.
-* Return : The new state of the CAN Interrupt (SET or RESET).
-*******************************************************************************/
-static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (u32)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
-
- return pendingbitstatus;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the CAN firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @defgroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */
+#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */
+#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */
+#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */
+#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */
+#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */
+#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */
+#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */
+#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Master Status Register bits */
+#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */
+#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */
+#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */
+
+/* CAN Transmit Status Register bits */
+#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */
+#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */
+#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */
+#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */
+#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */
+#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */
+#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */
+#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */
+#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */
+#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */
+#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */
+#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */
+
+/* CAN Receive FIFO 0 Register bits */
+#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */
+#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */
+#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */
+
+/* CAN Receive FIFO 1 Register bits */
+#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */
+#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */
+#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */
+
+/* CAN Error Status Register bits */
+#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */
+#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */
+#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TimeOut ((uint32_t)0x0000FFFF)
+
+/* Time out for SLAK bit */
+#define SLAK_TimeOut ((uint32_t)0x0000FFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @retval None.
+ */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (CANx == CAN1)
+ {
+ /* Enable CAN1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+ /* Release CAN1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+ }
+ else
+ {
+ /* Enable CAN2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+ /* Release CAN2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+ * contains the configuration information for the CAN peripheral.
+ * @retval Constant indicates initialization succeed which will be
+ * CANINITFAILED or CANINITOK.
+ */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+ uint8_t InitStatus = CANINITFAILED;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+ /* exit from sleep mode */
+ CANx->MCR &= ~MCR_SLEEP;
+
+ /* Request initialisation */
+ CANx->MCR |= MCR_INRQ ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & MSR_INAK) != MSR_INAK)
+ {
+ InitStatus = CANINITFAILED;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)
+ {
+ CANx->MCR |= MCR_TTCM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)
+ {
+ CANx->MCR |= MCR_ABOM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)
+ {
+ CANx->MCR |= MCR_AWUM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitStruct->CAN_NART == ENABLE)
+ {
+ CANx->MCR |= MCR_NART;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)
+ {
+ CANx->MCR |= MCR_RFLM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)
+ {
+ CANx->MCR |= MCR_TXFP;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCR &= ~MCR_INRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0x00;
+
+ while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & MSR_INAK) == MSR_INAK)
+ {
+ InitStatus = CANINITFAILED;
+ }
+ else
+ {
+ InitStatus = CANINITOK ;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+ * structure that contains the configuration information.
+ * @retval None.
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+ /* Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Filter Deactivation */
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CAN1->FS1R |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CAN1->FA1R |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Fills each CAN_InitStruct member with its default value.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+ * will be initialized.
+ * @retval None.
+ */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+ /* Reset CAN init structure parameters values */
+ /* Initialize the time triggered communication mode */
+ CAN_InitStruct->CAN_TTCM = DISABLE;
+ /* Initialize the automatic bus-off management */
+ CAN_InitStruct->CAN_ABOM = DISABLE;
+ /* Initialize the automatic wake-up mode */
+ CAN_InitStruct->CAN_AWUM = DISABLE;
+ /* Initialize the no automatic retransmission */
+ CAN_InitStruct->CAN_NART = DISABLE;
+ /* Initialize the receive FIFO locked mode */
+ CAN_InitStruct->CAN_RFLM = DISABLE;
+ /* Initialize the transmit FIFO priority */
+ CAN_InitStruct->CAN_TXFP = DISABLE;
+ /* Initialize the CAN_Mode member */
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+ /* Initialize the CAN_SJW member */
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+ /* Initialize the CAN_BS1 member */
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+ /* Initialize the CAN_BS2 member */
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+ /* Initialize the CAN_Prescaler member */
+ CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+ * @brief Select the start bank filter for slave CAN.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
+ * @retval None.
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+ /* enter Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+ /* Select the start slave bank */
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+ /* Leave Initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Enables or disables the specified CAN interrupts.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,
+ * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,
+ * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
+ * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or
+ * CAN_IT_SLK.
+ * @param NewState: new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ITConfig(CAN_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CAN interrupt */
+ CANx->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CAN interrupt */
+ CANx->IER &= ~CAN_IT;
+ }
+}
+
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN datas.
+ * @retval The number of the mailbox that is used for transmission
+ * or CAN_NO_MB if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+ assert_param(IS_CAN_RTR(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSR&TSR_TME0) == TSR_TME0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSR&TSR_TME1) == TSR_TME1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSR&TSR_TME2) == TSR_TME2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_NO_MB;
+ }
+
+ if (transmit_mailbox != CAN_NO_MB)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE |
+ TxMessage->RTR);
+ }
+
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
+ ((uint32_t)TxMessage->Data[2] << 16) |
+ ((uint32_t)TxMessage->Data[1] << 8) |
+ ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
+ ((uint32_t)TxMessage->Data[6] << 16) |
+ ((uint32_t)TxMessage->Data[5] << 8) |
+ ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission.
+ * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+ /* RQCP, TXOK and TME bits */
+ uint8_t state = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+ switch (TransmitMailbox)
+ {
+ case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2);
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0);
+ state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26);
+ break;
+ case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6);
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8);
+ state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27);
+ break;
+ case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14);
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16);
+ state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28);
+ break;
+ default:
+ state = CANTXFAILED;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0): state = CANTXPENDING;
+ break;
+ /* transmit failed */
+ case (0x5): state = CANTXFAILED;
+ break;
+ /* transmit succedeed */
+ case (0x7): state = CANTXOK;
+ break;
+ default:
+ state = CANTXFAILED;
+ break;
+ }
+ return state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Mailbox: Mailbox number.
+ * @retval None.
+ */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (0): CANx->TSR |= TSR_ABRQ0;
+ break;
+ case (1): CANx->TSR |= TSR_ABRQ1;
+ break;
+ case (2): CANx->TSR |= TSR_ABRQ2;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Releases a FIFO.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None.
+ */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R = RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R = RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval NbMessage which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ uint8_t message_pending=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ if (FIFONumber == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+ }
+ else if (FIFONumber == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief Receives a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage: pointer to a structure receive message which
+ * contains CAN Id, CAN DLC, CAN datas and FMI number.
+ * @retval None.
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ if (RxMessage->IDE == CAN_ID_STD)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ CAN_FIFORelease(CANx, FIFONumber);
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: new state of the CAN peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCR |= MCR_DBF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCR &= ~MCR_DBF;
+ }
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+ uint8_t sleepstatus = CANSLEEPFAILED;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CANSLEEPOK;
+ }
+ /* At this step, sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+ uint32_t wait_slak = SLAK_TimeOut ;
+ uint8_t wakeupstatus = CANWAKEUPFAILED;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCR &= ~MCR_SLEEP;
+
+ /* Sleep mode status */
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+ {
+ wait_slak--;
+ }
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+ {
+ /* Sleep mode exited */
+ wakeupstatus = CANWAKEUPOK;
+ }
+ /* At this step, sleep mode status */
+ return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to check.
+ * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF.
+ * @retval The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FLAG(CAN_FLAG));
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to clear.
+ * @retval None.
+ */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FLAG(CAN_FLAG));
+ /* Clear the selected CAN flags */
+ CANx->ESR &= ~CAN_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified CAN interrupt has occurred or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt source to check.
+ * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,
+ * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,
+ * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
+ * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.
+ * @retval The new state of CAN_IT (SET or RESET).
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ ITStatus pendingbitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ITStatus(CAN_IT));
+ switch (CAN_IT)
+ {
+ case CAN_IT_RQCP0:
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0);
+ break;
+ case CAN_IT_RQCP1:
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1);
+ break;
+ case CAN_IT_RQCP2:
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2);
+ break;
+ case CAN_IT_FF0:
+ pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0);
+ break;
+ case CAN_IT_FOV0:
+ pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0);
+ break;
+ case CAN_IT_FF1:
+ pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1);
+ break;
+ case CAN_IT_FOV1:
+ pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1);
+ break;
+ case CAN_IT_EWG:
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF);
+ break;
+ case CAN_IT_EPV:
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF);
+ break;
+ case CAN_IT_BOF:
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF);
+ break;
+ case CAN_IT_SLK:
+ pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI);
+ break;
+ case CAN_IT_WKU:
+ pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI);
+ break;
+ default :
+ pendingbitstatus = RESET;
+ break;
+ }
+ /* Return the CAN_IT status */
+ return pendingbitstatus;
+}
+
+/**
+ * @brief Clears the CAN’s interrupt pending bits.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the interrupt pending bit to clear.
+ * @retval None.
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ITStatus(CAN_IT));
+ switch (CAN_IT)
+ {
+ case CAN_IT_RQCP0:
+ CANx->TSR = TSR_RQCP0; /* rc_w1*/
+ break;
+ case CAN_IT_RQCP1:
+ CANx->TSR = TSR_RQCP1; /* rc_w1*/
+ break;
+ case CAN_IT_RQCP2:
+ CANx->TSR = TSR_RQCP2; /* rc_w1*/
+ break;
+ case CAN_IT_FF0:
+ CANx->RF0R = RF0R_FULL0; /* rc_w1*/
+ break;
+ case CAN_IT_FOV0:
+ CANx->RF0R = RF0R_FOVR0; /* rc_w1*/
+ break;
+ case CAN_IT_FF1:
+ CANx->RF1R = RF1R_FULL1; /* rc_w1*/
+ break;
+ case CAN_IT_FOV1:
+ CANx->RF1R = RF1R_FOVR1; /* rc_w1*/
+ break;
+ case CAN_IT_EWG:
+ CANx->ESR &= ~ ESR_EWGF; /* rw */
+ break;
+ case CAN_IT_EPV:
+ CANx->ESR &= ~ ESR_EPVF; /* rw */
+ break;
+ case CAN_IT_BOF:
+ CANx->ESR &= ~ ESR_BOFF; /* rw */
+ break;
+ case CAN_IT_WKU:
+ CANx->MSR = MSR_WKUI; /* rc_w1*/
+ break;
+ case CAN_IT_SLK:
+ CANx->MSR = MSR_SLAKI; /* rc_w1*/
+ break;
+ default :
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg: specifies the CAN interrupt register to check.
+ * @param It_Bit: specifies the interrupt source bit to check.
+ * @retval The new state of the CAN Interrupt (SET or RESET).
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_IT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_IT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_crc.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_crc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_crc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,114 +1,163 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_crc.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the CRC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_crc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CR register bit mask */
-#define CR_RESET_Set ((u32)0x00000001)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : CRC_ResetDR
-* Description : Resets the CRC Data register (DR).
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR = CR_RESET_Set;
-}
-
-/*******************************************************************************
-* Function Name : CRC_CalcCRC
-* Description : Computes the 32-bit CRC of a given data word(32-bit).
-* Input : - Data: data word(32-bit) to compute its CRC
-* Output : None
-* Return : 32-bit CRC
-*******************************************************************************/
-u32 CRC_CalcCRC(u32 Data)
-{
- CRC->DR = Data;
-
- return (CRC->DR);
-}
-
-/*******************************************************************************
-* Function Name : CRC_CalcBlockCRC
-* Description : Computes the 32-bit CRC of a given buffer of data word(32-bit).
-* Input : - pBuffer: pointer to the buffer containing the data to be
-* computed
-* - BufferLength: length of the buffer to be computed
-* Output : None
-* Return : 32-bit CRC
-*******************************************************************************/
-u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength)
-{
- u32 index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
-
- return (CRC->DR);
-}
-
-/*******************************************************************************
-* Function Name : CRC_GetCRC
-* Description : Returns the current CRC value.
-* Input : None
-* Output : None
-* Return : 32-bit CRC
-*******************************************************************************/
-u32 CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/*******************************************************************************
-* Function Name : CRC_SetIDRegister
-* Description : Stores a 8-bit data in the Independent Data(ID) register.
-* Input : - IDValue: 8-bit value to be stored in the ID register
-* Output : None
-* Return : None
-*******************************************************************************/
-void CRC_SetIDRegister(u8 IDValue)
-{
- CRC->IDR = IDValue;
-}
-
-/*******************************************************************************
-* Function Name : CRC_GetIDRegister
-* Description : Returns the 8-bit data stored in the Independent Data(ID) register
-* Input : None
-* Output : None
-* Return : 8-bit value of the ID register
-*******************************************************************************/
-u8 CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the CRC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @defgroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Defines
+ * @{
+ */
+
+/* CR register bit mask */
+
+#define CR_RESET_Set ((uint32_t)0x00000001)
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DR).
+ * @param None
+ * @retval None
+ */
+void CRC_ResetDR(void)
+{
+ /* Reset CRC generator */
+ CRC->CR = CR_RESET_Set;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data: data word(32-bit) to compute its CRC
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+ CRC->DR = Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer: pointer to the buffer containing the data to be computed
+ * @param BufferLength: length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < BufferLength; index++)
+ {
+ CRC->DR = pBuffer[index];
+ }
+ return (CRC->DR);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @param None
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_GetCRC(void)
+{
+ return (CRC->DR);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+ CRC->IDR = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @param None
+ * @retval 8-bit value of the ID register
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+ return (CRC->IDR);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dac.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dac.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dac.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,389 +1,431 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_dac.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the DAC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dac.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* DAC EN mask */
-#define CR_EN_Set ((u32)0x00000001)
-
-/* DAC DMAEN mask */
-#define CR_DMAEN_Set ((u32)0x00001000)
-
-/* CR register Mask */
-#define CR_CLEAR_Mask ((u32)0x00000FFE)
-
-/* DAC SWTRIG mask */
-#define SWTRIGR_SWTRIG_Set ((u32)0x00000001)
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_Set ((u32)0x00000003)
-#define DUAL_SWTRIG_Reset ((u32)0xFFFFFFFC)
-
-/* DHR registers offsets */
-#define DHR12R1_Offset ((u32)0x00000008)
-#define DHR12R2_Offset ((u32)0x00000014)
-#define DHR12RD_Offset ((u32)0x00000020)
-
-/* DOR register offset */
-#define DOR_Offset ((u32)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : DAC_DeInit
-* Description : Deinitializes the DAC peripheral registers to their default
-* reset values.
-* Input : None.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_DeInit(void)
-{
- /* Enable DAC reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
- /* Release DAC from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/*******************************************************************************
-* Function Name : DAC_Init
-* Description : Initializes the DAC peripheral according to the specified
-* parameters in the DAC_InitStruct.
-* Input : - DAC_Channel: the selected DAC channel.
-* This parameter can be one of the following values:
-* - DAC_Channel_1: DAC Channel1 selected
-* - DAC_Channel_2: DAC Channel2 selected
-* - DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
-* contains the configuration information for the specified
-* DAC channel.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
- u32 tmpreg1 = 0, tmpreg2 = 0;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DAC->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
- mask/amplitude for wave genration */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DAC->CR = tmpreg1;
-}
-
-/*******************************************************************************
-* Function Name : DAC_StructInit
-* Description : Fills each DAC_InitStruct member with its default value.
-* Input : - DAC_InitStruct : pointer to a DAC_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
-
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
-
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
-
- /* Initialize the DAC_OutputBuffer member */
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/*******************************************************************************
-* Function Name : DAC_Cmd
-* Description : Enables or disables the specified DAC channel.
-* Input - DAC_Channel: the selected DAC channel.
-* This parameter can be one of the following values:
-* - DAC_Channel_1: DAC Channel1 selected
-* - DAC_Channel_2: DAC Channel2 selected
-* - NewState: new state of the DAC channel.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DAC->CR |= CR_EN_Set << DAC_Channel;
- }
- else
- {
- /* Disable the selected DAC channel */
- DAC->CR &= ~(CR_EN_Set << DAC_Channel);
- }
-}
-
-/*******************************************************************************
-* Function Name : DAC_DMACmd
-* Description : Enables or disables the specified DAC channel DMA request.
-* Input - DAC_Channel: the selected DAC channel.
-* This parameter can be one of the following values:
-* - DAC_Channel_1: DAC Channel1 selected
-* - DAC_Channel_2: DAC Channel2 selected
-* - NewState: new state of the selected DAC channel DMA request.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DAC->CR |= CR_DMAEN_Set << DAC_Channel;
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
- }
-}
-
-/*******************************************************************************
-* Function Name : DAC_SoftwareTriggerCmd
-* Description : Enables or disables the selected DAC channel software trigger.
-* Input - DAC_Channel: the selected DAC channel.
-* This parameter can be one of the following values:
-* - DAC_Channel_1: DAC Channel1 selected
-* - DAC_Channel_2: DAC Channel2 selected
-* - NewState: new state of the selected DAC channel software trigger.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
- }
-}
-
-/*******************************************************************************
-* Function Name : DAC_DualSoftwareTriggerCmd
-* Description : Enables or disables simultaneously the two DAC channels software
-* triggers.
-* Input - NewState: new state of the DAC channels software triggers.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : DAC_WaveGenerationCmd
-* Description : Enables or disables the selected DAC channel wave generation.
-* Input - DAC_Channel: the selected DAC channel.
-* This parameter can be one of the following values:
-* - DAC_Channel_1: DAC Channel1 selected
-* - DAC_Channel_2: DAC Channel2 selected
-* - DAC_Wave: Specifies the wave type to enable or disable.
-* This parameter can be one of the following values:
-* - DAC_Wave_Noise: noise wave generation
-* - DAC_Wave_Triangle: triangle wave generation
-* - NewState: new state of the selected DAC channel wave generation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DAC->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DAC->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/*******************************************************************************
-* Function Name : DAC_SetChannel1Data
-* Description : Set the specified data holding register value for DAC channel1.
-* Input : - DAC_Align: Specifies the data alignement for DAC channel1.
-* This parameter can be one of the following values:
-* - DAC_Align_8b_R: 8bit right data alignement selected
-* - DAC_Align_12b_L: 12bit left data alignement selected
-* - DAC_Align_12b_R: 12bit right data alignement selected
-* - Data : Data to be loaded in the selected data holding
-* register.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_SetChannel1Data(u32 DAC_Align, u16 Data)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- /* Set the DAC channel1 selected data holding register */
- *((vu32 *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (u32)Data;
-}
-
-/*******************************************************************************
-* Function Name : DAC_SetChannel2Data
-* Description : Set the specified data holding register value for DAC channel2.
-* Input : - DAC_Align: Specifies the data alignement for DAC channel2.
-* This parameter can be one of the following values:
-* - DAC_Align_8b_R: 8bit right data alignement selected
-* - DAC_Align_12b_L: 12bit left data alignement selected
-* - DAC_Align_12b_R: 12bit right data alignement selected
-* - Data : Data to be loaded in the selected data holding
-* register.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_SetChannel2Data(u32 DAC_Align, u16 Data)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- /* Set the DAC channel2 selected data holding register */
- *((vu32 *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (u32)Data;
-}
-
-/*******************************************************************************
-* Function Name : DAC_SetDualChannelData
-* Description : Set the specified data holding register value for dual channel
-* DAC.
-* Input : - DAC_Align: Specifies the data alignement for dual channel DAC.
-* This parameter can be one of the following values:
-* - DAC_Align_8b_R: 8bit right data alignement selected
-* - DAC_Align_12b_L: 12bit left data alignement selected
-* - DAC_Align_12b_R: 12bit right data alignement selected
-* - Data2: Data for DAC Channel2 to be loaded in the selected data
-* holding register.
-* - Data1: Data for DAC Channel1 to be loaded in the selected data
-* holding register.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1)
-{
- u32 data = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((u32)Data2 << 8) | Data1;
- }
- else
- {
- data = ((u32)Data2 << 16) | Data1;
- }
-
- /* Set the dual DAC selected data holding register */
- *((vu32 *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data;
-}
-
-/*******************************************************************************
-* Function Name : DAC_GetDataOutputValue
-* Description : Returns the last data output value of the selected DAC cahnnel.
-* Input - DAC_Channel: the selected DAC channel.
-* This parameter can be one of the following values:
-* - DAC_Channel_1: DAC Channel1 selected
-* - DAC_Channel_2: DAC Channel2 selected
-* Output : None
-* Return : The selected DAC channel data output value.
-*******************************************************************************/
-u16 DAC_GetDataOutputValue(u32 DAC_Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- /* Returns the DAC channel data output register value */
- return (u16) (*(vu32*)(DAC_BASE + DOR_Offset + ((u32)DAC_Channel >> 2)));
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the DAC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @defgroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Defines
+ * @{
+ */
+
+/* DAC EN mask */
+#define CR_EN_Set ((uint32_t)0x00000001)
+
+/* DAC DMAEN mask */
+#define CR_DMAEN_Set ((uint32_t)0x00001000)
+
+/* CR register Mask */
+#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)
+
+/* DAC SWTRIG mask */
+#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_Offset ((uint32_t)0x00000008)
+#define DHR12R2_Offset ((uint32_t)0x00000014)
+#define DHR12RD_Offset ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_Offset ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+ * contains the configuration information for the specified DAC channel.
+ * @retval None
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
+ mask/amplitude for wave genration */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set WAVEx bits according to DAC_WaveGeneration value */
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the DAC_Trigger member */
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+ /* Initialize the DAC_WaveGeneration member */
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+ /* Initialize the DAC_OutputBuffer member */
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CR |= CR_EN_Set << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CR &= ~(CR_EN_Set << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CR |= CR_DMAEN_Set << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param NewState: new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_Wave: Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_Wave_Noise: noise wave generation
+ * @arg DAC_Wave_Triangle: triangle wave generation
+ * @param NewState: new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ DAC->CR |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align: Specifies the data alignement for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R1_Offset + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DAC_Align: Specifies the data alignement for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R2_Offset + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel
+ * DAC.
+ * @param DAC_Align: Specifies the data alignement for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ * @retval None
+ */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_Align_8b_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12RD_Offset + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC cahnnel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t) DAC_BASE ;
+ tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dbgmcu.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dbgmcu.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dbgmcu.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,97 +1,152 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_dbgmcu.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the DBGMCU firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dbgmcu.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_Mask ((u32)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : DBGMCU_GetREVID
-* Description : Returns the device revision identifier.
-* Input : None
-* Output : None
-* Return : Device revision identifier
-*******************************************************************************/
-u32 DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/*******************************************************************************
-* Function Name : DBGMCU_GetDEVID
-* Description : Returns the device identifier.
-* Input : None
-* Output : None
-* Return : Device identifier
-*******************************************************************************/
-u32 DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
-}
-
-/*******************************************************************************
-* Function Name : DBGMCU_Config
-* Description : Configures the specified peripheral and low power mode behavior
-* when the MCU under Debug mode.
-* Input : - DBGMCU_Periph: specifies the peripheral and low power mode.
-* This parameter can be any combination of the following values:
-* - DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
-* - DBGMCU_STOP: Keep debugger connection during STOP mode
-* - DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
-* - DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
-* - DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
-* - DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
-* - DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
-* - DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
-* - DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
-* - DBGMCU_CAN_STOP: Debug CAN stopped when Core is halted
-* - DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
-* when Core is halted
-* - DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped
-* when Core is halted
-* - DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
-* - DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
-* - DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
-* - DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
-* - NewState: new state of the specified peripheral in Debug mode.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the DBGMCU firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DBGMCU
+ * @brief DBGMCU driver modules
+ * @{
+ */
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Returns the device revision identifier.
+ * @param None
+ * @retval Device revision identifier
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+ return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @param None
+ * @retval Device identifier
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+ return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+ * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
+ * @param NewState: new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->CR |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->CR &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dma.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dma.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_dma.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,678 +1,693 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_dma.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the DMA firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dma.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* DMA ENABLE mask */
-#define CCR_ENABLE_Set ((u32)0x00000001)
-#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_Channel1_IT_Mask ((u32)0x0000000F)
-#define DMA1_Channel2_IT_Mask ((u32)0x000000F0)
-#define DMA1_Channel3_IT_Mask ((u32)0x00000F00)
-#define DMA1_Channel4_IT_Mask ((u32)0x0000F000)
-#define DMA1_Channel5_IT_Mask ((u32)0x000F0000)
-#define DMA1_Channel6_IT_Mask ((u32)0x00F00000)
-#define DMA1_Channel7_IT_Mask ((u32)0x0F000000)
-
-/* DMA2 Channelx interrupt pending bit masks */
-#define DMA2_Channel1_IT_Mask ((u32)0x0000000F)
-#define DMA2_Channel2_IT_Mask ((u32)0x000000F0)
-#define DMA2_Channel3_IT_Mask ((u32)0x00000F00)
-#define DMA2_Channel4_IT_Mask ((u32)0x0000F000)
-#define DMA2_Channel5_IT_Mask ((u32)0x000F0000)
-
-/* DMA2 FLAG mask */
-#define FLAG_Mask ((u32)0x10000000)
-
-/* DMA registers Masks */
-#define CCR_CLEAR_Mask ((u32)0xFFFF800F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : DMA_DeInit
-* Description : Deinitializes the DMAy Channelx registers to their default reset
-* values.
-* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
-* DMA Channel.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
-
- /* Reset DMAy Channelx control register */
- DMAy_Channelx->CCR = 0;
-
- /* Reset DMAy Channelx remaining bytes register */
- DMAy_Channelx->CNDTR = 0;
-
- /* Reset DMAy Channelx peripheral address register */
- DMAy_Channelx->CPAR = 0;
-
- /* Reset DMAy Channelx memory address register */
- DMAy_Channelx->CMAR = 0;
-
- switch (*(u32*)&DMAy_Channelx)
- {
- case DMA1_Channel1_BASE:
- /* Reset interrupt pending bits for DMA1 Channel1 */
- DMA1->IFCR |= DMA1_Channel1_IT_Mask;
- break;
-
- case DMA1_Channel2_BASE:
- /* Reset interrupt pending bits for DMA1 Channel2 */
- DMA1->IFCR |= DMA1_Channel2_IT_Mask;
- break;
-
- case DMA1_Channel3_BASE:
- /* Reset interrupt pending bits for DMA1 Channel3 */
- DMA1->IFCR |= DMA1_Channel3_IT_Mask;
- break;
-
- case DMA1_Channel4_BASE:
- /* Reset interrupt pending bits for DMA1 Channel4 */
- DMA1->IFCR |= DMA1_Channel4_IT_Mask;
- break;
-
- case DMA1_Channel5_BASE:
- /* Reset interrupt pending bits for DMA1 Channel5 */
- DMA1->IFCR |= DMA1_Channel5_IT_Mask;
- break;
-
- case DMA1_Channel6_BASE:
- /* Reset interrupt pending bits for DMA1 Channel6 */
- DMA1->IFCR |= DMA1_Channel6_IT_Mask;
- break;
-
- case DMA1_Channel7_BASE:
- /* Reset interrupt pending bits for DMA1 Channel7 */
- DMA1->IFCR |= DMA1_Channel7_IT_Mask;
- break;
-
- case DMA2_Channel1_BASE:
- /* Reset interrupt pending bits for DMA2 Channel1 */
- DMA2->IFCR |= DMA2_Channel1_IT_Mask;
- break;
-
- case DMA2_Channel2_BASE:
- /* Reset interrupt pending bits for DMA2 Channel2 */
- DMA2->IFCR |= DMA2_Channel2_IT_Mask;
- break;
-
- case DMA2_Channel3_BASE:
- /* Reset interrupt pending bits for DMA2 Channel3 */
- DMA2->IFCR |= DMA2_Channel3_IT_Mask;
- break;
-
- case DMA2_Channel4_BASE:
- /* Reset interrupt pending bits for DMA2 Channel4 */
- DMA2->IFCR |= DMA2_Channel4_IT_Mask;
- break;
-
- case DMA2_Channel5_BASE:
- /* Reset interrupt pending bits for DMA2 Channel5 */
- DMA2->IFCR |= DMA2_Channel5_IT_Mask;
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : DMA_Init
-* Description : Initializes the DMAy Channelx according to the specified
-* parameters in the DMA_InitStruct.
-* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
-* DMA Channel.
-* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
-* contains the configuration information for the specified
-* DMA Channel.
-* Output : None
-* Return : None
-******************************************************************************/
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
- /* Get the DMAy_Channelx CCR value */
- tmpreg = DMAy_Channelx->CCR;
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= CCR_CLEAR_Mask;
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
- /* Set DIR bit according to DMA_DIR value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set PL bits according to DMA_Priority value */
- /* Set the MEM2MEM bit according to DMA_M2M value */
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
- /* Write to DMAy Channelx CCR */
- DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
- /* Write to DMAy Channelx CPAR */
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
- /* Write to DMAy Channelx CMAR */
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/*******************************************************************************
-* Function Name : DMA_StructInit
-* Description : Fills each DMA_InitStruct member with its default value.
-* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-
- /* Initialize the DMA_MemoryBaseAddr member */
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;
-
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
-
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
-
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-
- /* Initialize the DMA_M2M member */
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/*******************************************************************************
-* Function Name : DMA_Cmd
-* Description : Enables or disables the specified DMAy Channelx.
-* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
-* DMA Channel.
-* - NewState: new state of the DMAy Channelx.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Channelx */
- DMAy_Channelx->CCR |= CCR_ENABLE_Set;
- }
- else
- {
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : DMA_ITConfig
-* Description : Enables or disables the specified DMAy Channelx interrupts.
-* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
-* DMA Channel.
-* - DMA_IT: specifies the DMA interrupts sources to be enabled
-* or disabled.
-* This parameter can be any combination of the following values:
-* - DMA_IT_TC: Transfer complete interrupt mask
-* - DMA_IT_HT: Half transfer interrupt mask
-* - DMA_IT_TE: Transfer error interrupt mask
-* - NewState: new state of the specified DMA interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA interrupts */
- DMAy_Channelx->CCR |= DMA_IT;
- }
- else
- {
- /* Disable the selected DMA interrupts */
- DMAy_Channelx->CCR &= ~DMA_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : DMA_GetCurrDataCounter
-* Description : Returns the number of remaining data units in the current
-* DMAy Channelx transfer.
-* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
-* DMA Channel.
-* Output : None
-* Return : The number of remaining data units in the current DMAy Channelx
-* transfer.
-*******************************************************************************/
-u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
- /* Return the number of remaining data units for DMAy Channelx */
- return ((u16)(DMAy_Channelx->CNDTR));
-}
-
-/*******************************************************************************
-* Function Name : DMA_GetFlagStatus
-* Description : Checks whether the specified DMAy Channelx flag is set or not.
-* Input : - DMA_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-* - DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-* - DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-* - DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-* - DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-* - DMA1_FLAG_GL6: DMA1 Channel6 global flag.
-* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
-* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
-* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
-* - DMA1_FLAG_GL7: DMA1 Channel7 global flag.
-* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
-* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
-* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
-* - DMA2_FLAG_GL1: DMA2 Channel1 global flag.
-* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
-* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
-* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
-* - DMA2_FLAG_GL2: DMA2 Channel2 global flag.
-* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
-* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
-* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
-* - DMA2_FLAG_GL3: DMA2 Channel3 global flag.
-* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
-* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
-* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
-* - DMA2_FLAG_GL4: DMA2 Channel4 global flag.
-* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
-* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
-* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
-* - DMA2_FLAG_GL5: DMA2 Channel5 global flag.
-* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
-* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
-* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
-* Output : None
-* Return : The new state of DMA_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Calculate the used DMA */
- if ((DMA_FLAG & FLAG_Mask) != (u32)RESET)
- {
- /* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR ;
- }
- else
- {
- /* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR ;
- }
-
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (u32)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : DMA_ClearFlag
-* Description : Clears the DMAy Channelx's pending flags.
-* Input : - DMA_FLAG: specifies the flag to clear.
-* This parameter can be any combination (for the same DMA) of
-* the following values:
-* - DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-* - DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-* - DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-* - DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-* - DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-* - DMA1_FLAG_GL6: DMA1 Channel6 global flag.
-* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
-* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
-* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
-* - DMA1_FLAG_GL7: DMA1 Channel7 global flag.
-* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
-* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
-* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
-* - DMA2_FLAG_GL1: DMA2 Channel1 global flag.
-* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
-* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
-* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
-* - DMA2_FLAG_GL2: DMA2 Channel2 global flag.
-* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
-* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
-* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
-* - DMA2_FLAG_GL3: DMA2 Channel3 global flag.
-* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
-* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
-* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
-* - DMA2_FLAG_GL4: DMA2 Channel4 global flag.
-* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
-* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
-* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
-* - DMA2_FLAG_GL5: DMA2 Channel5 global flag.
-* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
-* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
-* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA_ClearFlag(u32 DMA_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Calculate the used DMA */
- if ((DMA_FLAG & FLAG_Mask) != (u32)RESET)
- {
- /* Clear the selected DMA flags */
- DMA2->IFCR = DMA_FLAG;
- }
- else
- {
- /* Clear the selected DMA flags */
- DMA1->IFCR = DMA_FLAG;
- }
-}
-
-/*******************************************************************************
-* Function Name : DMA_GetITStatus
-* Description : Checks whether the specified DMAy Channelx interrupt has
-* occurred or not.
-* Input : - DMA_IT: specifies the DMA interrupt source to check.
-* This parameter can be one of the following values:
-* - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-* - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-* - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-* - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-* - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-* - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
-* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
-* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
-* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
-* - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
-* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
-* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
-* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
-* - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
-* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
-* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
-* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
-* - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
-* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
-* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
-* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
-* - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
-* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
-* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
-* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
-* - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
-* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
-* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
-* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
-* - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
-* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
-* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
-* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
-* Output : None
-* Return : The new state of DMA_IT (SET or RESET).
-*******************************************************************************/
-ITStatus DMA_GetITStatus(u32 DMA_IT)
-{
- ITStatus bitstatus = RESET;
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Calculate the used DMA */
- if ((DMA_IT & FLAG_Mask) != (u32)RESET)
- {
- /* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR ;
- }
- else
- {
- /* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR ;
- }
-
- /* Check the status of the specified DMA interrupt */
- if ((tmpreg & DMA_IT) != (u32)RESET)
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : DMA_ClearITPendingBit
-* Description : Clears the DMAy Channelx's interrupt pending bits.
-* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
-* This parameter can be any combination (for the same DMA) of
-* the following values:
-* - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-* - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-* - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-* - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-* - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-* - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
-* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
-* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
-* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
-* - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
-* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
-* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
-* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
-* - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
-* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
-* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
-* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
-* - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
-* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
-* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
-* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
-* - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
-* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
-* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
-* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
-* - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
-* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
-* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
-* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
-* - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
-* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
-* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
-* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA_ClearITPendingBit(u32 DMA_IT)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Calculate the used DMA */
- if ((DMA_IT & FLAG_Mask) != (u32)RESET)
- {
- /* Clear the selected DMA interrupt pending bits */
- DMA2->IFCR = DMA_IT;
- }
- else
- {
- /* Clear the selected DMA interrupt pending bits */
- DMA1->IFCR = DMA_IT;
- }
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
-
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the DMA firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @defgroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA ENABLE mask */
+#define CCR_ENABLE_Set ((uint32_t)0x00000001)
+#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
+#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
+#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
+#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
+#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
+#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
+#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)
+#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)
+#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)
+#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)
+#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval None
+ */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
+ /* Reset DMAy Channelx control register */
+ DMAy_Channelx->CCR = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAy_Channelx->CNDTR = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAy_Channelx->CPAR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAy_Channelx->CMAR = 0;
+
+ if (DMAy_Channelx == DMA1_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;
+ }
+ else
+ {
+ if (DMAy_Channelx == DMA2_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+ * contains the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+ /* Get the DMAy_Channelx CCR value */
+ tmpreg = DMAy_Channelx->CCR;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+ /* Write to DMAy Channelx CCR */
+ DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+ /* Write to DMAy Channelx CPAR */
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+ /* Write to DMAy Channelx CMAR */
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CCR |= CCR_ENABLE_Set;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAy_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAy_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMA_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval The new state of DMA_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+
+ /* Calculate the used DMA */
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMA flag */
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
+ {
+ /* DMA_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMA_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMA_FLAG: specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval None
+ */
+void DMA_ClearFlag(uint32_t DMA_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+ /* Calculate the used DMA */
+
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMA flags */
+ DMA2->IFCR = DMA_FLAG;
+ }
+ else
+ {
+ /* Clear the selected DMA flags */
+ DMA1->IFCR = DMA_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMA_IT: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval The new state of DMA_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMA interrupt */
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)
+ {
+ /* DMA_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMA_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx’s interrupt pending bits.
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval None
+ */
+void DMA_ClearITPendingBit(uint32_t DMA_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMA interrupt pending bits */
+ DMA2->IFCR = DMA_IT;
+ }
+ else
+ {
+ /* Clear the selected DMA interrupt pending bits */
+ DMA1->IFCR = DMA_IT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_exti.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_exti.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_exti.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,219 +1,268 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_exti.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the EXTI firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_exti.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : EXTI_DeInit
-* Description : Deinitializes the EXTI peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x00000000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->PR = 0x0007FFFF;
-}
-
-/*******************************************************************************
-* Function Name : EXTI_Init
-* Description : Initializes the EXTI peripheral according to the specified
-* parameters in the EXTI_InitStruct.
-* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
-* that contains the configuration information for the EXTI
-* peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
- *(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
- /* Select the trigger for the selected external interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
- }
- else
- {
- *(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line;
- }
- }
- else
- {
- /* Disable the selected external lines */
- *(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line;
- }
-}
-
-/*******************************************************************************
-* Function Name : EXTI_StructInit
-* Description : Fills each EXTI_InitStruct member with its reset value.
-* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/*******************************************************************************
-* Function Name : EXTI_GenerateSWInterrupt
-* Description : Generates a Software interrupt.
-* Input : - EXTI_Line: specifies the EXTI lines to be enabled or
-* disabled.
-* This parameter can be any combination of EXTI_Linex where
-* x can be (0..18).
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI_GenerateSWInterrupt(u32 EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->SWIER |= EXTI_Line;
-}
-
-/*******************************************************************************
-* Function Name : EXTI_GetFlagStatus
-* Description : Checks whether the specified EXTI line flag is set or not.
-* Input : - EXTI_Line: specifies the EXTI line flag to check.
-* This parameter can be:
-* - EXTI_Linex: External interrupt line x where x(0..18)
-* Output : None
-* Return : The new state of EXTI_Line (SET or RESET).
-*******************************************************************************/
-FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : EXTI_ClearFlag
-* Description : Clears the EXTI's line pending flags.
-* Input : - EXTI_Line: specifies the EXTI lines flags to clear.
-* This parameter can be any combination of EXTI_Linex where
-* x can be (0..18).
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI_ClearFlag(u32 EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/*******************************************************************************
-* Function Name : EXTI_GetITStatus
-* Description : Checks whether the specified EXTI line is asserted or not.
-* Input : - EXTI_Line: specifies the EXTI line to check.
-* This parameter can be:
-* - EXTI_Linex: External interrupt line x where x(0..18)
-* Output : None
-* Return : The new state of EXTI_Line (SET or RESET).
-*******************************************************************************/
-ITStatus EXTI_GetITStatus(u32 EXTI_Line)
-{
- ITStatus bitstatus = RESET;
- u32 enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- enablestatus = EXTI->IMR & EXTI_Line;
-
- if (((EXTI->PR & EXTI_Line) != (u32)RESET) && (enablestatus != (u32)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : EXTI_ClearITPendingBit
-* Description : Clears the EXTI's line pending bits.
-* Input : - EXTI_Line: specifies the EXTI lines to clear.
-* This parameter can be any combination of EXTI_Linex where
-* x can be (0..18).
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI_ClearITPendingBit(u32 EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the EXTI firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x00000000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->PR = 0x000FFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ * that contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI’s line pending flags.
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMR & EXTI_Line;
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI’s line pending bits.
+ * @param EXTI_Line: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_flash.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_flash.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_flash.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,911 +1,874 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_flash.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the FLASH firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_flash.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Flash Access Control Register bits */
-#define ACR_LATENCY_Mask ((u32)0x00000038)
-#define ACR_HLFCYA_Mask ((u32)0xFFFFFFF7)
-#define ACR_PRFTBE_Mask ((u32)0xFFFFFFEF)
-
-#ifdef _FLASH_PROG
-/* Flash Access Control Register bits */
-#define ACR_PRFTBS_Mask ((u32)0x00000020)
-
-/* Flash Control Register bits */
-#define CR_PG_Set ((u32)0x00000001)
-#define CR_PG_Reset ((u32)0x00001FFE)
-
-#define CR_PER_Set ((u32)0x00000002)
-#define CR_PER_Reset ((u32)0x00001FFD)
-
-#define CR_MER_Set ((u32)0x00000004)
-#define CR_MER_Reset ((u32)0x00001FFB)
-
-#define CR_OPTPG_Set ((u32)0x00000010)
-#define CR_OPTPG_Reset ((u32)0x00001FEF)
-
-#define CR_OPTER_Set ((u32)0x00000020)
-#define CR_OPTER_Reset ((u32)0x00001FDF)
-
-#define CR_STRT_Set ((u32)0x00000040)
-
-#define CR_LOCK_Set ((u32)0x00000080)
-
-/* FLASH Mask */
-#define RDPRT_Mask ((u32)0x00000002)
-#define WRP0_Mask ((u32)0x000000FF)
-#define WRP1_Mask ((u32)0x0000FF00)
-#define WRP2_Mask ((u32)0x00FF0000)
-#define WRP3_Mask ((u32)0xFF000000)
-
-/* FLASH Keys */
-#define RDP_Key ((u16)0x00A5)
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xCDEF89AB)
-
-/* Delay definition */
-#define EraseTimeout ((u32)0x00000FFF)
-#define ProgramTimeout ((u32)0x0000000F)
-#endif
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-#ifdef _FLASH_PROG
-static void delay(void);
-#endif
-
-/* Private functions ---------------------------------------------------------*/
-/*******************************************************************************
-* Function Name : FLASH_SetLatency
-* Description : Sets the code latency value.
-* Input : - FLASH_Latency: specifies the FLASH Latency value.
-* This parameter can be one of the following values:
-* - FLASH_Latency_0: FLASH Zero Latency cycle
-* - FLASH_Latency_1: FLASH One Latency cycle
-* - FLASH_Latency_2: FLASH Two Latency cycles
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_SetLatency(u32 FLASH_Latency)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Sets the Latency value */
- FLASH->ACR &= ACR_LATENCY_Mask;
- FLASH->ACR |= FLASH_Latency;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_HalfCycleAccessCmd
-* Description : Enables or disables the Half cycle flash access.
-* Input : - FLASH_HalfCycle: specifies the FLASH Half cycle Access mode.
-* This parameter can be one of the following values:
-* - FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
-* - FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
-
- /* Enable or disable the Half cycle access */
- FLASH->ACR &= ACR_HLFCYA_Mask;
- FLASH->ACR |= FLASH_HalfCycleAccess;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_PrefetchBufferCmd
-* Description : Enables or disables the Prefetch Buffer.
-* Input : - FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
-* This parameter can be one of the following values:
-* - FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
-* - FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
-
- /* Enable or disable the Prefetch Buffer */
- FLASH->ACR &= ACR_PRFTBE_Mask;
- FLASH->ACR |= FLASH_PrefetchBuffer;
-}
-
-#ifdef _FLASH_PROG
-/*******************************************************************************
-* Function Name : FLASH_Unlock
-* Description : Unlocks the FLASH Program Erase Controller.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_Unlock(void)
-{
- /* Authorize the FPEC Access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_Lock
-* Description : Locks the FLASH Program Erase Controller.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_Lock(void)
-{
- /* Set the Lock Bit to lock the FPEC and the FCR */
- FLASH->CR |= CR_LOCK_Set;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ErasePage
-* Description : Erases a specified FLASH page.
-* Input : - Page_Address: The page address to be erased.
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_ErasePage(u32 Page_Address)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Page_Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR|= CR_PER_Set;
- FLASH->AR = Page_Address;
- FLASH->CR|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the erase operation is completed, disable the PER Bit */
- FLASH->CR &= CR_PER_Reset;
- }
- }
- /* Return the Erase Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_EraseAllPages
-* Description : Erases all FLASH pages.
-* Input : None
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_EraseAllPages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
- }
- /* Return the Erase Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_EraseOptionBytes
-* Description : Erases the FLASH option bytes.
-* Input : None
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_EraseOptionBytes(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* if the previous operation is completed, proceed to erase the option bytes */
- FLASH->CR |= CR_OPTER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- /* Enable the readout access */
- OB->RDP= RDP_Key;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- else
- {
- if (status != FLASH_BUSY)
- {
- /* Disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- }
- /* Return the erase status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ProgramWord
-* Description : Programs a word at a specified address.
-* Input : - Address: specifies the address to be programmed.
-* - Data: specifies the data to be programmed.
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(vu16*)Address = (u16)Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- *(vu16*)(Address + 2) = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- else
- {
- if (status != FLASH_BUSY)
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- }
- /* Return the Program Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ProgramHalfWord
-* Description : Programs a half word at a specified address.
-* Input : - Address: specifies the address to be programmed.
-* - Data: specifies the data to be programmed.
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR |= CR_PG_Set;
-
- *(vu16*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- /* Return the Program Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ProgramOptionByteData
-* Description : Programs a half word at a specified Option Byte Data address.
-* Input : - Address: specifies the address to be programmed.
-* This parameter can be 0x1FFFF804 or 0x1FFFF806.
-* - Data: specifies the data to be programmed.
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
-
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Enables the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- *(vu16*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_EnableWriteProtection
-* Description : Write protects the desired pages
-* Input : - FLASH_Pages: specifies the address of the pages to be
-* write protected. This parameter can be:
-* - For STM32F10Xxx Medium-density devices (FLASH page size equal to 1 KB)
-* - A value between FLASH_WRProt_Pages0to3 and
-* FLASH_WRProt_Pages124to127
-* - For STM32F10Xxx High-density devices (FLASH page size equal to 2 KB)
-* - A value between FLASH_WRProt_Pages0to1 and
-* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
-* - FLASH_WRProt_AllPages
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages)
-{
- u16 WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
-
- FLASH_Pages = (u32)(~FLASH_Pages);
- WRP0_Data = (vu16)(FLASH_Pages & WRP0_Mask);
- WRP1_Data = (vu16)((FLASH_Pages & WRP1_Mask) >> 8);
- WRP2_Data = (vu16)((FLASH_Pages & WRP2_Mask) >> 16);
- WRP3_Data = (vu16)((FLASH_Pages & WRP3_Mask) >> 24);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorizes the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- FLASH->CR |= CR_OPTPG_Set;
-
- if(WRP0_Data != 0xFF)
- {
- OB->WRP0 = WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 = WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 = WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
- {
- OB->WRP3 = WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if(status != FLASH_BUSY)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the write protection operation Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ReadOutProtection
-* Description : Enables or disables the read out protection.
-* If the user has already programmed the other option bytes before
-* calling this function, he must re-program them since this
-* function erases all option bytes.
-* Input : - Newstate: new state of the ReadOut Protection.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorizes the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- FLASH->CR |= CR_OPTER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- if(NewState != DISABLE)
- {
- OB->RDP = 0x00;
- }
- else
- {
- OB->RDP = RDP_Key;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- else
- {
- if(status != FLASH_BUSY)
- {
- /* Disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
- }
- }
- }
- /* Return the protection operation Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_UserOptionByteConfig
-* Description : Programs the FLASH User Option Byte: IWDG_SW / RST_STOP /
-* RST_STDBY.
-* Input : - OB_IWDG: Selects the IWDG mode
-* This parameter can be one of the following values:
-* - OB_IWDG_SW: Software IWDG selected
-* - OB_IWDG_HW: Hardware IWDG selected
-* - OB_STOP: Reset event when entering STOP mode.
-* This parameter can be one of the following values:
-* - OB_STOP_NoRST: No reset generated when entering in STOP
-* - OB_STOP_RST: Reset generated when entering in STOP
-* - OB_STDBY: Reset event when entering Standby mode.
-* This parameter can be one of the following values:
-* - OB_STDBY_NoRST: No reset generated when entering in STANDBY
-* - OB_STDBY_RST: Reset generated when entering in STANDBY
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- OB->USER = ( OB_IWDG | OB_STOP |OB_STDBY) | (u16)0xF8;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_BUSY)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_GetUserOptionByte
-* Description : Returns the FLASH User Option Bytes values.
-* Input : None
-* Output : None
-* Return : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
-* and RST_STDBY(Bit2).
-*******************************************************************************/
-u32 FLASH_GetUserOptionByte(void)
-{
- /* Return the User Option Byte */
- return (u32)(FLASH->OBR >> 2);
-}
-
-/*******************************************************************************
-* Function Name : FLASH_GetWriteProtectionOptionByte
-* Description : Returns the FLASH Write Protection Option Bytes Register value.
-* Input : None
-* Output : None
-* Return : The FLASH Write Protection Option Bytes Register value
-*******************************************************************************/
-u32 FLASH_GetWriteProtectionOptionByte(void)
-{
- /* Return the Falsh write protection Register value */
- return (u32)(FLASH->WRPR);
-}
-
-/*******************************************************************************
-* Function Name : FLASH_GetReadOutProtectionStatus
-* Description : Checks whether the FLASH Read Out Protection Status is set
-* or not.
-* Input : None
-* Output : None
-* Return : FLASH ReadOut Protection Status(SET or RESET)
-*******************************************************************************/
-FlagStatus FLASH_GetReadOutProtectionStatus(void)
-{
- FlagStatus readoutstatus = RESET;
-
- if ((FLASH->OBR & RDPRT_Mask) != (u32)RESET)
- {
- readoutstatus = SET;
- }
- else
- {
- readoutstatus = RESET;
- }
- return readoutstatus;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_GetPrefetchBufferStatus
-* Description : Checks whether the FLASH Prefetch Buffer status is set or not.
-* Input : None
-* Output : None
-* Return : FLASH Prefetch Buffer Status (SET or RESET).
-*******************************************************************************/
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((FLASH->ACR & ACR_PRFTBS_Mask) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ITConfig
-* Description : Enables or disables the specified FLASH interrupts.
-* Input : - FLASH_IT: specifies the FLASH interrupt sources to be
-* enabled or disabled.
-* This parameter can be any combination of the following values:
-* - FLASH_IT_ERROR: FLASH Error Interrupt
-* - FLASH_IT_EOP: FLASH end of operation Interrupt
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(u32)FLASH_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : FLASH_GetFlagStatus
-* Description : Checks whether the specified FLASH flag is set or not.
-* Input : - FLASH_FLAG: specifies the FLASH flag to check.
-* This parameter can be one of the following values:
-* - FLASH_FLAG_BSY: FLASH Busy flag
-* - FLASH_FLAG_PGERR: FLASH Program error flag
-* - FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
-* - FLASH_FLAG_EOP: FLASH End of Operation flag
-* - FLASH_FLAG_OPTERR: FLASH Option Byte error flag
-* Output : None
-* Return : The new state of FLASH_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
-
- if(FLASH_FLAG == FLASH_FLAG_OPTERR)
- {
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_ClearFlag
-* Description : Clears the FLASH's pending flags.
-* Input : - FLASH_FLAG: specifies the FLASH flags to clear.
-* This parameter can be any combination of the following values:
-* - FLASH_FLAG_BSY: FLASH Busy flag
-* - FLASH_FLAG_PGERR: FLASH Program error flag
-* - FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
-* - FLASH_FLAG_EOP: FLASH End of Operation flag
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_ClearFlag(u16 FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_GetStatus
-* Description : Returns the FLASH Status.
-* Input : None
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE
-*******************************************************************************/
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if(FLASH->SR & FLASH_FLAG_PGERR)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if(FLASH->SR & FLASH_FLAG_WRPRTERR)
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-
-/*******************************************************************************
-* Function Name : FLASH_WaitForLastOperation
-* Description : Waits for a Flash operation to complete or a TIMEOUT to occur.
-* Input : - Timeout: FLASH progamming Timeout
-* Output : None
-* Return : FLASH Status: The returned value can be: FLASH_BUSY,
-* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
-* FLASH_TIMEOUT.
-*******************************************************************************/
-FLASH_Status FLASH_WaitForLastOperation(u32 Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetStatus();
-
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == FLASH_BUSY) && (Timeout != 0x00))
- {
- delay();
- status = FLASH_GetStatus();
- Timeout--;
- }
-
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
-
- /* Return the operation status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : delay
-* Description : Inserts a time delay.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-static void delay(void)
-{
- vu32 i = 0;
-
- for(i = 0xFF; i != 0; i--)
- {
- }
-}
-#endif
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the FLASH firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_flash.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @defgroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set ((uint32_t)0x00000001)
+#define CR_PG_Reset ((uint32_t)0x00001FFE)
+#define CR_PER_Set ((uint32_t)0x00000002)
+#define CR_PER_Reset ((uint32_t)0x00001FFD)
+#define CR_MER_Set ((uint32_t)0x00000004)
+#define CR_MER_Reset ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set ((uint32_t)0x00000020)
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
+#define CR_STRT_Set ((uint32_t)0x00000040)
+#define CR_LOCK_Set ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask ((uint32_t)0x00000002)
+#define WRP0_Mask ((uint32_t)0x000000FF)
+#define WRP1_Mask ((uint32_t)0x0000FF00)
+#define WRP2_Mask ((uint32_t)0x00FF0000)
+#define WRP3_Mask ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define RDP_Key ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x00000FFF)
+#define ProgramTimeout ((uint32_t)0x0000000F)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+static void delay(void);
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @param FLASH_Latency: specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+ * @arg FLASH_Latency_1: FLASH One Latency cycle
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles
+ * @retval None
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpreg = FLASH->ACR;
+
+ /* Sets the Latency value */
+ tmpreg &= ACR_LATENCY_Mask;
+ tmpreg |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->ACR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Half cycle flash access.
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+ * This parameter can be one of the following values:
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+ * @retval None
+ */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+
+ /* Enable or disable the Half cycle access */
+ FLASH->ACR &= ACR_HLFCYA_Mask;
+ FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+ * @retval None
+ */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->ACR &= ACR_PRFTBE_Mask;
+ FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @param None
+ * @retval None
+ */
+void FLASH_Unlock(void)
+{
+ /* Authorize the FPEC Access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @param None
+ * @retval None
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the FCR */
+ FLASH->CR |= CR_LOCK_Set;
+}
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @param Page_Address: The page address to be erased.
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR|= CR_PER_Set;
+ FLASH->AR = Page_Address;
+ FLASH->CR|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the erase operation is completed, disable the PER Bit */
+ FLASH->CR &= CR_PER_Reset;
+ }
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the erase operation is completed, disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ /* Enable the readout access */
+ OB->RDP= RDP_Key;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ }
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @param FLASH_Pages: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
+ * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
+ * and FLASH_WRProt_Pages124to127
+ * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
+ * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
+ * @arg FLASH_WRProt_AllPages
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTPG_Set;
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 = WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 = WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 = WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 = WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @param Newstate: new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ if(NewState != DISABLE)
+ {
+ OB->RDP = 0x00;
+ }
+ else
+ {
+ OB->RDP = RDP_Key;
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param OB_IWDG: Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+
+ OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @param None
+ * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+ /* Return the Falsh write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @param None
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+ * @param NewState: new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @param FLASH_FLAG: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+ {
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH’s pending flags.
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @retval None
+ */
+void FLASH_ClearFlag(uint16_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @param Timeout: FLASH progamming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetStatus();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ delay();
+ status = FLASH_GetStatus();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @brief Inserts a time delay.
+ * @param None
+ * @retval None
+ */
+static void delay(void)
+{
+ __IO uint32_t i = 0;
+ for(i = 0xFF; i != 0; i--)
+ {
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_fsmc.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_fsmc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_fsmc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,857 +1,858 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_fsmc.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the FSMC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------------------- FSMC registers bit mask ---------------------------- */
-/* FSMC BCRx Mask */
-#define BCR_MBKEN_Set ((u32)0x00000001)
-#define BCR_MBKEN_Reset ((u32)0x000FFFFE)
-#define BCR_FACCEN_Set ((u32)0x00000040)
-
-/* FSMC PCRx Mask */
-#define PCR_PBKEN_Set ((u32)0x00000004)
-#define PCR_PBKEN_Reset ((u32)0x000FFFFB)
-#define PCR_ECCEN_Set ((u32)0x00000040)
-#define PCR_ECCEN_Reset ((u32)0x000FFFBF)
-#define PCR_MemoryType_NAND ((u32)0x00000008)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : FSMC_NORSRAMDeInit
-* Description : Deinitializes the FSMC NOR/SRAM Banks registers to their default
-* reset values.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
-* - FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
-* - FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
-* - FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NORSRAMDeInit(u32 FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
-
- /* FSMC_Bank1_NORSRAM1 */
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
- }
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
- else
- {
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
- }
-
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NANDDeInit
-* Description : Deinitializes the FSMC NAND Banks registers to their default
-* reset values.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NANDDeInit(u32 FSMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Set the FSMC_Bank2 registers to their reset values */
- FSMC_Bank2->PCR2 = 0x00000018;
- FSMC_Bank2->SR2 = 0x00000040;
- FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
- FSMC_Bank2->PATT2 = 0xFCFCFCFC;
- }
- /* FSMC_Bank3_NAND */
- else
- {
- /* Set the FSMC_Bank3 registers to their reset values */
- FSMC_Bank3->PCR3 = 0x00000018;
- FSMC_Bank3->SR3 = 0x00000040;
- FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
- FSMC_Bank3->PATT3 = 0xFCFCFCFC;
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_PCCARDDeInit
-* Description : Deinitializes the FSMC PCCARD Bank registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_PCCARDDeInit(void)
-{
- /* Set the FSMC_Bank4 registers to their reset values */
- FSMC_Bank4->PCR4 = 0x00000018;
- FSMC_Bank4->SR4 = 0x00000000;
- FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
- FSMC_Bank4->PATT4 = 0xFCFCFCFC;
- FSMC_Bank4->PIO4 = 0xFCFCFCFC;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NORSRAMInit
-* Description : Initializes the FSMC NOR/SRAM Banks according to the
-* specified parameters in the FSMC_NORSRAMInitStruct.
-* Input : - FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
-* structure that contains the configuration information for
-* the FSMC NOR/SRAM specified Banks.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
-
- /* Bank1 NOR/SRAM control register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (u32)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
-
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
- {
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (u32)BCR_FACCEN_Set;
- }
-
- /* Bank1 NOR/SRAM timing register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
- (u32)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
-
-
-
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
- {
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
-
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (u32)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
- }
- else
- {
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NANDInit
-* Description : Initializes the FSMC NAND Banks according to the specified
-* parameters in the FSMC_NANDInitStruct.
-* Input : - FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
-* structure that contains the configuration information for
-* the FSMC NAND specified Banks.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- u32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
-
- /* Check the parameters */
- assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
- assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
- assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
- assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
- assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
- assert_param( IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_NANDInitStruct->FSMC_AddressLowMapping));
- assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
- assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
- tmppcr = (u32)FSMC_NANDInitStruct->FSMC_Waitfeature |
- PCR_MemoryType_NAND |
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
- FSMC_NANDInitStruct->FSMC_ECC |
- FSMC_NANDInitStruct->FSMC_ECCPageSize |
- FSMC_NANDInitStruct->FSMC_AddressLowMapping |
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
-
- /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
- tmppmem = (u32)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (u32)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* FSMC_Bank2_NAND registers configuration */
- FSMC_Bank2->PCR2 = tmppcr;
- FSMC_Bank2->PMEM2 = tmppmem;
- FSMC_Bank2->PATT2 = tmppatt;
- }
- else
- {
- /* FSMC_Bank3_NAND registers configuration */
- FSMC_Bank3->PCR3 = tmppcr;
- FSMC_Bank3->PMEM3 = tmppmem;
- FSMC_Bank3->PATT3 = tmppatt;
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_PCCARDInit
-* Description : Initializes the FSMC PCCARD Bank according to the specified
-* parameters in the FSMC_PCCARDInitStruct.
-* Input : - FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
-* structure that contains the configuration information for
-* the FSMC PCCARD Bank.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
- assert_param(IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_PCCARDInitStruct->FSMC_AddressLowMapping));
- assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
- assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
-
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
-
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
-
- /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
- FSMC_Bank4->PCR4 = (u32)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
- FSMC_MemoryDataWidth_16b |
- FSMC_PCCARDInitStruct->FSMC_AddressLowMapping |
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
-
- /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
- FSMC_Bank4->PMEM4 = (u32)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
- FSMC_Bank4->PATT4 = (u32)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
- /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
- FSMC_Bank4->PIO4 = (u32)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NORSRAMStructInit
-* Description : Fills each FSMC_NORSRAMInitStruct member with its default value.
-* Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
-{
- /* Reset NOR/SRAM Init structure parameters values */
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NANDStructInit
-* Description : Fills each FSMC_NANDInitStruct member with its default value.
-* Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NANDInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
-{
- /* Reset NAND Init structure parameters values */
- FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
- FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
- FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
- FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
- FSMC_NANDInitStruct->FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
- FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_PCCARDStructInit
-* Description : Fills each FSMC_PCCARDInitStruct member with its default value.
-* Input : - FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
-{
- /* Reset PCCARD Init structure parameters values */
- FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
- FSMC_PCCARDInitStruct->FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
- FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NORSRAMCmd
-* Description : Enables or disables the specified NOR/SRAM Memory Bank.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
-* - FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
-* - FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
-* - FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
-* : - NewState: new state of the FSMC_Bank.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
- }
- else
- {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NANDCmd
-* Description : Enables or disables the specified NAND Memory Bank.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* : - NewState: new state of the FSMC_Bank.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
- }
- }
- else
- {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
- }
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_PCCARDCmd
-* Description : Enables or disables the PCCARD Memory Bank.
-* Input : - NewState: new state of the PCCARD Memory Bank.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_PCCARDCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
- }
- else
- {
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
- FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_NANDECCCmd
-* Description : Enables or disables the FSMC NAND ECC feature.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* : - NewState: new state of the FSMC NAND ECC feature.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
- }
- else
- {
- FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
- }
- }
- else
- {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
- }
- else
- {
- FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
- }
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_GetECC
-* Description : Returns the error correction code register value.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* Output : None
-* Return : The Error Correction Code (ECC) value.
-*******************************************************************************/
-u32 FSMC_GetECC(u32 FSMC_Bank)
-{
- u32 eccval = 0x00000000;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- /* Get the ECCR2 register value */
- eccval = FSMC_Bank2->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- eccval = FSMC_Bank3->ECCR3;
- }
- /* Return the error correction code value */
- return(eccval);
-}
-
-/*******************************************************************************
-* Function Name : FSMC_ITConfig
-* Description : Enables or disables the specified FSMC interrupts.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
-* - FSMC_IT: specifies the FSMC interrupt sources to be
-* enabled or disabled.
-* This parameter can be any combination of the following values:
-* - FSMC_IT_RisingEdge: Rising edge detection interrupt.
-* - FSMC_IT_Level: Level edge detection interrupt.
-* - FSMC_IT_FallingEdge: Falling edge detection interrupt.
-* - NewState: new state of the specified FSMC interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState)
-{
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 |= FSMC_IT;
- }
- /* Enable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 |= FSMC_IT;
- }
- }
- else
- {
- /* Disable the selected FSMC_Bank2 interrupts */
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
-
- FSMC_Bank2->SR2 &= (u32)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank3 interrupts */
- else if (FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= (u32)~FSMC_IT;
- }
- /* Disable the selected FSMC_Bank4 interrupts */
- else
- {
- FSMC_Bank4->SR4 &= (u32)~FSMC_IT;
- }
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_GetFlagStatus
-* Description : Checks whether the specified FSMC flag is set or not.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
-* - FSMC_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - FSMC_FLAG_RisingEdge: Rising egde detection Flag.
-* - FSMC_FLAG_Level: Level detection Flag.
-* - FSMC_FLAG_FallingEdge: Falling egde detection Flag.
-* - FSMC_FLAG_FEMPT: Fifo empty Flag.
-* Output : None
-* Return : The new state of FSMC_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- u32 tmpsr = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- /* Get the flag status */
- if ((tmpsr & FSMC_FLAG) != (u16)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_ClearFlag
-* Description : Clears the FSMC's pending flags.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
-* - FSMC_FLAG: specifies the flag to clear.
-* This parameter can be any combination of the following values:
-* - FSMC_FLAG_RisingEdge: Rising egde detection Flag.
-* - FSMC_FLAG_Level: Level detection Flag.
-* - FSMC_FLAG_FallingEdge: Falling egde detection Flag.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
- assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~FSMC_FLAG;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~FSMC_FLAG;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~FSMC_FLAG;
- }
-}
-
-/*******************************************************************************
-* Function Name : FSMC_GetITStatus
-* Description : Checks whether the specified FSMC interrupt has occurred or not.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
-* - FSMC_IT: specifies the FSMC interrupt source to check.
-* This parameter can be one of the following values:
-* - FSMC_IT_RisingEdge: Rising edge detection interrupt.
-* - FSMC_IT_Level: Level edge detection interrupt.
-* - FSMC_IT_FallingEdge: Falling edge detection interrupt.
-* Output : None
-* Return : The new state of FSMC_IT (SET or RESET).
-*******************************************************************************/
-ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT)
-{
- ITStatus bitstatus = RESET;
- u32 tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_GET_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- tmpsr = FSMC_Bank2->SR2;
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- tmpsr = FSMC_Bank3->SR3;
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- tmpsr = FSMC_Bank4->SR4;
- }
-
- itstatus = tmpsr & FSMC_IT;
-
- itenable = tmpsr & (FSMC_IT >> 3);
-
- if ((itstatus != (u32)RESET) && (itenable != (u32)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : FSMC_ClearITPendingBit
-* Description : Clears the FSMC's interrupt pending bits.
-* Input : - FSMC_Bank: specifies the FSMC Bank to be used
-* This parameter can be one of the following values:
-* - FSMC_Bank2_NAND: FSMC Bank2 NAND
-* - FSMC_Bank3_NAND: FSMC Bank3 NAND
-* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
-* - FSMC_IT: specifies the interrupt pending bit to clear.
-* This parameter can be any combination of the following values:
-* - FSMC_IT_RisingEdge: Rising edge detection interrupt.
-* - FSMC_IT_Level: Level edge detection interrupt.
-* - FSMC_IT_FallingEdge: Falling edge detection interrupt.
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
- assert_param(IS_FSMC_IT(FSMC_IT));
-
- if(FSMC_Bank == FSMC_Bank2_NAND)
- {
- FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
- }
- else if(FSMC_Bank == FSMC_Bank3_NAND)
- {
- FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
- }
- /* FSMC_Bank4_PCCARD*/
- else
- {
- FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
- }
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the FSMC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FSMC
+ * @brief FSMC driver modules
+ * @{
+ */
+
+/** @defgroup FSMC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Defines
+ * @{
+ */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
+ * reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @retval None
+ */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+
+ /* FSMC_Bank1_NORSRAM1 */
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
+ }
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+ else
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
+ }
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval None
+ */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Set the FSMC_Bank2 registers to their reset values */
+ FSMC_Bank2->PCR2 = 0x00000018;
+ FSMC_Bank2->SR2 = 0x00000040;
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC;
+ }
+ /* FSMC_Bank3_NAND */
+ else
+ {
+ /* Set the FSMC_Bank3 registers to their reset values */
+ FSMC_Bank3->PCR3 = 0x00000018;
+ FSMC_Bank3->SR3 = 0x00000040;
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void FSMC_PCCARDDeInit(void)
+{
+ /* Set the FSMC_Bank4 registers to their reset values */
+ FSMC_Bank4->PCR4 = 0x00000018;
+ FSMC_Bank4->SR4 = 0x00000000;
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
+ * parameters in the FSMC_NORSRAMInitStruct.
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+ * structure that contains the configuration information for
+ * the FSMC NOR/SRAM specified Banks.
+ * @retval None
+ */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
+
+ /* Bank1 NOR/SRAM control register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+ {
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+ }
+ /* Bank1 NOR/SRAM timing register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+
+
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+ {
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+ }
+ else
+ {
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC NAND Banks according to the specified
+ * parameters in the FSMC_NANDInitStruct.
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
+ * structure that contains the configuration information for the FSMC NAND specified Banks.
+ * @retval None
+ */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+ /* Check the parameters */
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+ assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+ PCR_MemoryType_NAND |
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NANDInitStruct->FSMC_ECC |
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* FSMC_Bank2_NAND registers configuration */
+ FSMC_Bank2->PCR2 = tmppcr;
+ FSMC_Bank2->PMEM2 = tmppmem;
+ FSMC_Bank2->PATT2 = tmppatt;
+ }
+ else
+ {
+ /* FSMC_Bank3_NAND registers configuration */
+ FSMC_Bank3->PCR3 = tmppcr;
+ FSMC_Bank3->PMEM3 = tmppmem;
+ FSMC_Bank3->PATT3 = tmppatt;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC PCCARD Bank according to the specified
+ * parameters in the FSMC_PCCARDInitStruct.
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+ * structure that contains the configuration information for the FSMC PCCARD Bank.
+ * @retval None
+ */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+ FSMC_MemoryDataWidth_16b |
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+}
+
+/**
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Reset NOR/SRAM Init structure parameters values */
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ /* Reset NAND Init structure parameters values */
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Reset PCCARD Init structure parameters values */
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+ }
+ else
+ {
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified NAND Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the PCCARD Memory Bank.
+ * @param NewState: new state of the PCCARD Memory Bank.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the FSMC NAND ECC feature.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC NAND ECC feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Returns the error correction code register value.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval The Error Correction Code (ECC) value.
+ */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+ uint32_t eccval = 0x00000000;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the ECCR2 register value */
+ eccval = FSMC_Bank2->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ eccval = FSMC_Bank3->ECCR3;
+ }
+ /* Return the error correction code value */
+ return(eccval);
+}
+
+/**
+ * @brief Enables or disables the specified FSMC interrupts.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @param NewState: new state of the specified FSMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 |= FSMC_IT;
+ }
+ }
+ else
+ {
+ /* Disable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC flag is set or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
+ * @retval The new state of FSMC_FLAG (SET or RESET).
+ */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ /* Get the flag status */
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC’s pending flags.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @retval None
+ */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval The new state of FSMC_IT (SET or RESET).
+ */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ itstatus = tmpsr & FSMC_IT;
+
+ itenable = tmpsr & (FSMC_IT >> 3);
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC’s interrupt pending bits.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval None
+ */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_gpio.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_gpio.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_gpio.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,583 +1,617 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_gpio.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the GPIO firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
-
-/* --- EVENTCR Register ---*/
-/* Alias word address of EVOE bit */
-#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
-#define EVOE_BitNumber ((u8)0x07)
-#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
-
-#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)
-#define LSB_MASK ((u16)0xFFFF)
-#define DBGAFR_POSITION_MASK ((u32)0x000F0000)
-#define DBGAFR_SWJCFG_MASK ((u32)0xF0FFFFFF)
-#define DBGAFR_LOCATION_MASK ((u32)0x00200000)
-#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : GPIO_DeInit
-* Description : Deinitializes the GPIOx peripheral registers to their default
-* reset values.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- switch (*(u32*)&GPIOx)
- {
- case GPIOA_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
- break;
-
- case GPIOB_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
- break;
-
- case GPIOC_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
- break;
-
- case GPIOD_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
- break;
-
- case GPIOE_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
- break;
-
- case GPIOF_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
- break;
-
- case GPIOG_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : GPIO_AFIODeInit
-* Description : Deinitializes the Alternate Functions (remap, event control
-* and EXTI configuration) registers to their default reset
-* values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_AFIODeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
-}
-
-/*******************************************************************************
-* Function Name : GPIO_Init
-* Description : Initializes the GPIOx peripheral according to the specified
-* parameters in the GPIO_InitStruct.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
-* contains the configuration information for the specified GPIO
-* peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
- u32 tmpreg = 0x00, pinmask = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
-
-/*---------------------------- GPIO Mode Configuration -----------------------*/
- currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
-
- if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
- {
- /* Check the parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
- /* Output mode */
- currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
- }
-
-/*---------------------------- GPIO CRL Configuration ------------------------*/
- /* Configure the eight low port pins */
- if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
- {
- tmpreg = GPIOx->CRL;
-
- for (pinpos = 0x00; pinpos < 0x08; pinpos++)
- {
- pos = ((u32)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- pos = pinpos << 2;
- /* Clear the corresponding low control register bits */
- pinmask = ((u32)0x0F) << pos;
- tmpreg &= ~pinmask;
-
- /* Write the mode configuration in the corresponding bits */
- tmpreg |= (currentmode << pos);
-
- /* Reset the corresponding ODR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
- {
- GPIOx->BRR = (((u32)0x01) << pinpos);
- }
- else
- {
- /* Set the corresponding ODR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
- {
- GPIOx->BSRR = (((u32)0x01) << pinpos);
- }
- }
- }
- }
- GPIOx->CRL = tmpreg;
- }
-
-/*---------------------------- GPIO CRH Configuration ------------------------*/
- /* Configure the eight high port pins */
- if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
- {
- tmpreg = GPIOx->CRH;
- for (pinpos = 0x00; pinpos < 0x08; pinpos++)
- {
- pos = (((u32)0x01) << (pinpos + 0x08));
- /* Get the port pins position */
- currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
- if (currentpin == pos)
- {
- pos = pinpos << 2;
- /* Clear the corresponding high control register bits */
- pinmask = ((u32)0x0F) << pos;
- tmpreg &= ~pinmask;
-
- /* Write the mode configuration in the corresponding bits */
- tmpreg |= (currentmode << pos);
-
- /* Reset the corresponding ODR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
- {
- GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
- }
- /* Set the corresponding ODR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
- {
- GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
- }
- }
- }
- GPIOx->CRH = tmpreg;
- }
-}
-
-/*******************************************************************************
-* Function Name : GPIO_StructInit
-* Description : Fills each GPIO_InitStruct member with its default value.
-* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_ReadInputDataBit
-* Description : Reads the specified input port pin.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* : - GPIO_Pin: specifies the port bit to read.
-* This parameter can be GPIO_Pin_x where x can be (0..15).
-* Output : None
-* Return : The input port pin value.
-*******************************************************************************/
-u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
-{
- u8 bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)
- {
- bitstatus = (u8)Bit_SET;
- }
- else
- {
- bitstatus = (u8)Bit_RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_ReadInputData
-* Description : Reads the specified GPIO input data port.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* Output : None
-* Return : GPIO input data port value.
-*******************************************************************************/
-u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((u16)GPIOx->IDR);
-}
-
-/*******************************************************************************
-* Function Name : GPIO_ReadOutputDataBit
-* Description : Reads the specified output data port bit.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* : - GPIO_Pin: specifies the port bit to read.
-* This parameter can be GPIO_Pin_x where x can be (0..15).
-* Output : None
-* Return : The output port pin value.
-*******************************************************************************/
-u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
-{
- u8 bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)
- {
- bitstatus = (u8)Bit_SET;
- }
- else
- {
- bitstatus = (u8)Bit_RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_ReadOutputData
-* Description : Reads the specified GPIO output data port.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* Output : None
-* Return : GPIO output data port value.
-*******************************************************************************/
-u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((u16)GPIOx->ODR);
-}
-
-/*******************************************************************************
-* Function Name : GPIO_SetBits
-* Description : Sets the selected data port bits.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* - GPIO_Pin: specifies the port bits to be written.
-* This parameter can be any combination of GPIO_Pin_x where
-* x can be (0..15).
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = GPIO_Pin;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_ResetBits
-* Description : Clears the selected data port bits.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* - GPIO_Pin: specifies the port bits to be written.
-* This parameter can be any combination of GPIO_Pin_x where
-* x can be (0..15).
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BRR = GPIO_Pin;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_WriteBit
-* Description : Sets or clears the selected data port bit.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* - GPIO_Pin: specifies the port bit to be written.
-* This parameter can be one of GPIO_Pin_x where x can be (0..15).
-* - BitVal: specifies the value to be written to the selected bit.
-* This parameter can be one of the BitAction enum values:
-* - Bit_RESET: to clear the port pin
-* - Bit_SET: to set the port pin
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = GPIO_Pin;
- }
-}
-
-/*******************************************************************************
-* Function Name : GPIO_Write
-* Description : Writes data to the specified GPIO data port.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* - PortVal: specifies the value to be written to the port output
-* data register.
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_PinLockConfig
-* Description : Locks GPIO Pins configuration registers.
-* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
-* - GPIO_Pin: specifies the port bit to be written.
-* This parameter can be any combination of GPIO_Pin_x where
-* x can be (0..15).
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
-{
- u32 tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_EventOutputConfig
-* Description : Selects the GPIO pin used as Event output.
-* Input : - GPIO_PortSource: selects the GPIO port to be used as source
-* for Event output.
-* This parameter can be GPIO_PortSourceGPIOx where x can be
-* (A..E).
-* - GPIO_PinSource: specifies the pin for the Event output.
-* This parameter can be GPIO_PinSourcex where x can be (0..15).
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
-{
- u32 tmpreg = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-
- tmpreg = AFIO->EVCR;
- /* Clear the PORT[6:4] and PIN[3:0] bits */
- tmpreg &= EVCR_PORTPINCONFIG_MASK;
- tmpreg |= (u32)GPIO_PortSource << 0x04;
- tmpreg |= GPIO_PinSource;
-
- AFIO->EVCR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_EventOutputCmd
-* Description : Enables or disables the Event Output.
-* Input : - NewState: new state of the Event output.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_EventOutputCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) EVCR_EVOE_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_PinRemapConfig
-* Description : Changes the mapping of the specified pin.
-* Input : - GPIO_Remap: selects the pin to remap.
-* This parameter can be one of the following values:
-* - GPIO_Remap_SPI1
-* - GPIO_Remap_I2C1
-* - GPIO_Remap_USART1
-* - GPIO_Remap_USART2
-* - GPIO_PartialRemap_USART3
-* - GPIO_FullRemap_USART3
-* - GPIO_PartialRemap_TIM1
-* - GPIO_FullRemap_TIM1
-* - GPIO_PartialRemap1_TIM2
-* - GPIO_PartialRemap2_TIM2
-* - GPIO_FullRemap_TIM2
-* - GPIO_PartialRemap_TIM3
-* - GPIO_FullRemap_TIM3
-* - GPIO_Remap_TIM4
-* - GPIO_Remap1_CAN
-* - GPIO_Remap2_CAN
-* - GPIO_Remap_PD01
-* - GPIO_Remap_TIM5CH4_LSI
-* - GPIO_Remap_ADC1_ETRGINJ
-* - GPIO_Remap_ADC1_ETRGREG
-* - GPIO_Remap_ADC2_ETRGINJ
-* - GPIO_Remap_ADC2_ETRGREG
-* - GPIO_Remap_SWJ_NoJTRST
-* - GPIO_Remap_SWJ_JTAGDisable
-* - GPIO_Remap_SWJ_Disable
-* - NewState: new state of the port pin remapping.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
-{
- u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_REMAP(GPIO_Remap));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- tmpreg = AFIO->MAPR;
-
- tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
- tmp = GPIO_Remap & LSB_MASK;
-
- if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
- {
- tmpreg &= DBGAFR_SWJCFG_MASK;
- AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
- }
- else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
- {
- tmp1 = ((u32)0x03) << tmpmask;
- tmpreg &= ~tmp1;
- tmpreg |= ~DBGAFR_SWJCFG_MASK;
- }
- else
- {
- tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
- tmpreg |= ~DBGAFR_SWJCFG_MASK;
- }
-
- if (NewState != DISABLE)
- {
- tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
- }
-
- AFIO->MAPR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : GPIO_EXTILineConfig
-* Description : Selects the GPIO pin used as EXTI Line.
-* Input : - GPIO_PortSource: selects the GPIO port to be used as
-* source for EXTI lines.
-* This parameter can be GPIO_PortSourceGPIOx where x can be
-* (A..G).
-* - GPIO_PinSource: specifies the EXTI line to be configured.
-* This parameter can be GPIO_PinSourcex where x can be (0..15).
-* Output : None
-* Return : None
-*******************************************************************************/
-void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
-{
- u32 tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-
- tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
-
- AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
- AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the GPIO firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @defgroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* --- MAPR Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber ((u8)0x17)
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
+#define LSB_MASK ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+ }
+ else if (GPIOx == GPIOE)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+ }
+ else if (GPIOx == GPIOF)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+ }
+ else
+ {
+ if (GPIOx == GPIOG)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void GPIO_AFIODeInit(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+ uint32_t tmpreg = 0x00, pinmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+ /* Output mode */
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+ }
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+ /* Configure the eight low port pins */
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+ {
+ tmpreg = GPIOx->CRL;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding low control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+ }
+ else
+ {
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+ }
+ }
+ }
+ }
+ GPIOx->CRL = tmpreg;
+ }
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+ /* Configure the eight high port pins */
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+ {
+ tmpreg = GPIOx->CRH;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));
+ /* Get the port pins position */
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding high control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ }
+ }
+ GPIOx->CRH = tmpreg;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enum values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ * @param GPIO_PinSource: specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmpreg = AFIO->EVCR;
+ /* Clear the PORT[6:4] and PIN[3:0] bits */
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+ tmpreg |= GPIO_PinSource;
+ AFIO->EVCR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param NewState: new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param GPIO_Remap: selects the pin to remap.
+ * This parameter can be one of the following values:
+ * @arg GPIO_Remap_SPI1
+ * @arg GPIO_Remap_I2C1
+ * @arg GPIO_Remap_USART1
+ * @arg GPIO_Remap_USART2
+ * @arg GPIO_PartialRemap_USART3
+ * @arg GPIO_FullRemap_USART3
+ * @arg GPIO_PartialRemap_TIM1
+ * @arg GPIO_FullRemap_TIM1
+ * @arg GPIO_PartialRemap1_TIM2
+ * @arg GPIO_PartialRemap2_TIM2
+ * @arg GPIO_FullRemap_TIM2
+ * @arg GPIO_PartialRemap_TIM3
+ * @arg GPIO_FullRemap_TIM3
+ * @arg GPIO_Remap_TIM4
+ * @arg GPIO_Remap1_CAN1
+ * @arg GPIO_Remap2_CAN1
+ * @arg GPIO_Remap_PD01
+ * @arg GPIO_Remap_TIM5CH4_LSI
+ * @arg GPIO_Remap_ADC1_ETRGINJ
+ * @arg GPIO_Remap_ADC1_ETRGREG
+ * @arg GPIO_Remap_ADC2_ETRGINJ
+ * @arg GPIO_Remap_ADC2_ETRGREG
+ * @arg GPIO_Remap_ETH
+ * @arg GPIO_Remap_CAN2
+ * @arg GPIO_Remap_SWJ_NoJTRST
+ * @arg GPIO_Remap_SWJ_JTAGDisable
+ * @arg GPIO_Remap_SWJ_Disable
+ * @arg GPIO_Remap_SPI3
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF
+ * @arg GPIO_Remap_PTP_PPS
+ * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected
+ * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
+ * @param NewState: new state of the port pin remapping.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ tmpreg = AFIO->MAPR;
+
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+ tmp = GPIO_Remap & LSB_MASK;
+
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+ {
+ tmpreg &= DBGAFR_SWJCFG_MASK;
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+ }
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+ {
+ tmp1 = ((uint32_t)0x03) << tmpmask;
+ tmpreg &= ~tmp1;
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+ else
+ {
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+
+ if (NewState != DISABLE)
+ {
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+ }
+
+ AFIO->MAPR = tmpreg;
+}
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+ * @brief Selects the Ethernet media interface.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+ * This parameter can be one of the following values:
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode
+ * @retval None
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
+
+ /* Configure MII_RMII selection bit */
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_i2c.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_i2c.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_i2c.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,1216 +1,1152 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_i2c.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the I2C firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* I2C SPE mask */
-#define CR1_PE_Set ((u16)0x0001)
-#define CR1_PE_Reset ((u16)0xFFFE)
-
-/* I2C START mask */
-#define CR1_START_Set ((u16)0x0100)
-#define CR1_START_Reset ((u16)0xFEFF)
-
-/* I2C STOP mask */
-#define CR1_STOP_Set ((u16)0x0200)
-#define CR1_STOP_Reset ((u16)0xFDFF)
-
-/* I2C ACK mask */
-#define CR1_ACK_Set ((u16)0x0400)
-#define CR1_ACK_Reset ((u16)0xFBFF)
-
-/* I2C ENGC mask */
-#define CR1_ENGC_Set ((u16)0x0040)
-#define CR1_ENGC_Reset ((u16)0xFFBF)
-
-/* I2C SWRST mask */
-#define CR1_SWRST_Set ((u16)0x8000)
-#define CR1_SWRST_Reset ((u16)0x7FFF)
-
-/* I2C PEC mask */
-#define CR1_PEC_Set ((u16)0x1000)
-#define CR1_PEC_Reset ((u16)0xEFFF)
-
-/* I2C ENPEC mask */
-#define CR1_ENPEC_Set ((u16)0x0020)
-#define CR1_ENPEC_Reset ((u16)0xFFDF)
-
-/* I2C ENARP mask */
-#define CR1_ENARP_Set ((u16)0x0010)
-#define CR1_ENARP_Reset ((u16)0xFFEF)
-
-/* I2C NOSTRETCH mask */
-#define CR1_NOSTRETCH_Set ((u16)0x0080)
-#define CR1_NOSTRETCH_Reset ((u16)0xFF7F)
-
-/* I2C registers Masks */
-#define CR1_CLEAR_Mask ((u16)0xFBF5)
-
-/* I2C DMAEN mask */
-#define CR2_DMAEN_Set ((u16)0x0800)
-#define CR2_DMAEN_Reset ((u16)0xF7FF)
-
-/* I2C LAST mask */
-#define CR2_LAST_Set ((u16)0x1000)
-#define CR2_LAST_Reset ((u16)0xEFFF)
-
-/* I2C FREQ mask */
-#define CR2_FREQ_Reset ((u16)0xFFC0)
-
-/* I2C ADD0 mask */
-#define OAR1_ADD0_Set ((u16)0x0001)
-#define OAR1_ADD0_Reset ((u16)0xFFFE)
-
-/* I2C ENDUAL mask */
-#define OAR2_ENDUAL_Set ((u16)0x0001)
-#define OAR2_ENDUAL_Reset ((u16)0xFFFE)
-
-/* I2C ADD2 mask */
-#define OAR2_ADD2_Reset ((u16)0xFF01)
-
-/* I2C F/S mask */
-#define CCR_FS_Set ((u16)0x8000)
-
-/* I2C CCR mask */
-#define CCR_CCR_Set ((u16)0x0FFF)
-
-/* I2C FLAG mask */
-#define FLAG_Mask ((u32)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define ITEN_Mask ((u32)0x07000000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : I2C_DeInit
-* Description : Deinitializes the I2Cx peripheral registers to their default
-* reset values.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- switch (*(u32*)&I2Cx)
- {
- case I2C1_BASE:
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
- break;
-
- case I2C2_BASE:
- /* Enable I2C2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_Init
-* Description : Initializes the I2Cx peripheral according to the specified
-* parameters in the I2C_InitStruct.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
-* contains the configuration information for the specified
-* I2C peripheral.
-* Output : None
-* Return : None
-******************************************************************************/
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
- u16 tmpreg = 0, freqrange = 0;
- u16 result = 0x04;
- u32 pclk1 = 8000000;
- RCC_ClocksTypeDef rcc_clocks;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= CR2_FREQ_Reset;
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (u16)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= CR1_PE_Reset;
-
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
- /* Test if CCR value is under 0x1*/
- if ((result & CCR_CCR_Set) == 0)
- {
- /* Set minimum allowed value */
- result |= (u16)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= result | CCR_FS_Set;
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1);
- }
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
-
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= CR1_PE_Set;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/*******************************************************************************
-* Function Name : I2C_StructInit
-* Description : Fills each I2C_InitStruct member with its default value.
-* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
-
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
-
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
-
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
-
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
-}
-
-/*******************************************************************************
-* Function Name : I2C_Cmd
-* Description : Enables or disables the specified I2C peripheral.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2Cx peripheral. This parameter
-* can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= CR1_PE_Set;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= CR1_PE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_DMACmd
-* Description : Enables or disables the specified I2C DMA requests.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C DMA transfer.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= CR2_DMAEN_Set;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= CR2_DMAEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_DMALastTransferCmd
-* Description : Specifies that the next DMA transfer is the last one.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C DMA last transfer.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= CR2_LAST_Set;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= CR2_LAST_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_GenerateSTART
-* Description : Generates I2Cx communication START condition.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C START condition generation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None.
-*******************************************************************************/
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= CR1_START_Set;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= CR1_START_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_GenerateSTOP
-* Description : Generates I2Cx communication STOP condition.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C STOP condition generation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None.
-*******************************************************************************/
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= CR1_STOP_Set;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= CR1_STOP_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_AcknowledgeConfig
-* Description : Enables or disables the specified I2C acknowledge feature.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C Acknowledgement.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None.
-*******************************************************************************/
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= CR1_ACK_Set;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= CR1_ACK_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_OwnAddress2Config
-* Description : Configures the specified I2C own address2.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - Address: specifies the 7bit I2C own address2.
-* Output : None
-* Return : None.
-*******************************************************************************/
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address)
-{
- u16 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= OAR2_ADD2_Reset;
- /* Set I2Cx Own address2 */
- tmpreg |= (u16)(Address & (u16)0x00FE);
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : I2C_DualAddressCmd
-* Description : Enables or disables the specified I2C dual addressing mode.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C dual addressing mode.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= OAR2_ENDUAL_Set;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_GeneralCallCmd
-* Description : Enables or disables the specified I2C general call feature.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C General call.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable generall call */
- I2Cx->CR1 |= CR1_ENGC_Set;
- }
- else
- {
- /* Disable generall call */
- I2Cx->CR1 &= CR1_ENGC_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_ITConfig
-* Description : Enables or disables the specified I2C interrupts.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_IT: specifies the I2C interrupts sources to be enabled
-* or disabled.
-* This parameter can be any combination of the following values:
-* - I2C_IT_BUF: Buffer interrupt mask
-* - I2C_IT_EVT: Event interrupt mask
-* - I2C_IT_ERR: Error interrupt mask
-* - NewState: new state of the specified I2C interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (u16)~I2C_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_SendData
-* Description : Sends a data byte through the I2Cx peripheral.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - Data: Byte to be transmitted..
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/*******************************************************************************
-* Function Name : I2C_ReceiveData
-* Description : Returns the most recent received data by the I2Cx peripheral.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* Output : None
-* Return : The value of the received data.
-*******************************************************************************/
-u8 I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the data in the DR register */
- return (u8)I2Cx->DR;
-}
-
-/*******************************************************************************
-* Function Name : I2C_Send7bitAddress
-* Description : Transmits the address byte to select the slave device.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - Address: specifies the slave address which will be transmitted
-* - I2C_Direction: specifies whether the I2C device will be a
-* Transmitter or a Receiver.
-* This parameter can be one of the following values
-* - I2C_Direction_Transmitter: Transmitter mode
-* - I2C_Direction_Receiver: Receiver mode
-* Output : None
-* Return : None.
-*******************************************************************************/
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
-
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= OAR1_ADD0_Set;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= OAR1_ADD0_Reset;
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/*******************************************************************************
-* Function Name : I2C_ReadRegister
-* Description : Reads the specified I2C register and returns its value.
-* Input1 : - I2C_Register: specifies the register to read.
-* This parameter can be one of the following values:
-* - I2C_Register_CR1: CR1 register.
-* - I2C_Register_CR2: CR2 register.
-* - I2C_Register_OAR1: OAR1 register.
-* - I2C_Register_OAR2: OAR2 register.
-* - I2C_Register_DR: DR register.
-* - I2C_Register_SR1: SR1 register.
-* - I2C_Register_SR2: SR2 register.
-* - I2C_Register_CCR: CCR register.
-* - I2C_Register_TRISE: TRISE register.
-* Output : None
-* Return : The value of the read register.
-*******************************************************************************/
-u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- /* Return the selected register value */
- return (*(vu16 *)(*((vu32 *)&I2Cx) + I2C_Register));
-}
-
-/*******************************************************************************
-* Function Name : I2C_SoftwareResetCmd
-* Description : Enables or disables the specified I2C software reset.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C software reset.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= CR1_SWRST_Set;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= CR1_SWRST_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_SMBusAlertConfig
-* Description : Drives the SMBusAlert pin high or low for the specified I2C.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_SMBusAlert: specifies SMBAlert pin level.
-* This parameter can be one of the following values:
-* - I2C_SMBusAlert_Low: SMBAlert pin driven low
-* - I2C_SMBusAlert_High: SMBAlert pin driven high
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
-
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_TransmitPEC
-* Description : Enables or disables the specified I2C PEC transfer.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2C PEC transmission.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= CR1_PEC_Set;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= CR1_PEC_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_PECPositionConfig
-* Description : Selects the specified I2C PEC position.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_PECPosition: specifies the PEC position.
-* This parameter can be one of the following values:
-* - I2C_PECPosition_Next: indicates that the next
-* byte is PEC
-* - I2C_PECPosition_Current: indicates that current
-* byte is PEC
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
-
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_CalculatePEC
-* Description : Enables or disables the PEC value calculation of the
-* transfered bytes.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2Cx PEC value calculation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= CR1_ENPEC_Set;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= CR1_ENPEC_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_GetPEC
-* Description : Returns the PEC value for the specified I2C.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* Output : None
-* Return : The PEC value.
-*******************************************************************************/
-u8 I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/*******************************************************************************
-* Function Name : I2C_ARPCmd
-* Description : Enables or disables the specified I2C ARP.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2Cx ARP.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= CR1_ENARP_Set;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= CR1_ENARP_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_StretchClockCmd
-* Description : Enables or disables the specified I2C Clock stretching.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - NewState: new state of the I2Cx Clock stretching.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= CR1_NOSTRETCH_Set;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_FastModeDutyCycleConfig
-* Description : Selects the specified I2C fast mode duty cycle.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_DutyCycle: specifies the fast mode duty cycle.
-* This parameter can be one of the following values:
-* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
-* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
-
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2C_GetLastEvent
-* Description : Returns the last I2Cx Event.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* Output : None
-* Return : The last event
-*******************************************************************************/
-u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- u32 lastevent = 0;
- u32 flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_Mask;
-
- /* Return status */
- return lastevent;
-}
-
-/*******************************************************************************
-* Function Name : I2C_CheckEvent
-* Description : Checks whether the last I2Cx Event is equal to the one passed
-* as parameter.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_EVENT: specifies the event to be checked.
-* This parameter can be one of the following values:
-* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1
-* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
-* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
-* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2
-* - I2C_EVENT_MASTER_MODE_SELECT : EV5
-* - I2C_EVENT_MASTER_MODE_SELECTED : EV6
-* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
-* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
-* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
-* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4
-* Output : None
-* Return : An ErrorStatus enumuration value:
-* - SUCCESS: Last event is equal to the I2C_EVENT
-* - ERROR: Last event is different from the I2C_EVENT
-*******************************************************************************/
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT)
-{
- u32 lastevent = 0;
- u32 flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_Mask;
-
- /* Check whether the last event is equal to I2C_EVENT */
- if (lastevent == I2C_EVENT )
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
-
- /* Return status */
- return status;
-}
-
-/*******************************************************************************
-* Function Name : I2C_GetFlagStatus
-* Description : Checks whether the specified I2C flag is set or not.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - I2C_FLAG_DUALF: Dual flag (Slave mode)
-* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
-* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
-* - I2C_FLAG_GENCALL: General call header flag (Slave mode)
-* - I2C_FLAG_TRA: Transmitter/Receiver flag
-* - I2C_FLAG_BUSY: Bus busy flag
-* - I2C_FLAG_MSL: Master/Slave flag
-* - I2C_FLAG_SMBALERT: SMBus Alert flag
-* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-* - I2C_FLAG_PECERR: PEC error in reception flag
-* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-* - I2C_FLAG_AF: Acknowledge failure flag
-* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-* - I2C_FLAG_BERR: Bus error flag
-* - I2C_FLAG_TXE: Data register empty flag (Transmitter)
-* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag
-* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)
-* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
-* - I2C_FLAG_BTF: Byte transfer finished flag
-* - I2C_FLAG_ADDR: Address sent flag (Master mode) 'ADSL'
-* Address matched flag (Slave mode)'ENDAD'
-* - I2C_FLAG_SB: Start bit flag (Master mode)
-* Output : None
-* Return : The new state of I2C_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- u32 i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (*(u32*)&(I2Cx));
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_Mask;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (u32)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(vu32 *)i2cxbase) & I2C_FLAG) != (u32)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : I2C_ClearFlag
-* Description : Clears the I2Cx's pending flags.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_FLAG: specifies the flag to clear.
-* This parameter can be any combination of the following
-* values:
-* - I2C_FLAG_SMBALERT: SMBus Alert flag
-* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-* - I2C_FLAG_PECERR: PEC error in reception flag
-* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-* - I2C_FLAG_AF: Acknowledge failure flag
-* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-* - I2C_FLAG_BERR: Bus error flag
-*
-* Notes:
-* - STOPF (STOP detection) is cleared by software
-* sequence: a read operation to I2C_SR1 register
-* (I2C_GetFlagStatus()) followed by a write operation
-* to I2C_CR1 register (I2C_Cmd() to re-enable the
-* I2C peripheral).
-* - ADD10 (10-bit header sent) is cleared by software
-* sequence: a read operation to I2C_SR1
-* (I2C_GetFlagStatus()) followed by writing the
-* second byte of the address in DR register.
-* - BTF (Byte Transfer Finished) is cleared by software
-* sequence: a read operation to I2C_SR1 register
-* (I2C_GetFlagStatus()) followed by a read/write to
-* I2C_DR register (I2C_SendData()).
-* - ADDR (Address sent) is cleared by software sequence:
-* a read operation to I2C_SR1 register
-* (I2C_GetFlagStatus()) followed by a read operation to
-* I2C_SR2 register ((void)(I2Cx->SR2)).
-* - SB (Start Bit) is cleared software sequence: a read
-* operation to I2C_SR1 register (I2C_GetFlagStatus())
-* followed by a write operation to I2C_DR reigister
-* (I2C_SendData()).
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG)
-{
- u32 flagpos = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_Mask;
-
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (u16)~flagpos;
-}
-
-/*******************************************************************************
-* Function Name : I2C_GetITStatus
-* Description : Checks whether the specified I2C interrupt has occurred or not.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_IT: specifies the interrupt source to check.
-* This parameter can be one of the following values:
-* - I2C_IT_SMBALERT: SMBus Alert flag
-* - I2C_IT_TIMEOUT: Timeout or Tlow error flag
-* - I2C_IT_PECERR: PEC error in reception flag
-* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
-* - I2C_IT_AF: Acknowledge failure flag
-* - I2C_IT_ARLO: Arbitration lost flag (Master mode)
-* - I2C_IT_BERR: Bus error flag
-* - I2C_IT_TXE: Data register empty flag (Transmitter)
-* - I2C_IT_RXNE: Data register not empty (Receiver) flag
-* - I2C_IT_STOPF: Stop detection flag (Slave mode)
-* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)
-* - I2C_IT_BTF: Byte transfer finished flag
-* - I2C_IT_ADDR: Address sent flag (Master mode) 'ADSL'
-* Address matched flag (Slave mode)'ENDAD'
-* - I2C_IT_SB: Start bit flag (Master mode)
-* Output : None
-* Return : The new state of I2C_IT (SET or RESET).
-*******************************************************************************/
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT)
-{
- ITStatus bitstatus = RESET;
- u32 enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (u32)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_Mask;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (u32)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : I2C_ClearITPendingBit
-* Description : Clears the I2Cx's interrupt pending bits.
-* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-* - I2C_IT: specifies the interrupt pending bit to clear.
-* This parameter can be any combination of the following
-* values:
-* - I2C_IT_SMBALERT: SMBus Alert interrupt
-* - I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
-* - I2C_IT_PECERR: PEC error in reception interrupt
-* - I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
-* - I2C_IT_AF: Acknowledge failure interrupt
-* - I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
-* - I2C_IT_BERR: Bus error interrupt
-*
-* Notes:
-* - STOPF (STOP detection) is cleared by software
-* sequence: a read operation to I2C_SR1 register
-* (I2C_GetITStatus()) followed by a write operation to
-* I2C_CR1 register (I2C_Cmd() to re-enable the I2C
-* peripheral).
-* - ADD10 (10-bit header sent) is cleared by software
-* sequence: a read operation to I2C_SR1
-* (I2C_GetITStatus()) followed by writing the second
-* byte of the address in I2C_DR register.
-* - BTF (Byte Transfer Finished) is cleared by software
-* sequence: a read operation to I2C_SR1 register
-* (I2C_GetITStatus()) followed by a read/write to
-* I2C_DR register (I2C_SendData()).
-* - ADDR (Address sent) is cleared by software sequence:
-* a read operation to I2C_SR1 register (I2C_GetITStatus())
-* followed by a read operation to I2C_SR2 register
-* ((void)(I2Cx->SR2)).
-* - SB (Start Bit) is cleared by software sequence: a
-* read operation to I2C_SR1 register (I2C_GetITStatus())
-* followed by a write operation to I2C_DR reigister
-* (I2C_SendData()).
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT)
-{
- u32 flagpos = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_Mask;
-
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (u16)~flagpos;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the I2C firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @defgroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CR1_PE_Set ((uint16_t)0x0001)
+#define CR1_PE_Reset ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CR1_START_Set ((uint16_t)0x0100)
+#define CR1_START_Reset ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set ((uint16_t)0x0200)
+#define CR1_STOP_Reset ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set ((uint16_t)0x0400)
+#define CR1_ACK_Reset ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set ((uint16_t)0x0040)
+#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set ((uint16_t)0x8000)
+#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set ((uint16_t)0x1000)
+#define CR1_PEC_Reset ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set ((uint16_t)0x0020)
+#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set ((uint16_t)0x0010)
+#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
+#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set ((uint16_t)0x0800)
+#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set ((uint16_t)0x1000)
+#define CR2_LAST_Reset ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set ((uint16_t)0x0001)
+#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
+#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CCR_FS_Set ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+ * contains the configuration information for the specified I2C peripheral.
+ * @retval None
+ */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+ uint16_t tmpreg = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksTypeDef rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpreg &= CR2_FREQ_Reset;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreq(&rcc_clocks);
+ pclk1 = rcc_clocks.PCLK1_Frequency;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpreg |= freqrange;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TRISE */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ /* Reset tmpreg value */
+ /* Clear F/S, DUTY and CCR[11:0] bits */
+ tmpreg = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+ /* Test if CCR value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpreg |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+ {
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+ }
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_DutyCycle_16_9;
+ }
+
+ /* Test if CCR value is under 0x1*/
+ if ((result & CCR_CCR_Set) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpreg |= (uint16_t)(result | CCR_FS_Set);
+ /* Set Maximum Rise Time for fast mode */
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+
+ /* Write to I2Cx CCR */
+ I2Cx->CCR = tmpreg;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+ /* Set ACK bit according to I2C_Ack value */
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the I2C_ClockSpeed member */
+ I2C_InitStruct->I2C_ClockSpeed = 5000;
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+ /* Initialize the I2C_DutyCycle member */
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR2 |= CR2_DMAEN_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR2 &= CR2_DMAEN_Reset;
+ }
+}
+
+/**
+ * @brief Specifies that the next DMA transfer is the last one.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CR2 |= CR2_LAST_Set;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CR2 &= CR2_LAST_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR1 |= CR1_START_Set;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR1 &= CR1_START_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR1 |= CR1_STOP_Set;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR1 &= CR1_STOP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CR1 &= CR1_ACK_Reset;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the 7bit I2C own address2.
+ * @retval None.
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpreg &= OAR2_ADD2_Reset;
+
+ /* Set I2Cx Own address2 */
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CR1 |= CR1_ENGC_Set;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CR1 &= CR1_ENGC_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt mask
+ * @arg I2C_IT_EVT: Event interrupt mask
+ * @arg I2C_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data: Byte to be transmitted..
+ * @retval None
+ */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Write in the DR register the data to be sent */
+ I2Cx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the data in the DR register */
+ return (uint8_t)I2Cx->DR;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address which will be transmitted
+ * @param I2C_Direction: specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_Direction_Transmitter: Transmitter mode
+ * @arg I2C_Direction_Receiver: Receiver mode
+ * @retval None.
+ */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_Direction_Transmitter)
+ {
+ /* Set the address bit0 for read */
+ Address |= OAR1_ADD0_Set;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OAR1_ADD0_Reset;
+ }
+ /* Send the address */
+ I2Cx->DR = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2C_Register: specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_Register_CR1: CR1 register.
+ * @arg I2C_Register_CR2: CR2 register.
+ * @arg I2C_Register_OAR1: OAR1 register.
+ * @arg I2C_Register_OAR2: OAR2 register.
+ * @arg I2C_Register_DR: DR register.
+ * @arg I2C_Register_SR1: SR1 register.
+ * @arg I2C_Register_SR2: SR2 register.
+ * @arg I2C_Register_CCR: CCR register.
+ * @arg I2C_Register_TRISE: TRISE register.
+ * @retval The value of the read register.
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_REGISTER(I2C_Register));
+
+ tmp = (uint32_t) I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CR1 |= CR1_SWRST_Set;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CR1 &= CR1_SWRST_Reset;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+ * @retval None
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CR1 &= I2C_SMBusAlert_High;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CR1 |= CR1_PEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CR1 &= CR1_PEC_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition: specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC
+ * @retval None
+ */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PECPosition_Next)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CR1 |= I2C_PECPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CR1 &= I2C_PECPosition_Current;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transfered bytes.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CR1 |= CR1_ENPEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CR1 &= CR1_ENPEC_Reset;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->SR2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CR1 |= CR1_ENARP_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CR1 &= CR1_ENARP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+ * @retval None
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CCR &= I2C_DutyCycle_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CCR |= I2C_DutyCycle_16_9;
+ }
+}
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT: specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
+ * @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
+ * @retval An ErrorStatus enumuration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVENT(I2C_EVENT));
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+ /* Check whether the last event is equal to I2C_EVENT */
+ if (lastevent == I2C_EVENT )
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL”
+ * Address matched flag (Slave mode)”ENDAD”
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_Mask;
+
+ if(i2creg != 0)
+ {
+ /* Get the I2Cx SR1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx SR2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx SR2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
+ * second byte of the address in DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+ * register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_IT_PECERR: PEC error in reception flag
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure flag
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_IT_BERR: Bus error flag
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_IT_BTF: Byte transfer finished flag
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL”
+ * Address matched flag (Slave mode)”ENDAD”
+ * @arg I2C_IT_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_IT(I2C_IT));
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_Mask;
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx’s interrupt pending bits.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure interrupt
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+ * @arg I2C_IT_BERR: Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
+ * byte of the address in I2C_DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_DR register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_iwdg.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_iwdg.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_iwdg.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,148 +1,189 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_iwdg.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the IWDG firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_iwdg.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- IWDG registers bit mask ------------------------ */
-/* KR register bit mask */
-#define KR_KEY_Reload ((u16)0xAAAA)
-#define KR_KEY_Enable ((u16)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : IWDG_WriteAccessCmd
-* Description : Enables or disables write access to IWDG_PR and IWDG_RLR
-* registers.
-* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and
-* IWDG_RLR registers.
-* This parameter can be one of the following values:
-* - IWDG_WriteAccess_Enable: Enable write access to
-* IWDG_PR and IWDG_RLR registers
-* - IWDG_WriteAccess_Disable: Disable write access to
-* IWDG_PR and IWDG_RLR registers
-* Output : None
-* Return : None
-*******************************************************************************/
-void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
-
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/*******************************************************************************
-* Function Name : IWDG_SetPrescaler
-* Description : Sets IWDG Prescaler value.
-* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.
-* This parameter can be one of the following values:
-* - IWDG_Prescaler_4: IWDG prescaler set to 4
-* - IWDG_Prescaler_8: IWDG prescaler set to 8
-* - IWDG_Prescaler_16: IWDG prescaler set to 16
-* - IWDG_Prescaler_32: IWDG prescaler set to 32
-* - IWDG_Prescaler_64: IWDG prescaler set to 64
-* - IWDG_Prescaler_128: IWDG prescaler set to 128
-* - IWDG_Prescaler_256: IWDG prescaler set to 256
-* Output : None
-* Return : None
-*******************************************************************************/
-void IWDG_SetPrescaler(u8 IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
-
- IWDG->PR = IWDG_Prescaler;
-}
-
-/*******************************************************************************
-* Function Name : IWDG_SetReload
-* Description : Sets IWDG Reload value.
-* Input : - Reload: specifies the IWDG Reload value.
-* This parameter must be a number between 0 and 0x0FFF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void IWDG_SetReload(u16 Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
-
- IWDG->RLR = Reload;
-}
-
-/*******************************************************************************
-* Function Name : IWDG_ReloadCounter
-* Description : Reloads IWDG counter with value defined in the reload register
-* (write access to IWDG_PR and IWDG_RLR registers disabled).
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_Reload;
-}
-
-/*******************************************************************************
-* Function Name : IWDG_Enable
-* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
-* disabled).
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_Enable;
-}
-
-/*******************************************************************************
-* Function Name : IWDG_GetFlagStatus
-* Description : Checks whether the specified IWDG flag is set or not.
-* Input : - IWDG_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - IWDG_FLAG_PVU: Prescaler Value Update on going
-* - IWDG_FLAG_RVU: Reload Value Update on going
-* Output : None
-* Return : The new state of IWDG_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
-
- if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- /* Return the flag status */
- return bitstatus;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the IWDG firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @defgroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload ((uint16_t)0xAAAA)
+#define KR_KEY_Enable ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+ * @retval None
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+ * @retval None
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload: specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ * @retval None
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RLR = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going
+ * @retval The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_lib.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_lib.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_lib.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,303 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_lib.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all peripherals pointers initialization.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-#define EXT
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_lib.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#ifdef DEBUG
-/*******************************************************************************
-* Function Name : debug
-* Description : This function initialize peripherals pointers.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void debug(void)
-{
-
-/************************************* ADC ************************************/
-#ifdef _ADC1
- ADC1 = (ADC_TypeDef *) ADC1_BASE;
-#endif /*_ADC1 */
-
-#ifdef _ADC2
- ADC2 = (ADC_TypeDef *) ADC2_BASE;
-#endif /*_ADC2 */
-
-#ifdef _ADC3
- ADC3 = (ADC_TypeDef *) ADC3_BASE;
-#endif /*_ADC3 */
-
-/************************************* BKP ************************************/
-#ifdef _BKP
- BKP = (BKP_TypeDef *) BKP_BASE;
-#endif /*_BKP */
-
-/************************************* CAN ************************************/
-#ifdef _CAN
- CAN = (CAN_TypeDef *) CAN_BASE;
-#endif /*_CAN */
-
-/************************************* CRC ************************************/
-#ifdef _CRC
- CRC = (CRC_TypeDef *) CRC_BASE;
-#endif /*_CRC */
-
-/************************************* DAC ************************************/
-#ifdef _DAC
- DAC = (DAC_TypeDef *) DAC_BASE;
-#endif /*_DAC */
-
-/************************************* DBGMCU**********************************/
-#ifdef _DBGMCU
- DBGMCU = (DBGMCU_TypeDef *) DBGMCU_BASE;
-#endif /*_DBGMCU */
-
-/************************************* DMA ************************************/
-#ifdef _DMA
- DMA1 = (DMA_TypeDef *) DMA1_BASE;
- DMA2 = (DMA_TypeDef *) DMA2_BASE;
-#endif /*_DMA */
-
-#ifdef _DMA1_Channel1
- DMA1_Channel1 = (DMA_Channel_TypeDef *) DMA1_Channel1_BASE;
-#endif /*_DMA1_Channel1 */
-
-#ifdef _DMA1_Channel2
- DMA1_Channel2 = (DMA_Channel_TypeDef *) DMA1_Channel2_BASE;
-#endif /*_DMA1_Channel2 */
-
-#ifdef _DMA1_Channel3
- DMA1_Channel3 = (DMA_Channel_TypeDef *) DMA1_Channel3_BASE;
-#endif /*_DMA1_Channel3 */
-
-#ifdef _DMA1_Channel4
- DMA1_Channel4 = (DMA_Channel_TypeDef *) DMA1_Channel4_BASE;
-#endif /*_DMA1_Channel4 */
-
-#ifdef _DMA1_Channel5
- DMA1_Channel5 = (DMA_Channel_TypeDef *) DMA1_Channel5_BASE;
-#endif /*_DMA1_Channel5 */
-
-#ifdef _DMA1_Channel6
- DMA1_Channel6 = (DMA_Channel_TypeDef *) DMA1_Channel6_BASE;
-#endif /*_DMA1_Channel6 */
-
-#ifdef _DMA1_Channel7
- DMA1_Channel7 = (DMA_Channel_TypeDef *) DMA1_Channel7_BASE;
-#endif /*_DMA1_Channel7 */
-
-#ifdef _DMA2_Channel1
- DMA2_Channel1 = (DMA_Channel_TypeDef *) DMA2_Channel1_BASE;
-#endif /*_DMA2_Channel1 */
-
-#ifdef _DMA2_Channel2
- DMA2_Channel2 = (DMA_Channel_TypeDef *) DMA2_Channel2_BASE;
-#endif /*_DMA2_Channel2 */
-
-#ifdef _DMA2_Channel3
- DMA2_Channel3 = (DMA_Channel_TypeDef *) DMA2_Channel3_BASE;
-#endif /*_DMA2_Channel3 */
-
-#ifdef _DMA2_Channel4
- DMA2_Channel4 = (DMA_Channel_TypeDef *) DMA2_Channel4_BASE;
-#endif /*_DMA2_Channel4 */
-
-#ifdef _DMA2_Channel5
- DMA2_Channel5 = (DMA_Channel_TypeDef *) DMA2_Channel5_BASE;
-#endif /*_DMA2_Channel5 */
-
-/************************************* EXTI ***********************************/
-#ifdef _EXTI
- EXTI = (EXTI_TypeDef *) EXTI_BASE;
-#endif /*_EXTI */
-
-/************************************* FLASH and Option Bytes *****************/
-#ifdef _FLASH
- FLASH = (FLASH_TypeDef *) FLASH_R_BASE;
- OB = (OB_TypeDef *) OB_BASE;
-#endif /*_FLASH */
-
-/************************************* FSMC ***********************************/
-#ifdef _FSMC
- FSMC_Bank1 = (FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE;
- FSMC_Bank1E = (FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE;
- FSMC_Bank2 = (FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE;
- FSMC_Bank3 = (FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE;
- FSMC_Bank4 = (FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE;
-#endif /*_FSMC */
-
-/************************************* GPIO ***********************************/
-#ifdef _GPIOA
- GPIOA = (GPIO_TypeDef *) GPIOA_BASE;
-#endif /*_GPIOA */
-
-#ifdef _GPIOB
- GPIOB = (GPIO_TypeDef *) GPIOB_BASE;
-#endif /*_GPIOB */
-
-#ifdef _GPIOC
- GPIOC = (GPIO_TypeDef *) GPIOC_BASE;
-#endif /*_GPIOC */
-
-#ifdef _GPIOD
- GPIOD = (GPIO_TypeDef *) GPIOD_BASE;
-#endif /*_GPIOD */
-
-#ifdef _GPIOE
- GPIOE = (GPIO_TypeDef *) GPIOE_BASE;
-#endif /*_GPIOE */
-
-#ifdef _GPIOF
- GPIOF = (GPIO_TypeDef *) GPIOF_BASE;
-#endif /*_GPIOF */
-
-#ifdef _GPIOG
- GPIOG = (GPIO_TypeDef *) GPIOG_BASE;
-#endif /*_GPIOG */
-
-#ifdef _AFIO
- AFIO = (AFIO_TypeDef *) AFIO_BASE;
-#endif /*_AFIO */
-
-/************************************* I2C ************************************/
-#ifdef _I2C1
- I2C1 = (I2C_TypeDef *) I2C1_BASE;
-#endif /*_I2C1 */
-
-#ifdef _I2C2
- I2C2 = (I2C_TypeDef *) I2C2_BASE;
-#endif /*_I2C2 */
-
-/************************************* IWDG ***********************************/
-#ifdef _IWDG
- IWDG = (IWDG_TypeDef *) IWDG_BASE;
-#endif /*_IWDG */
-
-/************************************* NVIC ***********************************/
-#ifdef _NVIC
- NVIC = (NVIC_TypeDef *) NVIC_BASE;
- SCB = (SCB_TypeDef *) SCB_BASE;
-#endif /*_NVIC */
-
-/************************************* PWR ************************************/
-#ifdef _PWR
- PWR = (PWR_TypeDef *) PWR_BASE;
-#endif /*_PWR */
-
-/************************************* RCC ************************************/
-#ifdef _RCC
- RCC = (RCC_TypeDef *) RCC_BASE;
-#endif /*_RCC */
-
-/************************************* RTC ************************************/
-#ifdef _RTC
- RTC = (RTC_TypeDef *) RTC_BASE;
-#endif /*_RTC */
-
-/************************************* SDIO ***********************************/
-#ifdef _SDIO
- SDIO = (SDIO_TypeDef *) SDIO_BASE;
-#endif /*_SDIO */
-
-/************************************* SPI ************************************/
-#ifdef _SPI1
- SPI1 = (SPI_TypeDef *) SPI1_BASE;
-#endif /*_SPI1 */
-
-#ifdef _SPI2
- SPI2 = (SPI_TypeDef *) SPI2_BASE;
-#endif /*_SPI2 */
-
-#ifdef _SPI3
- SPI3 = (SPI_TypeDef *) SPI3_BASE;
-#endif /*_SPI3 */
-
-/************************************* SysTick ********************************/
-#ifdef _SysTick
- SysTick = (SysTick_TypeDef *) SysTick_BASE;
-#endif /*_SysTick */
-
-/************************************* TIM ************************************/
-#ifdef _TIM1
- TIM1 = (TIM_TypeDef *) TIM1_BASE;
-#endif /*_TIM1 */
-
-#ifdef _TIM2
- TIM2 = (TIM_TypeDef *) TIM2_BASE;
-#endif /*_TIM2 */
-
-#ifdef _TIM3
- TIM3 = (TIM_TypeDef *) TIM3_BASE;
-#endif /*_TIM3 */
-
-#ifdef _TIM4
- TIM4 = (TIM_TypeDef *) TIM4_BASE;
-#endif /*_TIM4 */
-
-#ifdef _TIM5
- TIM5 = (TIM_TypeDef *) TIM5_BASE;
-#endif /*_TIM5 */
-
-#ifdef _TIM6
- TIM6 = (TIM_TypeDef *) TIM6_BASE;
-#endif /*_TIM6 */
-
-#ifdef _TIM7
- TIM7 = (TIM_TypeDef *) TIM7_BASE;
-#endif /*_TIM7 */
-
-#ifdef _TIM8
- TIM8 = (TIM_TypeDef *) TIM8_BASE;
-#endif /*_TIM8 */
-
-/************************************* USART **********************************/
-#ifdef _USART1
- USART1 = (USART_TypeDef *) USART1_BASE;
-#endif /*_USART1 */
-
-#ifdef _USART2
- USART2 = (USART_TypeDef *) USART2_BASE;
-#endif /*_USART2 */
-
-#ifdef _USART3
- USART3 = (USART_TypeDef *) USART3_BASE;
-#endif /*_USART3 */
-
-#ifdef _UART4
- UART4 = (USART_TypeDef *) UART4_BASE;
-#endif /*_UART4 */
-
-#ifdef _UART5
- UART5 = (USART_TypeDef *) UART5_BASE;
-#endif /*_UART5 */
-
-/************************************* WWDG ***********************************/
-#ifdef _WWDG
- WWDG = (WWDG_TypeDef *) WWDG_BASE;
-#endif /*_WWDG */
-}
-#endif /* DEBUG*/
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_nvic.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_nvic.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_nvic.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,751 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_nvic.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the NVIC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_nvic.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : NVIC_DeInit
-* Description : Deinitializes the NVIC peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_DeInit(void)
-{
- u32 index = 0;
-
- NVIC->ICER[0] = 0xFFFFFFFF;
- NVIC->ICER[1] = 0x0FFFFFFF;
- NVIC->ICPR[0] = 0xFFFFFFFF;
- NVIC->ICPR[1] = 0x0FFFFFFF;
-
- for(index = 0; index < 0x0F; index++)
- {
- NVIC->IPR[index] = 0x00000000;
- }
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SCBDeInit
-* Description : Deinitializes the SCB peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SCBDeInit(void)
-{
- u32 index = 0x00;
-
- SCB->ICSR = 0x0A000000;
- SCB->VTOR = 0x00000000;
- SCB->AIRCR = AIRCR_VECTKEY_MASK;
- SCB->SCR = 0x00000000;
- SCB->CCR = 0x00000000;
- for(index = 0; index < 0x03; index++)
- {
- SCB->SHPR[index] = 0;
- }
- SCB->SHCSR = 0x00000000;
- SCB->CFSR = 0xFFFFFFFF;
- SCB->HFSR = 0xFFFFFFFF;
- SCB->DFSR = 0xFFFFFFFF;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_PriorityGroupConfig
-* Description : Configures the priority grouping: pre-emption priority
-* and subpriority.
-* Input : - NVIC_PriorityGroup: specifies the priority grouping bits
-* length. This parameter can be one of the following values:
-* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority
-* 4 bits for subpriority
-* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority
-* 3 bits for subpriority
-* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority
-* 2 bits for subpriority
-* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority
-* 1 bits for subpriority
-* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority
-* 0 bits for subpriority
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_Init
-* Description : Initializes the NVIC peripheral according to the specified
-* parameters in the NVIC_InitStruct.
-* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
-* that contains the configuration information for the
-* specified NVIC peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
- u32 tmppre = 0, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
-
- tmppriority = tmppriority << 0x04;
- tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
-
- tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
- tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
- tmpreg &= ~tmpmask;
- tmppriority &= tmpmask;
- tmpreg |= tmppriority;
-
- NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
- (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
- (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
- }
-}
-
-/*******************************************************************************
-* Function Name : NVIC_StructInit
-* Description : Fills each NVIC_InitStruct member with its default value.
-* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which
-* will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- /* NVIC_InitStruct members default value */
- NVIC_InitStruct->NVIC_IRQChannel = 0x00;
- NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
- NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
- NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SETPRIMASK
-* Description : Enables the PRIMASK priority: Raises the execution priority to 0.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SETPRIMASK(void)
-{
- __SETPRIMASK();
-}
-
-/*******************************************************************************
-* Function Name : NVIC_RESETPRIMASK
-* Description : Disables the PRIMASK priority.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_RESETPRIMASK(void)
-{
- __RESETPRIMASK();
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SETFAULTMASK
-* Description : Enables the FAULTMASK priority: Raises the execution priority to -1.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SETFAULTMASK(void)
-{
- __SETFAULTMASK();
-}
-
-/*******************************************************************************
-* Function Name : NVIC_RESETFAULTMASK
-* Description : Disables the FAULTMASK priority.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_RESETFAULTMASK(void)
-{
- __RESETFAULTMASK();
-}
-
-/*******************************************************************************
-* Function Name : NVIC_BASEPRICONFIG
-* Description : The execution priority can be changed from 15 (lowest
- configurable priority) to 1. Writing a zero value will disable
-* the mask of execution priority.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_BASEPRICONFIG(u32 NewPriority)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_BASE_PRI(NewPriority));
-
- __BASEPRICONFIG(NewPriority << 0x04);
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetBASEPRI
-* Description : Returns the BASEPRI mask value.
-* Input : None
-* Output : None
-* Return : BASEPRI register value
-*******************************************************************************/
-u32 NVIC_GetBASEPRI(void)
-{
- return (__GetBASEPRI());
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetCurrentPendingIRQChannel
-* Description : Returns the current pending IRQ channel identifier.
-* Input : None
-* Output : None
-* Return : Pending IRQ Channel Identifier.
-*******************************************************************************/
-u16 NVIC_GetCurrentPendingIRQChannel(void)
-{
- return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetIRQChannelPendingBitStatus
-* Description : Checks whether the specified IRQ Channel pending bit is set
-* or not.
-* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check.
-* Output : None
-* Return : The new state of IRQ Channel pending bit(SET or RESET).
-*******************************************************************************/
-ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
-{
- ITStatus pendingirqstatus = RESET;
- u32 tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
-
- tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
-
- if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
- {
- pendingirqstatus = SET;
- }
- else
- {
- pendingirqstatus = RESET;
- }
- return pendingirqstatus;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SetIRQChannelPendingBit
-* Description : Sets the NVIC's interrupt pending bit.
-* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
-
- *(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_ClearIRQChannelPendingBit
-* Description : Clears the NVIC's interrupt pending bit.
-* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
-
- NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetCurrentActiveHandler
-* Description : Returns the current active Handler (IRQ Channel and
-* SystemHandler) identifier.
-* Input : None
-* Output : None
-* Return : Active Handler Identifier.
-*******************************************************************************/
-u16 NVIC_GetCurrentActiveHandler(void)
-{
- return ((u16)(SCB->ICSR & (u32)0x3FF));
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetIRQChannelActiveBitStatus
-* Description : Checks whether the specified IRQ Channel active bit is set
-* or not.
-* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check.
-* Output : None
-* Return : The new state of IRQ Channel active bit(SET or RESET).
-*******************************************************************************/
-ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
-{
- ITStatus activeirqstatus = RESET;
- u32 tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
-
- tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
-
- if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
- {
- activeirqstatus = SET;
- }
- else
- {
- activeirqstatus = RESET;
- }
- return activeirqstatus;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetCPUID
-* Description : Returns the ID number, the version number and the implementation
-* details of the Cortex-M3 core.
-* Input : None
-* Output : None
-* Return : CPU ID.
-*******************************************************************************/
-u32 NVIC_GetCPUID(void)
-{
- return (SCB->CPUID);
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SetVectorTable
-* Description : Sets the vector table location and Offset.
-* Input : - NVIC_VectTab: specifies if the vector table is in RAM or
-* FLASH memory.
-* This parameter can be one of the following values:
-* - NVIC_VectTab_RAM
-* - NVIC_VectTab_FLASH
-* - Offset: Vector Table base offset field.
-* This value must be a multiple of 0x100.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GenerateSystemReset
-* Description : Generates a system reset.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_GenerateSystemReset(void)
-{
- SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GenerateCoreReset
-* Description : Generates a Core (Core + NVIC) reset.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_GenerateCoreReset(void)
-{
- SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SystemLPConfig
-* Description : Selects the condition for the system to enter low power mode.
-* Input : - LowPowerMode: Specifies the new mode for the system to enter
-* low power mode.
-* This parameter can be one of the following values:
-* - NVIC_LP_SEVONPEND
-* - NVIC_LP_SLEEPDEEP
-* - NVIC_LP_SLEEPONEXIT
-* - NewState: new state of LP condition.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (u32)(~(u32)LowPowerMode);
- }
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SystemHandlerConfig
-* Description : Enables or disables the specified System Handlers.
-* Input : - SystemHandler: specifies the system handler to be enabled
-* or disabled.
-* This parameter can be one of the following values:
-* - SystemHandler_MemoryManage
-* - SystemHandler_BusFault
-* - SystemHandler_UsageFault
-* - NewState: new state of specified System Handlers.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)
-{
- u32 tmpreg = 0x00;
-
- /* Check the parameters */
- assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);
-
- if (NewState != DISABLE)
- {
- SCB->SHCSR |= tmpreg;
- }
- else
- {
- SCB->SHCSR &= ~tmpreg;
- }
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SystemHandlerPriorityConfig
-* Description : Configures the specified System Handlers priority.
-* Input : - SystemHandler: specifies the system handler to be
-* enabled or disabled.
-* This parameter can be one of the following values:
-* - SystemHandler_MemoryManage
-* - SystemHandler_BusFault
-* - SystemHandler_UsageFault
-* - SystemHandler_SVCall
-* - SystemHandler_DebugMonitor
-* - SystemHandler_PSV
-* - SystemHandler_SysTick
-* - SystemHandlerPreemptionPriority: new priority group of the
-* specified system handlers.
-* - SystemHandlerSubPriority: new sub priority of the specified
-* system handlers.
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
- u8 SystemHandlerSubPriority)
-{
- u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;
- u32 tmppriority = 0x00;
-
- /* Check the parameters */
- assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));
-
- tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
- tmp1 = (0x4 - tmppriority);
- tmp2 = tmp2 >> tmppriority;
-
- tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;
- tmppriority |= SystemHandlerSubPriority & tmp2;
-
- tmppriority = tmppriority << 0x04;
- tmp1 = SystemHandler & (u32)0xC0;
- tmp1 = tmp1 >> 0x06;
- tmp2 = (SystemHandler >> 0x08) & (u32)0x03;
- tmppriority = tmppriority << (tmp2 * 0x08);
- handlermask = (u32)0xFF << (tmp2 * 0x08);
-
- SCB->SHPR[tmp1] &= ~handlermask;
- SCB->SHPR[tmp1] |= tmppriority;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetSystemHandlerPendingBitStatus
-* Description : Checks whether the specified System handlers pending bit is
-* set or not.
-* Input : - SystemHandler: specifies the system handler pending bit to
-* check.
-* This parameter can be one of the following values:
-* - SystemHandler_MemoryManage
-* - SystemHandler_BusFault
-* - SystemHandler_SVCall
-* Output : None
-* Return : The new state of System Handler pending bit(SET or RESET).
-*******************************************************************************/
-ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)
-{
- ITStatus bitstatus = RESET;
- u32 tmp = 0x00, tmppos = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));
-
- tmppos = (SystemHandler >> 0x0A);
- tmppos &= (u32)0x0F;
-
- tmppos = (u32)0x01 << tmppos;
-
- tmp = SCB->SHCSR & tmppos;
-
- if (tmp == tmppos)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_SetSystemHandlerPendingBit
-* Description : Sets System Handler pending bit.
-* Input : - SystemHandler: specifies the system handler pending bit
-* to be set.
-* This parameter can be one of the following values:
-* - SystemHandler_NMI
-* - SystemHandler_PSV
-* - SystemHandler_SysTick
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)
-{
- u32 tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));
-
- /* Get the System Handler pending bit position */
- tmp = SystemHandler & (u32)0x1F;
- /* Set the corresponding System Handler pending bit */
- SCB->ICSR |= ((u32)0x01 << tmp);
-}
-
-/*******************************************************************************
-* Function Name : NVIC_ClearSystemHandlerPendingBit
-* Description : Clears System Handler pending bit.
-* Input : - SystemHandler: specifies the system handler pending bit to
-* be clear.
-* This parameter can be one of the following values:
-* - SystemHandler_PSV
-* - SystemHandler_SysTick
-* Output : None
-* Return : None
-*******************************************************************************/
-void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)
-{
- u32 tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));
-
- /* Get the System Handler pending bit position */
- tmp = SystemHandler & (u32)0x1F;
- /* Clear the corresponding System Handler pending bit */
- SCB->ICSR |= ((u32)0x01 << (tmp - 0x01));
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetSystemHandlerActiveBitStatus
-* Description : Checks whether the specified System handlers active bit is
-* set or not.
-* Input : - SystemHandler: specifies the system handler active bit to
-* check.
-* This parameter can be one of the following values:
-* - SystemHandler_MemoryManage
-* - SystemHandler_BusFault
-* - SystemHandler_UsageFault
-* - SystemHandler_SVCall
-* - SystemHandler_DebugMonitor
-* - SystemHandler_PSV
-* - SystemHandler_SysTick
-* Output : None
-* Return : The new state of System Handler active bit(SET or RESET).
-*******************************************************************************/
-ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)
-{
- ITStatus bitstatus = RESET;
-
- u32 tmp = 0x00, tmppos = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));
-
- tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;
-
- tmppos = (u32)0x01 << tmppos;
-
- tmp = SCB->SHCSR & tmppos;
-
- if (tmp == tmppos)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetFaultHandlerSources
-* Description : Returns the system fault handlers sources.
-* Input : - SystemHandler: specifies the system handler to get its fault
-* sources.
-* This parameter can be one of the following values:
-* - SystemHandler_HardFault
-* - SystemHandler_MemoryManage
-* - SystemHandler_BusFault
-* - SystemHandler_UsageFault
-* - SystemHandler_DebugMonitor
-* Output : None
-* Return : Source of the fault handler.
-*******************************************************************************/
-u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)
-{
- u32 faultsources = 0x00;
- u32 tmpreg = 0x00, tmppos = 0x00;
-
- /* Check the parameters */
- assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));
-
- tmpreg = (SystemHandler >> 0x12) & (u32)0x03;
- tmppos = (SystemHandler >> 0x14) & (u32)0x03;
-
- if (tmpreg == 0x00)
- {
- faultsources = SCB->HFSR;
- }
- else if (tmpreg == 0x01)
- {
- faultsources = SCB->CFSR >> (tmppos * 0x08);
- if (tmppos != 0x02)
- {
- faultsources &= (u32)0x0F;
- }
- else
- {
- faultsources &= (u32)0xFF;
- }
- }
- else
- {
- faultsources = SCB->DFSR;
- }
- return faultsources;
-}
-
-/*******************************************************************************
-* Function Name : NVIC_GetFaultAddress
-* Description : Returns the address of the location that generated a fault
-* handler.
-* Input : - SystemHandler: specifies the system handler to get its
-* fault address.
-* This parameter can be one of the following values:
-* - SystemHandler_MemoryManage
-* - SystemHandler_BusFault
-* Output : None
-* Return : Fault address.
-*******************************************************************************/
-u32 NVIC_GetFaultAddress(u32 SystemHandler)
-{
- u32 faultaddress = 0x00;
- u32 tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));
-
- tmp = (SystemHandler >> 0x16) & (u32)0x01;
-
- if (tmp == 0x00)
- {
- faultaddress = SCB->MMFAR;
- }
- else
- {
- faultaddress = SCB->BFAR;
- }
- return faultaddress;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_pwr.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_pwr.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_pwr.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,280 +1,311 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_pwr.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the PWR firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-/* CR register bit mask */
-#define CR_PDDS_Set ((u32)0x00000002)
-#define CR_DS_Mask ((u32)0xFFFFFFFC)
-#define CR_CWUF_Set ((u32)0x00000004)
-#define CR_PLS_Mask ((u32)0xFFFFFF1F)
-
-/* --------- Cortex System Control register bit mask ---------------- */
-/* Cortex System Control register address */
-#define SCB_SysCtrl ((u32)0xE000ED10)
-/* SLEEPDEEP bit mask */
-#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : PWR_DeInit
-* Description : Deinitializes the PWR peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/*******************************************************************************
-* Function Name : PWR_BackupAccessCmd
-* Description : Enables or disables access to the RTC and backup registers.
-* Input : - NewState: new state of the access to the RTC and backup
-* registers. This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CR_DBP_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : PWR_PVDCmd
-* Description : Enables or disables the Power Voltage Detector(PVD).
-* Input : - NewState: new state of the PVD.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CR_PVDE_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : PWR_PVDLevelConfig
-* Description : Configures the voltage threshold detected by the Power Voltage
-* Detector(PVD).
-* Input : - PWR_PVDLevel: specifies the PVD detection level
-* This parameter can be one of the following values:
-* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
-* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
-* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
-* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
-* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
-* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
-* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
-* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_Mask;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : PWR_WakeUpPinCmd
-* Description : Enables or disables the WakeUp Pin functionality.
-* Input : - NewState: new state of the WakeUp Pin functionality.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CSR_EWUP_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : PWR_EnterSTOPMode
-* Description : Enters STOP mode.
-* Input : - PWR_Regulator: specifies the regulator state in STOP mode.
-* This parameter can be one of the following values:
-* - PWR_Regulator_ON: STOP mode with regulator ON
-* - PWR_Regulator_LowPower: STOP mode with
-* regulator in low power mode
-* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or
-* WFE instruction.
-* This parameter can be one of the following values:
-* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
-* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
-
- /* Clear PDDS and LPDS bits */
- tmpreg &= CR_DS_Mask;
-
- /* Set LPDS bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
-}
-
-/*******************************************************************************
-* Function Name : PWR_EnterSTANDBYMode
-* Description : Enters STANDBY mode.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wake-up flag */
- PWR->CR |= CR_CWUF_Set;
-
- /* Select STANDBY mode */
- PWR->CR |= CR_PDDS_Set;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
-
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/*******************************************************************************
-* Function Name : PWR_GetFlagStatus
-* Description : Checks whether the specified PWR flag is set or not.
-* Input : - PWR_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - PWR_FLAG_WU: Wake Up flag
-* - PWR_FLAG_SB: StandBy flag
-* - PWR_FLAG_PVDO: PVD Output
-* Output : None
-* Return : The new state of PWR_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- /* Return the flag status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : PWR_ClearFlag
-* Description : Clears the PWR's pending flags.
-* Input : - PWR_FLAG: specifies the flag to clear.
-* This parameter can be one of the following values:
-* - PWR_FLAG_WU: Wake Up flag
-* - PWR_FLAG_SB: StandBy flag
-* Output : None
-* Return : None
-*******************************************************************************/
-void PWR_ClearFlag(u32 PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the PWR firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @defgroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_PDDS_Set ((uint32_t)0x00000002)
+#define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
+#define CR_CWUF_Set ((uint32_t)0x00000004)
+#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F)
+
+/* --------- Cortex System Control register bit mask ---------------- */
+
+/* Cortex System Control register address */
+#define SCB_SysCtrl ((uint32_t)0xE000ED10)
+
+/* SLEEPDEEP bit mask */
+#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void PWR_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param NewState: new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param NewState: new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+ * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+ * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+ * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+ * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+ * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+ * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+ * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpreg = PWR->CR;
+ /* Clear PLS[7:5] bits */
+ tmpreg &= CR_PLS_Mask;
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+ tmpreg |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param NewState: new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= CR_DS_Mask;
+ /* Set LPDS bit according to PWR_Regulator value */
+ tmpreg |= PWR_Regulator;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @param None
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+ /* Clear Wake-up flag */
+ PWR->CR |= CR_CWUF_Set;
+ /* Select STANDBY mode */
+ PWR->CR |= CR_PDDS_Set;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @arg PWR_FLAG_PVDO: PVD Output
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @retval None
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CR |= PWR_FLAG << 2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rcc.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rcc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rcc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,1105 +1,1447 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_rcc.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the RCC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of USBPRE bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x04)
-#define USBPRE_BitNumber 0x16
-#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x20)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x24)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* CR register bit mask */
-#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
-#define CR_HSEBYP_Set ((u32)0x00040000)
-#define CR_HSEON_Reset ((u32)0xFFFEFFFF)
-#define CR_HSEON_Set ((u32)0x00010000)
-#define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
-
-/* CFGR register bit mask */
-#define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
-#define CFGR_PLLMull_Mask ((u32)0x003C0000)
-#define CFGR_PLLSRC_Mask ((u32)0x00010000)
-#define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
-#define CFGR_SWS_Mask ((u32)0x0000000C)
-#define CFGR_SW_Mask ((u32)0xFFFFFFFC)
-#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
-#define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
-#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
-#define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
-#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
-#define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
-#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
-#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
-
-/* CSR register bit mask */
-#define CSR_RMVF_Set ((u32)0x01000000)
-
-/* RCC Flag Mask */
-#define FLAG_Mask ((u8)0x1F)
-
-/* Typical Value of the HSI in Hz */
-#define HSI_Value ((u32)8000000)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((u32)0x40021009)
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((u32)0x4002100A)
-
-/* CFGR register byte 4 (Bits[31:24]) base address */
-#define CFGR_BYTE4_ADDRESS ((u32)0x40021007)
-
-/* BDCR register base address */
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
-
-#ifndef HSEStartUp_TimeOut
-/* Time out for HSE start up */
-#define HSEStartUp_TimeOut ((u16)0x0500)
-#endif
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : RCC_DeInit
-* Description : Resets the RCC clock configuration to the default reset state.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (u32)0x00000001;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
- RCC->CFGR &= (u32)0xF8FF0000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (u32)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (u32)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
- RCC->CFGR &= (u32)0xFF80FFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/*******************************************************************************
-* Function Name : RCC_HSEConfig
-* Description : Configures the External High Speed oscillator (HSE).
-* HSE can not be stopped if it is used directly or through the
-* PLL as system clock.
-* Input : - RCC_HSE: specifies the new state of the HSE.
-* This parameter can be one of the following values:
-* - RCC_HSE_OFF: HSE oscillator OFF
-* - RCC_HSE_ON: HSE oscillator ON
-* - RCC_HSE_Bypass: HSE oscillator bypassed with external
-* clock
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_HSEConfig(u32 RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- /* Reset HSEON bit */
- RCC->CR &= CR_HSEON_Reset;
-
- /* Reset HSEBYP bit */
- RCC->CR &= CR_HSEBYP_Reset;
-
- /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
- switch(RCC_HSE)
- {
- case RCC_HSE_ON:
- /* Set HSEON bit */
- RCC->CR |= CR_HSEON_Set;
- break;
-
- case RCC_HSE_Bypass:
- /* Set HSEBYP and HSEON bits */
- RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_WaitForHSEStartUp
-* Description : Waits for HSE start-up.
-* Input : None
-* Output : None
-* Return : An ErrorStatus enumuration value:
-* - SUCCESS: HSE oscillator is stable and ready to use
-* - ERROR: HSE oscillator not yet ready
-*******************************************************************************/
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- vu32 StartUpCounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus HSEStatus = RESET;
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- StartUpCounter++;
- } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
-
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/*******************************************************************************
-* Function Name : RCC_AdjustHSICalibrationValue
-* Description : Adjusts the Internal High Speed oscillator (HSI) calibration
-* value.
-* Input : - HSICalibrationValue: specifies the calibration trimming value.
-* This parameter must be a number between 0 and 0x1F.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= CR_HSITRIM_Mask;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (u32)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_HSICmd
-* Description : Enables or disables the Internal High Speed oscillator (HSI).
-* HSI can not be stopped if it is used directly or through the
-* PLL as system clock.
-* Input : - NewState: new state of the HSI.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CR_HSION_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : RCC_PLLConfig
-* Description : Configures the PLL clock source and multiplication factor.
-* This function must be used only when the PLL is disabled.
-* Input : - RCC_PLLSource: specifies the PLL entry clock source.
-* This parameter can be one of the following values:
-* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
-* by 2 selected as PLL clock entry
-* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
-* as PLL clock entry
-* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
-* by 2 selected as PLL clock entry
-* - RCC_PLLMul: specifies the PLL multiplication factor.
-* This parameter can be RCC_PLLMul_x where x:[2,16]
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- tmpreg &= CFGR_PLL_Mask;
-
- /* Set the PLL configuration bits */
- tmpreg |= RCC_PLLSource | RCC_PLLMul;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_PLLCmd
-* Description : Enables or disables the PLL.
-* The PLL can not be disabled if it is used as system clock.
-* Input : - NewState: new state of the PLL.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CR_PLLON_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : RCC_SYSCLKConfig
-* Description : Configures the system clock (SYSCLK).
-* Input : - RCC_SYSCLKSource: specifies the clock source used as system
-* clock. This parameter can be one of the following values:
-* - RCC_SYSCLKSource_HSI: HSI selected as system clock
-* - RCC_SYSCLKSource_HSE: HSE selected as system clock
-* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= CFGR_SW_Mask;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_GetSYSCLKSource
-* Description : Returns the clock source used as system clock.
-* Input : None
-* Output : None
-* Return : The clock source used as system clock. The returned value can
-* be one of the following:
-* - 0x00: HSI used as system clock
-* - 0x04: HSE used as system clock
-* - 0x08: PLL used as system clock
-*******************************************************************************/
-u8 RCC_GetSYSCLKSource(void)
-{
- return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
-}
-
-/*******************************************************************************
-* Function Name : RCC_HCLKConfig
-* Description : Configures the AHB clock (HCLK).
-* Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is
-* derived from the system clock (SYSCLK).
-* This parameter can be one of the following values:
-* - RCC_SYSCLK_Div1: AHB clock = SYSCLK
-* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
-* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
-* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
-* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
-* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
-* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
-* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
-* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_HCLKConfig(u32 RCC_SYSCLK)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= CFGR_HPRE_Reset_Mask;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_PCLK1Config
-* Description : Configures the Low Speed APB clock (PCLK1).
-* Input : - RCC_HCLK: defines the APB1 clock divider. This clock is
-* derived from the AHB clock (HCLK).
-* This parameter can be one of the following values:
-* - RCC_HCLK_Div1: APB1 clock = HCLK
-* - RCC_HCLK_Div2: APB1 clock = HCLK/2
-* - RCC_HCLK_Div4: APB1 clock = HCLK/4
-* - RCC_HCLK_Div8: APB1 clock = HCLK/8
-* - RCC_HCLK_Div16: APB1 clock = HCLK/16
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_PCLK1Config(u32 RCC_HCLK)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= CFGR_PPRE1_Reset_Mask;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_PCLK2Config
-* Description : Configures the High Speed APB clock (PCLK2).
-* Input : - RCC_HCLK: defines the APB2 clock divider. This clock is
-* derived from the AHB clock (HCLK).
-* This parameter can be one of the following values:
-* - RCC_HCLK_Div1: APB2 clock = HCLK
-* - RCC_HCLK_Div2: APB2 clock = HCLK/2
-* - RCC_HCLK_Div4: APB2 clock = HCLK/4
-* - RCC_HCLK_Div8: APB2 clock = HCLK/8
-* - RCC_HCLK_Div16: APB2 clock = HCLK/16
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_PCLK2Config(u32 RCC_HCLK)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= CFGR_PPRE2_Reset_Mask;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_ITConfig
-* Description : Enables or disables the specified RCC interrupts.
-* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
-* or disabled.
-* This parameter can be any combination of the following values:
-* - RCC_IT_LSIRDY: LSI ready interrupt
-* - RCC_IT_LSERDY: LSE ready interrupt
-* - RCC_IT_HSIRDY: HSI ready interrupt
-* - RCC_IT_HSERDY: HSE ready interrupt
-* - RCC_IT_PLLRDY: PLL ready interrupt
-* - NewState: new state of the specified RCC interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
- *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
- *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_USBCLKConfig
-* Description : Configures the USB clock (USBCLK).
-* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
-* is derived from the PLL output.
-* This parameter can be one of the following values:
-* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
-* selected as USB clock source
-* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
-* clock source
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
-
- *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
-}
-
-/*******************************************************************************
-* Function Name : RCC_ADCCLKConfig
-* Description : Configures the ADC clock (ADCCLK).
-* Input : - RCC_PCLK2: defines the ADC clock divider. This clock is
-* derived from the APB2 clock (PCLK2).
-* This parameter can be one of the following values:
-* - RCC_PCLK2_Div2: ADC clock = PCLK2/2
-* - RCC_PCLK2_Div4: ADC clock = PCLK2/4
-* - RCC_PCLK2_Div6: ADC clock = PCLK2/6
-* - RCC_PCLK2_Div8: ADC clock = PCLK2/8
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_ADCCLKConfig(u32 RCC_PCLK2)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
-
- tmpreg = RCC->CFGR;
-
- /* Clear ADCPRE[1:0] bits */
- tmpreg &= CFGR_ADCPRE_Reset_Mask;
-
- /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
- tmpreg |= RCC_PCLK2;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : RCC_LSEConfig
-* Description : Configures the External Low Speed oscillator (LSE).
-* Input : - RCC_LSE: specifies the new state of the LSE.
-* This parameter can be one of the following values:
-* - RCC_LSE_OFF: LSE oscillator OFF
-* - RCC_LSE_ON: LSE oscillator ON
-* - RCC_LSE_Bypass: LSE oscillator bypassed with external
-* clock
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_LSEConfig(u8 RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Reset LSEBYP bit */
- *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
- switch(RCC_LSE)
- {
- case RCC_LSE_ON:
- /* Set LSEON bit */
- *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
- break;
-
- case RCC_LSE_Bypass:
- /* Set LSEBYP and LSEON bits */
- *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_LSICmd
-* Description : Enables or disables the Internal Low Speed oscillator (LSI).
-* LSI can not be disabled if the IWDG is running.
-* Input : - NewState: new state of the LSI.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CSR_LSION_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : RCC_RTCCLKConfig
-* Description : Configures the RTC clock (RTCCLK).
-* Once the RTC clock is selected it can't be changed unless the
-* Backup domain is reset.
-* Input : - RCC_RTCCLKSource: specifies the RTC clock source.
-* This parameter can be one of the following values:
-* - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
-* - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
-* - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
-* selected as RTC clock
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- /* Select the RTC clock source */
- RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/*******************************************************************************
-* Function Name : RCC_RTCCLKCmd
-* Description : Enables or disables the RTC clock.
-* This function must be used only after the RTC clock was
-* selected using the RCC_RTCCLKConfig function.
-* Input : - NewState: new state of the RTC clock.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : RCC_GetClocksFreq
-* Description : Returns the frequencies of different on chip clocks.
-* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
-* will hold the clocks frequencies.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & CFGR_SWS_Mask;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_Value;
- break;
-
- case 0x04: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_Value;
- break;
-
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
- pllmull = ( pllmull >> 18) + 2;
-
- pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
-
- if (pllsource == 0x00)
- {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
- RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
- }
- else
- {/* HSE selected as PLL clock entry */
-
- if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
- {/* HSE oscillator clock divided by 2 */
-
- RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
- }
- else
- {
- RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
- }
- }
- break;
-
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_Value;
- break;
- }
-
- /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
-
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
-
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
- tmp = tmp >> 11;
- presc = APBAHBPrescTable[tmp];
-
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get ADCCLK prescaler */
- tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
- tmp = tmp >> 14;
- presc = ADCPrescTable[tmp];
-
- /* ADCCLK clock frequency */
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
-}
-
-/*******************************************************************************
-* Function Name : RCC_AHBPeriphClockCmd
-* Description : Enables or disables the AHB peripheral clock.
-* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
-* This parameter can be any combination of the following values:
-* - RCC_AHBPeriph_DMA1
-* - RCC_AHBPeriph_DMA2
-* - RCC_AHBPeriph_SRAM
-* - RCC_AHBPeriph_FLITF
-* - RCC_AHBPeriph_CRC
-* - RCC_AHBPeriph_FSMC
-* - RCC_AHBPeriph_SDIO
-* SRAM and FLITF clock can be disabled only during sleep mode.
-* - NewState: new state of the specified peripheral clock.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBENR &= ~RCC_AHBPeriph;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_APB2PeriphClockCmd
-* Description : Enables or disables the High Speed APB (APB2) peripheral clock.
-* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
-* clock.
-* This parameter can be any combination of the following values:
-* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
-* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
-* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
-* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
-* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
-* RCC_APB2Periph_ALL
-* - NewState: new state of the specified peripheral clock.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_APB1PeriphClockCmd
-* Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
-* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
-* clock.
-* This parameter can be any combination of the following values:
-* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
-* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
-* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
-* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
-* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
-* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
-* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
-* - NewState: new state of the specified peripheral clock.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_APB2PeriphResetCmd
-* Description : Forces or releases High Speed APB (APB2) peripheral reset.
-* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
-* This parameter can be any combination of the following values:
-* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
-* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
-* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
-* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
-* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
-* RCC_APB2Periph_ALL
-* - NewState: new state of the specified peripheral reset.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_APB1PeriphResetCmd
-* Description : Forces or releases Low Speed APB (APB1) peripheral reset.
-* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
-* This parameter can be any combination of the following values:
-* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
-* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
-* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
-* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
-* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
-* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
-* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
-* - NewState: new state of the specified peripheral clock.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/*******************************************************************************
-* Function Name : RCC_BackupResetCmd
-* Description : Forces or releases the Backup domain reset.
-* Input : - NewState: new state of the Backup domain reset.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : RCC_ClockSecuritySystemCmd
-* Description : Enables or disables the Clock Security System.
-* Input : - NewState: new state of the Clock Security System..
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CR_CSSON_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : RCC_MCOConfig
-* Description : Selects the clock source to output on MCO pin.
-* Input : - RCC_MCO: specifies the clock source to output.
-* This parameter can be one of the following values:
-* - RCC_MCO_NoClock: No clock selected
-* - RCC_MCO_SYSCLK: System clock selected
-* - RCC_MCO_HSI: HSI oscillator clock selected
-* - RCC_MCO_HSE: HSE oscillator clock selected
-* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_MCOConfig(u8 RCC_MCO)
-{
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCO));
-
- /* Perform Byte access to MCO[2:0] bits to select the MCO source */
- *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO;
-}
-
-/*******************************************************************************
-* Function Name : RCC_GetFlagStatus
-* Description : Checks whether the specified RCC flag is set or not.
-* Input : - RCC_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - RCC_FLAG_HSIRDY: HSI oscillator clock ready
-* - RCC_FLAG_HSERDY: HSE oscillator clock ready
-* - RCC_FLAG_PLLRDY: PLL clock ready
-* - RCC_FLAG_LSERDY: LSE oscillator clock ready
-* - RCC_FLAG_LSIRDY: LSI oscillator clock ready
-* - RCC_FLAG_PINRST: Pin reset
-* - RCC_FLAG_PORRST: POR/PDR reset
-* - RCC_FLAG_SFTRST: Software reset
-* - RCC_FLAG_IWDGRST: Independent Watchdog reset
-* - RCC_FLAG_WWDGRST: Window Watchdog reset
-* - RCC_FLAG_LPWRRST: Low Power reset
-* Output : None
-* Return : The new state of RCC_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
-{
- u32 tmp = 0;
- u32 statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
-
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 2) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_Mask;
-
- if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- /* Return the flag status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : RCC_ClearFlag
-* Description : Clears the RCC reset flags.
-* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
-* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
-* RCC_FLAG_LPWRRST
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= CSR_RMVF_Set;
-}
-
-/*******************************************************************************
-* Function Name : RCC_GetITStatus
-* Description : Checks whether the specified RCC interrupt has occurred or not.
-* Input : - RCC_IT: specifies the RCC interrupt source to check.
-* This parameter can be one of the following values:
-* - RCC_IT_LSIRDY: LSI ready interrupt
-* - RCC_IT_LSERDY: LSE ready interrupt
-* - RCC_IT_HSIRDY: HSI ready interrupt
-* - RCC_IT_HSERDY: HSE ready interrupt
-* - RCC_IT_PLLRDY: PLL ready interrupt
-* - RCC_IT_CSS: Clock Security System interrupt
-* Output : None
-* Return : The new state of RCC_IT (SET or RESET).
-*******************************************************************************/
-ITStatus RCC_GetITStatus(u8 RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : RCC_ClearITPendingBit
-* Description : Clears the RCC's interrupt pending bits.
-* Input : - RCC_IT: specifies the interrupt pending bit to clear.
-* This parameter can be any combination of the following values:
-* - RCC_IT_LSIRDY: LSI ready interrupt
-* - RCC_IT_LSERDY: LSE ready interrupt
-* - RCC_IT_HSIRDY: HSI ready interrupt
-* - RCC_IT_HSERDY: HSE ready interrupt
-* - RCC_IT_PLLRDY: PLL ready interrupt
-* - RCC_IT_CSS: Clock Security System interrupt
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_ClearITPendingBit(u8 RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the RCC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @defgroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+ /* Alias word address of PLL2ON bit */
+ #define PLL2ON_BitNumber 0x1A
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
+
+ /* Alias word address of PLL3ON bit */
+ #define PLL3ON_BitNumber 0x1C
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+
+#ifndef STM32F10X_CL
+ #define USBPRE_BitNumber 0x16
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+#else
+ #define OTGFSPRE_BitNumber 0x16
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+/* --- CFGR2 Register ---*/
+
+ /* Alias word address of I2S2SRC bit */
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
+ #define I2S2SRC_BitNumber 0x11
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
+
+ /* Alias word address of I2S3SRC bit */
+ #define I2S3SRC_BitNumber 0x12
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
+#define CR_HSEON_Set ((uint32_t)0x00010000)
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#ifndef STM32F10X_CL
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
+#else
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
+#endif /* STM32F10X_CL */
+
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RMVF_Set ((uint32_t)0x01000000)
+
+#ifdef STM32F10X_CL
+/* CFGR2 register bit mask */
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
+#endif /* STM32F10X_CL */
+
+/* RCC Flag Mask */
+#define FLAG_Mask ((uint8_t)0x1F)
+
+#ifndef HSI_Value
+/* Typical Value of the HSI in Hz */
+ #define HSI_Value ((uint32_t)8000000)
+#endif /* HSI_Value */
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CFGR register byte 4 (Bits[31:24]) base address */
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
+
+/* BDCR register base address */
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
+
+#ifndef HSEStartUp_TimeOut
+/* Time out for HSE start up */
+ #define HSEStartUp_TimeOut ((uint16_t)0x0500)
+#endif /* HSEStartUp_TimeOut */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Variables
+ * @{
+ */
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifndef STM32F10X_CL
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#else
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#endif /* STM32F10X_CL */
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: HSE oscillator OFF
+ * @arg RCC_HSE_ON: HSE oscillator ON
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CR &= CR_HSEON_Reset;
+ /* Reset HSEBYP bit */
+ RCC->CR &= CR_HSEBYP_Reset;
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+ switch(RCC_HSE)
+ {
+ case RCC_HSE_ON:
+ /* Set HSEON bit */
+ RCC->CR |= CR_HSEON_Set;
+ break;
+
+ case RCC_HSE_Bypass:
+ /* Set HSEBYP and HSEON bits */
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @param None
+ * @retval An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+ tmpreg = RCC->CR;
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= CR_HSITRIM_Mask;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ tmpreg &= CFGR_PLL_Mask;
+ /* Set the PLL configuration bits */
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the PREDIV1 division factor.
+ * @note
+ * - This function must be used only when the PLL is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+ /* Set the PREDIV1 clock source and division factor */
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Configures the PREDIV2 division factor.
+ * @note
+ * - This function must be used only when both PLL2 and PLL3 are disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV2[3:0] bits */
+ tmpreg &= ~CFGR2_PREDIV2;
+ /* Set the PREDIV2 division factor */
+ tmpreg |= RCC_PREDIV2_Div;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the PLL2 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL2 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL2Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL2MUL;
+ /* Set the PLL2 configuration bits */
+ tmpreg |= RCC_PLL2Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL2.
+ * @note
+ * - The PLL2 can not be disabled if it is used indirectly as system clock
+ * (i.e. it is used as PLL clock entry that is used as System clock).
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
+}
+
+
+/**
+ * @brief Configures the PLL3 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL3 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL3Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL3MUL;
+ /* Set the PLL3 configuration bits */
+ tmpreg |= RCC_PLL3Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL3.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+ tmpreg = RCC->CFGR;
+ /* Clear SW[1:0] bits */
+ tmpreg &= CFGR_SW_Mask;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= CFGR_HPRE_Reset_Mask;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= CFGR_PPRE1_Reset_Mask;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= CFGR_PPRE2_Reset_Mask;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+#ifndef STM32F10X_CL
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ * clock source
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+ * @retval None
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+#else
+/**
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).
+ * This function applies only to STM32 Connectivity line devices.
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
+ * This clock is derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @retval None
+ */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
+
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the ADC clock (ADCCLK).
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
+ * the APB2 clock (PCLK2).
+ * This parameter can be one of the following values:
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+ * @retval None
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+ tmpreg = RCC->CFGR;
+ /* Clear ADCPRE[1:0] bits */
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+ tmpreg |= RCC_PCLK2;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the I2S2 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S2 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
+ * @retval None
+ */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
+}
+
+/**
+ * @brief Configures the I2S3 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S3 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
+ * @retval None
+ */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: LSE oscillator OFF
+ * @arg RCC_LSE_ON: LSE oscillator ON
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Reset LSEBYP bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+ switch(RCC_LSE)
+ {
+ case RCC_LSE_ON:
+ /* Set LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
+ break;
+
+ case RCC_LSE_Bypass:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can’t be changed unless the Backup domain is reset.
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & CFGR_SWS_Mask;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
+ }
+ else
+ {/* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
+ }
+ else
+ {
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
+ }
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+ tmp = tmp >> 4;
+ presc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+ tmp = tmp >> 11;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get ADCCLK prescaler */
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+ tmp = tmp >> 14;
+ presc = ADCPrescTable[tmp];
+ /* ADCCLK clock frequency */
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_FSMC
+ * @arg RCC_AHBPeriph_SDIO
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBRSTR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;
+ }
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param NewState: new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO: specifies the clock source to output.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ *
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ /* Perform Byte access to MCO bits to select the MCO source */
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_Mask;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= CSR_RMVF_Set;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC’s interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rtc.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rtc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_rtc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,320 +1,341 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_rtc.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the RTC firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rtc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */
-#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */
-#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */
-#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : RTC_ITConfig
-* Description : Enables or disables the specified RTC interrupts.
-* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled
-* or disabled.
-* This parameter can be any combination of the following values:
-* - RTC_IT_OW: Overflow interrupt
-* - RTC_IT_ALR: Alarm interrupt
-* - RTC_IT_SEC: Second interrupt
-* - NewState: new state of the specified RTC interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RTC->CRH |= RTC_IT;
- }
- else
- {
- RTC->CRH &= (u16)~RTC_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : RTC_EnterConfigMode
-* Description : Enters the RTC configuration mode.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_EnterConfigMode(void)
-{
- /* Set the CNF flag to enter in the Configuration Mode */
- RTC->CRL |= CRL_CNF_Set;
-}
-
-/*******************************************************************************
-* Function Name : RTC_ExitConfigMode
-* Description : Exits from the RTC configuration mode.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_ExitConfigMode(void)
-{
- /* Reset the CNF flag to exit from the Configuration Mode */
- RTC->CRL &= CRL_CNF_Reset;
-}
-
-/*******************************************************************************
-* Function Name : RTC_GetCounter
-* Description : Gets the RTC counter value.
-* Input : None
-* Output : None
-* Return : RTC counter value.
-*******************************************************************************/
-u32 RTC_GetCounter(void)
-{
- u16 tmp = 0;
- tmp = RTC->CNTL;
-
- return (((u32)RTC->CNTH << 16 ) | tmp) ;
-}
-
-/*******************************************************************************
-* Function Name : RTC_SetCounter
-* Description : Sets the RTC counter value.
-* Input : - CounterValue: RTC counter new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_SetCounter(u32 CounterValue)
-{
- RTC_EnterConfigMode();
-
- /* Set RTC COUNTER MSB word */
- RTC->CNTH = CounterValue >> 16;
- /* Set RTC COUNTER LSB word */
- RTC->CNTL = (CounterValue & RTC_LSB_Mask);
-
- RTC_ExitConfigMode();
-}
-
-/*******************************************************************************
-* Function Name : RTC_SetPrescaler
-* Description : Sets the RTC prescaler value.
-* Input : - PrescalerValue: RTC prescaler new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_SetPrescaler(u32 PrescalerValue)
-{
- /* Check the parameters */
- assert_param(IS_RTC_PRESCALER(PrescalerValue));
-
- RTC_EnterConfigMode();
-
- /* Set RTC PRESCALER MSB word */
- RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
- /* Set RTC PRESCALER LSB word */
- RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
-
- RTC_ExitConfigMode();
-}
-
-/*******************************************************************************
-* Function Name : RTC_SetAlarm
-* Description : Sets the RTC alarm value.
-* Input : - AlarmValue: RTC alarm new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_SetAlarm(u32 AlarmValue)
-{
- RTC_EnterConfigMode();
-
- /* Set the ALARM MSB word */
- RTC->ALRH = AlarmValue >> 16;
- /* Set the ALARM LSB word */
- RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
-
- RTC_ExitConfigMode();
-}
-
-/*******************************************************************************
-* Function Name : RTC_GetDivider
-* Description : Gets the RTC divider value.
-* Input : None
-* Output : None
-* Return : RTC Divider value.
-*******************************************************************************/
-u32 RTC_GetDivider(void)
-{
- u32 tmp = 0x00;
-
- tmp = ((u32)RTC->DIVH & (u32)0x000F) << 16;
- tmp |= RTC->DIVL;
-
- return tmp;
-}
-
-/*******************************************************************************
-* Function Name : RTC_WaitForLastTask
-* Description : Waits until last write operation on RTC registers has finished.
-* This function must be called before any write to RTC registers.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_WaitForLastTask(void)
-{
- /* Loop until RTOFF flag is set */
- while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET)
- {
- }
-}
-
-/*******************************************************************************
-* Function Name : RTC_WaitForSynchro
-* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
-* are synchronized with RTC APB clock.
-* This function must be called before any read operation after
-* an APB reset or an APB clock stop.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_WaitForSynchro(void)
-{
- /* Clear RSF flag */
- RTC->CRL &= (u16)~RTC_FLAG_RSF;
-
- /* Loop until RSF flag is set */
- while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET)
- {
- }
-}
-
-/*******************************************************************************
-* Function Name : RTC_GetFlagStatus
-* Description : Checks whether the specified RTC flag is set or not.
-* Input : - RTC_FLAG: specifies the flag to check.
-* This parameter can be one the following values:
-* - RTC_FLAG_RTOFF: RTC Operation OFF flag
-* - RTC_FLAG_RSF: Registers Synchronized flag
-* - RTC_FLAG_OW: Overflow flag
-* - RTC_FLAG_ALR: Alarm flag
-* - RTC_FLAG_SEC: Second flag
-* Output : None
-* Return : The new state of RTC_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- if ((RTC->CRL & RTC_FLAG) != (u16)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : RTC_ClearFlag
-* Description : Clears the RTC's pending flags.
-* Input : - RTC_FLAG: specifies the flag to clear.
-* This parameter can be any combination of the following values:
-* - RTC_FLAG_RSF: Registers Synchronized flag. This flag
-* is cleared only after an APB reset or an APB Clock stop.
-* - RTC_FLAG_OW: Overflow flag
-* - RTC_FLAG_ALR: Alarm flag
-* - RTC_FLAG_SEC: Second flag
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_ClearFlag(u16 RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the coressponding RTC flag */
- RTC->CRL &= (u16)~RTC_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : RTC_GetITStatus
-* Description : Checks whether the specified RTC interrupt has occured or not.
-* Input : - RTC_IT: specifies the RTC interrupts sources to check.
-* This parameter can be one of the following values:
-* - RTC_IT_OW: Overflow interrupt
-* - RTC_IT_ALR: Alarm interrupt
-* - RTC_IT_SEC: Second interrupt
-* Output : None
-* Return : The new state of the RTC_IT (SET or RESET).
-*******************************************************************************/
-ITStatus RTC_GetITStatus(u16 RTC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
-
- if (((RTC->CRH & RTC_IT) != (u16)RESET) && (bitstatus != (u16)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : RTC_ClearITPendingBit
-* Description : Clears the RTC's interrupt pending bits.
-* Input : - RTC_IT: specifies the interrupt pending bit to clear.
-* This parameter can be any combination of the following values:
-* - RTC_IT_OW: Overflow interrupt
-* - RTC_IT_ALR: Alarm interrupt
-* - RTC_IT_SEC: Second interrupt
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_ClearITPendingBit(u16 RTC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RTC_IT(RTC_IT));
-
- /* Clear the coressponding RTC pending bit */
- RTC->CRL &= (u16)~RTC_IT;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the RTC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/** @defgroup RTC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Defines
+ * @{
+ */
+
+#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */
+#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */
+#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
+#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @param NewState: new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RTC->CRH |= RTC_IT;
+ }
+ else
+ {
+ RTC->CRH &= (uint16_t)~RTC_IT;
+ }
+}
+
+/**
+ * @brief Enters the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_EnterConfigMode(void)
+{
+ /* Set the CNF flag to enter in the Configuration Mode */
+ RTC->CRL |= CRL_CNF_Set;
+}
+
+/**
+ * @brief Exits from the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_ExitConfigMode(void)
+{
+ /* Reset the CNF flag to exit from the Configuration Mode */
+ RTC->CRL &= CRL_CNF_Reset;
+}
+
+/**
+ * @brief Gets the RTC counter value.
+ * @param None
+ * @retval RTC counter value.
+ */
+uint32_t RTC_GetCounter(void)
+{
+ uint16_t tmp = 0;
+ tmp = RTC->CNTL;
+ return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+ * @brief Sets the RTC counter value.
+ * @param CounterValue: RTC counter new value.
+ * @retval None
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+ RTC_EnterConfigMode();
+ /* Set RTC COUNTER MSB word */
+ RTC->CNTH = CounterValue >> 16;
+ /* Set RTC COUNTER LSB word */
+ RTC->CNTL = (CounterValue & RTC_LSB_Mask);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC prescaler value.
+ * @param PrescalerValue: RTC prescaler new value.
+ * @retval None
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_PRESCALER(PrescalerValue));
+
+ RTC_EnterConfigMode();
+ /* Set RTC PRESCALER MSB word */
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
+ /* Set RTC PRESCALER LSB word */
+ RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC alarm value.
+ * @param AlarmValue: RTC alarm new value.
+ * @retval None
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+ RTC_EnterConfigMode();
+ /* Set the ALARM MSB word */
+ RTC->ALRH = AlarmValue >> 16;
+ /* Set the ALARM LSB word */
+ RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Gets the RTC divider value.
+ * @param None
+ * @retval RTC Divider value.
+ */
+uint32_t RTC_GetDivider(void)
+{
+ uint32_t tmp = 0x00;
+ tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+ tmp |= RTC->DIVL;
+ return tmp;
+}
+
+/**
+ * @brief Waits until last write operation on RTC registers has finished.
+ * @note This function must be called before any write to RTC registers.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForLastTask(void)
+{
+ /* Loop until RTOFF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+ * are synchronized with RTC APB clock.
+ * @note This function must be called before any read operation after an APB reset
+ * or an APB clock stop.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForSynchro(void)
+{
+ /* Clear RSF flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
+ /* Loop until RSF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG: specifies the flag to check.
+ * This parameter can be one the following values:
+ * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC’s pending flags.
+ * @param RTC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
+ * an APB reset or an APB Clock stop.
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval None
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the coressponding RTC flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occured or not.
+ * @param RTC_IT: specifies the RTC interrupts sources to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval The new state of the RTC_IT (SET or RESET).
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_IT(RTC_IT));
+
+ bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
+ if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC’s interrupt pending bits.
+ * @param RTC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval None
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+
+ /* Clear the coressponding RTC pending bit */
+ RTC->CRL &= (uint16_t)~RTC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_sdio.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_sdio.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_sdio.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,832 +1,798 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_sdio.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the SDIO firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* ------------ SDIO registers bit address in the alias region ----------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
-
-
-/* ---------------------- SDIO registers bit mask ------------------------ */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((u32)0xFFFF8100)
-
-/* --- PWRCTRL Register ---*/
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((u32)0xFFFFFFFC)
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((u32)0xFFFFFF08)
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((u32)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((u32)(SDIO_BASE + 0x14))
-
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : SDIO_DeInit
-* Description : Deinitializes the SDIO peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_DeInit(void)
-{
- SDIO->POWER = 0x00000000;
- SDIO->CLKCR = 0x00000000;
- SDIO->ARG = 0x00000000;
- SDIO->CMD = 0x00000000;
- SDIO->DTIMER = 0x00000000;
- SDIO->DLEN = 0x00000000;
- SDIO->DCTRL = 0x00000000;
- SDIO->ICR = 0x00C007FF;
- SDIO->MASK = 0x00000000;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_Init
-* Description : Initializes the SDIO peripheral according to the specified
-* parameters in the SDIO_InitStruct.
-* Input : SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
-* that contains the configuration information for the SDIO
-* peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
-
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/
- /* Get the SDIO CLKCR value */
- tmpreg = SDIO->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
- /* Set CLKDIV bits according to SDIO_ClockDiv value */
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
- /* Set BYPASS bit according to SDIO_ClockBypass value */
- /* Set WIDBUS bits according to SDIO_BusWide value */
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
-
- /* Write to SDIO CLKCR */
- SDIO->CLKCR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_StructInit
-* Description : Fills each SDIO_InitStruct member with its default value.
-* Input : SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
-* will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- /* SDIO_InitStruct members default value */
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_ClockCmd
-* Description : Enables or disables the SDIO Clock.
-* Input : NewState: new state of the SDIO Clock.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_ClockCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CLKCR_CLKEN_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_SetPowerState
-* Description : Sets the power status of the controller.
-* Input : SDIO_PowerState: new state of the Power state.
-* This parameter can be one of the following values:
-* - SDIO_PowerState_OFF
-* - SDIO_PowerState_ON
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_SetPowerState(u32 SDIO_PowerState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
-
- SDIO->POWER &= PWR_PWRCTRL_MASK;
- SDIO->POWER |= SDIO_PowerState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetPowerState
-* Description : Gets the power status of the controller.
-* Input : None
-* Output : None
-* Return : Power status of the controller. The returned value can
-* be one of the following:
-* - 0x00: Power OFF
-* - 0x02: Power UP
-* - 0x03: Power ON
-*******************************************************************************/
-u32 SDIO_GetPowerState(void)
-{
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
-}
-
-/*******************************************************************************
-* Function Name : SDIO_ITConfig
-* Description : Enables or disables the SDIO interrupts.
-* Input : - SDIO_IT: specifies the SDIO interrupt sources to be
-* enabled or disabled.
-* This parameter can be one or a combination of the following
-* values:
-* - SDIO_IT_CCRCFAIL: Command response received (CRC check
-* failed) interrupt
-* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
-* failed) interrupt
-* - SDIO_IT_CTIMEOUT: Command response timeout interrupt
-* - SDIO_IT_DTIMEOUT: Data timeout interrupt
-* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
-* - SDIO_IT_CMDREND: Command response received (CRC check
-* passed) interrupt
-* - SDIO_IT_CMDSENT: Command sent (no response required)
-* interrupt
-* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
-* zero) interrupt
-* - SDIO_IT_STBITERR: Start bit not detected on all data
-* signals in wide bus mode interrupt
-* - SDIO_IT_DBCKEND: Data block sent/received (CRC check
-* passed) interrupt
-* - SDIO_IT_CMDACT: Command transfer in progress interrupt
-* - SDIO_IT_TXACT: Data transmit in progress interrupt
-* - SDIO_IT_RXACT: Data receive in progress interrupt
-* - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-* - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-* - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
-* - SDIO_IT_RXFIFOF: Receive FIFO full interrupt
-* - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
-* - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
-* - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
-* - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
-* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
-* - SDIO_IT_CEATAEND: CE-ATA command completion signal
-* received for CMD61 interrupt
-* - NewState: new state of the specified SDIO interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_IT(SDIO_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SDIO interrupts */
- SDIO->MASK |= SDIO_IT;
- }
- else
- {
- /* Disable the SDIO interrupts */
- SDIO->MASK &= ~SDIO_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : SDIO_DMACmd
-* Description : Enables or disables the SDIO DMA request.
-* Input : NewState: new state of the selected SDIO DMA request.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) DCTRL_DMAEN_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_SendCommand
-* Description : Initializes the SDIO Command according to the specified
-* parameters in the SDIO_CmdInitStruct and send the command.
-* Input : SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
-* structure that contains the configuration information
-* for the SDIO command.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
-
-/*---------------------------- SDIO ARG Configuration ------------------------*/
- /* Set the SDIO Argument value */
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
-
-/*---------------------------- SDIO CMD Configuration ------------------------*/
- /* Get the SDIO CMD value */
- tmpreg = SDIO->CMD;
-
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */
- /* Set WAITRESP bits according to SDIO_Response value */
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
- /* Set CPSMEN bits according to SDIO_CPSM value */
- tmpreg |= (u32)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
-
- /* Write to SDIO CMD */
- SDIO->CMD = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_CmdStructInit
-* Description : Fills each SDIO_CmdInitStruct member with its default value.
-* Input : SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
- /* SDIO_CmdInitStruct members default value */
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetCommandResponse
-* Description : Returns command index of last command for which response
-* received.
-* Input : None
-* Output : None
-* Return : Returns the command index of the last command response received.
-*******************************************************************************/
-u8 SDIO_GetCommandResponse(void)
-{
- return (u8)(SDIO->RESPCMD);
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetResponse
-* Description : Returns response received from the card for the last command.
-* Input : - SDIO_RESP: Specifies the SDIO response register.
-* This parameter can be one of the following values:
-* - SDIO_RESP1: Response Register 1
-* - SDIO_RESP2: Response Register 2
-* - SDIO_RESP3: Response Register 3
-* - SDIO_RESP4: Response Register 4
-* Output : None
-* Return : The Corresponding response register value.
-*******************************************************************************/
-u32 SDIO_GetResponse(u32 SDIO_RESP)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(SDIO_RESP));
-
- return (*(vu32 *)(SDIO_RESP_ADDR + SDIO_RESP));
-}
-
-/*******************************************************************************
-* Function Name : SDIO_DataConfig
-* Description : Initializes the SDIO data path according to the specified
-* parameters in the SDIO_DataInitStruct.
-* Input : SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef
-* structure that contains the configuration information
-* for the SDIO command.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
-
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/
- /* Set the SDIO Data TimeOut value */
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-/*---------------------------- SDIO DLEN Configuration -----------------------*/
- /* Set the SDIO DataLength value */
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
-
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/
- /* Get the SDIO DCTRL value */
- tmpreg = SDIO->DCTRL;
-
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
- /* Set DEN bit according to SDIO_DPSM value */
- /* Set DTMODE bit according to SDIO_TransferMode value */
- /* Set DTDIR bit according to SDIO_TransferDir value */
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
- tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
- /* Write to SDIO DCTRL */
- SDIO->DCTRL = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_DataStructInit
-* Description : Fills each SDIO_DataInitStruct member with its default value.
-* Input : SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- /* SDIO_DataInitStruct members default value */
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetDataCounter
-* Description : Returns number of remaining data bytes to be transferred.
-* Input : None
-* Output : None
-* Return : Number of remaining data bytes to be transferred
-*******************************************************************************/
-u32 SDIO_GetDataCounter(void)
-{
- return SDIO->DCOUNT;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_ReadData
-* Description : Read one data word from Rx FIFO.
-* Input : None
-* Output : None
-* Return : Data received
-*******************************************************************************/
-u32 SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_WriteData
-* Description : Write one data word to Tx FIFO.
-* Input : Data: 32-bit data word to write.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_WriteData(u32 Data)
-{
- SDIO->FIFO = Data;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetFIFOCount
-* Description : Returns the number of words left to be written to or read
-* from FIFO.
-* Input : None
-* Output : None
-* Return : Remaining number of words.
-*******************************************************************************/
-u32 SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_StartSDIOReadWait
-* Description : Starts the SD I/O Read Wait operation.
-* Input : NewState: new state of the Start SDIO Read Wait operation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_StartSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) DCTRL_RWSTART_BB = (u32) NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_StopSDIOReadWait
-* Description : Stops the SD I/O Read Wait operation.
-* Input : NewState: new state of the Stop SDIO Read Wait operation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_StopSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) DCTRL_RWSTOP_BB = (u32) NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_SetSDIOReadWaitMode
-* Description : Sets one of the two options of inserting read wait interval.
-* Input : SDIOReadWaitMode: SD I/O Read Wait operation mode.
-* This parametre can be:
-* - SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
-* - SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- *(vu32 *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_SetSDIOOperation
-* Description : Enables or disables the SD I/O Mode Operation.
-* Input : NewState: new state of SDIO specific operation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_SetSDIOOperation(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) DCTRL_SDIOEN_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_SendSDIOSuspendCmd
-* Description : Enables or disables the SD I/O Mode suspend command sending.
-* Input : NewState: new state of the SD I/O Mode suspend command.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CMD_SDIOSUSPEND_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_CommandCompletionCmd
-* Description : Enables or disables the command completion signal.
-* Input : NewState: new state of command completion signal.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_CommandCompletionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CMD_ENCMDCOMPL_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_CEATAITCmd
-* Description : Enables or disables the CE-ATA interrupt.
-* Input : NewState: new state of CE-ATA interrupt.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_CEATAITCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CMD_NIEN_BB = (u32)((~((u32)NewState)) & ((u32)0x1));
-}
-
-/*******************************************************************************
-* Function Name : SDIO_SendCEATACmd
-* Description : Sends CE-ATA command (CMD61).
-* Input : NewState: new state of CE-ATA command.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_SendCEATACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(vu32 *) CMD_ATACMD_BB = (u32)NewState;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetFlagStatus
-* Description : Checks whether the specified SDIO flag is set or not.
-* Input : SDIO_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - SDIO_FLAG_CCRCFAIL: Command response received (CRC check
-* failed)
-* - SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check
-* failed)
-* - SDIO_FLAG_CTIMEOUT: Command response timeout
-* - SDIO_FLAG_DTIMEOUT: Data timeou
-* - SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-* - SDIO_FLAG_RXOVERR: Received FIFO overrun error
-* - SDIO_FLAG_CMDREND: Command response received (CRC check
-* passed)
-* - SDIO_FLAG_CMDSENT: Command sent (no response required)
-* - SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is
-* zero)
-* - SDIO_FLAG_STBITERR: Start bit not detected on all data
-* signals in wide bus mode
-* - SDIO_FLAG_DBCKEND: Data block sent/received (CRC check
-* passed)
-* - SDIO_FLAG_CMDACT: Command transfer in progress
-* - SDIO_FLAG_TXACT: Data transmit in progress
-* - SDIO_FLAG_RXACT: Data receive in progress
-* - SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-* - SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-* - SDIO_FLAG_TXFIFOF: Transmit FIFO full
-* - SDIO_FLAG_RXFIFOF: Receive FIFO full
-* - SDIO_FLAG_TXFIFOE: Transmit FIFO empty
-* - SDIO_FLAG_RXFIFOE: Receive FIFO empty
-* - SDIO_FLAG_TXDAVL: Data available in transmit FIFO
-* - SDIO_FLAG_RXDAVL: Data available in receive FIFO
-* - SDIO_FLAG_SDIOIT: SD I/O interrupt received
-* - SDIO_FLAG_CEATAEND: CE-ATA command completion signal
-* received for CMD61
-* Output : None
-* Return : The new state of SDIO_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));
-
- if ((SDIO->STA & SDIO_FLAG) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_ClearFlag
-* Description : Clears the SDIO's pending flags.
-* Input : SDIO_FLAG: specifies the flag to clear.
-* This parameter can be one or a combination of the following
-* values:
-* - SDIO_FLAG_CCRCFAIL: Command response received (CRC check
-* failed)
-* - SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check
-* failed)
-* - SDIO_FLAG_CTIMEOUT: Command response timeout
-* - SDIO_FLAG_DTIMEOUT: Data timeou
-* - SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-* - SDIO_FLAG_RXOVERR: Received FIFO overrun error
-* - SDIO_FLAG_CMDREND: Command response received (CRC check
-* passed)
-* - SDIO_FLAG_CMDSENT: Command sent (no response required)
-* - SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is
-* zero)
-* - SDIO_FLAG_STBITERR: Start bit not detected on all data
-* signals in wide bus mode
-* - SDIO_FLAG_DBCKEND: Data block sent/received (CRC check
-* passed)
-* - SDIO_FLAG_SDIOIT: SD I/O interrupt received
-* - SDIO_FLAG_CEATAEND: CE-ATA command completion signal
-* received for CMD61
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_ClearFlag(u32 SDIO_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
-
- SDIO->ICR = SDIO_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_GetITStatus
-* Description : Checks whether the specified SDIO interrupt has occurred or not.
-* Input : SDIO_IT: specifies the SDIO interrupt source to check.
-* This parameter can be one of the following values:
-* - SDIO_IT_CCRCFAIL: Command response received (CRC check
-* failed) interrupt
-* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
-* failed) interrupt
-* - SDIO_IT_CTIMEOUT: Command response timeout interrupt
-* - SDIO_IT_DTIMEOUT: Data timeout interrupt
-* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
-* - SDIO_IT_CMDREND: Command response received (CRC check
-* passed) interrupt
-* - SDIO_IT_CMDSENT: Command sent (no response required)
-* interrupt
-* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
-* zero) interrupt
-* - SDIO_IT_STBITERR: Start bit not detected on all data
-* signals in wide bus mode interrupt
-* - SDIO_IT_DBCKEND: Data block sent/received (CRC check
-* passed) interrupt
-* - SDIO_IT_CMDACT: Command transfer in progress interrupt
-* - SDIO_IT_TXACT: Data transmit in progress interrupt
-* - SDIO_IT_RXACT: Data receive in progress interrupt
-* - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-* - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-* - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
-* - SDIO_IT_RXFIFOF: Receive FIFO full interrupt
-* - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
-* - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
-* - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
-* - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
-* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
-* - SDIO_IT_CEATAEND: CE-ATA command completion signal
-* received for CMD61 interrupt
-* Output : None
-* Return : The new state of SDIO_IT (SET or RESET).
-*******************************************************************************/
-ITStatus SDIO_GetITStatus(u32 SDIO_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_GET_IT(SDIO_IT));
-
- if ((SDIO->STA & SDIO_IT) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : SDIO_ClearITPendingBit
-* Description : Clears the SDIO's interrupt pending bits.
-* Input : SDIO_IT: specifies the interrupt pending bit to clear.
-* This parameter can be one or a combination of the following
-* values:
-* - SDIO_IT_CCRCFAIL: Command response received (CRC check
-* failed) interrupt
-* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
-* failed) interrupt
-* - SDIO_IT_CTIMEOUT: Command response timeout interrupt
-* - SDIO_IT_DTIMEOUT: Data timeout interrupt
-* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
-* - SDIO_IT_CMDREND: Command response received (CRC check
-* passed) interrupt
-* - SDIO_IT_CMDSENT: Command sent (no response required)
-* interrupt
-* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
-* zero) interrupt
-* - SDIO_IT_STBITERR: Start bit not detected on all data
-* signals in wide bus mode interrupt
-* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
-* - SDIO_IT_CEATAEND: CE-ATA command completion signal
-* received for CMD61
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_ClearITPendingBit(u32 SDIO_IT)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
-
- SDIO->ICR = SDIO_IT;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the SDIO firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+/** @defgroup SDIO_Private_TypesDefinitions
+ * @{
+ */
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void SDIO_DeInit(void)
+{
+ SDIO->POWER = 0x00000000;
+ SDIO->CLKCR = 0x00000000;
+ SDIO->ARG = 0x00000000;
+ SDIO->CMD = 0x00000000;
+ SDIO->DTIMER = 0x00000000;
+ SDIO->DLEN = 0x00000000;
+ SDIO->DCTRL = 0x00000000;
+ SDIO->ICR = 0x00C007FF;
+ SDIO->MASK = 0x00000000;
+}
+
+/**
+ * @brief Initializes the SDIO peripheral according to the specified
+ * parameters in the SDIO_InitStruct.
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+ * that contains the configuration information for the SDIO peripheral.
+ * @retval None
+ */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
+
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/
+ /* Get the SDIO CLKCR value */
+ tmpreg = SDIO->CLKCR;
+
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+ tmpreg &= CLKCR_CLEAR_MASK;
+
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+ /* Set BYPASS bit according to SDIO_ClockBypass value */
+ /* Set WIDBUS bits according to SDIO_BusWide value */
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
+
+ /* Write to SDIO CLKCR */
+ SDIO->CLKCR = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_InitStruct member with its default value.
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ /* SDIO_InitStruct members default value */
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+ * @brief Enables or disables the SDIO Clock.
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Sets the power status of the controller.
+ * @param SDIO_PowerState: new state of the Power state.
+ * This parameter can be one of the following values:
+ * @arg SDIO_PowerState_OFF
+ * @arg SDIO_PowerState_ON
+ * @retval None
+ */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+
+ SDIO->POWER &= PWR_PWRCTRL_MASK;
+ SDIO->POWER |= SDIO_PowerState;
+}
+
+/**
+ * @brief Gets the power status of the controller.
+ * @param None
+ * @retval Power status of the controller. The returned value can
+ * be one of the following:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDIO_GetPowerState(void)
+{
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+ * @brief Enables or disables the SDIO interrupts.
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @param NewState: new state of the specified SDIO interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_IT(SDIO_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the SDIO interrupts */
+ SDIO->MASK |= SDIO_IT;
+ }
+ else
+ {
+ /* Disable the SDIO interrupts */
+ SDIO->MASK &= ~SDIO_IT;
+ }
+}
+
+/**
+ * @brief Enables or disables the SDIO DMA request.
+ * @param NewState: new state of the selected SDIO DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Initializes the SDIO Command according to the specified
+ * parameters in the SDIO_CmdInitStruct and send the command.
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
+ * structure that contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+ /* Set the SDIO Argument value */
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+
+/*---------------------------- SDIO CMD Configuration ------------------------*/
+ /* Get the SDIO CMD value */
+ tmpreg = SDIO->CMD;
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+ tmpreg &= CMD_CLEAR_MASK;
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+ /* Set WAITRESP bits according to SDIO_Response value */
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+ /* Set CPSMEN bits according to SDIO_CPSM value */
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+ /* Write to SDIO CMD */
+ SDIO->CMD = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+ /* SDIO_CmdInitStruct members default value */
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+ * @brief Returns command index of last command for which response received.
+ * @param None
+ * @retval Returns the command index of the last command response received.
+ */
+uint8_t SDIO_GetCommandResponse(void)
+{
+ return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+ * @brief Returns response received from the card for the last command.
+ * @param SDIO_RESP: Specifies the SDIO response register.
+ * This parameter can be one of the following values:
+ * @arg SDIO_RESP1: Response Register 1
+ * @arg SDIO_RESP2: Response Register 2
+ * @arg SDIO_RESP3: Response Register 3
+ * @arg SDIO_RESP4: Response Register 4
+ * @retval The Corresponding response register value.
+ */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;
+
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @brief Initializes the SDIO data path according to the specified
+ * parameters in the SDIO_DataInitStruct.
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+ * contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+ /* Set the SDIO Data TimeOut value */
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+ /* Set the SDIO DataLength value */
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/
+ /* Get the SDIO DCTRL value */
+ tmpreg = SDIO->DCTRL;
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+ tmpreg &= DCTRL_CLEAR_MASK;
+ /* Set DEN bit according to SDIO_DPSM value */
+ /* Set DTMODE bit according to SDIO_TransferMode value */
+ /* Set DTDIR bit according to SDIO_TransferDir value */
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+ /* Write to SDIO DCTRL */
+ SDIO->DCTRL = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_DataInitStruct member with its default value.
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ /* SDIO_DataInitStruct members default value */
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @param None
+ * @retval Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCounter(void)
+{
+ return SDIO->DCOUNT;
+}
+
+/**
+ * @brief Read one data word from Rx FIFO.
+ * @param None
+ * @retval Data received
+ */
+uint32_t SDIO_ReadData(void)
+{
+ return SDIO->FIFO;
+}
+
+/**
+ * @brief Write one data word to Tx FIFO.
+ * @param Data: 32-bit data word to write.
+ * @retval None
+ */
+void SDIO_WriteData(uint32_t Data)
+{
+ SDIO->FIFO = Data;
+}
+
+/**
+ * @brief Returns the number of words left to be written to or read from FIFO.
+ * @param None
+ * @retval Remaining number of words.
+ */
+uint32_t SDIO_GetFIFOCount(void)
+{
+ return SDIO->FIFOCNT;
+}
+
+/**
+ * @brief Starts the SD I/O Read Wait operation.
+ * @param NewState: new state of the Start SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Stops the SD I/O Read Wait operation.
+ * @param NewState: new state of the Stop SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+ * This parametre can be:
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+ * @retval None
+ */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode Operation.
+ * @param NewState: new state of SDIO specific operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode suspend command sending.
+ * @param NewState: new state of the SD I/O Mode suspend command.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the command completion signal.
+ * @param NewState: new state of command completion signal.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the CE-ATA interrupt.
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+ * @brief Sends CE-ATA command (CMD61).
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param SDIO_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param SDIO_FLAG: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+
+ SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param SDIO_IT: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO’s interrupt pending bits.
+ * @param SDIO_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+
+ SDIO->ICR = SDIO_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_spi.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_spi.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_spi.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,863 +1,907 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_spi.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the SPI firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_spi.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* SPI SPE mask */
-#define CR1_SPE_Set ((u16)0x0040)
-#define CR1_SPE_Reset ((u16)0xFFBF)
-
-/* I2S I2SE mask */
-#define I2SCFGR_I2SE_Set ((u16)0x0400)
-#define I2SCFGR_I2SE_Reset ((u16)0xFBFF)
-
-/* SPI CRCNext mask */
-#define CR1_CRCNext_Set ((u16)0x1000)
-
-/* SPI CRCEN mask */
-#define CR1_CRCEN_Set ((u16)0x2000)
-#define CR1_CRCEN_Reset ((u16)0xDFFF)
-
-/* SPI SSOE mask */
-#define CR2_SSOE_Set ((u16)0x0004)
-#define CR2_SSOE_Reset ((u16)0xFFFB)
-
-/* SPI registers Masks */
-#define CR1_CLEAR_Mask ((u16)0x3040)
-#define I2SCFGR_CLEAR_Mask ((u16)0xF040)
-
-/* SPI or I2S mode selection masks */
-#define SPI_Mode_Select ((u16)0xF7FF)
-#define I2S_Mode_Select ((u16)0x0800)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : SPI_I2S_DeInit
-* Description : Deinitializes the SPIx peripheral registers to their default
-* reset values (Affects also the I2Ss).
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- switch (*(u32*)&SPIx)
- {
- case SPI1_BASE:
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- break;
-
- case SPI2_BASE:
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- break;
-
- case SPI3_BASE:
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_Init
-* Description : Initializes the SPIx peripheral according to the specified
-* parameters in the SPI_InitStruct.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
-* contains the configuration information for the specified
-* SPI peripheral.
-* Output : None
-* Return : None
-******************************************************************************/
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- u16 tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= SPI_Mode_Select;
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/*******************************************************************************
-* Function Name : I2S_Init
-* Description : Initializes the SPIx peripheral according to the specified
-* parameters in the I2S_InitStruct.
-* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral
-* (configured in I2S mode).
-* - I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
-* contains the configuration information for the specified
-* SPI peripheral configured in I2S mode.
-* Output : None
-* Return : None
-******************************************************************************/
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- u32 tmp = 0;
- RCC_ClocksTypeDef RCC_Clocks;
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
-
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (u16)0;
- i2sdiv = (u16)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) */
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
- /* Get System Clock frequency */
- RCC_GetClocksFreq(&RCC_Clocks);
-
- /* Compute the Real divider depending on the MCLK output state with a flaoting point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flaoting point */
- tmp = tmp/10;
-
- /* Check the parity of the divider */
- i2sodd = (u16)(tmp & (u16)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (u16)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (u16) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (u16)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \
- I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \
- I2S_InitStruct->I2S_CPOL);
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : SPI_StructInit
-* Description : Fills each SPI_InitStruct member with its default value.
-* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
-
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
-
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
-
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
-
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
-
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
-
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/*******************************************************************************
-* Function Name : I2S_StructInit
-* Description : Fills each I2S_InitStruct member with its default value.
-* Input : - I2S_InitStruct : pointer to a I2S_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/*******************************************************************************
-* Function Name : SPI_Cmd
-* Description : Enables or disables the specified SPI peripheral.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - NewState: new state of the SPIx peripheral.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= CR1_SPE_Set;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= CR1_SPE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : I2S_Cmd
-* Description : Enables or disables the specified SPI peripheral (in I2S mode).
-* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral.
-* - NewState: new state of the SPIx peripheral.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
- }
- else
- {
- /* Disable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_ITConfig
-* Description : Enables or disables the specified SPI/I2S interrupts.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - 2 or 3 in I2S mode
-* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to be
-* enabled or disabled.
-* This parameter can be one of the following values:
-* - SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
-* - SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
-* - SPI_I2S_IT_ERR: Error interrupt mask
-* - NewState: new state of the specified SPI/I2S interrupt.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState)
-{
- u16 itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI/I2S IT index */
- itpos = SPI_I2S_IT >> 4;
- /* Set the IT mask */
- itmask = (u16)((u16)1 << itpos);
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI/I2S interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI/I2S interrupt */
- SPIx->CR2 &= (u16)~itmask;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_DMACmd
-* Description : Enables or disables the SPIx/I2Sx DMA interface.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - 2 or 3 in I2S mode
-* - SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request
-* to be enabled or disabled.
-* This parameter can be any combination of the following values:
-* - SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
-* - SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
-* - NewState: new state of the selected SPI/I2S DMA transfer
-* request.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI/I2S DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI/I2S DMA requests */
- SPIx->CR2 &= (u16)~SPI_I2S_DMAReq;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_SendData
-* Description : Transmits a Data through the SPIx/I2Sx peripheral.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - 2 or 3 in I2S mode
-* - Data : Data to be transmitted..
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_ReceiveData
-* Description : Returns the most recent received data by the SPIx/I2Sx peripheral.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - 2 or 3 in I2S mode
-* Output : None
-* Return : The value of the received data.
-*******************************************************************************/
-u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/*******************************************************************************
-* Function Name : SPI_NSSInternalSoftwareConfig
-* Description : Configures internally by software the NSS pin for the selected
-* SPI.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - SPI_NSSInternalSoft: specifies the SPI NSS internal state.
-* This parameter can be one of the following values:
-* - SPI_NSSInternalSoft_Set: Set NSS pin internally
-* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_SSOutputCmd
-* Description : Enables or disables the SS output for the selected SPI.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - NewState: new state of the SPIx SS output.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= CR2_SSOE_Set;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= CR2_SSOE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_DataSizeConfig
-* Description : Configures the data size for the selected SPI.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - SPI_DataSize: specifies the SPI data size.
-* This parameter can be one of the following values:
-* - SPI_DataSize_16b: Set data frame format to 16bit
-* - SPI_DataSize_8b: Set data frame format to 8bit
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
-
- /* Clear DFF bit */
- SPIx->CR1 &= (u16)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/*******************************************************************************
-* Function Name : SPI_TransmitCRC
-* Description : Transmit the SPIx CRC value.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= CR1_CRCNext_Set;
-}
-
-/*******************************************************************************
-* Function Name : SPI_CalculateCRC
-* Description : Enables or disables the CRC value calculation of the
-* transfered bytes.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - NewState: new state of the SPIx CRC value calculation.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= CR1_CRCEN_Set;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= CR1_CRCEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_GetCRC
-* Description : Returns the transmit or the receive CRC register value for
-* the specified SPI.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - SPI_CRC: specifies the CRC register to be read.
-* This parameter can be one of the following values:
-* - SPI_CRC_Tx: Selects Tx CRC register
-* - SPI_CRC_Rx: Selects Rx CRC register
-* Output : None
-* Return : The selected CRC register value..
-*******************************************************************************/
-u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC)
-{
- u16 crcreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
-
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
-
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/*******************************************************************************
-* Function Name : SPI_GetCRCPolynomial
-* Description : Returns the CRC Polynomial register value for the specified SPI.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* Output : None
-* Return : The CRC Polynomial register value.
-*******************************************************************************/
-u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/*******************************************************************************
-* Function Name : SPI_BiDirectionalLineConfig
-* Description : Selects the data transfer direction in bi-directional mode
-* for the specified SPI.
-* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-* - SPI_Direction: specifies the data transfer direction in
-* bi-directional mode.
-* This parameter can be one of the following values:
-* - SPI_Direction_Tx: Selects Tx transmission direction
-* - SPI_Direction_Rx: Selects Rx receive direction
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
-
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_GetFlagStatus
-* Description : Checks whether the specified SPI/I2S flag is set or not.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - 2 or 3 in I2S mode
-* - SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
-* This parameter can be one of the following values:
-* - SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
-* - SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
-* - SPI_I2S_FLAG_BSY: Busy flag.
-* - SPI_I2S_FLAG_OVR: Overrun flag.
-* - SPI_FLAG_MODF: Mode Fault flag.
-* - SPI_FLAG_CRCERR: CRC Error flag.
-* - I2S_FLAG_UDR: Underrun Error flag.
-* - I2S_FLAG_CHSIDE: Channel Side flag.
-* Output : None
-* Return : The new state of SPI_I2S_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI/I2S flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (u16)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_ClearFlag
-* Description : Clears the SPIx CRC Error (CRCERR) flag.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - SPI_I2S_FLAG: specifies the SPI flag to clear.
-* This function clears only CRCERR flag.
-* Notes:
-* - OVR (OverRun error) flag is cleared by software
-* sequence: a read operation to SPI_DR register
-* (SPI_I2S_ReceiveData()) followed by a read operation
-* to SPI_SR register (SPI_I2S_GetFlagStatus()).
-* - UDR (UnderRun error) flag is cleared by a read
-* operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
-* - MODF (Mode Fault) flag is cleared by software sequence:
-* a read/write operation to SPI_SR register
-* (SPI_I2S_GetFlagStatus()) followed by a write
-* operation to SPI_CR1 register (SPI_Cmd() to enable
-* the SPI).
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (u16)~SPI_I2S_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_GetITStatus
-* Description : Checks whether the specified SPI/I2S interrupt has occurred or not.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - 2 or 3 in I2S mode
-* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
-* This parameter can be one of the following values:
-* - SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
-* - SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
-* - SPI_I2S_IT_OVR: Overrun interrupt.
-* - SPI_IT_MODF: Mode Fault interrupt.
-* - SPI_IT_CRCERR: CRC Error interrupt.
-* - I2S_IT_UDR: Underrun Error interrupt.
-* Output : None
-* Return : The new state of SPI_I2S_IT (SET or RESET).
-*******************************************************************************/
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- u16 itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI/I2S IT index */
- itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
-
- /* Get the SPI/I2S IT mask */
- itmask = SPI_I2S_IT >> 4;
- /* Set the IT mask */
- itmask = (u16)((u16)0x01 << itmask);
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI/I2S interrupt */
- if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : SPI_I2S_ClearITPendingBit
-* Description : Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
-* Input : - SPIx: where x can be :
-* - 1, 2 or 3 in SPI mode
-* - SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
-* This function clears only CRCERR intetrrupt pending bit.
-* Notes:
-* - OVR (OverRun Error) interrupt pending bit is cleared
-* by software sequence: a read operation to SPI_DR
-* register (SPI_I2S_ReceiveData()) followed by a read
-* operation to SPI_SR register (SPI_I2S_GetITStatus()).
-* - UDR (UnderRun Error) interrupt pending bit is cleared
-* by a read operation to SPI_SR register
-* (SPI_I2S_GetITStatus()).
-* - MODF (Mode Fault) interrupt pending bit is cleared by
-* software sequence: a read/write operation to SPI_SR
-* register (SPI_I2S_GetITStatus()) followed by a write
-* operation to SPI_CR1 register (SPI_Cmd() to enable the
-* SPI).
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)
-{
- u16 itpos = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (u16)~itpos;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the SPI firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @defgroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPE mask */
+#define CR1_SPE_Set ((uint16_t)0x0040)
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set ((uint16_t)0x2000)
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set ((uint16_t)0x0004)
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select ((uint16_t)0xF7FF)
+#define I2S_Mode_Select ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC ((u32)(0x00020000))
+#define I2S3_CLOCK_SRC ((u32)(0x00040000))
+#define I2S_MUL_MASK ((u32)(0x0000F000))
+#define I2S_DIV_MASK ((u32)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+ }
+ else
+ {
+ if (SPIx == SPI3)
+ {
+ /* Enable SPI3 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+ /* Release SPI3 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral.
+ * @retval None
+ */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ SPIx->I2SCFGR &= SPI_Mode_Select;
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ * @retval None
+ */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksTypeDef RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+ SPIx->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = SPIx->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if(((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLOCK_SRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S3 */
+ tmp = I2S3_CLOCK_SRC;
+ }
+
+ /* Check the I2S clock source configuration depending on the Device:
+ Only Connectivity line devices have the PLL3 VCO clock */
+#ifdef STM32F10X_CL
+ if((RCC->CFGR2 & tmp) != 0)
+ {
+ /* Get the configuration bits of RCC PLL3 multiplier */
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
+
+ /* Get the value of the PLL3 multiplier */
+ if((tmp > 5) && (tmp < 15))
+ {
+ /* Multplier is between 8 and 14 (value 15 is forbidden) */
+ tmp += 2;
+ }
+ else
+ {
+ if (tmp == 15)
+ {
+ /* Multiplier is 20 */
+ tmp = 20;
+ }
+ }
+ /* Get the PREDIV2 value */
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
+
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
+ }
+ else
+ {
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+ }
+#else /* STM32F10X_HD */
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+#endif /* STM32F10X_CL */
+
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+
+ /* Remove the flaoting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (u16)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the SPI_Direction member */
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ /* initialize the SPI_Mode member */
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+ /* initialize the SPI_DataSize member */
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+ /* Initialize the SPI_CPOL member */
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+ /* Initialize the SPI_CPHA member */
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+ /* Initialize the SPI_NSS member */
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+ /* Initialize the SPI_BaudRatePrescaler member */
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ /* Initialize the SPI_FirstBit member */
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+ /* Initialize the SPI_CRCPolynomial member */
+ SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2S_Mode member */
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+ /* Initialize the I2S_Standard member */
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+ /* Initialize the I2S_DataFormat member */
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+ /* Initialize the I2S_MCLKOutput member */
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+ /* Initialize the I2S_AudioFreq member */
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+ /* Initialize the I2S_CPOL member */
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CR1 &= CR1_SPE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+ uint16_t itpos = 0, itmask = 0 ;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CR2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CR2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CR2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param Data : Data to be transmitted.
+ * @retval None
+ */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Write in the DR register the data to be sent */
+ SPIx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @retval The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the data in the DR register */
+ return SPIx->DR;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+ * @retval None
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CR2 |= CR2_SSOE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CR2 &= CR2_SSOE_Reset;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_DataSize: specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit
+ * @retval None
+ */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+ /* Clear DFF bit */
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+ /* Set new DFF bit value */
+ SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transfered bytes.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CR1 |= CR1_CRCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CR1 &= CR1_CRCEN_Reset;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRC: specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_Tx: Selects Tx CRC register
+ * @arg SPI_CRC_Rx: Selects Rx CRC register
+ * @retval The selected CRC register value..
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_Rx)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->TXCRCR;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->RXCRCR;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPR;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction
+ * @arg SPI_Direction_Rx: Selects Rx receive direction
+ * @retval None
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));
+ if (SPI_Direction == SPI_Direction_Tx)
+ {
+ /* Set the Tx only mode */
+ SPIx->CR1 |= SPI_Direction_Tx;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CR1 &= SPI_Direction_Rx;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.
+ * @arg SPI_FLAG_MODF: Mode Fault flag.
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.
+ * @arg I2S_FLAG_UDR: Underrun Error flag.
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.
+ * @arg SPI_IT_MODF: Mode Fault interrupt.
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.
+ * @arg I2S_IT_UDR: Underrun Error interrupt.
+ * @retval The new state of SPI_I2S_IT (SET or RESET).
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CR2 & itmask) ;
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR intetrrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
+ * the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->SR = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_systick.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_systick.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_systick.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,181 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_systick.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the SysTick firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_systick.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- SysTick registers bit mask -------------------- */
-/* CTRL TICKINT Mask */
-#define CTRL_TICKINT_Set ((u32)0x00000002)
-#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : SysTick_CLKSourceConfig
-* Description : Configures the SysTick clock source.
-* Input : - SysTick_CLKSource: specifies the SysTick clock source.
-* This parameter can be one of the following values:
-* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
-* selected as SysTick clock source.
-* - SysTick_CLKSource_HCLK: AHB clock selected as
-* SysTick clock source.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/*******************************************************************************
-* Function Name : SysTick_SetReload
-* Description : Sets SysTick Reload value.
-* Input : - Reload: SysTick Reload new value.
-* This parameter must be a number between 1 and 0xFFFFFF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SysTick_SetReload(u32 Reload)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_RELOAD(Reload));
-
- SysTick->LOAD = Reload;
-}
-
-/*******************************************************************************
-* Function Name : SysTick_CounterCmd
-* Description : Enables or disables the SysTick counter.
-* Input : - SysTick_Counter: new state of the SysTick counter.
-* This parameter can be one of the following values:
-* - SysTick_Counter_Disable: Disable counter
-* - SysTick_Counter_Enable: Enable counter
-* - SysTick_Counter_Clear: Clear counter value to 0
-* Output : None
-* Return : None
-*******************************************************************************/
-void SysTick_CounterCmd(u32 SysTick_Counter)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_COUNTER(SysTick_Counter));
-
- if (SysTick_Counter == SysTick_Counter_Enable)
- {
- SysTick->CTRL |= SysTick_Counter_Enable;
- }
- else if (SysTick_Counter == SysTick_Counter_Disable)
- {
- SysTick->CTRL &= SysTick_Counter_Disable;
- }
- else /* SysTick_Counter == SysTick_Counter_Clear */
- {
- SysTick->VAL = SysTick_Counter_Clear;
- }
-}
-
-/*******************************************************************************
-* Function Name : SysTick_ITConfig
-* Description : Enables or disables the SysTick Interrupt.
-* Input : - NewState: new state of the SysTick Interrupt.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void SysTick_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SysTick->CTRL |= CTRL_TICKINT_Set;
- }
- else
- {
- SysTick->CTRL &= CTRL_TICKINT_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : SysTick_GetCounter
-* Description : Gets SysTick counter value.
-* Input : None
-* Output : None
-* Return : SysTick current value
-*******************************************************************************/
-u32 SysTick_GetCounter(void)
-{
- return(SysTick->VAL);
-}
-
-/*******************************************************************************
-* Function Name : SysTick_GetFlagStatus
-* Description : Checks whether the specified SysTick flag is set or not.
-* Input : - SysTick_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - SysTick_FLAG_COUNT
-* - SysTick_FLAG_SKEW
-* - SysTick_FLAG_NOREF
-* Output : None
-* Return : None
-*******************************************************************************/
-FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
-{
- u32 statusreg = 0, tmp = 0 ;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SYSTICK_FLAG(SysTick_FLAG));
-
- /* Get the SysTick register index */
- tmp = SysTick_FLAG >> 3;
-
- if (tmp == 2) /* The flag to check is in CTRL register */
- {
- statusreg = SysTick->CTRL;
- }
- else /* The flag to check is in CALIB register */
- {
- statusreg = SysTick->CALIB;
- }
-
- if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_tim.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_tim.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_tim.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,3219 +1,2799 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_tim.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the TIM firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_tim.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define CR1_CEN_Set ((u16)0x0001)
-#define CR1_CEN_Reset ((u16)0x03FE)
-#define CR1_UDIS_Set ((u16)0x0002)
-#define CR1_UDIS_Reset ((u16)0x03FD)
-#define CR1_URS_Set ((u16)0x0004)
-#define CR1_URS_Reset ((u16)0x03FB)
-#define CR1_OPM_Reset ((u16)0x03F7)
-#define CR1_CounterMode_Mask ((u16)0x038F)
-#define CR1_ARPE_Set ((u16)0x0080)
-#define CR1_ARPE_Reset ((u16)0x037F)
-#define CR1_CKD_Mask ((u16)0x00FF)
-
-#define CR2_CCPC_Set ((u16)0x0001)
-#define CR2_CCPC_Reset ((u16)0xFFFE)
-#define CR2_CCUS_Set ((u16)0x0004)
-#define CR2_CCUS_Reset ((u16)0xFFFB)
-#define CR2_CCDS_Set ((u16)0x0008)
-#define CR2_CCDS_Reset ((u16)0xFFF7)
-#define CR2_MMS_Mask ((u16)0xFF8F)
-#define CR2_TI1S_Set ((u16)0x0080)
-#define CR2_TI1S_Reset ((u16)0xFF7F)
-#define CR2_OIS1_Reset ((u16)0x7EFF)
-#define CR2_OIS1N_Reset ((u16)0x7DFF)
-#define CR2_OIS2_Reset ((u16)0x7BFF)
-#define CR2_OIS2N_Reset ((u16)0x77FF)
-#define CR2_OIS3_Reset ((u16)0x6FFF)
-#define CR2_OIS3N_Reset ((u16)0x5FFF)
-#define CR2_OIS4_Reset ((u16)0x3FFF)
-
-#define SMCR_SMS_Mask ((u16)0xFFF8)
-#define SMCR_ETR_Mask ((u16)0x00FF)
-#define SMCR_TS_Mask ((u16)0xFF8F)
-#define SMCR_MSM_Reset ((u16)0xFF7F)
-#define SMCR_ECE_Set ((u16)0x4000)
-
-#define CCMR_CC13S_Mask ((u16)0xFFFC)
-#define CCMR_CC24S_Mask ((u16)0xFCFF)
-#define CCMR_TI13Direct_Set ((u16)0x0001)
-#define CCMR_TI24Direct_Set ((u16)0x0100)
-#define CCMR_OC13FE_Reset ((u16)0xFFFB)
-#define CCMR_OC24FE_Reset ((u16)0xFBFF)
-#define CCMR_OC13PE_Reset ((u16)0xFFF7)
-#define CCMR_OC24PE_Reset ((u16)0xF7FF)
-#define CCMR_OC13M_Mask ((u16)0xFF8F)
-#define CCMR_OC24M_Mask ((u16)0x8FFF)
-
-#define CCMR_OC13CE_Reset ((u16)0xFF7F)
-#define CCMR_OC24CE_Reset ((u16)0x7FFF)
-
-#define CCMR_IC13PSC_Mask ((u16)0xFFF3)
-#define CCMR_IC24PSC_Mask ((u16)0xF3FF)
-#define CCMR_IC13F_Mask ((u16)0xFF0F)
-#define CCMR_IC24F_Mask ((u16)0x0FFF)
-
-#define CCMR_Offset ((u16)0x0018)
-#define CCER_CCE_Set ((u16)0x0001)
-#define CCER_CCNE_Set ((u16)0x0004)
-
-#define CCER_CC1P_Reset ((u16)0xFFFD)
-#define CCER_CC2P_Reset ((u16)0xFFDF)
-#define CCER_CC3P_Reset ((u16)0xFDFF)
-#define CCER_CC4P_Reset ((u16)0xDFFF)
-
-#define CCER_CC1NP_Reset ((u16)0xFFF7)
-#define CCER_CC2NP_Reset ((u16)0xFF7F)
-#define CCER_CC3NP_Reset ((u16)0xF7FF)
-
-#define CCER_CC1E_Set ((u16)0x0001)
-#define CCER_CC1E_Reset ((u16)0xFFFE)
-
-#define CCER_CC1NE_Reset ((u16)0xFFFB)
-
-#define CCER_CC2E_Set ((u16)0x0010)
-#define CCER_CC2E_Reset ((u16)0xFFEF)
-
-#define CCER_CC2NE_Reset ((u16)0xFFBF)
-
-#define CCER_CC3E_Set ((u16)0x0100)
-#define CCER_CC3E_Reset ((u16)0xFEFF)
-
-#define CCER_CC3NE_Reset ((u16)0xFBFF)
-
-#define CCER_CC4E_Set ((u16)0x1000)
-#define CCER_CC4E_Reset ((u16)0xEFFF)
-
-#define BDTR_MOE_Set ((u16)0x8000)
-#define BDTR_MOE_Reset ((u16)0x7FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter);
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/*******************************************************************************
-* Function Name : TIM_DeInit
-* Description : Deinitializes the TIMx peripheral registers to their default
-* reset values.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- switch (*(u32*)&TIMx)
- {
- case TIM1_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- break;
-
- case TIM2_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- break;
-
- case TIM3_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- break;
-
- case TIM4_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- break;
-
- case TIM5_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- break;
-
- case TIM6_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- break;
-
- case TIM7_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- break;
-
- case TIM8_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_TimeBaseInit
-* Description : Initializes the TIMx Time Base Unit peripheral according to
-* the specified parameters in the TIM_TimeBaseInitStruct.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
-* structure that contains the configuration information for
-* the specified TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- /* Select the Counter Mode and set the clock division */
- TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
- TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
- TIM_TimeBaseInitStruct->TIM_CounterMode;
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- /* Generate an update event to reload the Prescaler value immediatly */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-
- if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC1Init
-* Description : Initializes the TIMx Channel1 according to the specified
-* parameters in the TIM_OCInitStruct.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-* that contains the configuration information for the specified
-* TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= CCER_CC1E_Reset;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= CCMR_OC13M_Mask;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= CCER_CC1P_Reset;
-
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= CCER_CC1NP_Reset;
-
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-
- /* Reset the Output N State */
- tmpccer &= CCER_CC1NE_Reset;
-
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= CR2_OIS1_Reset;
- tmpcr2 &= CR2_OIS1N_Reset;
-
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
-
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC2Init
-* Description : Initializes the TIMx Channel2 according to the specified
-* parameters in the TIM_OCInitStruct.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-* that contains the configuration information for the specified
-* TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= CCER_CC2E_Reset;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= CCMR_OC24M_Mask;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= CCER_CC2P_Reset;
-
- /* Set the Output Compare Polarity */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= CCER_CC2NP_Reset;
-
- /* Set the Output N Polarity */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-
- /* Reset the Output N State */
- tmpccer &= CCER_CC2NE_Reset;
-
- /* Set the Output N State */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4);
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= CR2_OIS2_Reset;
- tmpcr2 &= CR2_OIS2N_Reset;
-
- /* Set the Output Idle state */
- tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2);
-
- /* Set the Output N Idle state */
- tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC3Init
-* Description : Initializes the TIMx Channel3 according to the specified
-* parameters in the TIM_OCInitStruct.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-* that contains the configuration information for the specified
-* TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= CCER_CC3E_Reset;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= CCMR_OC13M_Mask;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= CCER_CC3P_Reset;
-
- /* Set the Output Compare Polarity */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= CCER_CC3NP_Reset;
-
- /* Set the Output N Polarity */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
-
- /* Reset the Output N State */
- tmpccer &= CCER_CC3NE_Reset;
-
- /* Set the Output N State */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8);
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= CR2_OIS3_Reset;
- tmpcr2 &= CR2_OIS3N_Reset;
-
- /* Set the Output Idle state */
- tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4);
-
- /* Set the Output N Idle state */
- tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC4Init
-* Description : Initializes the TIMx Channel4 according to the specified
-* parameters in the TIM_OCInitStruct.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-* that contains the configuration information for the specified
-* TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC4E Bit */
- TIMx->CCER &= CCER_CC4E_Reset;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= CCMR_OC24M_Mask;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= CCER_CC4P_Reset;
-
- /* Set the Output Compare Polarity */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Ouput Compare IDLE State */
- tmpcr2 &= CR2_OIS4_Reset;
-
- /* Set the Output Idle state */
- tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ICInit
-* Description : Initializes the TIM peripheral according to the specified
-* parameters in the TIM_ICInitStruct.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-* that contains the configuration information for the specified
-* TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_PWMIConfig
-* Description : Configures the TIM peripheral according to the specified
-* parameters in the TIM_ICInitStruct to measure an external PWM
-* signal.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-* that contains the configuration information for the specified
-* TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- u16 icoppositepolarity = TIM_ICPolarity_Rising;
- u16 icoppositeselection = TIM_ICSelection_DirectTI;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
-
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_BDTRConfig
-* Description : Configures the: Break feature, dead time, Lock level, the OSSI,
-* the OSSR State and the AOE(automatic output enable).
-* Input :- TIMx: where x can be 1 or 8 to select the TIM
-* - TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef
-* structure that contains the BDTR Register configuration
-* information for the TIM peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- TIMx->BDTR = (u32)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-
-}
-
-/*******************************************************************************
-* Function Name : TIM_TimeBaseStructInit
-* Description : Fills each TIM_TimeBaseInitStruct member with its default value.
-* Input : - TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OCStructInit
-* Description : Fills each TIM_OCInitStruct member with its default value.
-* Input : - TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x0000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ICStructInit
-* Description : Fills each TIM_ICInitStruct member with its default value.
-* Input : - TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/*******************************************************************************
-* Function Name : TIM_BDTRStructInit
-* Description : Fills each TIM_BDTRInitStruct member with its default value.
-* Input : - TIM_BDTRInitStruct : pointer to a TIM_BDTRInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/*******************************************************************************
-* Function Name : TIM_Cmd
-* Description : Enables or disables the specified TIM peripheral.
-* Input : - TIMx: where x can be 1 to 8 to select the TIMx peripheral.
-* - NewState: new state of the TIMx peripheral.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= CR1_CEN_Set;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= CR1_CEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_CtrlPWMOutputs
-* Description : Enables or disables the TIM peripheral Main Outputs.
-* Input :- TIMx: where x can be 1 or 8 to select the TIMx peripheral.
-* - NewState: new state of the TIM peripheral Main Outputs.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= BDTR_MOE_Set;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= BDTR_MOE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_ITConfig
-* Description : Enables or disables the specified TIM interrupts.
-* Input : - TIMx: where x can be 1 to 8 to select the TIMx peripheral.
-* - TIM_IT: specifies the TIM interrupts sources to be enabled
-* or disabled.
-* This parameter can be any combination of the following values:
-* - TIM_IT_Update: TIM update Interrupt source
-* - TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-* - TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-* - TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-* - TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-* - TIM_IT_COM: TIM Commutation Interrupt source
-* - TIM_IT_Trigger: TIM Trigger Interrupt source
-* - TIM_IT_Break: TIM Break Interrupt source
-* - NewState: new state of the TIM interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_TIM_PERIPH_IT((TIMx), (TIM_IT)));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (u16)~TIM_IT;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_GenerateEvent
-* Description : Configures the TIMx event to be generate by software.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_EventSource: specifies the event source.
-* This parameter can be one or more of the following values:
-* - TIM_EventSource_Update: Timer update Event source
-* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source
-* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source
-* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source
-* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source
-* - TIM_EventSource_Trigger: Timer Trigger Event source
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
- assert_param(IS_TIM_PERIPH_EVENT((TIMx), (TIM_EventSource)));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/*******************************************************************************
-* Function Name : TIM_DMAConfig
-* Description : Configures the TIMx's DMA interface.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_DMABase: DMA Base address.
-* This parameter can be one of the following values:
-* - TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
-* TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
-* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
-* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
-* TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
-* TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
-* TIM_DMABase_DCR.
-* - TIM_DMABurstLength: DMA Burst length.
-* This parameter can be one value between:
-* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/*******************************************************************************
-* Function Name : TIM_DMACmd
-* Description : Enables or disables the TIMx's DMA Requests.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_DMASources: specifies the DMA Request sources.
-* This parameter can be any combination of the following values:
-* - TIM_DMA_Update: TIM update Interrupt source
-* - TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-* - TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-* - TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-* - TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-* - TIM_DMA_COM: TIM Commutation DMA source
-* - TIM_DMA_Trigger: TIM Trigger DMA source
-* - NewState: new state of the DMA Request sources.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_TIM_PERIPH_DMA(TIMx, TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (u16)~TIM_DMASource;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_InternalClockConfig
-* Description : Configures the TIMx interrnal Clock
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= SMCR_SMS_Mask;
-}
-/*******************************************************************************
-* Function Name : TIM_ITRxExternalClockConfig
-* Description : Configures the TIMx Internal Trigger as External Clock
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ITRSource: Trigger source.
-* This parameter can be one of the following values:
-* - TIM_TS_ITR0: Internal Trigger 0
-* - TIM_TS_ITR1: Internal Trigger 1
-* - TIM_TS_ITR2: Internal Trigger 2
-* - TIM_TS_ITR3: Internal Trigger 3
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-/*******************************************************************************
-* Function Name : TIM_TIxExternalClockConfig
-* Description : Configures the TIMx Trigger as External Clock
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_TIxExternalCLKSource: Trigger source.
-* This parameter can be one of the following values:
-* - TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
-* - TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
-* - TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
-* - TIM_ICPolarity: specifies the TIx Polarity.
-* This parameter can be:
-* - TIM_ICPolarity_Rising
-* - TIM_ICPolarity_Falling
-* - ICFilter : specifies the filter value.
-* This parameter must be a value between 0x0 and 0xF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
- u16 TIM_ICPolarity, u16 ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
-
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ETRClockMode1Config
-* Description : Configures the External clock Mode1
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-* It can be one of the following values:
-* - TIM_ExtTRGPSC_OFF
-* - TIM_ExtTRGPSC_DIV2
-* - TIM_ExtTRGPSC_DIV4
-* - TIM_ExtTRGPSC_DIV8.
-* - TIM_ExtTRGPolarity: The external Trigger Polarity.
-* It can be one of the following values:
-* - TIM_ExtTRGPolarity_Inverted
-* - TIM_ExtTRGPolarity_NonInverted
-* - ExtTRGFilter: External Trigger Filter.
-* This parameter must be a value between 0x00 and 0x0F
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
- u16 ExtTRGFilter)
-{
- u16 tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the SMS Bits */
- tmpsmcr &= SMCR_SMS_Mask;
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= SMCR_TS_Mask;
- tmpsmcr |= TIM_TS_ETRF;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ETRClockMode2Config
-* Description : Configures the External clock Mode2
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-* It can be one of the following values:
-* - TIM_ExtTRGPSC_OFF
-* - TIM_ExtTRGPSC_DIV2
-* - TIM_ExtTRGPSC_DIV4
-* - TIM_ExtTRGPSC_DIV8
-* - TIM_ExtTRGPolarity: The external Trigger Polarity.
-* It can be one of the following values:
-* - TIM_ExtTRGPolarity_Inverted
-* - TIM_ExtTRGPolarity_NonInverted
-* - ExtTRGFilter: External Trigger Filter.
-* This parameter must be a value between 0x00 and 0x0F
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
- u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Enable the External clock mode2 */
- TIMx->SMCR |= SMCR_ECE_Set;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ETRConfig
-* Description : Configures the TIMx External Trigger (ETR).
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-* This parameter can be one of the following values:
-* - TIM_ExtTRGPSC_OFF
-* - TIM_ExtTRGPSC_DIV2
-* - TIM_ExtTRGPSC_DIV4
-* - TIM_ExtTRGPSC_DIV8
-* - TIM_ExtTRGPolarity: The external Trigger Polarity.
-* This parameter can be one of the following values:
-* - TIM_ExtTRGPolarity_Inverted
-* - TIM_ExtTRGPolarity_NonInverted
-* - ExtTRGFilter: External Trigger Filter.
-* This parameter must be a value between 0x00 and 0x0F.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
- u16 ExtTRGFilter)
-{
- u16 tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_Mask;
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)(ExtTRGFilter << 8);
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/*******************************************************************************
-* Function Name : TIM_PrescalerConfig
-* Description : Configures the TIMx Prescaler.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - Prescaler: specifies the Prescaler Register value
-* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
-* This parameter can be one of the following values:
-* - TIM_PSCReloadMode_Update: The Prescaler is loaded at
-* the update event.
-* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded
-* immediatly.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
-
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/*******************************************************************************
-* Function Name : TIM_CounterModeConfig
-* Description : Specifies the TIMx Counter Mode to be used.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_CounterMode: specifies the Counter Mode to be used
-* This parameter can be one of the following values:
-* - TIM_CounterMode_Up: TIM Up Counting Mode
-* - TIM_CounterMode_Down: TIM Down Counting Mode
-* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
-* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
-* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode)
-{
- u16 tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
-
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= CR1_CounterMode_Mask;
-
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
-
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectInputTrigger
-* Description : Selects the Input Trigger source
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_InputTriggerSource: The Input Trigger source.
-* This parameter can be one of the following values:
-* - TIM_TS_ITR0: Internal Trigger 0
-* - TIM_TS_ITR1: Internal Trigger 1
-* - TIM_TS_ITR2: Internal Trigger 2
-* - TIM_TS_ITR3: Internal Trigger 3
-* - TIM_TS_TI1F_ED: TI1 Edge Detector
-* - TIM_TS_TI1FP1: Filtered Timer Input 1
-* - TIM_TS_TI2FP2: Filtered Timer Input 2
-* - TIM_TS_ETRF: External Trigger input
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
-{
- u16 tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the TS Bits */
- tmpsmcr &= SMCR_TS_Mask;
-
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/*******************************************************************************
-* Function Name : TIM_EncoderInterfaceConfig
-* Description : Configures the TIMx Encoder Interface.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_EncoderMode: specifies the TIMx Encoder Mode.
-* This parameter can be one of the following values:
-* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge
-* depending on TI2FP2 level.
-* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge
-* depending on TI1FP1 level.
-* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and
-* TI2FP2 edges depending on the level of the other input.
-* - TIM_IC1Polarity: specifies the IC1 Polarity
-* This parmeter can be one of the following values:
-* - TIM_ICPolarity_Falling: IC Falling edge.
-* - TIM_ICPolarity_Rising: IC Rising edge.
-* - TIM_IC2Polarity: specifies the IC2 Polarity
-* This parmeter can be one of the following values:
-* - TIM_ICPolarity_Falling: IC Falling edge.
-* - TIM_ICPolarity_Rising: IC Rising edge.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
- u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
-{
- u16 tmpsmcr = 0;
- u16 tmpccmr1 = 0;
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= SMCR_SMS_Mask;
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
- tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
- tmpccer |= (TIM_IC1Polarity | (u16)(TIM_IC2Polarity << 4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ForcedOC1Config
-* Description : Forces the TIMx output 1 waveform to active or inactive level.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ForcedAction: specifies the forced Action to be set to
-* the output waveform.
-* This parameter can be one of the following values:
-* - TIM_ForcedAction_Active: Force active level on OC1REF
-* - TIM_ForcedAction_InActive: Force inactive level on
-* OC1REF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1M Bits */
- tmpccmr1 &= CCMR_OC13M_Mask;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ForcedOC2Config
-* Description : Forces the TIMx output 2 waveform to active or inactive level.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ForcedAction: specifies the forced Action to be set to
-* the output waveform.
-* This parameter can be one of the following values:
-* - TIM_ForcedAction_Active: Force active level on OC2REF
-* - TIM_ForcedAction_InActive: Force inactive level on
-* OC2REF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2M Bits */
- tmpccmr1 &= CCMR_OC24M_Mask;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= (u16)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ForcedOC3Config
-* Description : Forces the TIMx output 3 waveform to active or inactive level.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ForcedAction: specifies the forced Action to be set to
-* the output waveform.
-* This parameter can be one of the following values:
-* - TIM_ForcedAction_Active: Force active level on OC3REF
-* - TIM_ForcedAction_InActive: Force inactive level on
-* OC3REF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC1M Bits */
- tmpccmr2 &= CCMR_OC13M_Mask;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ForcedOC4Config
-* Description : Forces the TIMx output 4 waveform to active or inactive level.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ForcedAction: specifies the forced Action to be set to
-* the output waveform.
-* This parameter can be one of the following values:
-* - TIM_ForcedAction_Active: Force active level on OC4REF
-* - TIM_ForcedAction_InActive: Force inactive level on
-* OC4REF.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC2M Bits */
- tmpccmr2 &= CCMR_OC24M_Mask;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= (u16)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ARRPreloadConfig
-* Description : Enables or disables TIMx peripheral Preload register on ARR.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - NewState: new state of the TIMx peripheral Preload register
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= CR1_ARPE_Set;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= CR1_ARPE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectCOM
-* Description : Selects the TIM peripheral Commutation event.
-* Input :- TIMx: where x can be 1 or 8 to select the TIMx peripheral
-* - NewState: new state of the Commutation event.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= CR2_CCUS_Set;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= CR2_CCUS_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectCCDMA
-* Description : Selects the TIMx peripheral Capture Compare DMA source.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - NewState: new state of the Capture Compare DMA source
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= CR2_CCDS_Set;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= CR2_CCDS_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_CCPreloadControl
-* Description : Sets or Resets the TIM peripheral Capture Compare Preload
-* Control bit.
-* Input :- TIMx: where x can be 1 or 8 to select the TIMx peripheral
-* - NewState: new state of the Capture Compare Preload Control bit
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= CR2_CCPC_Set;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= CR2_CCPC_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC1PreloadConfig
-* Description : Enables or disables the TIMx peripheral Preload register on CCR1.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPreload: new state of the TIMx peripheral Preload
-* register
-* This parameter can be one of the following values:
-* - TIM_OCPreload_Enable
-* - TIM_OCPreload_Disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1PE Bit */
- tmpccmr1 &= CCMR_OC13PE_Reset;
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC2PreloadConfig
-* Description : Enables or disables the TIMx peripheral Preload register on CCR2.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPreload: new state of the TIMx peripheral Preload
-* register
-* This parameter can be one of the following values:
-* - TIM_OCPreload_Enable
-* - TIM_OCPreload_Disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2PE Bit */
- tmpccmr1 &= CCMR_OC24PE_Reset;
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (u16)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC3PreloadConfig
-* Description : Enables or disables the TIMx peripheral Preload register on CCR3.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPreload: new state of the TIMx peripheral Preload
-* register
-* This parameter can be one of the following values:
-* - TIM_OCPreload_Enable
-* - TIM_OCPreload_Disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3PE Bit */
- tmpccmr2 &= CCMR_OC13PE_Reset;
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC4PreloadConfig
-* Description : Enables or disables the TIMx peripheral Preload register on CCR4.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPreload: new state of the TIMx peripheral Preload
-* register
-* This parameter can be one of the following values:
-* - TIM_OCPreload_Enable
-* - TIM_OCPreload_Disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4PE Bit */
- tmpccmr2 &= CCMR_OC24PE_Reset;
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (u16)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC1FastConfig
-* Description : Configures the TIMx Output Compare 1 Fast feature.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCFast_Enable: TIM output compare fast enable
-* - TIM_OCFast_Disable: TIM output compare fast disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1FE Bit */
- tmpccmr1 &= CCMR_OC13FE_Reset;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC2FastConfig
-* Description : Configures the TIMx Output Compare 2 Fast feature.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCFast_Enable: TIM output compare fast enable
-* - TIM_OCFast_Disable: TIM output compare fast disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2FE Bit */
- tmpccmr1 &= CCMR_OC24FE_Reset;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (u16)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC3FastConfig
-* Description : Configures the TIMx Output Compare 3 Fast feature.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCFast_Enable: TIM output compare fast enable
-* - TIM_OCFast_Disable: TIM output compare fast disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3FE Bit */
- tmpccmr2 &= CCMR_OC13FE_Reset;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC4FastConfig
-* Description : Configures the TIMx Output Compare 4 Fast feature.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCFast_Enable: TIM output compare fast enable
-* - TIM_OCFast_Disable: TIM output compare fast disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4FE Bit */
- tmpccmr2 &= CCMR_OC24FE_Reset;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (u16)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ClearOC1Ref
-* Description : Clears or safeguards the OCREF1 signal on an external event
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCClear_Enable: TIM Output clear enable
-* - TIM_OCClear_Disable: TIM Output clear disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= CCMR_OC13CE_Reset;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ClearOC2Ref
-* Description : Clears or safeguards the OCREF2 signal on an external event
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCClear_Enable: TIM Output clear enable
-* - TIM_OCClear_Disable: TIM Output clear disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear)
-{
- u16 tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2CE Bit */
- tmpccmr1 &= CCMR_OC24CE_Reset;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (u16)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ClearOC3Ref
-* Description : Clears or safeguards the OCREF3 signal on an external event
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCClear_Enable: TIM Output clear enable
-* - TIM_OCClear_Disable: TIM Output clear disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3CE Bit */
- tmpccmr2 &= CCMR_OC13CE_Reset;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ClearOC4Ref
-* Description : Clears or safeguards the OCREF4 signal on an external event
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-* This parameter can be one of the following values:
-* - TIM_OCClear_Enable: TIM Output clear enable
-* - TIM_OCClear_Disable: TIM Output clear disable
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear)
-{
- u16 tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4CE Bit */
- tmpccmr2 &= CCMR_OC24CE_Reset;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (u16)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC1PolarityConfig
-* Description : Configures the TIMx channel 1 polarity.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPolarity: specifies the OC1 Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCPolarity_High: Output Compare active high
-* - TIM_OCPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1P Bit */
- tmpccer &= CCER_CC1P_Reset;
- tmpccer |= TIM_OCPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC1NPolarityConfig
-* Description : Configures the TIMx Channel 1N polarity.
-* Input : - TIMx: where x can be 1 or 8 to select the TIM peripheral.
-* - TIM_OCNPolarity: specifies the OC1N Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCNPolarity_High: Output Compare active high
-* - TIM_OCNPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1NP Bit */
- tmpccer &= CCER_CC1NP_Reset;
- tmpccer |= TIM_OCNPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC2PolarityConfig
-* Description : Configures the TIMx channel 2 polarity.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPolarity: specifies the OC2 Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCPolarity_High: Output Compare active high
-* - TIM_OCPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2P Bit */
- tmpccer &= CCER_CC2P_Reset;
- tmpccer |= (u16)(TIM_OCPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC2NPolarityConfig
-* Description : Configures the TIMx Channel 2N polarity.
-* Input : - TIMx: where x can be 1 or 8 to select the TIM peripheral.
-* - TIM_OCNPolarity: specifies the OC2N Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCNPolarity_High: Output Compare active high
-* - TIM_OCNPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2NP Bit */
- tmpccer &= CCER_CC2NP_Reset;
- tmpccer |= (u16)(TIM_OCNPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC3PolarityConfig
-* Description : Configures the TIMx channel 3 polarity.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPolarity: specifies the OC3 Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCPolarity_High: Output Compare active high
-* - TIM_OCPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3P Bit */
- tmpccer &= CCER_CC3P_Reset;
- tmpccer |= (u16)(TIM_OCPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC3NPolarityConfig
-* Description : Configures the TIMx Channel 3N polarity.
-* Input : - TIMx: where x can be 1 or 8 to select the TIM peripheral.
-* - TIM_OCNPolarity: specifies the OC3N Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCNPolarity_High: Output Compare active high
-* - TIM_OCNPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3NP Bit */
- tmpccer &= CCER_CC3NP_Reset;
- tmpccer |= (u16)(TIM_OCNPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_OC4PolarityConfig
-* Description : Configures the TIMx channel 4 polarity.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_OCPolarity: specifies the OC4 Polarity
-* This parmeter can be one of the following values:
-* - TIM_OCPolarity_High: Output Compare active high
-* - TIM_OCPolarity_Low: Output Compare active low
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
-{
- u16 tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC4P Bit */
- tmpccer &= CCER_CC4P_Reset;
- tmpccer |= (u16)(TIM_OCPolarity << 12);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TIM_CCxCmd
-* Description : Enables or disables the TIM Capture Compare Channel x.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_Channel: specifies the TIM Channel
-* This parmeter can be one of the following values:
-* - TIM_Channel_1: TIM Channel 1
-* - TIM_Channel_2: TIM Channel 2
-* - TIM_Channel_3: TIM Channel 3
-* - TIM_Channel_4: TIM Channel 4
-* - TIM_CCx: specifies the TIM Channel CCxE bit new state.
-* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (u16)(~((u16)(CCER_CCE_Set << TIM_Channel)));
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (u16)(TIM_CCx << TIM_Channel);
-}
-
-/*******************************************************************************
-* Function Name : TIM_CCxNCmd
-* Description : Enables or disables the TIM Capture Compare Channel xN.
-* Input :- TIMx: where x can be 1 or 8 to select the TIM peripheral.
-* - TIM_Channel: specifies the TIM Channel
-* This parmeter can be one of the following values:
-* - TIM_Channel_1: TIM Channel 1
-* - TIM_Channel_2: TIM Channel 2
-* - TIM_Channel_3: TIM Channel 3
-* - TIM_CCx: specifies the TIM Channel CCxNE bit new state.
-* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN)
-{
- /* Check the parameters */
- assert_param(IS_TIM_18_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (u16)(~((u16)(CCER_CCNE_Set << TIM_Channel)));
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (u16)(TIM_CCxN << TIM_Channel);
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectOCxM
-* Description : Selects the TIM Ouput Compare Mode.
-* This function disables the selected channel before changing
-* the Ouput Compare Mode. User has to enable this channel using
-* TIM_CCxCmd and TIM_CCxNCmd functions.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_Channel: specifies the TIM Channel
-* This parmeter can be one of the following values:
-* - TIM_Channel_1: TIM Channel 1
-* - TIM_Channel_2: TIM Channel 2
-* - TIM_Channel_3: TIM Channel 3
-* - TIM_Channel_4: TIM Channel 4
-* - TIM_OCMode: specifies the TIM Output Compare Mode.
-* This paramter can be one of the following values:
-* - TIM_OCMode_Timing
-* - TIM_OCMode_Active
-* - TIM_OCMode_Toggle
-* - TIM_OCMode_PWM1
-* - TIM_OCMode_PWM2
-* - TIM_ForcedAction_Active
-* - TIM_ForcedAction_InActive
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (u16)(~((u16)(CCER_CCE_Set << TIM_Channel)));
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- /* Reset the OCxM bits in the CCMRx register */
- *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + (TIM_Channel>>1))) &= CCMR_OC13M_Mask;
-
- /* Configure the OCxM bits in the CCMRx register */
- *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + (TIM_Channel>>1))) |= TIM_OCMode;
-
- }
- else
- {
- /* Reset the OCxM bits in the CCMRx register */
- *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + ((u16)(TIM_Channel - 4)>> 1))) &= CCMR_OC24M_Mask;
-
- /* Configure the OCxM bits in the CCMRx register */
- *((vu32 *)((*(u32*)&TIMx) + CCMR_Offset + ((u16)(TIM_Channel - 4)>> 1))) |= (u16)(TIM_OCMode << 8);
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_UpdateDisableConfig
-* Description : Enables or Disables the TIMx Update event.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - NewState: new state of the TIMx UDIS bit
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= CR1_UDIS_Set;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= CR1_UDIS_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_UpdateRequestConfig
-* Description : Configures the TIMx Update Request Interrupt source.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_UpdateSource: specifies the Update source.
-* This parameter can be one of the following values:
-* - TIM_UpdateSource_Regular
-* - TIM_UpdateSource_Global
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= CR1_URS_Set;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= CR1_URS_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectHallSensor
-* Description : Enables or disables the TIMx's Hall sensor interface.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-* - NewState: new state of the TIMx Hall sensor interface.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= CR2_TI1S_Set;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= CR2_TI1S_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectOnePulseMode
-* Description : Selects the TIMx's One Pulse Mode.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_OPMode: specifies the OPM Mode to be used.
-* This parameter can be one of the following values:
-* - TIM_OPMode_Single
-* - TIM_OPMode_Repetitive
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= CR1_OPM_Reset;
-
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectOutputTrigger
-* Description : Selects the TIMx Trigger Output Mode.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_TRGOSource: specifies the Trigger Output source.
-* This paramter can be as follow:
-* 1/ For TIM1 to TIM8:
-* - TIM_TRGOSource_Reset
-* - TIM_TRGOSource_Enable
-* - TIM_TRGOSource_Update
-* 2/ These parameters are available for all TIMx except
-* TIM6 and TIM7:
-* - TIM_TRGOSource_OC1
-* - TIM_TRGOSource_OC1Ref
-* - TIM_TRGOSource_OC2Ref
-* - TIM_TRGOSource_OC3Ref
-* - TIM_TRGOSource_OC4Ref
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
- assert_param(IS_TIM_PERIPH_TRGO(TIMx, TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= CR2_MMS_Mask;
-
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectSlaveMode
-* Description : Selects the TIMx Slave Mode.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_SlaveMode: specifies the Timer Slave Mode.
-* This paramter can be one of the following values:
-* - TIM_SlaveMode_Reset
-* - TIM_SlaveMode_Gated
-* - TIM_SlaveMode_Trigger
-* - TIM_SlaveMode_External1
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= SMCR_SMS_Mask;
-
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SelectMasterSlaveMode
-* Description : Sets or Resets the TIMx Master/Slave Mode.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
-* This paramter can be one of the following values:
-* - TIM_MasterSlaveMode_Enable: synchronization between the
-* current timer and its slaves (through TRGO).
-* - TIM_MasterSlaveMode_Disable: No action
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= SMCR_MSM_Reset;
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetCounter
-* Description : Sets the TIMx Counter Register value
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - Counter: specifies the Counter register new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetAutoreload
-* Description : Sets the TIMx Autoreload Register value
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - Autoreload: specifies the Autoreload register new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetCompare1
-* Description : Sets the TIMx Capture Compare1 Register value
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - Compare1: specifies the Capture Compare1 register new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetCompare2
-* Description : Sets the TIMx Capture Compare2 Register value
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - Compare2: specifies the Capture Compare2 register new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetCompare3
-* Description : Sets the TIMx Capture Compare3 Register value
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - Compare3: specifies the Capture Compare3 register new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetCompare4
-* Description : Sets the TIMx Capture Compare4 Register value
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - Compare4: specifies the Capture Compare4 register new value.
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetIC1Prescaler
-* Description : Sets the TIMx Input Capture 1 prescaler.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPSC: specifies the Input Capture1 prescaler
-* new value.
-* This parameter can be one of the following values:
-* - TIM_ICPSC_DIV1: no prescaler
-* - TIM_ICPSC_DIV2: capture is done once every 2 events
-* - TIM_ICPSC_DIV4: capture is done once every 4 events
-* - TIM_ICPSC_DIV8: capture is done once every 8 events
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
-
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetIC2Prescaler
-* Description : Sets the TIMx Input Capture 2 prescaler.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPSC: specifies the Input Capture2 prescaler
-* new value.
-* This parameter can be one of the following values:
-* - TIM_ICPSC_DIV1: no prescaler
-* - TIM_ICPSC_DIV2: capture is done once every 2 events
-* - TIM_ICPSC_DIV4: capture is done once every 4 events
-* - TIM_ICPSC_DIV8: capture is done once every 8 events
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
-
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (u16)(TIM_ICPSC << 8);
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetIC3Prescaler
-* Description : Sets the TIMx Input Capture 3 prescaler.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPSC: specifies the Input Capture3 prescaler
-* new value.
-* This parameter can be one of the following values:
-* - TIM_ICPSC_DIV1: no prescaler
-* - TIM_ICPSC_DIV2: capture is done once every 2 events
-* - TIM_ICPSC_DIV4: capture is done once every 4 events
-* - TIM_ICPSC_DIV8: capture is done once every 8 events
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
-
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetIC4Prescaler
-* Description : Sets the TIMx Input Capture 4 prescaler.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPSC: specifies the Input Capture4 prescaler
-* new value.
-* This parameter can be one of the following values:
-* - TIM_ICPSC_DIV1: no prescaler
-* - TIM_ICPSC_DIV2: capture is done once every 2 events
-* - TIM_ICPSC_DIV4: capture is done once every 4 events
-* - TIM_ICPSC_DIV8: capture is done once every 8 events
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
-
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (u16)(TIM_ICPSC << 8);
-}
-
-/*******************************************************************************
-* Function Name : TIM_SetClockDivision
-* Description : Sets the TIMx Clock Division value.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_CKD: specifies the clock division value.
-* This parameter can be one of the following value:
-* - TIM_CKD_DIV1: TDTS = Tck_tim
-* - TIM_CKD_DIV2: TDTS = 2*Tck_tim
-* - TIM_CKD_DIV4: TDTS = 4*Tck_tim
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= CR1_CKD_Mask;
-
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-/*******************************************************************************
-* Function Name : TIM_GetCapture1
-* Description : Gets the TIMx Input Capture 1 value.
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* Output : None
-* Return : Capture Compare 1 Register value.
-*******************************************************************************/
-u16 TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetCapture2
-* Description : Gets the TIMx Input Capture 2 value.
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* Output : None
-* Return : Capture Compare 2 Register value.
-*******************************************************************************/
-u16 TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetCapture3
-* Description : Gets the TIMx Input Capture 3 value.
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* Output : None
-* Return : Capture Compare 3 Register value.
-*******************************************************************************/
-u16 TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetCapture4
-* Description : Gets the TIMx Input Capture 4 value.
-* Input : TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* Output : None
-* Return : Capture Compare 4 Register value.
-*******************************************************************************/
-u16 TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_123458_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetCounter
-* Description : Gets the TIMx Counter value.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* Output : None
-* Return : Counter Register value.
-*******************************************************************************/
-u16 TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetPrescaler
-* Description : Gets the TIMx Prescaler value.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* Output : None
-* Return : Prescaler Register value.
-*******************************************************************************/
-u16 TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetFlagStatus
-* Description : Checks whether the specified TIM flag is set or not.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - TIM_FLAG_Update: TIM update Flag
-* - TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-* - TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-* - TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-* - TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-* - TIM_FLAG_COM: TIM Commutation Flag
-* - TIM_FLAG_Trigger: TIM Trigger Flag
-* - TIM_FLAG_Break: TIM Break Flag
-* - TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-* - TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-* - TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-* - TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-* Output : None
-* Return : The new state of TIM_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
- assert_param(IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG));
-
- if ((TIMx->SR & TIM_FLAG) != (u16)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ClearFlag
-* Description : Clears the TIMx's pending flags.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_FLAG: specifies the flag bit to clear.
-* This parameter can be any combination of the following values:
-* - TIM_FLAG_Update: TIM update Flag
-* - TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-* - TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-* - TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-* - TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-* - TIM_FLAG_COM: TIM Commutation Flag
-* - TIM_FLAG_Trigger: TIM Trigger Flag
-* - TIM_FLAG_Break: TIM Break Flag
-* - TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-* - TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-* - TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-* - TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_CLEAR_FLAG(TIMx, TIM_FLAG));
-
- /* Clear the flags */
- TIMx->SR = (u16)~TIM_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : TIM_GetITStatus
-* Description : Checks whether the TIM interrupt has occurred or not.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_IT: specifies the TIM interrupt source to check.
-* This parameter can be one of the following values:
-* - TIM_IT_Update: TIM update Interrupt source
-* - TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-* - TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-* - TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-* - TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-* - TIM_IT_COM: TIM Commutation Interrupt
-* source
-* - TIM_IT_Trigger: TIM Trigger Interrupt source
-* - TIM_IT_Break: TIM Break Interrupt source
-* Output : None
-* Return : The new state of the TIM_IT(SET or RESET).
-*******************************************************************************/
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)
-{
- ITStatus bitstatus = RESET;
- u16 itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
- assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
-
- if ((itstatus != (u16)RESET) && (itenable != (u16)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : TIM_ClearITPendingBit
-* Description : Clears the TIMx's interrupt pending bits.
-* Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
-* - TIM_IT: specifies the pending bit to clear.
-* This parameter can be any combination of the following values:
-* - TIM_IT_Update: TIM1 update Interrupt source
-* - TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-* - TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-* - TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-* - TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-* - TIM_IT_COM: TIM Commutation Interrupt
-* source
-* - TIM_IT_Trigger: TIM Trigger Interrupt source
-* - TIM_IT_Break: TIM Break Interrupt source
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (u16)~TIM_IT;
-}
-
-/*******************************************************************************
-* Function Name : TI1_Config
-* Description : Configure the TI1 as Input.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPolarity : The Input Polarity.
-* This parameter can be one of the following values:
-* - TIM_ICPolarity_Rising
-* - TIM_ICPolarity_Falling
-* - TIM_ICSelection: specifies the input to be used.
-* This parameter can be one of the following values:
-* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to
-* be connected to IC1.
-* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to
-* be connected to IC2.
-* - TIM_ICSelection_TRC: TIM Input 1 is selected to be
-* connected to TRC.
-* - TIM_ICFilter: Specifies the Input Capture Filter.
-* This parameter must be a value between 0x00 and 0x0F.
-* Output : None
-* Return : None
-*******************************************************************************/
-static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter)
-{
- u16 tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= CCER_CC1E_Reset;
-
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input and set the filter */
- tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
- tmpccmr1 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= CCER_CC1P_Reset;
- tmpccer |= TIM_ICPolarity | CCER_CC1E_Set;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TI2_Config
-* Description : Configure the TI2 as Input.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPolarity : The Input Polarity.
-* This parameter can be one of the following values:
-* - TIM_ICPolarity_Rising
-* - TIM_ICPolarity_Falling
-* - TIM_ICSelection: specifies the input to be used.
-* This parameter can be one of the following values:
-* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to
-* be connected to IC2.
-* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to
-* be connected to IC1.
-* - TIM_ICSelection_TRC: TIM Input 2 is selected to be
-* connected to TRC.
-* - TIM_ICFilter: Specifies the Input Capture Filter.
-* This parameter must be a value between 0x00 and 0x0F.
-* Output : None
-* Return : None
-*******************************************************************************/
-static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter)
-{
- u16 tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= CCER_CC2E_Reset;
-
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (u16)(TIM_ICPolarity << 4);
-
- /* Select the Input and set the filter */
- tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
- tmpccmr1 |= (u16)(TIM_ICFilter << 12);
- tmpccmr1 |= (u16)(TIM_ICSelection << 8);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= CCER_CC2P_Reset;
- tmpccer |= tmp | CCER_CC2E_Set;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TI3_Config
-* Description : Configure the TI3 as Input.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPolarity : The Input Polarity.
-* This parameter can be one of the following values:
-* - TIM_ICPolarity_Rising
-* - TIM_ICPolarity_Falling
-* - TIM_ICSelection: specifies the input to be used.
-* This parameter can be one of the following values:
-* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to
-* be connected to IC3.
-* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to
-* be connected to IC4.
-* - TIM_ICSelection_TRC: TIM Input 3 is selected to be
-* connected to TRC.
-* - TIM_ICFilter: Specifies the Input Capture Filter.
-* This parameter must be a value between 0x00 and 0x0F.
-* Output : None
-* Return : None
-*******************************************************************************/
-static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter)
-{
- u16 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= CCER_CC3E_Reset;
-
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (u16)(TIM_ICPolarity << 8);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
- tmpccmr2 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= CCER_CC3P_Reset;
- tmpccer |= tmp | CCER_CC3E_Set;
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/*******************************************************************************
-* Function Name : TI4_Config
-* Description : Configure the TI1 as Input.
-* Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
-* peripheral.
-* - TIM_ICPolarity : The Input Polarity.
-* This parameter can be one of the following values:
-* - TIM_ICPolarity_Rising
-* - TIM_ICPolarity_Falling
-* - TIM_ICSelection: specifies the input to be used.
-* This parameter can be one of the following values:
-* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to
-* be connected to IC4.
-* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to
-* be connected to IC3.
-* - TIM_ICSelection_TRC: TIM Input 4 is selected to be
-* connected to TRC.
-* - TIM_ICFilter: Specifies the Input Capture Filter.
-* This parameter must be a value between 0x00 and 0x0F.
-* Output : None
-* Return : None
-*******************************************************************************/
-static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
- u16 TIM_ICFilter)
-{
- u16 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= CCER_CC4E_Reset;
-
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (u16)(TIM_ICPolarity << 12);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
- tmpccmr2 |= (u16)(TIM_ICSelection << 8) | (u16)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= CCER_CC4P_Reset;
- tmpccer |= tmp | CCER_CC4E_Set;
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the TIM firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @defgroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define CR1_CEN_Set ((uint16_t)0x0001)
+#define CR1_CEN_Reset ((uint16_t)0x03FE)
+#define CR1_UDIS_Set ((uint16_t)0x0002)
+#define CR1_UDIS_Reset ((uint16_t)0x03FD)
+#define CR1_URS_Set ((uint16_t)0x0004)
+#define CR1_URS_Reset ((uint16_t)0x03FB)
+#define CR1_OPM_Reset ((uint16_t)0x03F7)
+#define CR1_CounterMode_Mask ((uint16_t)0x038F)
+#define CR1_ARPE_Set ((uint16_t)0x0080)
+#define CR1_ARPE_Reset ((uint16_t)0x037F)
+#define CR1_CKD_Mask ((uint16_t)0x00FF)
+#define CR2_CCPC_Set ((uint16_t)0x0001)
+#define CR2_CCPC_Reset ((uint16_t)0xFFFE)
+#define CR2_CCUS_Set ((uint16_t)0x0004)
+#define CR2_CCUS_Reset ((uint16_t)0xFFFB)
+#define CR2_CCDS_Set ((uint16_t)0x0008)
+#define CR2_CCDS_Reset ((uint16_t)0xFFF7)
+#define CR2_MMS_Mask ((uint16_t)0xFF8F)
+#define CR2_TI1S_Set ((uint16_t)0x0080)
+#define CR2_TI1S_Reset ((uint16_t)0xFF7F)
+#define CR2_OIS1_Reset ((uint16_t)0x7EFF)
+#define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
+#define CR2_OIS2_Reset ((uint16_t)0x7BFF)
+#define CR2_OIS2N_Reset ((uint16_t)0x77FF)
+#define CR2_OIS3_Reset ((uint16_t)0x6FFF)
+#define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
+#define CR2_OIS4_Reset ((uint16_t)0x3FFF)
+#define SMCR_SMS_Mask ((uint16_t)0xFFF8)
+#define SMCR_ETR_Mask ((uint16_t)0x00FF)
+#define SMCR_TS_Mask ((uint16_t)0xFF8F)
+#define SMCR_MSM_Reset ((uint16_t)0xFF7F)
+#define SMCR_ECE_Set ((uint16_t)0x4000)
+#define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
+#define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
+#define CCMR_TI13Direct_Set ((uint16_t)0x0001)
+#define CCMR_TI24Direct_Set ((uint16_t)0x0100)
+#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
+#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
+#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
+#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
+#define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
+#define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
+#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
+#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
+#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
+#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
+#define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
+#define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
+#define CCMR_Offset ((uint16_t)0x0018)
+#define CCER_CCE_Set ((uint16_t)0x0001)
+#define CCER_CCNE_Set ((uint16_t)0x0004)
+#define CCER_CC1P_Reset ((uint16_t)0xFFFD)
+#define CCER_CC2P_Reset ((uint16_t)0xFFDF)
+#define CCER_CC3P_Reset ((uint16_t)0xFDFF)
+#define CCER_CC4P_Reset ((uint16_t)0xDFFF)
+#define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
+#define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
+#define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
+#define CCER_CC1E_Set ((uint16_t)0x0001)
+#define CCER_CC1E_Reset ((uint16_t)0xFFFE)
+#define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
+#define CCER_CC2E_Set ((uint16_t)0x0010)
+#define CCER_CC2E_Reset ((uint16_t)0xFFEF)
+#define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
+#define CCER_CC3E_Set ((uint16_t)0x0100)
+#define CCER_CC3E_Reset ((uint16_t)0xFEFF)
+#define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
+#define CCER_CC4E_Set ((uint16_t)0x1000)
+#define CCER_CC4E_Reset ((uint16_t)0xEFFF)
+#define BDTR_MOE_Set ((uint16_t)0x8000)
+#define BDTR_MOE_Reset ((uint16_t)0x7FFF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+ }
+ else
+ {
+ if (TIMx == TIM8)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+ * structure that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+ /* Select the Counter Mode and set the clock division */
+ TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+ TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision |
+ TIM_TimeBaseInitStruct->TIM_CounterMode;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler value immediatly */
+ TIMx->EGR = TIM_PSCReloadMode_Immediate;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= CCER_CC1E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= CCMR_OC13M_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC1P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= CCER_CC1NP_Reset;
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= CCER_CC1NE_Reset;
+
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+ /* Reset the Ouput Compare and Output Compare N IDLE State */
+ tmpcr2 &= CR2_OIS1_Reset;
+ tmpcr2 &= CR2_OIS1N_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= CCER_CC2E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= CCMR_OC24M_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC2P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= CCER_CC2NP_Reset;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= CCER_CC2NE_Reset;
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+ /* Reset the Ouput Compare and Output Compare N IDLE State */
+ tmpcr2 &= CR2_OIS2_Reset;
+ tmpcr2 &= CR2_OIS2N_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= CCER_CC3E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= CCMR_OC13M_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC3P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= CCER_CC3NP_Reset;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= CCER_CC3NE_Reset;
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+ /* Reset the Ouput Compare and Output Compare N IDLE State */
+ tmpcr2 &= CR2_OIS3_Reset;
+ tmpcr2 &= CR2_OIS3N_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCER &= CCER_CC4E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= CCMR_OC24M_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC4P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Ouput Compare IDLE State */
+ tmpcr2 &= CR2_OIS4_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ /* TI3 Configuration */
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI4 Configuration */
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+ {
+ icoppositepolarity = TIM_ICPolarity_Falling;
+ }
+ else
+ {
+ icoppositepolarity = TIM_ICPolarity_Rising;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+ {
+ icoppositeselection = TIM_ICSelection_IndirectTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_ICSelection_DirectTI;
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI2 Configuration */
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI1 Configuration */
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval None
+ */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
+ * @param NewState: new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= CR1_CEN_Set;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= CR1_CEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BDTR |= BDTR_MOE_Set;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BDTR &= BDTR_MOE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource: specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EventSource_Update: Timer update Event source
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM: Timer COM event source
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source
+ * @arg TIM_EventSource_Break: Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx’s DMA interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_DMABase: DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+ * TIM_DMABase_DCR.
+ * @param TIM_DMABurstLength: DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
+ * @retval None
+ */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx’s DMA Requests.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_DMASource: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_Update: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DIER |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx interrnal Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= SMCR_SMS_Mask;
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ITRSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @param TIM_TS_ITR0: Internal Trigger 0
+ * @param TIM_TS_ITR1: Internal Trigger 1
+ * @param TIM_TS_ITR2: Internal Trigger 2
+ * @param TIM_TS_ITR3: Internal Trigger 3
+ * @retval None
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+ * @param TIM_ICPolarity: specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param ICFilter : specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ * @retval None
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert_param(IS_TIM_IC_FILTER(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the SMS Bits */
+ tmpsmcr &= SMCR_SMS_Mask;
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SlaveMode_External1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= SMCR_TS_Mask;
+ tmpsmcr |= TIM_TS_ETRF;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= SMCR_ECE_Set;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCR_ETR_Mask;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler: specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+ * @retval None
+ */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CounterMode: specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+ * @retval None
+ */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+ uint16_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+ tmpcr1 = TIMx->CR1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= CR1_CounterMode_Mask;
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+ /* Write to TIMx CR1 register */
+ TIMx->CR1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= SMCR_TS_Mask;
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @retval None
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= SMCR_SMS_Mask;
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+ * @retval None
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= CCMR_OC13M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+ * @retval None
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= CCMR_OC24M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+ * @retval None
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= CCMR_OC13M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+ * @retval None
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= CCMR_OC24M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ TIMx->CR1 |= CR1_ARPE_Set;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ TIMx->CR1 &= CR1_ARPE_Reset;
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CR2 |= CR2_CCUS_Set;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CR2 &= CR2_CCUS_Reset;
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CR2 |= CR2_CCDS_Set;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CR2 &= CR2_CCDS_Reset;
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CR2 |= CR2_CCPC_Set;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CR2 &= CR2_CCPC_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= CCMR_OC13PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= CCMR_OC24PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= CCMR_OC13PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= CCMR_OC24PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= CCMR_OC13FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= CCMR_OC24FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= CCMR_OC13FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= CCMR_OC24FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= CCMR_OC13CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= CCMR_OC24CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= CCMR_OC13CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= CCMR_OC24CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC1 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= CCER_CC1P_Reset;
+ tmpccer |= TIM_OCPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= CCER_CC1NP_Reset;
+ tmpccer |= TIM_OCNPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC2 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= CCER_CC2P_Reset;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= CCER_CC2NP_Reset;
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC3 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= CCER_CC3P_Reset;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= CCER_CC3NP_Reset;
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC4 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= CCER_CC4P_Reset;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parmeter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCX(TIM_CCx));
+
+ tmp = CCER_CCE_Set << TIM_Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t)~ tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parmeter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+ * @retval None
+ */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+ tmp = CCER_CCNE_Set << TIM_Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+ * @brief Selects the TIM Ouput Compare Mode.
+ * @note This function disables the selected channel before changing the Ouput
+ * Compare Mode.
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parmeter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.
+ * This paramter can be one of the following values:
+ * @arg TIM_OCMode_Timing
+ * @arg TIM_OCMode_Active
+ * @arg TIM_OCMode_Toggle
+ * @arg TIM_OCMode_PWM1
+ * @arg TIM_OCMode_PWM2
+ * @arg TIM_ForcedAction_Active
+ * @arg TIM_ForcedAction_InActive
+ * @retval None
+ */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_OCM(TIM_OCMode));
+
+ tmp = (uint32_t) TIMx;
+ tmp += CCMR_Offset;
+
+ tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp1;
+
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+ {
+ tmp += (TIM_Channel>>1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC13M_Mask;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= TIM_OCMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC24M_Mask;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CR1 |= CR1_UDIS_Set;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CR1 &= CR1_UDIS_Reset;
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_UpdateSource: specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+ * @retval None
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)
+ {
+ /* Set the URS Bit */
+ TIMx->CR1 |= CR1_URS_Set;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CR1 &= CR1_URS_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx’s Hall sensor interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= CR2_TI1S_Set;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= CR2_TI1S_Reset;
+ }
+}
+
+/**
+ * @brief Selects the TIMx’s One Pulse Mode.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode: specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMode_Single
+ * @arg TIM_OPMode_Repetitive
+ * @retval None
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CR1 &= CR1_OPM_Reset;
+ /* Configure the OPM Mode */
+ TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource: specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= CR2_MMS_Mask;
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.
+ * This paramter can be one of the following values:
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+ * @retval None
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCR &= SMCR_SMS_Mask;
+ /* Select the Slave Mode */
+ TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+ * This paramter can be one of the following values:
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MasterSlaveMode_Disable: No action
+ * @retval None
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCR &= SMCR_MSM_Reset;
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter: specifies the Counter register new value.
+ * @retval None
+ */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload: specifies the Autoreload register new value.
+ * @retval None
+ */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare1: specifies the Capture Compare1 register new value.
+ * @retval None
+ */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare2: specifies the Capture Compare2 register new value.
+ * @retval None
+ */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3: specifies the Capture Compare3 register new value.
+ * @retval None
+ */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4: specifies the Capture Compare4 register new value.
+ * @retval None
+ */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
+ /* Set the IC1PSC value */
+ TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
+ /* Set the IC2PSC value */
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
+ /* Set the IC3PSC value */
+ TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
+ /* Set the IC4PSC value */
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CKD: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+ * @retval None
+ */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CR1 &= CR1_CKD_Mask;
+ /* Set the CKD value */
+ TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @retval Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @retval Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+ * @retval The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ * @retval The new state of the TIM_IT(SET or RESET).
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_IT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT: specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM1 update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= CCER_CC1E_Reset;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= CCER_CC1P_Reset;
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set);
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= CCER_CC2E_Reset;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= CCER_CC2P_Reset;
+ tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set);
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= CCER_CC3E_Reset;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= CCER_CC3P_Reset;
+ tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set);
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= CCER_CC4E_Reset;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 12);
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= CCER_CC4P_Reset;
+ tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set);
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_usart.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_usart.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_usart.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,1001 +1,967 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_usart.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the USART firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_usart.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* USART UE Mask */
-#define CR1_UE_Set ((u16)0x2000) /* USART Enable Mask */
-#define CR1_UE_Reset ((u16)0xDFFF) /* USART Disable Mask */
-
-/* USART WakeUp Method */
-#define CR1_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */
-
-/* USART RWU Mask */
-#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */
-#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */
-
-#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */
-
-#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */
-
-#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */
-
-/* USART LIN Mask */
-#define CR2_LINEN_Set ((u16)0x4000) /* USART LIN Enable Mask */
-#define CR2_LINEN_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */
-
-/* USART LIN Break detection */
-#define CR2_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */
-
-#define CR2_STOP_CLEAR_Mask ((u16)0xCFFF) /* USART CR2 STOP Bits Mask */
-#define CR2_CLOCK_CLEAR_Mask ((u16)0xF0FF) /* USART CR2 Clock Mask */
-
-/* USART SC Mask */
-#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */
-#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */
-
-/* USART SC NACK Mask */
-#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */
-#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */
-
-/* USART Half-Duplex Mask */
-#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */
-#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */
-
-/* USART IrDA Mask */
-#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */
-
-#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */
-
-/* USART IrDA Mask */
-#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */
-#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */
-
-#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */
-#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */
-
-#define IT_Mask ((u16)0x001F) /* USART Interrupt Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : USART_DeInit
-* Description : Deinitializes the USARTx peripheral registers to their
-* default reset values.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- switch (*(u32*)&USARTx)
- {
- case USART1_BASE:
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- break;
-
- case USART2_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- break;
-
- case USART3_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- break;
-
- case UART4_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- break;
-
- case UART5_BASE:
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- break;
-
- default:
- break;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_Init
-* Description : Initializes the USARTx peripheral according to the specified
-* parameters in the USART_InitStruct .
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_InitStruct: pointer to a USART_InitTypeDef structure
-* that contains the configuration information for the
-* specified USART peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- u32 tmpreg = 0x00, apbclock = 0x00;
- u32 integerdivider = 0x00;
- u32 fractionaldivider = 0x00;
- u32 usartxbase = 0;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
- /* The hardware flow control is available only for USART1, USART2 and USART3 */
- assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl));
-
- usartxbase = (*(u32*)&USARTx);
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= CR2_STOP_CLEAR_Mask;
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (u32)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (u16)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= CR1_CLEAR_Mask;
-
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = (u16)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= CR3_CLEAR_Mask;
-
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = (u16)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
- if (usartxbase == USART1_BASE)
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
- tmpreg = (integerdivider / 0x64) << 0x04;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
- tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
-
- /* Write to USART BRR */
- USARTx->BRR = (u16)tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : USART_StructInit
-* Description : Fills each USART_InitStruct member with its default value.
-* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure
-* which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/*******************************************************************************
-* Function Name : USART_ClockInit
-* Description : Initializes the USARTx peripheral Clock according to the
-* specified parameters in the USART_ClockInitStruct .
-* Input : - USARTx: where x can be 1, 2, 3 to select the USART peripheral.
-* Note: The Smart Card mode is not available for UART4 and UART5.
-* - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-* structure that contains the configuration information for
-* the specified USART peripheral.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- u32 tmpreg = 0x00;
-
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= CR2_CLOCK_CLEAR_Mask;
-
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (u32)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (u16)tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : USART_ClockStructInit
-* Description : Fills each USART_ClockInitStruct member with its default value.
-* Input : - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-* structure which will be initialized.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/*******************************************************************************
-* Function Name : USART_Cmd
-* Description : Enables or disables the specified USART peripheral.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* : - NewState: new state of the USARTx peripheral.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= CR1_UE_Set;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= CR1_UE_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_ITConfig
-* Description : Enables or disables the specified USART interrupts.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_IT: specifies the USART interrupt sources to be
-* enabled or disabled.
-* This parameter can be one of the following values:
-* - USART_IT_CTS: CTS change interrupt (not available for
-* UART4 and UART5)
-* - USART_IT_LBD: LIN Break detection interrupt
-* - USART_IT_TXE: Tansmit Data Register empty interrupt
-* - USART_IT_TC: Transmission complete interrupt
-* - USART_IT_RXNE: Receive Data register not empty
-* interrupt
-* - USART_IT_IDLE: Idle line detection interrupt
-* - USART_IT_PE: Parity Error interrupt
-* - USART_IT_ERR: Error interrupt(Frame error, noise
-* error, overrun error)
-* - NewState: new state of the specified USARTx interrupts.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)
-{
- u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- u32 usartxbase = 0x00;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- usartxbase = (*(u32*)&(USARTx));
-
- /* Get the USART register index */
- usartreg = (((u8)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_Mask;
-
- itmask = (((u32)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(vu32*)usartxbase |= itmask;
- }
- else
- {
- *(vu32*)usartxbase &= ~itmask;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_DMACmd
-* Description : Enables or disables the USART's DMA interface.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3 or UART4.
-* Note: The DMA mode is not available for UART5.
-* - USART_DMAReq: specifies the DMA request.
-* This parameter can be any combination of the following values:
-* - USART_DMAReq_Tx: USART DMA transmit request
-* - USART_DMAReq_Rx: USART DMA receive request
-* - NewState: new state of the DMA Request sources.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1234_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (u16)~USART_DMAReq;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_SetAddress
-* Description : Sets the address of the USART node.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_Address: Indicates the address of the USART node.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= CR2_Address_Mask;
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/*******************************************************************************
-* Function Name : USART_WakeUpConfig
-* Description : Selects the USART WakeUp method.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_WakeUp: specifies the USART wakeup method.
-* This parameter can be one of the following values:
-* - USART_WakeUp_IdleLine: WakeUp by an idle line detection
-* - USART_WakeUp_AddressMark: WakeUp by an address mark
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= CR1_WAKE_Mask;
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/*******************************************************************************
-* Function Name : USART_ReceiverWakeUpCmd
-* Description : Determines if the USART is in mute mode or not.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - NewState: new state of the USART mute mode.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= CR1_RWU_Set;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= CR1_RWU_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_LINBreakDetectLengthConfig
-* Description : Sets the USART LIN Break detection length.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_LINBreakDetectLength: specifies the LIN break
-* detection length.
-* This parameter can be one of the following values:
-* - USART_LINBreakDetectLength_10b: 10-bit break detection
-* - USART_LINBreakDetectLength_11b: 11-bit break detection
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= CR2_LBDL_Mask;
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/*******************************************************************************
-* Function Name : USART_LINCmd
-* Description : Enables or disables the USART's LIN mode.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - NewState: new state of the USART LIN mode.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= CR2_LINEN_Set;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= CR2_LINEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_SendData
-* Description : Transmits single data through the USARTx peripheral.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - Data: the data to transmit.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SendData(USART_TypeDef* USARTx, u16 Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (u16)0x01FF);
-}
-
-/*******************************************************************************
-* Function Name : USART_ReceiveData
-* Description : Returns the most recent received data by the USARTx peripheral.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* Output : None
-* Return : The received data.
-*******************************************************************************/
-u16 USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (u16)(USARTx->DR & (u16)0x01FF);
-}
-
-/*******************************************************************************
-* Function Name : USART_SendBreak
-* Description : Transmits break characters.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= CR1_SBK_Set;
-}
-
-/*******************************************************************************
-* Function Name : USART_SetGuardTime
-* Description : Sets the specified USART guard time.
-* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
-* peripheral.
-* Note: The guard time bits are not available for UART4 and UART5.
-* - USART_GuardTime: specifies the guard time.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= GTPR_LSB_Mask;
- /* Set the USART guard time */
- USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08);
-}
-
-/*******************************************************************************
-* Function Name : USART_SetPrescaler
-* Description : Sets the system clock prescaler.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* Note: The function is used for IrDA mode with UART4 and UART5.
-* - USART_Prescaler: specifies the prescaler clock.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= GTPR_MSB_Mask;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/*******************************************************************************
-* Function Name : USART_SmartCardCmd
-* Description : Enables or disables the USART's Smart Card mode.
-* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
-* peripheral.
-* Note: The Smart Card mode is not available for UART4 and UART5.
-* - NewState: new state of the Smart Card mode.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= CR3_SCEN_Set;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= CR3_SCEN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_SmartCardNACKCmd
-* Description : Enables or disables NACK transmission.
-* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
-* peripheral.
-* Note: The Smart Card mode is not available for UART4 and UART5.
-* - NewState: new state of the NACK transmission.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= CR3_NACK_Set;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= CR3_NACK_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_HalfDuplexCmd
-* Description : Enables or disables the USART's Half Duplex communication.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - NewState: new state of the USART Communication.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= CR3_HDSEL_Set;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= CR3_HDSEL_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_IrDAConfig
-* Description : Configures the USART's IrDA interface.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_IrDAMode: specifies the IrDA mode.
-* This parameter can be one of the following values:
-* - USART_IrDAMode_LowPower
-* - USART_IrDAMode_Normal
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= CR3_IRLP_Mask;
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/*******************************************************************************
-* Function Name : USART_IrDACmd
-* Description : Enables or disables the USART's IrDA interface.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - NewState: new state of the IrDA mode.
-* This parameter can be: ENABLE or DISABLE.
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= CR3_IREN_Set;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= CR3_IREN_Reset;
- }
-}
-
-/*******************************************************************************
-* Function Name : USART_GetFlagStatus
-* Description : Checks whether the specified USART flag is set or not.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_FLAG: specifies the flag to check.
-* This parameter can be one of the following values:
-* - USART_FLAG_CTS: CTS Change flag (not available for
-* UART4 and UART5)
-* - USART_FLAG_LBD: LIN Break detection flag
-* - USART_FLAG_TXE: Transmit data register empty flag
-* - USART_FLAG_TC: Transmission Complete flag
-* - USART_FLAG_RXNE: Receive data register not empty flag
-* - USART_FLAG_IDLE: Idle Line detection flag
-* - USART_FLAG_ORE: OverRun Error flag
-* - USART_FLAG_NE: Noise Error flag
-* - USART_FLAG_FE: Framing Error flag
-* - USART_FLAG_PE: Parity Error flag
-* Output : None
-* Return : The new state of USART_FLAG (SET or RESET).
-*******************************************************************************/
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
- assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */
-
- if ((USARTx->SR & USART_FLAG) != (u16)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : USART_ClearFlag
-* Description : Clears the USARTx's pending flags.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_FLAG: specifies the flag to clear.
-* This parameter can be any combination of the following values:
-* - USART_FLAG_CTS: CTS Change flag (not available for
-* UART4 and UART5).
-* - USART_FLAG_LBD: LIN Break detection flag.
-* - USART_FLAG_TC: Transmission Complete flag.
-* - USART_FLAG_RXNE: Receive data register not empty flag.
-*
-* Notes:
-* - PE (Parity error), FE (Framing error), NE (Noise error),
-* ORE (OverRun error) and IDLE (Idle line detected)
-* flags are cleared by software sequence: a read
-* operation to USART_SR register (USART_GetFlagStatus())
-* followed by a read operation to USART_DR register
-* (USART_ReceiveData()).
-* - RXNE flag can be also cleared by a read to the
-* USART_DR register (USART_ReceiveData()).
-* - TC flag can be also cleared by software sequence: a
-* read operation to USART_SR register
-* (USART_GetFlagStatus()) followed by a write operation
-* to USART_DR register (USART_SendData()).
-* - TXE flag is cleared only by a write to the USART_DR
-* register (USART_SendData()).
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
- assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */
-
- USARTx->SR = (u16)~USART_FLAG;
-}
-
-/*******************************************************************************
-* Function Name : USART_GetITStatus
-* Description : Checks whether the specified USART interrupt has occurred or not.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_IT: specifies the USART interrupt source to check.
-* This parameter can be one of the following values:
-* - USART_IT_CTS: CTS change interrupt (not available for
-* UART4 and UART5)
-* - USART_IT_LBD: LIN Break detection interrupt
-* - USART_IT_TXE: Tansmit Data Register empty interrupt
-* - USART_IT_TC: Transmission complete interrupt
-* - USART_IT_RXNE: Receive Data register not empty
-* interrupt
-* - USART_IT_IDLE: Idle line detection interrupt
-* - USART_IT_ORE: OverRun Error interrupt
-* - USART_IT_NE: Noise Error interrupt
-* - USART_IT_FE: Framing Error interrupt
-* - USART_IT_PE: Parity Error interrupt
-* Output : None
-* Return : The new state of USART_IT (SET or RESET).
-*******************************************************************************/
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT)
-{
- u32 bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
- assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
-
- /* Get the USART register index */
- usartreg = (((u8)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itmask = USART_IT & IT_Mask;
-
- itmask = (u32)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
-
- bitpos = (u32)0x01 << bitpos;
- bitpos &= USARTx->SR;
-
- if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/*******************************************************************************
-* Function Name : USART_ClearITPendingBit
-* Description : Clears the USARTx's interrupt pending bits.
-* Input : - USARTx: Select the USART or the UART peripheral.
-* This parameter can be one of the following values:
-* - USART1, USART2, USART3, UART4 or UART5.
-* - USART_IT: specifies the interrupt pending bit to clear.
-* This parameter can be one of the following values:
-* - USART_IT_CTS: CTS change interrupt (not available for
-* UART4 and UART5)
-* - USART_IT_LBD: LIN Break detection interrupt
-* - USART_IT_TC: Transmission complete interrupt.
-* - USART_IT_RXNE: Receive Data register not empty interrupt.
-*
-* Notes:
-* - PE (Parity error), FE (Framing error), NE (Noise error),
-* ORE (OverRun error) and IDLE (Idle line detected)
-* pending bits are cleared by software sequence: a read
-* operation to USART_SR register (USART_GetITStatus())
-* followed by a read operation to USART_DR register
-* (USART_ReceiveData()).
-* - RXNE pending bit can be also cleared by a read to the
-* USART_DR register (USART_ReceiveData()).
-* - TC pending bit can be also cleared by software
-* sequence: a read operation to USART_SR register
-* (USART_GetITStatus()) followed by a write operation
-* to USART_DR register (USART_SendData()).
-* - TXE pending bit is cleared only by a write to the
-* USART_DR register (USART_SendData()).
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT)
-{
- u16 bitpos = 0x00, itmask = 0x00;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
- assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
-
- bitpos = USART_IT >> 0x08;
-
- itmask = (u16)((u16)0x01 << bitpos);
- USARTx->SR = (u16)~itmask;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the USART firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @defgroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Defines
+ * @{
+ */
+
+#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
+#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
+#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
+
+#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
+
+#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+ }
+ else
+ {
+ if (USARTx == UART5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval None
+ */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+ uint32_t tmpreg = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksTypeDef RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear STOP[13:12] bits */
+ tmpreg &= CR2_STOP_CLEAR_Mask;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to USART_StopBits value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = USARTx->CR1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to USART_WordLength value */
+ /* Set PCE and PS bits according to USART_Parity value */
+ /* Set TE and RE bits according to USART_Mode value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+ USART_InitStruct->USART_Mode;
+ /* Write to USART CR1 */
+ USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = USARTx->CR3;
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= CR3_CLEAR_Mask;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+ /* Write to USART CR3 */
+ USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreq(&RCC_ClocksStatus);
+ if (usartxbase == USART1_BASE)
+ {
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+ }
+ /* Determine the integer part */
+ integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
+ tmpreg = (integerdivider / 0x64) << 0x04;
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
+ tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((uint8_t)0x0F);
+ /* Write to USART BRR */
+ USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->USART_BaudRate = 9600;
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;
+ USART_InitStruct->USART_Parity = USART_Parity_No ;
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to USART_Clock value */
+ /* Set CPOL bit according to USART_CPOL value */
+ /* Set CPHA bit according to USART_CPHA value */
+ /* Set LBCL bit according to USART_LastBit value */
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CR1 register */
+ USARTx->CR1 |= CR1_UE_Set;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */
+ USARTx->CR1 &= CR1_UE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CONFIG_IT(USART_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_IT & IT_Mask;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CR3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART’s DMA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3 or UART4.
+ * @param USART_DMAReq: specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAReq_Tx: USART DMA transmit request
+ * @arg USART_DMAReq_Rx: USART DMA receive request
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The DMA mode is not available for UART5.
+ * @retval None
+ */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_1234_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Address: Indicates the address of the USART node.
+ * @retval None
+ */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Address));
+
+ /* Clear the USART address */
+ USARTx->CR2 &= CR2_Address_Mask;
+ /* Set the USART address node */
+ USARTx->CR2 |= USART_Address;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUp: specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+ * @retval None
+ */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));
+
+ USARTx->CR1 &= CR1_WAKE_Mask;
+ USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
+ USARTx->CR1 |= CR1_RWU_Set;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+ USARTx->CR1 &= CR1_RWU_Reset;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+ * @retval None
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CR2 &= CR2_LBDL_Mask;
+ USARTx->CR2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART’s LIN mode.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ USARTx->CR2 |= CR2_LINEN_Set;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+ USARTx->CR2 &= CR2_LINEN_Reset;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime: specifies the guard time.
+ * @note The guard time bits are not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTPR &= GTPR_LSB_Mask;
+ /* Set the USART guard time */
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler: specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ * @retval None
+ */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTPR &= GTPR_MSB_Mask;
+ /* Set the USART prescaler */
+ USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART’s Smart Card mode.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ USARTx->CR3 |= CR3_SCEN_Set;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+ USARTx->CR3 &= CR3_SCEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+ USARTx->CR3 |= CR3_NACK_Set;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+ USARTx->CR3 &= CR3_NACK_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART’s Half Duplex communication.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ USARTx->CR3 |= CR3_HDSEL_Set;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+ USARTx->CR3 &= CR3_HDSEL_Reset;
+ }
+}
+
+/**
+ * @brief Configures the USART’s IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode: specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IrDAMode_LowPower
+ * @arg USART_IrDAMode_Normal
+ * @retval None
+ */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CR3 &= CR3_IRLP_Mask;
+ USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART’s IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ USARTx->CR3 |= CR3_IREN_Set;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+ USARTx->CR3 &= CR3_IREN_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LBD: LIN Break detection flag
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if (USART_FLAG == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LBD: LIN Break detection flag.
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of USART_IT (SET or RESET).
+ */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_IT & IT_Mask;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ itmask &= USARTx->CR1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ itmask &= USARTx->CR2;
+ }
+ else /* The IT is in CR3 register */
+ {
+ itmask &= USARTx->CR3;
+ }
+
+ bitpos = USART_IT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->SR;
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx’s interrupt pending bits.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_IT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->SR = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_wwdg.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_wwdg.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/library/src/stm32f10x_wwdg.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,185 +1,223 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_wwdg.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file provides all the WWDG firmware functions.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_wwdg.h"
-#include "stm32f10x_rcc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ----------- WWDG registers bit address in the alias region ----------- */
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
-
-/* Alias word address of EWI bit */
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)
-#define EWI_BitNumber 0x09
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
-
-/* --------------------- WWDG registers bit mask ------------------------ */
-/* CR register bit mask */
-#define CR_WDGA_Set ((u32)0x00000080)
-
-/* CFR register bit mask */
-#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
-#define CFR_W_Mask ((u32)0xFFFFFF80)
-
-#define BIT_Mask ((u8)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/*******************************************************************************
-* Function Name : WWDG_DeInit
-* Description : Deinitializes the WWDG peripheral registers to their default
-* reset values.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/*******************************************************************************
-* Function Name : WWDG_SetPrescaler
-* Description : Sets the WWDG Prescaler.
-* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
-* This parameter can be one of the following values:
-* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
-* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
-* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
-* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_SetPrescaler(u32 WWDG_Prescaler)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
-
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
-
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : WWDG_SetWindowValue
-* Description : Sets the WWDG window value.
-* Input : - WindowValue: specifies the window value to be compared to
-* the downcounter.
-* This parameter value must be lower than 0x80.
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_SetWindowValue(u8 WindowValue)
-{
- u32 tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
-
- /* Clear W[6:0] bits */
- tmpreg = WWDG->CFR & CFR_W_Mask;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & BIT_Mask;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/*******************************************************************************
-* Function Name : WWDG_EnableIT
-* Description : Enables the WWDG Early Wakeup interrupt(EWI).
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_EnableIT(void)
-{
- *(vu32 *) CFR_EWI_BB = (u32)ENABLE;
-}
-
-/*******************************************************************************
-* Function Name : WWDG_SetCounter
-* Description : Sets the WWDG counter value.
-* Input : - Counter: specifies the watchdog counter value.
-* This parameter must be a number between 0x40 and 0x7F.
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_SetCounter(u8 Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
-
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_Mask;
-}
-
-/*******************************************************************************
-* Function Name : WWDG_Enable
-* Description : Enables WWDG and load the counter value.
-* - Counter: specifies the watchdog counter value.
-* This parameter must be a number between 0x40 and 0x7F.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_Enable(u8 Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
-
- WWDG->CR = CR_WDGA_Set | Counter;
-}
-
-/*******************************************************************************
-* Function Name : WWDG_GetFlagStatus
-* Description : Checks whether the Early Wakeup interrupt flag is set or not.
-* Input : None
-* Output : None
-* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
-*******************************************************************************/
-FlagStatus WWDG_GetFlagStatus(void)
-{
- return (FlagStatus)(WWDG->SR);
-}
-
-/*******************************************************************************
-* Function Name : WWDG_ClearFlag
-* Description : Clears Early Wakeup interrupt flag.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (u32)RESET;
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file provides all the WWDG firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber 0x09
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_WDGA_Set ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
+#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
+#define BIT_Mask ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void WWDG_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+ * @retval None
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpreg |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ * @retval None
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpreg = WWDG->CFR & CFR_W_Mask;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ * @param None
+ * @retval None
+ */
+void WWDG_EnableIT(void)
+{
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CR = Counter & BIT_Mask;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @param None
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+ return (FlagStatus)(WWDG->SR);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ * @param None
+ * @retval None
+ */
+void WWDG_ClearFlag(void)
+{
+ WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/FWLib/stm32f10x_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/FWLib/stm32f10x_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/FWLib/stm32f10x_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,174 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_conf.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : Library configuration file.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_type.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
- the "assert_param" macro in the firmware library code (see "Exported macro"
- section below) */
-/* #define DEBUG 1*/
-
-/* Comment the line below to disable the specific peripheral inclusion */
-/************************************* ADC ************************************/
-#define _ADC
-#define _ADC1
-#define _ADC2
-#define _ADC3
-
-/************************************* BKP ************************************/
-#define _BKP
-
-/************************************* CAN ************************************/
-#define _CAN
-
-/************************************* CRC ************************************/
-#define _CRC
-
-/************************************* DAC ************************************/
-#define _DAC
-
-/************************************* DBGMCU *********************************/
-#define _DBGMCU
-
-/************************************* DMA ************************************/
-#define _DMA
-#define _DMA1_Channel1
-#define _DMA1_Channel2
-#define _DMA1_Channel3
-#define _DMA1_Channel4
-#define _DMA1_Channel5
-#define _DMA1_Channel6
-#define _DMA1_Channel7
-#define _DMA2_Channel1
-#define _DMA2_Channel2
-#define _DMA2_Channel3
-#define _DMA2_Channel4
-#define _DMA2_Channel5
-
-/************************************* EXTI ***********************************/
-#define _EXTI
-
-/************************************* FLASH and Option Bytes *****************/
-#define _FLASH
-/* Uncomment the line below to enable FLASH program/erase/protections functions,
- otherwise only FLASH configuration (latency, prefetch, half cycle) functions
- are enabled */
-/* #define _FLASH_PROG */
-
-/************************************* FSMC ***********************************/
-#define _FSMC
-
-/************************************* GPIO ***********************************/
-#define _GPIO
-#define _GPIOA
-#define _GPIOB
-#define _GPIOC
-#define _GPIOD
-#define _GPIOE
-#define _GPIOF
-#define _GPIOG
-#define _AFIO
-
-/************************************* I2C ************************************/
-#define _I2C
-#define _I2C1
-#define _I2C2
-
-/************************************* IWDG ***********************************/
-#define _IWDG
-
-/************************************* NVIC ***********************************/
-#define _NVIC
-
-/************************************* PWR ************************************/
-#define _PWR
-
-/************************************* RCC ************************************/
-#define _RCC
-
-/************************************* RTC ************************************/
-#define _RTC
-
-/************************************* SDIO ***********************************/
-#define _SDIO
-
-/************************************* SPI ************************************/
-#define _SPI
-#define _SPI1
-#define _SPI2
-#define _SPI3
-
-/************************************* SysTick ********************************/
-#define _SysTick
-
-/************************************* TIM ************************************/
-#define _TIM
-#define _TIM1
-#define _TIM2
-#define _TIM3
-#define _TIM4
-#define _TIM5
-#define _TIM6
-#define _TIM7
-#define _TIM8
-
-/************************************* USART **********************************/
-#define _USART
-#define _USART1
-#define _USART2
-#define _USART3
-#define _UART4
-#define _UART5
-
-/************************************* WWDG ***********************************/
-#define _WWDG
-
-/* In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application */
-#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
-
-/* In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value */
-#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef DEBUG
-/*******************************************************************************
-* Macro Name : assert_param
-* Description : The assert_param macro is used for function's parameters check.
-* It is used only if the library is compiled in DEBUG mode.
-* Input : - expr: If expr is false, it calls assert_failed function
-* which reports the name of the source file and the source
-* line number of the call that failed.
-* If expr is true, it returns no value.
-* Return : None
-*******************************************************************************/
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(u8* file, u32 line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* DEBUG */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/stm32/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -3,12 +3,12 @@
import glob
import os
-local_include = local_include + " -Isrc/platform/%s/FWLib/library/inc" % platform
+local_include += ['src/platform/%s/FWLib/library/inc' % platform]
fwlib_files = " ".join(glob.glob("src/platform/%s/FWLib/library/src/*.c" % platform))
#print "FWLib: %s " % fwlib_files
-specific_files = "cortexm3_macro.s stm32f10x_vector.c systick.c platform.c stm32f10x_it.c lcd.c lua_lcd.c"
+specific_files = "core_cm3.c systick.c system_stm32f10x.c startup_stm32f10x_hd.s platform.c stm32f10x_it.c lcd.c lua_lcd.c"
ldscript = "stm32.ld"
@@ -23,17 +23,17 @@
# Toolset data
tools[ 'stm32' ] = {}
-tools[ 'stm32' ][ 'cccom' ] = "arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -mlittle-endian %s %s -ffunction-sections -fdata-sections -fno-strict-aliasing %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, cdefs )
-#tools[ 'stm32' ][ 'linkcom' ] = "arm-none-eabi-gcc -nostartfiles -nostdlib -T %s -Wl,--gc-sections -Wl,-e,ResetISR -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( ldscript, local_libs )
-tools[ 'stm32' ][ 'linkcom' ] = "arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -Wl,-T -Xlinker %s -u _start -Wl,-e,Reset_Handler -Wl,-static -Wl,--gc-sections -nostartfiles -nostdlib -Wl,-Map -Xlinker project.map -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( ldscript, local_libs )
-tools[ 'stm32' ][ 'ascom' ] = "arm-none-eabi-gcc -x assembler-with-cpp %s -mcpu=cortex-m3 -mthumb %s -Wall -c $SOURCE -o $TARGET" % ( local_include, cdefs )
+tools[ 'stm32' ][ 'cccom' ] = "%s -mcpu=cortex-m3 -mthumb -mlittle-endian %s $_CPPINCFLAGS -ffunction-sections -fdata-sections -fno-strict-aliasing %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], opt, cdefs )
+tools[ 'stm32' ][ 'linkcom' ] = "%s -mcpu=cortex-m3 -mthumb -Wl,-T -Xlinker %s -u _start -Wl,-e,Reset_Handler -Wl,-static -Wl,--gc-sections -nostartfiles -nostdlib -Wl,--allow-multiple-definition -o $TARGET $SOURCES -lc -lgcc -lm %s" % ( toolset[ 'compile' ], ldscript, local_libs )
+tools[ 'stm32' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=cortex-m3 -mthumb %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], cdefs )
# Programming function
def progfunc_stm32( target, source, env ):
outname = output + ".elf"
- os.system( "arm-none-eabi-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( "arm-none-eabi-objcopy -O binary %s %s.bin" % ( outname, output ) )
- os.system( "arm-none-eabi-objcopy -O ihex %s %s.hex" % ( outname, output ) )
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
+ os.system( "%s -O ihex %s %s.hex" % ( toolset[ 'bin' ], outname, output ) )
tools[ 'stm32' ][ 'progfunc' ] = progfunc_stm32
+
Added: branches/eagle_mmc/src/platform/stm32/core_cm3.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/core_cm3.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/core_cm3.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,829 @@
+/******************************************************************************
+ * @file: core_cm3.c
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version: V1.20
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+
+#include <stdint.h>
+
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for armcc */
+ #define __INLINE __inline /*!< inline keyword for armcc */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for iarcc */
+ #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for gcc */
+ #define __INLINE inline /*!< inline keyword for gcc */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+ clrex
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ __ASM("rev16 r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, psp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, msp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+uint32_t __get_PRIMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int32_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ uint8_t result=0;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ uint16_t result=0;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Property changes on: branches/eagle_mmc/src/platform/stm32/core_cm3.c
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/stm32/core_cm3.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/core_cm3.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/core_cm3.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,1367 @@
+/******************************************************************************
+ * @file: core_cm3.h
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version: V1.20
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+/**
+ * Lint configuration \n
+ * ----------------------- \n
+ *
+ * The following Lint messages will be suppressed and not shown: \n
+ * \n
+ * --- Error 10: --- \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';' \n
+ * \n
+ * --- Error 530: --- \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ * \n
+ * --- Error 550: --- \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * } \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ * \n
+ * --- Error 754: --- \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 750: --- \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 528: --- \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 751: --- \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ * Note: To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+#include <stdint.h> /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+#define __I volatile /*!< defines 'read only' permissions */
+#else
+#define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+
+
+/* System Reset */
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
+
+/* Core Debug */
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */
+
+
+
+
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
+} NVIC_Type;
+
+
+/* memory mapping struct for System Control Block */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< System Control Register */
+ __IO uint32_t CCR; /*!< Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */
+ __I uint32_t DFR; /*!< Debug Feature Register */
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */
+} SCB_Type;
+
+
+/* memory mapping struct for SysTick */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */
+} SysTick_Type;
+
+
+/* memory mapping structur for ITM */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< ITM Product ID Registers */
+ __I uint32_t PID5;
+ __I uint32_t PID6;
+ __I uint32_t PID7;
+ __I uint32_t PID0;
+ __I uint32_t PID1;
+ __I uint32_t PID2;
+ __I uint32_t PID3;
+ __I uint32_t CID0;
+ __I uint32_t CID1;
+ __I uint32_t CID2;
+ __I uint32_t CID3;
+} ITM_Type;
+
+
+/* memory mapped struct for Interrupt Type */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+
+/* Memory Protection Unit */
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+typedef struct
+{
+ __I uint32_t TYPE; /*!< MPU Type Register */
+ __IO uint32_t CTRL; /*!< MPU Control Register */
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+#endif
+
+
+/* Core Debug Register */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0x1ff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
+
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
+static __INLINE void __WFI() { __ASM ("wfi"); }
+static __INLINE void __WFE() { __ASM ("wfe"); }
+static __INLINE void __SEV() { __ASM ("sev"); }
+static __INLINE void __CLREX() { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void) */
+/* intrinsic void __DSB(void) */
+/* intrinsic void __DMB(void) */
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }
+static __INLINE void __SEV() { __ASM volatile ("sev"); }
+static __INLINE void __ISB() { __ASM volatile ("isb"); }
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @param none
+* @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+
+/* ########################## NVIC functions #################################### */
+
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param uint32_t priority_grouping is priority grouping field
+ * @return none
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @param none
+ * @return uint32_t priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn_Type IRQn specifies the interrupt number
+ * @return none
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt
+ * @return uint32_t 1 if pending interrupt else 0
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return uint32_t 1 if active else 0
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @param priority is the priority for the interrupt
+ * @return none
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt. \n
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return uint32_t priority is the priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/**
+ * @brief Encode the priority for an interrupt
+ *
+ * @param uint32_t PriorityGroup is the used priority group
+ * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
+ * @param uint32_t SubPriority is the sub priority value (starting from 0)
+ * @return uint32_t the priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/**
+ * @brief Decode the priority of an interrupt
+ *
+ * @param uint32_t Priority the priority for the interrupt
+ * @param uint32_t PrioGroup is the used priority group
+ * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
+ * @param uint32_t* pSubPrio is the sub priority value (starting from 0)
+ * @return none
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/* SysTick constants */
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param uint32_t ticks is the number of ticks between two interrupts
+ * @return none
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+
+
+
+
+/* ################################## Reset function ############################################ */
+
+/**
+ * @brief Initiate a system reset request.
+ *
+ * @param none
+ * @return none
+ *
+ * Initialize a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+
+/* ################################## Debug Output function ############################################ */
+
+
+/**
+ * @brief Outputs a character via the ITM channel 0
+ *
+ * @param uint32_t character to output
+ * @return uint32_t input character
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (ch == '\n') ITM_SendChar('\r');
+
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 0)) )
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
Property changes on: branches/eagle_mmc/src/platform/stm32/core_cm3.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/stm32/fonts.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/fonts.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/fonts.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -18,7 +18,7 @@
#define __FONTS_H
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_lib.h"
+#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* ASCII Table: each character is 16 column (16dots large)
Modified: branches/eagle_mmc/src/platform/stm32/lcd.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/lcd.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/lcd.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -19,7 +19,7 @@
#define __LCD_H
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_lib.h"
+#include "stm32f10x.h"
extern void Delay(u32 nCount);
Modified: branches/eagle_mmc/src/platform/stm32/platform.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/platform.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/platform.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -11,35 +11,22 @@
#include <stdio.h>
#include "uip_arp.h"
#include "elua_uip.h"
+#include "elua_adc.h"
#include "uip-conf.h"
#include "platform_conf.h"
#include "common.h"
+#include "buf.h"
+#include "utils.h"
// Platform specific includes
-#include "stm32f10x_lib.h"
-#include "stm32f10x_map.h"
-#include "stm32f10x_type.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_nvic.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_systick.h"
-#include "stm32f10x_flash.h"
+#include "stm32f10x.h"
-#include "systick.h"
+// Clock data
+// IMPORTANT: if you change these, make sure to modify RCC_Configuration() too!
+#define HCLK ( HSE_Value * 9 )
+#define PCLK1_DIV 2
+#define PCLK2_DIV 1
-#define STM32_USE_PIO
-#define STM32_USE_USART
-
-void exit(int ret)
-{
- while(1);
-}
-
// ****************************************************************************
// Platform initialization
@@ -48,11 +35,12 @@
static void NVIC_Configuration(void);
static void timers_init();
+static void pwms_init();
static void uarts_init();
static void spis_init();
static void pios_init();
-static void pwms_init();
-static void eth_init();
+static void adcs_init();
+static void cans_init();
int platform_init()
{
@@ -63,32 +51,29 @@
NVIC_Configuration();
// Enable SysTick timer.
- SysTick_Config();
+ SysTick_Config(720000);
-#ifdef STM32_USE_PIO
// Setup PIO
pios_init();
-#endif
-#ifdef STM32_USE_SPI
- // Setup SPIs
- //spis_init();
-#endif
-
-#ifdef STM32_USE_USART
// Setup UARTs
uarts_init();
-#endif
-
+
+ // Setup SPIs
+ spis_init();
+
// Setup timers
- //timers_init();
-
+ timers_init();
+
// Setup PWMs
- //pwms_init();
+ pwms_init();
+
+ // Setup ADCs
+ adcs_init();
+
+ // Setup CANs
+ cans_init();
- // Setup ethernet (TCP/IP)
- //eth_init();
-
cmn_platform_init();
// All done
@@ -109,53 +94,10 @@
*******************************************************************************/
static void RCC_Configuration(void)
{
- ErrorStatus HSEStartUpStatus;
- /* RCC system reset(for debug purpose) */
- RCC_DeInit();
+ SystemInit();
+
+ RCC_PCLK1Config(RCC_HCLK_Div2);
- /* Enable HSE */
- RCC_HSEConfig(RCC_HSE_ON);
-
- /* Wait till HSE is ready */
- HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
- if(HSEStartUpStatus == SUCCESS)
- {
- /* Enable Prefetch Buffer */
- FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
- /* Flash 2 wait state */
- FLASH_SetLatency(FLASH_Latency_2);
-
- /* HCLK = SYSCLK */
- RCC_HCLKConfig(RCC_SYSCLK_Div1);
-
- /* PCLK2 = HCLK */
- RCC_PCLK2Config(RCC_HCLK_Div1);
-
- /* PCLK1 = HCLK/2 */
- RCC_PCLK1Config(RCC_HCLK_Div2);
-
- /* PLLCLK = 8MHz * 9 = 72 MHz */
- RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
-
- /* Enable PLL */
- RCC_PLLCmd(ENABLE);
-
- /* Wait till PLL is ready */
- while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
- {
- }
-
- /* Select PLL as system clock source */
- RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
- /* Wait till PLL is used as system clock source */
- while(RCC_GetSYSCLKSource() != 0x08)
- {
- }
- }
-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
}
@@ -170,12 +112,14 @@
* Output : None
* Return : None
*******************************************************************************/
+/* This struct is used for later reconfiguration of ADC interrupt */
+NVIC_InitTypeDef nvic_init_structure_adc;
+
static void NVIC_Configuration(void)
{
- NVIC_InitTypeDef NVIC_InitStructure;
+ NVIC_InitTypeDef nvic_init_structure;
+
- NVIC_DeInit();
-
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x20000000 */
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
@@ -187,15 +131,27 @@
/* Configure the NVIC Preemption Priority Bits */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
- /* Configure the SysTick handler priority */
- NVIC_SystemHandlerPriorityConfig(SystemHandler_SysTick, 0, 0);
+#ifdef BUILD_ADC
+ nvic_init_structure_adc.NVIC_IRQChannel = DMA1_Channel1_IRQn;
+ nvic_init_structure_adc.NVIC_IRQChannelPreemptionPriority = 1;
+ nvic_init_structure_adc.NVIC_IRQChannelSubPriority = 3;
+ nvic_init_structure_adc.NVIC_IRQChannelCmd = DISABLE;
+ NVIC_Init(&nvic_init_structure_adc);
+#endif
+
+#if defined( BUF_ENABLE_UART ) && defined( CON_BUF_SIZE )
+ /* Enable the USART1 Interrupt */
+ nvic_init_structure.NVIC_IRQChannel = USART1_IRQn;
+ nvic_init_structure.NVIC_IRQChannelSubPriority = 0;
+ nvic_init_structure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&nvic_init_structure);
+#endif
}
// ****************************************************************************
// PIO
// This is pretty much common code to all STM32 devices.
// todo: Needs updates to support different processor lines.
-#ifdef STM32_USE_PIO
static GPIO_TypeDef * const pio_port[] = { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG };
static const u32 pio_port_clk[] = { RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG };
@@ -291,63 +247,260 @@
}
return retval;
}
-#endif
-#ifdef STM32_USE_SPI
// ****************************************************************************
-// SPI
-// TODO: Just about everything.
+// CAN
+// TODO: Many things
-static const u32 spi_base[] = { SSI0_BASE, SSI1_BASE };
-static const u32 spi_sysctl[] = { SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1 };
-static const u32 spi_gpio_base[] = { GPIO_PORTA_BASE | GPIO_PORTE_BASE };
-static const u8 spi_gpio_pins[] = { GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5,
- GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 };
-// SSIxClk SSIxFss SSIxRx SSIxTx
-static const u8 spi_gpio_clk_pin[] = { GPIO_PIN_2, GPIO_PIN_0 };
-#define SPIS_COUNT 1
+void cans_init( void )
+{
+ /* CAN Periph clock enable */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
+}
-static void spis_init()
+/* BS1 BS2 SJW Pre
+1M: 5 3 1 4
+500k: 7 4 1 6
+250k: 9 8 1 8
+125k: 9 8 1 16
+100k: 9 8 1 20 */
+
+#define CAN_BAUD_COUNT 5
+static const u8 can_baud_bs1[] = { CAN_BS1_9tq, CAN_BS1_9tq, CAN_BS1_9tq, CAN_BS1_7tq, CAN_BS1_5tq };
+static const u8 can_baud_bs2[] = { CAN_BS1_8tq, CAN_BS1_8tq, CAN_BS1_8tq, CAN_BS1_4tq, CAN_BS1_3tq };
+static const u8 can_baud_sjw[] = { CAN_SJW_1tq, CAN_SJW_1tq, CAN_SJW_1tq, CAN_SJW_1tq, CAN_SJW_1tq };
+static const u8 can_baud_pre[] = { 20, 16, 8, 6, 4 };
+static const u32 can_baud_rate[] = { 100000, 125000, 250000, 500000, 1000000 };
+
+u32 platform_can_setup( unsigned id, u32 clock )
{
- unsigned i;
+ CAN_InitTypeDef CAN_InitStructure;
+ CAN_FilterInitTypeDef CAN_FilterInitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
+ int cbaudidx = -1;
- for( i = 0; i < SPIS_COUNT; i ++ )
+ // Configure IO Pins -- This is for STM32F103RE
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_Init( GPIOB, &GPIO_InitStructure );
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init( GPIOB, &GPIO_InitStructure );
+
+ GPIO_PinRemapConfig( GPIO_Remap1_CAN1, ENABLE );
+
+ // Select baud rate up to requested rate, except for below min, where min is selected
+ if ( clock >= can_baud_rate[ CAN_BAUD_COUNT - 1 ] ) // round down to peak rate if >= peak rate
+ cbaudidx = CAN_BAUD_COUNT - 1;
+ else
{
- SysCtlPeripheralEnable(spi_sysctl[ i ]);
+ for( cbaudidx = 0; cbaudidx < CAN_BAUD_COUNT - 1; cbaudidx ++ )
+ {
+ if( clock < can_baud_rate[ cbaudidx + 1 ] ) // take current idx if next is too large
+ break;
+ }
}
+
+ /* Deinitialize CAN Peripheral */
+ CAN_DeInit( CAN1 );
+ CAN_StructInit( &CAN_InitStructure );
+
+ /* CAN cell init */
+ CAN_InitStructure.CAN_TTCM=DISABLE;
+ CAN_InitStructure.CAN_ABOM=DISABLE;
+ CAN_InitStructure.CAN_AWUM=DISABLE;
+ CAN_InitStructure.CAN_NART=DISABLE;
+ CAN_InitStructure.CAN_RFLM=DISABLE;
+ CAN_InitStructure.CAN_TXFP=DISABLE;
+ CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;
+ CAN_InitStructure.CAN_SJW=can_baud_sjw[ cbaudidx ];
+ CAN_InitStructure.CAN_BS1=can_baud_bs1[ cbaudidx ];
+ CAN_InitStructure.CAN_BS2=can_baud_bs2[ cbaudidx ];
+ CAN_InitStructure.CAN_Prescaler=can_baud_pre[ cbaudidx ];
+ CAN_Init( CAN1, &CAN_InitStructure );
+
+ /* CAN filter init */
+ CAN_FilterInitStructure.CAN_FilterNumber=0;
+ CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
+ CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
+ CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
+ CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
+ CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
+ CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
+ CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_FIFO0;
+ CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
+ CAN_FilterInit(&CAN_FilterInitStructure);
+
+ return can_baud_rate[ cbaudidx ];
}
+/*
+u32 platform_can_op( unsigned id, int op, u32 data )
+{
+ u32 res = 0;
+ TIM_TypeDef *ptimer = timer[ id ];
+ volatile unsigned dummy;
-int platform_spi_exists( unsigned id )
+ data = data;
+ switch( op )
+ {
+ case PLATFORM_TIMER_OP_READ:
+ res = TIM_GetCounter( ptimer );
+ break;
+ }
+ return res;
+}
+*/
+
+void platform_can_send( unsigned id, u32 canid, u8 idtype, u8 len, const u8 *data )
{
- return id < SPIS_COUNT;
+ CanTxMsg TxMessage;
+ const char *s = ( char * )data;
+ char *d;
+
+ switch( idtype )
+ {
+ case 0: /* Standard ID Type */
+ TxMessage.IDE = CAN_ID_STD;
+ TxMessage.StdId = canid;
+ break;
+ case 1: /* Extended ID Type */
+ TxMessage.IDE=CAN_ID_EXT;
+ TxMessage.ExtId = canid;
+ break;
+ }
+
+ TxMessage.RTR=CAN_RTR_DATA;
+ TxMessage.DLC=len;
+
+ d = ( char * )TxMessage.Data;
+ DUFF_DEVICE_8( len, *d++ = *s++ );
+
+ CAN_Transmit( CAN1, &TxMessage );
}
-u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
+void USB_LP_CAN_RX0_IRQHandler(void)
{
- unsigned protocol;
+/*
+ CanRxMsg RxMessage;
- if( cpol == 0 )
- protocol = cpha ? SSI_FRF_MOTO_MODE_1 : SSI_FRF_MOTO_MODE_0;
+ RxMessage.StdId=0x00;
+ RxMessage.ExtId=0x00;
+ RxMessage.IDE=0;
+ RxMessage.DLC=0;
+ RxMessage.FMI=0;
+ RxMessage.Data[0]=0x00;
+ RxMessage.Data[1]=0x00;
+
+ CAN_Receive(CAN_FIFO0, &RxMessage);
+
+ if((RxMessage.ExtId==0x1234) && (RxMessage.IDE==CAN_ID_EXT)
+ && (RxMessage.DLC==2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8)==0xDECA))
+ {
+ ret = 1;
+ }
else
- protocol = cpha ? SSI_FRF_MOTO_MODE_3 : SSI_FRF_MOTO_MODE_2;
- mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
- SSIDisable( spi_base[ id ] );
+ {
+ ret = 0;
+ }*/
+}
- GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
+void platform_can_recv( unsigned id, u32 *canid, u8 *idtype, u8 *len, u8 *data )
+{
+ CanRxMsg RxMessage;
+ const char *s;
+ char *d;
+ u32 i = 0;
+
+ // Check up to 256 times for message
+ while( ( CAN_MessagePending(CAN1, CAN_FIFO0) < 1 ) && ( i++ != 0xFF ) );
+
+ RxMessage.StdId=0x00;
+ RxMessage.IDE=CAN_ID_STD;
+ RxMessage.DLC=0;
+ RxMessage.Data[0]=0x00;
+ RxMessage.Data[1]=0x00;
+ CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
+
+ if( RxMessage.IDE == CAN_ID_STD )
+ {
+ *canid = ( u32 )RxMessage.StdId;
+ *idtype = 0;
+ }
+ else
+ {
+ *canid = ( u32 )RxMessage.ExtId;
+ *idtype = 1;
+ }
+
+ *len = RxMessage.DLC;
+
+ s = ( const char * )RxMessage.Data;
+ d = ( char* )data;
+ DUFF_DEVICE_8( RxMessage.DLC, *d++ = *s++ );
+}
- // FIXME: not sure this is always "right"
- GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
+// ****************************************************************************
+// SPI
+// NOTE: Only configuring 2 SPI peripherals, since the third one shares pins with JTAG
- SSIConfigSetExpClk( spi_base[ id ], SysCtlClockGet(), protocol, mode, clock, databits );
- SSIEnable( spi_base[ id ] );
- return clock;
+static SPI_TypeDef *const spi[] = { SPI1, SPI2 };
+static const u16 spi_prescaler[] = { SPI_BaudRatePrescaler_2, SPI_BaudRatePrescaler_4, SPI_BaudRatePrescaler_8,
+ SPI_BaudRatePrescaler_16, SPI_BaudRatePrescaler_32, SPI_BaudRatePrescaler_64,
+ SPI_BaudRatePrescaler_128, SPI_BaudRatePrescaler_256 };
+
+static const u16 spi_gpio_pins[] = { GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7,
+ GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15 };
+// SCK MISO MOSI
+static GPIO_TypeDef *const spi_gpio_port[] = { GPIOA, GPIOB };
+
+static void spis_init()
+{
+ // Enable Clocks
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
}
+#define SPI_GET_BASE_CLK( id ) ( ( id ) == 0 ? ( HCLK / PCLK2_DIV ) : ( HCLK / PCLK1_DIV ) )
+
+u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
+{
+ SPI_InitTypeDef SPI_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
+ u8 prescaler_idx = intlog2( ( unsigned ) ( SPI_GET_BASE_CLK( id ) / clock ) );
+ if ( prescaler_idx < 0 )
+ prescaler_idx = 0;
+ if ( prescaler_idx > 7 )
+ prescaler_idx = 7;
+
+ /* Configure SPI pins */
+ GPIO_InitStructure.GPIO_Pin = spi_gpio_pins[ id ];
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(spi_gpio_port[ id ], &GPIO_InitStructure);
+
+ /* Take down, then reconfigure SPI peripheral */
+ SPI_Cmd( spi[ id ], DISABLE );
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = mode ? SPI_Mode_Master : SPI_Mode_Slave;
+ SPI_InitStructure.SPI_DataSize = ( databits == 16 ) ? SPI_DataSize_16b : SPI_DataSize_8b; // not ideal, but defaults to sane 8-bits
+ SPI_InitStructure.SPI_CPOL = cpol ? SPI_CPOL_High : SPI_CPOL_Low;
+ SPI_InitStructure.SPI_CPHA = cpha ? SPI_CPHA_1Edge : SPI_CPHA_2Edge;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = spi_prescaler[ prescaler_idx ];
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
+ SPI_Init( spi[ id ], &SPI_InitStructure );
+ SPI_Cmd( spi[ id ], ENABLE );
+
+ return ( SPI_GET_BASE_CLK( id ) / ( ( ( u16 )2 << ( prescaler_idx ) ) ) );
+}
+
spi_data_type platform_spi_send_recv( unsigned id, spi_data_type data )
{
- SSIDataPut( spi_base[ id ], data );
- SSIDataGet( spi_base[ id ], &data );
- return data;
+ SPI_I2S_SendData( spi[ id ], data );
+ return SPI_I2S_ReceiveData( spi[ id ] );
}
void platform_spi_select( unsigned id, int is_select )
@@ -356,22 +509,35 @@
id = id;
is_select = is_select;
}
-#endif
-#ifdef STM32_USE_USART
+
// ****************************************************************************
// UART
// TODO: Support timeouts.
// All possible STM32 uarts defs
-static USART_TypeDef * usart[] = { USART1, USART2, USART3, UART4 };
-static GPIO_TypeDef * usart_gpio_port[] = { GPIOA, GPIOA, GPIOB, GPIOC };
-static const u16 usart_gpio_tx_pin[] = { GPIO_Pin_9, GPIO_Pin_2, GPIO_Pin_10, GPIO_Pin_10 };
-static const u16 usart_gpio_rx_pin[] = { GPIO_Pin_10, GPIO_Pin_3, GPIO_Pin_11, GPIO_Pin_11 };
-//static const u32 uart_sysctl[] = { SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2 };
-//static const u32 uart_gpio_base[] = { _BASE, GPIO_PORTD_BASE, GPIO_PORTG_BASE };
-//static const u8 uart_gpio_pins[] = { GPIO_PIN_0 | GPIO_PIN_1, GPIO_PIN_2 | GPIO_PIN_3, GPIO_PIN_0 | GPIO_PIN_1 };
+static USART_TypeDef *const usart[] = { USART1, USART2, USART3, UART4, UART5 };
+static GPIO_TypeDef *const usart_gpio_rx_port[] = { GPIOA, GPIOA, GPIOB, GPIOC, GPIOD };
+static GPIO_TypeDef *const usart_gpio_tx_port[] = { GPIOA, GPIOA, GPIOB, GPIOC, GPIOC };
+static const u16 usart_gpio_rx_pin[] = { GPIO_Pin_10, GPIO_Pin_3, GPIO_Pin_11, GPIO_Pin_11, GPIO_Pin_2 };
+static const u16 usart_gpio_tx_pin[] = { GPIO_Pin_9, GPIO_Pin_2, GPIO_Pin_10, GPIO_Pin_10, GPIO_Pin_12 };
+#ifdef BUF_ENABLE_UART
+void USART1_IRQHandler(void)
+{
+ int c;
+
+ if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)
+ {
+ /* Read one byte from the receive data register */
+ c = USART_ReceiveData(USART1);
+ buf_write( BUF_ID_UART, CON_UART_ID, ( t_buf_data* )&c );
+ }
+}
+#endif
+
+
+
static void usart_init(u32 id, USART_InitTypeDef * initVals)
{
/* Configure USART IO */
@@ -381,21 +547,23 @@
GPIO_InitStructure.GPIO_Pin = usart_gpio_tx_pin[id];
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(usart_gpio_port[id], &GPIO_InitStructure);
+ GPIO_Init(usart_gpio_tx_port[id], &GPIO_InitStructure);
/* Configure USART Rx Pin as input floating */
GPIO_InitStructure.GPIO_Pin = usart_gpio_rx_pin[id];
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_Init(usart_gpio_port[id], &GPIO_InitStructure);
+ GPIO_Init(usart_gpio_rx_port[id], &GPIO_InitStructure);
/* Configure USART */
USART_Init(usart[id], initVals);
-
+
+#if defined( BUF_ENABLE_UART ) && defined( CON_BUF_SIZE )
/* Enable USART1 Receive and Transmit interrupts */
- //USART_ITConfig(usart[id], USART_IT_RXNE, ENABLE);
+ USART_ITConfig(usart[id], USART_IT_RXNE, ENABLE);
//USART_ITConfig(usart[id], USART_IT_TXE, ENABLE);
+#endif
- /* Enable the USART1 */
+ /* Enable USART */
USART_Cmd(usart[id], ENABLE);
}
@@ -409,8 +577,7 @@
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
- // Configure the U(S)ART for 115,200, 8-N-1 operation.
-
+ // Configure the U(S)ART
USART_InitStructure.USART_BaudRate = CON_UART_SPEED;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
@@ -418,7 +585,12 @@
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+#if defined( BUF_ENABLE_UART ) && defined( CON_BUF_SIZE )
+ buf_set( BUF_ID_UART, CON_UART_ID, CON_BUF_SIZE, BUF_DSIZE_U8 );
+#endif
+
usart_init(CON_UART_ID, &USART_InitStructure);
+
}
u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
@@ -498,86 +670,98 @@
while(USART_GetFlagStatus(usart[id], USART_FLAG_RXNE) == RESET);
return USART_ReceiveData(usart[id]);
}
-#endif
-#ifdef STM32_USE_TIMERS
// ****************************************************************************
// Timers
-// All possible LM3S timers defs
-static TIM_TypeDef * timer[] = { TIM2, TIM3, TIM4, TIM5};
+// We leave out TIM6/TIM for now, as they are dedicated
+static TIM_TypeDef * const timer[] = { TIM1, TIM2, TIM3, TIM4, TIM5 };
+#define TIM_GET_BASE_CLK( id ) ( ( id ) == 0 || ( id ) == 5 ? ( HCLK / PCLK2_DIV ) : ( HCLK / PCLK1_DIV ) )
+#define TIM_STARTUP_CLOCK 50000
static void timers_init()
{
-#if 0
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
unsigned i;
+ // Enable clocks.
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_TIM1, ENABLE );
+ RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
+ RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE );
+ RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM4, ENABLE );
+ RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM5, ENABLE );
+
+
+ // Configure timers
for( i = 0; i < NUM_TIMER; i ++ )
{
- SysCtlPeripheralEnable(timer_sysctl[ i ]);
- TimerConfigure(timer_base[ i ], TIMER_CFG_32_BIT_PER);
- TimerEnable(timer_base[ i ], TIMER_A);
+ TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
+ TIM_TimeBaseStructure.TIM_Prescaler = TIM_GET_BASE_CLK( i ) / TIM_STARTUP_CLOCK;
+ TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
+ TIM_TimeBaseInit( timer[ i ], &TIM_TimeBaseStructure );
}
-#endif
}
-static u32 platform_timer_get_clock(unsigned id)
+static u32 timer_get_clock( unsigned id )
{
- RCC_ClocksTypeDef Clocks;
+ TIM_TypeDef* ptimer = timer[ id ];
- RCC_GetClocksFreq(&Clocks);
-
- return Clocks.PCLK1_Frequency / (TIM_GetPrescaler(timer[id]) + 1)
+ return TIM_GET_BASE_CLK( id ) / ( TIM_GetPrescaler( ptimer ) + 1 );
}
-static u32 platform_timer_set_clock(unsigned id, u32 clock)
+static u32 timer_set_clock( unsigned id, u32 clock )
{
- RCC_ClocksTypeDef Clocks;
- u32 pclk, clkdiv;
- u64 tmp;
-
- RCC_GetClocksFreq(&Clocks);
-
- pclk = Clocks.PCLK1_Frequency; // Get peripheral bus clock frequency.
- tmp = ((u64)pclk << 16) / clock; // Convert to u32.16 fixed point and calculate prescaler divisor
- clkdiv = ((tmp & 0x8000) ? (tmp + 0x10000) : tmp) >> 16; // Round up or down and convert back to u32.0
- if (clkdiv > 0x10000) // Saturate to u16 (+1 for a clkdiv value of 1 is a reg value of 0)
- clkdiv = 0x10000;
-
- TIM_PrescalerConfig(timer[id], clkdiv - 1, TIM_PSCReloadMode_Immediate); // Update timer prescaler immediately
-
- return pclk / clkdiv; // Return actual clock rate used.
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+ TIM_TypeDef *ptimer = timer[ id ];
+ u16 pre;
+
+ TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
+ TIM_TimeBaseStructure.TIM_Prescaler = TIM_GET_BASE_CLK( id ) / TIM_STARTUP_CLOCK;
+ TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
+ TIM_TimeBaseInit( timer[ id ], &TIM_TimeBaseStructure );
+ TIM_Cmd( ptimer, ENABLE );
+
+ pre = TIM_GET_BASE_CLK( id ) / clock;
+ TIM_PrescalerConfig( ptimer, pre, TIM_PSCReloadMode_Immediate );
+ return TIM_GET_BASE_CLK( id ) / pre;
}
void platform_s_timer_delay( unsigned id, u32 delay_us )
{
+ TIM_TypeDef *ptimer = timer[ id ];
+ volatile unsigned dummy;
timer_data_type final;
- u32 base = timer_base[ id ];
- final = 0xFFFFFFFF - ( ( ( u64 )delay_us * SysCtlClockGet() ) / 1000000 );
- TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
- while( TimerValueGet( base, TIMER_A ) > final );
+ final = ( ( u64 )delay_us * timer_get_clock( id ) ) / 1000000;
+ TIM_SetCounter( ptimer, 0 );
+ for( dummy = 0; dummy < 200; dummy ++ );
+ while( TIM_GetCounter( ptimer ) < final );
}
u32 platform_s_timer_op( unsigned id, int op, u32 data )
{
u32 res = 0;
- u32 base = timer_base[ id ];
+ TIM_TypeDef *ptimer = timer[ id ];
+ volatile unsigned dummy;
data = data;
switch( op )
{
case PLATFORM_TIMER_OP_START:
- res = 0xFFFFFFFF;
- TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
+ TIM_SetCounter( ptimer, 0 );
+ for( dummy = 0; dummy < 200; dummy ++ );
break;
case PLATFORM_TIMER_OP_READ:
- res = TimerValueGet( base, TIMER_A );
+ res = TIM_GetCounter( ptimer );
break;
case PLATFORM_TIMER_OP_GET_MAX_DELAY:
- res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
+ res = platform_timer_get_diff_us( id, 0, 0xFFFF );
break;
case PLATFORM_TIMER_OP_GET_MIN_DELAY:
@@ -585,92 +769,112 @@
break;
case PLATFORM_TIMER_OP_SET_CLOCK:
+ res = timer_set_clock( id, data );
+ break;
+
case PLATFORM_TIMER_OP_GET_CLOCK:
- res = SysCtlClockGet();
+ res = timer_get_clock( id );
break;
}
return res;
}
-#else
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
-{
- return 0;
-}
-#endif
-#ifdef STM32_USE_PWM
+
// ****************************************************************************
// PWMs
-// TODO: Everything.
+// Using Timer 8 (5 in eLua)
-#define PLATFORM_NUM_PWMS 6
+#define PWM_TIMER_ID 5
+#define PWM_TIMER_NAME TIM8
-// SYSCTL div data and actual div factors
-const static u32 pwm_div_ctl[] = { SYSCTL_PWMDIV_1, SYSCTL_PWMDIV_2, SYSCTL_PWMDIV_4, SYSCTL_PWMDIV_8, SYSCTL_PWMDIV_16, SYSCTL_PWMDIV_32, SYSCTL_PWMDIV_64 };
-const static u8 pwm_div_data[] = { 1, 2, 4, 8, 16, 32, 64 };
-// Port/pin information for all channels
-const static u32 pwm_ports[] = { GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
-const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
-// PWM generators
-const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
-// PWM outputs
-const static u16 pwm_outs[] = { PWM_OUT_0, PWM_OUT_1, PWM_OUT_2, PWM_OUT_3, PWM_OUT_4, PWM_OUT_5 };
+static const u16 pwm_gpio_pins[] = { GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9 };
static void pwms_init()
{
- SysCtlPeripheralEnable( SYSCTL_PERIPH_PWM );
- SysCtlPWMClockSet( SYSCTL_PWMDIV_1 );
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_TIM8, ENABLE );
+ //
}
// Helper function: return the PWM clock
+// NOTE: Can't find a function to query for the period set for the timer, therefore using the struct.
+// This may require adjustment if driver libraries are updated.
static u32 platform_pwm_get_clock()
{
- unsigned i;
- u32 clk;
-
- clk = SysCtlPWMClockGet();
- for( i = 0; i < sizeof( pwm_div_ctl ) / sizeof( u32 ); i ++ )
- if( clk == pwm_div_ctl[ i ] )
- break;
- return SysCtlClockGet() / pwm_div_data[ i ];
+ return ( ( TIM_GET_BASE_CLK( PWM_TIMER_ID ) / ( TIM_GetPrescaler( PWM_TIMER_NAME ) + 1 ) ) / ( PWM_TIMER_NAME->ARR + 1 ) );
}
// Helper function: set the PWM clock
static u32 platform_pwm_set_clock( u32 clock )
{
- unsigned i, min_i;
- u32 sysclk;
-
- sysclk = SysCtlClockGet();
- for( i = min_i = 0; i < sizeof( pwm_div_data ) / sizeof( u8 ); i ++ )
- if( ABSDIFF( clock, sysclk / pwm_div_data[ i ] ) < ABSDIFF( clock, sysclk / pwm_div_data[ min_i ] ) )
- min_i = i;
- SysCtlPWMClockSet( pwm_div_ctl[ min_i ] );
- return sysclk / pwm_div_data[ min_i ];
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+ TIM_TypeDef* ptimer = PWM_TIMER_NAME;
+
+ /* Time base configuration */
+ TIM_TimeBaseStructure.TIM_Period = ( TIM_GET_BASE_CLK( PWM_TIMER_ID ) / clock ) - 1;
+ TIM_TimeBaseStructure.TIM_Prescaler = 0;
+ TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
+ TIM_TimeBaseInit( ptimer, &TIM_TimeBaseStructure );
+
+ return ( TIM_GET_BASE_CLK( PWM_TIMER_ID ) / ( TIM_TimeBaseStructure.TIM_Period + 1 ) ) ;
}
-int platform_pwm_exists( unsigned id )
-{
- return id < PLATFORM_NUM_PWMS;
-}
-
u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
{
- u32 pwmclk = platform_pwm_get_clock();
- u32 period;
-
- // Set pin as PWM
- GPIOPinTypePWM( pwm_ports[ id ], pwm_pins[ id ] );
- // Compute period
- period = pwmclk / frequency;
- // Set the period
- PWMGenConfigure( PWM_BASE, pwm_gens[ id >> 1 ], PWM_GEN_MODE_UP_DOWN | PWM_GEN_MODE_NO_SYNC );
- PWMGenPeriodSet( PWM_BASE, pwm_gens[ id >> 1 ], period );
- // Set duty cycle
- PWMPulseWidthSet( PWM_BASE, pwm_outs[ id ], ( period * duty ) / 100 );
- // Return actual frequency
- return pwmclk / period;
+ TIM_OCInitTypeDef TIM_OCInitStructure;
+ TIM_TypeDef* ptimer = TIM8;
+ GPIO_InitTypeDef GPIO_InitStructure;
+ u32 clock;
+
+ TIM_Cmd( ptimer, DISABLE);
+ TIM_SetCounter( ptimer, 0 );
+
+ /* Configure USART Tx Pin as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = pwm_gpio_pins[ id ];
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+ clock = platform_pwm_set_clock( frequency );
+ TIM_ARRPreloadConfig( ptimer, ENABLE );
+
+ /* PWM Mode configuration */
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_OutputState = ( PWM_TIMER_NAME->CCER & ( ( u16 )1 << 4*id ) ) ? TIM_OutputState_Enable : TIM_OutputState_Disable;
+ TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
+ TIM_OCInitStructure.TIM_Pulse = ( u16 )( duty * ( PWM_TIMER_NAME->ARR + 1 ) / 100 );
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
+
+ switch ( id )
+ {
+ case 0:
+ TIM_OC1Init( ptimer, &TIM_OCInitStructure );
+ TIM_OC1PreloadConfig( ptimer, TIM_OCPreload_Enable );
+ break;
+ case 1:
+ TIM_OC2Init( ptimer, &TIM_OCInitStructure );
+ TIM_OC2PreloadConfig( ptimer, TIM_OCPreload_Enable );
+ break;
+ case 2:
+ TIM_OC3Init( ptimer, &TIM_OCInitStructure );
+ TIM_OC3PreloadConfig( ptimer, TIM_OCPreload_Enable );
+ break;
+ case 3:
+ TIM_OC4Init( ptimer, &TIM_OCInitStructure );
+ TIM_OC4PreloadConfig( ptimer, TIM_OCPreload_Enable ) ;
+ break;
+ default:
+ return 0;
+ }
+
+ TIM_CtrlPWMOutputs(ptimer, ENABLE);
+
+ TIM_Cmd( ptimer, ENABLE );
+
+ return clock;
}
u32 platform_pwm_op( unsigned id, int op, u32 data )
@@ -688,198 +892,289 @@
break;
case PLATFORM_PWM_OP_START:
- PWMOutputState( PWM_BASE, 1 << id, true );
- PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
+ PWM_TIMER_NAME->CCER |= ( ( u16 )1 << 4*id );
break;
case PLATFORM_PWM_OP_STOP:
- PWMOutputState( PWM_BASE, 1 << id, false );
- PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
+ PWM_TIMER_NAME->CCER &= ~( ( u16 )1 << 4*id );
break;
}
return res;
}
-#endif
+
+
// *****************************************************************************
// CPU specific functions
-
+
void platform_cpu_enable_interrupts()
{
- //IntMasterEnable();
+ void NVIC_RESETPRIMASK(void); // enable interrupts
}
void platform_cpu_disable_interrupts()
{
- //IntMasterDisable();
+ void NVIC_SETPRIMASK(void); // disable interrupts
}
u32 platform_s_cpu_get_frequency()
{
- RCC_ClocksTypeDef clocks;
+ return HCLK;
+}
- RCC_GetClocksFreq(&clocks);
+// *****************************************************************************
+// ADC specific functions and variables
- return clocks.HCLK_Frequency;
-}
+#define ADC1_DR_Address ((u32)ADC1_BASE + 0x4C)
-u32 platform_pclk1_get_frequency()
-{
- RCC_ClocksTypeDef clocks;
+static ADC_TypeDef *const adc[] = { ADC1, ADC2, ADC3 };
+static const u32 adc_timer[] = { ADC_ExternalTrigConv_T1_CC1, ADC_ExternalTrigConv_T2_CC2, ADC_ExternalTrigConv_T3_TRGO, ADC_ExternalTrigConv_T4_CC4 };
- RCC_GetClocksFreq(&clocks);
+ADC_InitTypeDef adc_init_struct;
+DMA_InitTypeDef dma_init_struct;
- return clocks.PCLK1_Frequency;
+int platform_adc_check_timer_id( unsigned id, unsigned timer_id )
+{
+ // NOTE: We only allow timer 2 at the moment, for the sake of implementation simplicity
+ return ( timer_id == 2 );
}
-u32 platform_pclk2_get_frequency()
+void platform_adc_stop( unsigned id )
{
- RCC_ClocksTypeDef clocks;
+ elua_adc_ch_state *s = adc_get_ch_state( id );
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+ s->op_pending = 0;
+ INACTIVATE_CHANNEL( d, id );
- RCC_GetClocksFreq(&clocks);
+ // If there are no more active channels, stop the sequencer
+ if( d->ch_active == 0 )
+ {
+ // Ensure that no external triggers are firing
+ ADC_ExternalTrigConvCmd( adc[ d->seq_id ], DISABLE );
+
+ // Also ensure that DMA interrupt won't fire ( this shouldn't really be necessary )
+ nvic_init_structure_adc.NVIC_IRQChannelCmd = DISABLE;
+ NVIC_Init(&nvic_init_structure_adc);
+
+ d->running = 0;
+ }
+}
- return clocks.PCLK2_Frequency;
+int platform_adc_update_sequence( )
+{
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+ // NOTE: this shutdown/startup stuff may or may not be absolutely necessary
+ // it is here to deal with the situation that a dma conversion has
+ // already started and should be reset.
+ ADC_ExternalTrigConvCmd( adc[ d->seq_id ], DISABLE );
+
+ // Stop in-progress adc dma transfers
+ // Later de/reinitialization should flush out synchronization problems
+ ADC_DMACmd( adc[ d->seq_id ], DISABLE );
+
+ // Bring down adc, update setup, bring back up
+ ADC_Cmd( adc[ d->seq_id ], DISABLE );
+ ADC_DeInit( adc[ d->seq_id ] );
+
+ d->seq_ctr = 0;
+ while( d->seq_ctr < d->seq_len )
+ {
+ ADC_RegularChannelConfig( adc[ d->seq_id ], d->ch_state[ d->seq_ctr ]->id, d->seq_ctr+1, ADC_SampleTime_1Cycles5 );
+ d->seq_ctr++;
+ }
+ d->seq_ctr = 0;
+
+ adc_init_struct.ADC_NbrOfChannel = d->seq_len;
+ ADC_Init( adc[ d->seq_id ], &adc_init_struct );
+ ADC_Cmd( adc[ d->seq_id ], ENABLE );
+
+ // Bring down adc dma, update setup, bring back up
+ DMA_Cmd( DMA1_Channel1, DISABLE );
+ DMA_DeInit( DMA1_Channel1 );
+ dma_init_struct.DMA_BufferSize = d->seq_len;
+ dma_init_struct.DMA_MemoryBaseAddr = (u32)d->sample_buf;
+ DMA_Init( DMA1_Channel1, &dma_init_struct );
+ DMA_Cmd( DMA1_Channel1, ENABLE );
+
+ ADC_DMACmd( adc[ d->seq_id ], ENABLE );
+ DMA_ITConfig( DMA1_Channel1, DMA1_IT_TC1 , ENABLE );
+
+ if ( d->clocked == 1 && d->running == 1 )
+ ADC_ExternalTrigConvCmd( adc[ d->seq_id ], ENABLE );
+
+ return PLATFORM_OK;
}
-// ****************************************************************************
-// Ethernet functions
-
-static void eth_init()
+void DMA1_Channel1_IRQHandler(void)
{
-#ifdef BUILD_UIP
- u32 user0, user1, temp;
- static struct uip_eth_addr sTempAddr;
-
- // Enable and reset the controller
- SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );
- SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );
-
- // Enable Ethernet LEDs
- GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW );
- GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );
-
- // Configure SysTick for a periodic interrupt.
- SysTickPeriodSet(SysCtlClockGet() / SYSTICKHZ);
- SysTickEnable();
- SysTickIntEnable();
-
- // Intialize the Ethernet Controller and disable all Ethernet Controller interrupt sources.
- EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
- ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
- temp = EthernetIntStatus(ETH_BASE, false);
- EthernetIntClear(ETH_BASE, temp);
-
- // Initialize the Ethernet Controller for operation.
- EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
-
- // Configure the Ethernet Controller for normal operation.
- // - Full Duplex
- // - TX CRC Auto Generation
- // - TX Padding Enabled
- EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
- ETH_CFG_TX_PADEN));
-
- // Enable the Ethernet Controller.
- EthernetEnable(ETH_BASE);
-
- // Enable the Ethernet interrupt.
- IntEnable(INT_ETH);
-
- // Enable the Ethernet RX Packet interrupt source.
- EthernetIntEnable(ETH_BASE, ETH_INT_RX);
-
- // Enable all processor interrupts.
- IntMasterEnable();
-
- // Configure the hardware MAC address for Ethernet Controller filtering of
- // incoming packets.
- //
- // For the Ethernet Eval Kits, the MAC address will be stored in the
- // non-volatile USER0 and USER1 registers. These registers can be read
- // using the FlashUserGet function, as illustrated below.
- FlashUserGet(&user0, &user1);
-
- // Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
- // address needed to program the hardware registers, then program the MAC
- // address into the Ethernet Controller registers.
- sTempAddr.addr[0] = ((user0 >> 0) & 0xff);
- sTempAddr.addr[1] = ((user0 >> 8) & 0xff);
- sTempAddr.addr[2] = ((user0 >> 16) & 0xff);
- sTempAddr.addr[3] = ((user1 >> 0) & 0xff);
- sTempAddr.addr[4] = ((user1 >> 8) & 0xff);
- sTempAddr.addr[5] = ((user1 >> 16) & 0xff);
-
- // Program the hardware with it's MAC address (for filtering).
- EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
-
- // Initialize the eLua uIP layer
- elua_uip_init( &sTempAddr );
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+ elua_adc_ch_state *s;
+
+ DMA_ClearITPendingBit( DMA1_IT_TC1 );
+
+ d->seq_ctr = 0;
+ while( d->seq_ctr < d->seq_len )
+ {
+ s = d->ch_state[ d->seq_ctr ];
+ s->value_fresh = 1;
+
+ // Fill in smoothing buffer until warmed up
+ if ( s->logsmoothlen > 0 && s->smooth_ready == 0)
+ adc_smooth_data( s->id );
+#if defined( BUF_ENABLE_ADC )
+ else if ( s->reqsamples > 1 )
+ {
+ buf_write( BUF_ID_ADC, s->id, ( t_buf_data* )s->value_ptr );
+ s->value_fresh = 0;
+ }
#endif
-}
-#ifdef BUILD_UIP
-static int eth_timer_fired;
+ // If we have the number of requested samples, stop sampling
+ if ( adc_samples_available( s->id ) >= s->reqsamples && s->freerunning == 0 )
+ platform_adc_stop( s->id );
-void platform_eth_send_packet( const void* src, u32 size )
-{
- EthernetPacketPut( ETH_BASE, uip_buf, uip_len );
-}
+ d->seq_ctr++;
+ }
+ d->seq_ctr = 0;
-u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
-{
- return EthernetPacketGetNonBlocking( ETH_BASE, uip_buf, sizeof( uip_buf ) );
+ if( d->running == 1 )
+ adc_update_dev_sequence( 0 );
+
+ if ( d->clocked == 0 && d->running == 1 )
+ ADC_SoftwareStartConvCmd( adc[ d->seq_id ], ENABLE );
}
-void platform_eth_force_interrupt()
+static void adcs_init()
{
- HWREG( NVIC_SW_TRIG) |= INT_ETH - 16;
+ unsigned id;
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+ for( id = 0; id < NUM_ADC; id ++ )
+ adc_init_ch_state( id );
+
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_ADC1, ENABLE );
+ RCC_ADCCLKConfig( RCC_PCLK2_Div8 );
+
+ ADC_DeInit( adc[ d->seq_id ] );
+ ADC_StructInit( &adc_init_struct );
+
+ // Universal Converter Setup
+ adc_init_struct.ADC_Mode = ADC_Mode_Independent;
+ adc_init_struct.ADC_ScanConvMode = ENABLE;
+ adc_init_struct.ADC_ContinuousConvMode = DISABLE;
+ adc_init_struct.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+ adc_init_struct.ADC_DataAlign = ADC_DataAlign_Right;
+ adc_init_struct.ADC_NbrOfChannel = 1;
+
+ // Apply default config
+ ADC_Init( adc[ d->seq_id ], &adc_init_struct );
+ ADC_ExternalTrigConvCmd( adc[ d->seq_id ], DISABLE );
+
+ // Enable ADC
+ ADC_Cmd( adc[ d->seq_id ], ENABLE );
+
+ // Reset/Perform ADC Calibration
+ ADC_ResetCalibration( adc[ d->seq_id ] );
+ while( ADC_GetResetCalibrationStatus( adc[ d->seq_id ] ) );
+ ADC_StartCalibration( adc[ d->seq_id ] );
+ while( ADC_GetCalibrationStatus( adc[ d->seq_id ] ) );
+
+ // Set up DMA to handle samples
+ RCC_AHBPeriphClockCmd( RCC_AHBPeriph_DMA1, ENABLE );
+
+ DMA_DeInit( DMA1_Channel1 );
+ dma_init_struct.DMA_PeripheralBaseAddr = ADC1_DR_Address;
+ dma_init_struct.DMA_MemoryBaseAddr = (u32)d->sample_buf;
+ dma_init_struct.DMA_DIR = DMA_DIR_PeripheralSRC;
+ dma_init_struct.DMA_BufferSize = 1;
+ dma_init_struct.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ dma_init_struct.DMA_MemoryInc = DMA_MemoryInc_Enable;
+ dma_init_struct.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+ dma_init_struct.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+ dma_init_struct.DMA_Mode = DMA_Mode_Circular;
+ dma_init_struct.DMA_Priority = DMA_Priority_Low;
+ dma_init_struct.DMA_M2M = DMA_M2M_Disable;
+ DMA_Init( DMA1_Channel1, &dma_init_struct );
+
+ ADC_DMACmd(ADC1, ENABLE );
+
+ DMA_Cmd( DMA1_Channel1, ENABLE );
+ DMA_ITConfig( DMA1_Channel1, DMA1_IT_TC1 , ENABLE );
+
+ platform_adc_setclock( 0, 0 );
}
-u32 platform_eth_get_elapsed_time()
+u32 platform_adc_setclock( unsigned id, u32 frequency )
{
- if( eth_timer_fired )
+ TIM_TimeBaseInitTypeDef timer_base_struct;
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+ unsigned period, prescaler;
+
+ // Make sure sequencer is disabled before making changes
+ ADC_ExternalTrigConvCmd( adc[ d->seq_id ], DISABLE );
+
+ if ( frequency > 0 )
{
- eth_timer_fired = 0;
- return SYSTICKMS;
+ d->clocked = 1;
+ // Attach timer to converter
+ adc_init_struct.ADC_ExternalTrigConv = adc_timer[ d->timer_id ];
+
+ period = TIM_GET_BASE_CLK( id ) / frequency;
+
+ prescaler = (period / 0x10000) + 1;
+ period /= prescaler;
+
+ timer_base_struct.TIM_Period = period - 1;
+ timer_base_struct.TIM_Prescaler = (2 * prescaler) - 1;
+ timer_base_struct.TIM_ClockDivision = TIM_CKD_DIV1;
+ timer_base_struct.TIM_CounterMode = TIM_CounterMode_Down;
+ TIM_TimeBaseInit( timer[ d->timer_id ], &timer_base_struct );
+
+ frequency = 2 * ( TIM_GET_BASE_CLK( id ) / ( TIM_GetPrescaler( timer[ d->timer_id ] ) + 1 ) ) / period;
+
+ // Set up output compare for timer
+ TIM_SelectOutputTrigger(timer[ d->timer_id ], TIM_TRGOSource_Update);
}
else
- return 0;
+ {
+ d->clocked = 0;
+
+ // Switch to Software-only Trigger
+ adc_init_struct.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+ }
+
+ // Apply config
+ ADC_Init( adc[ d->seq_id ], &adc_init_struct );
+
+ return frequency;
}
-#if 0
-void SysTickHandler(void)
-{
- // Indicate that a SysTick interrupt has occurred.
- eth_timer_fired = 1;
+int platform_adc_start_sequence( )
+{
+ elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+ // Only force update and initiate if we weren't already running
+ // changes will get picked up during next interrupt cycle
+ if ( d->running != 1 )
+ {
+ adc_update_dev_sequence( 0 );
+
+ d->running = 1;
+
+ DMA_ClearITPendingBit( DMA1_IT_TC1 );
- // Generate a fake Ethernet interrupt. This will perform the actual work
- // of incrementing the timers and taking the appropriate actions.
- platform_eth_force_interrupt();
-}
-#endif
+ nvic_init_structure_adc.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&nvic_init_structure_adc);
-void EthernetIntHandler()
-{
- u32 temp;
+ if( d->clocked == 1 )
+ ADC_ExternalTrigConvCmd( adc[ d->seq_id ], ENABLE );
+ else
+ ADC_SoftwareStartConvCmd( adc[ d->seq_id ], ENABLE );
+ }
- // Read and Clear the interrupt.
- temp = EthernetIntStatus( ETH_BASE, false );
- EthernetIntClear( ETH_BASE, temp );
-
- // Call the UIP main loop
- elua_uip_mainloop();
-}
-
-#else // #ifdef ELUA_UIP
-
-#if 0
-void SysTickHandler()
-{
-}
-#endif
-
-void EthernetIntHandler()
-{
-}
-#endif // #ifdef ELUA_UIP
+ return PLATFORM_OK;
+}
\ No newline at end of file
Modified: branches/eagle_mmc/src/platform/stm32/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -5,11 +5,13 @@
#include "auxmods.h"
#include "type.h"
+#include "stacks.h"
+#include "stm32f10x.h"
// *****************************************************************************
// Define here what components you want for this platform
-//#define BUILD_XMODEM
+#define BUILD_XMODEM
#define BUILD_SHELL
#define BUILD_ROMFS
#define BUILD_TERM
@@ -17,53 +19,47 @@
//#define BUILD_DHCPC
//#define BUILD_DNS
#define BUILD_CON_GENERIC
+#define BUILD_ADC
+#define BUILD_LUARPC
//#define BUILD_CON_TCP
-#define EXTENDED_PLATFORM_DATA
// *****************************************************************************
// UART/Timer IDs configuration data (used in main.c)
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
+#ifdef FORSTM3210E_EVAL
#define AUXLIB_LCD "stm3210lcd"
LUALIB_API int ( luaopen_lcd )( lua_State* L );
-
-#if 0
-#define LUA_PLATFORM_LIBS\
- { AUXLIB_PIO, luaopen_pio },\
- { AUXLIB_SPI, luaopen_spi },\
- { AUXLIB_TMR, luaopen_tmr },\
- { AUXLIB_PD, luaopen_pd },\
- { AUXLIB_UART, luaopen_uart },\
- { AUXLIB_TERM, luaopen_term },\
- { AUXLIB_PWM, luaopen_pwm },\
- { AUXLIB_PACK, luaopen_pack },\
- { AUXLIB_BIT, luaopen_bit },\
- { AUXLIB_NET, luaopen_net },\
- { AUXLIB_CPU, luaopen_cpu },\
- { LUA_MATHLIBNAME, luaopen_math }
+#define LCDLINE _ROM( AUXLIB_LCD, luaopen_lcd, lcd_map )
#else
+#define LCDLINE
+#endif
+
#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+ _ROM( AUXLIB_SPI, luaopen_spi, spi_map )\
_ROM( AUXLIB_PD, luaopen_pd, pd_map )\
_ROM( AUXLIB_UART, luaopen_uart, uart_map )\
_ROM( AUXLIB_TERM, luaopen_term, term_map )\
_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
_ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
- _ROM( AUXLIB_LCD, luaopen_lcd, lcd_map )\
+ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+ _ROM( AUXLIB_ADC, luaopen_adc, adc_map )\
+ _ROM( AUXLIB_CAN, luaopen_can, can_map )\
+ _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+ _ROM( AUXLIB_LUARPC, luaopen_luarpc, rpc_map )\
+ LCDLINE\
_ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
-#endif
-
+
// *****************************************************************************
// Configuration data
@@ -97,12 +93,27 @@
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 7
-#define NUM_SPI 0
-#define NUM_UART 4
-#define NUM_TIMER 0
-#define NUM_PWM 0
-#define NUM_ADC 0
+#define NUM_SPI 2
+#define NUM_UART 5
+#define NUM_TIMER 5
+#define NUM_PWM 4
+#define NUM_ADC 16
+#define NUM_CAN 1
+// Enable RX buffering on UART
+#define BUF_ENABLE_UART
+#define CON_BUF_SIZE BUF_SIZE_128
+
+// ADC Configuration Params
+#define ADC_BIT_RESOLUTION 12
+#define BUF_ENABLE_ADC
+#define ADC_BUF_SIZE BUF_SIZE_2
+
+// These should be adjusted to support multiple ADC devices
+#define ADC_TIMER_FIRST_ID 0
+#define ADC_NUM_TIMERS 4
+
+
// CPU frequency (needed by the CPU module, 0 if not used)
u32 platform_s_cpu_get_frequency();
#define CPU_FREQUENCY platform_s_cpu_get_frequency()
@@ -113,70 +124,13 @@
// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
-#define PIO_PIN_ARRAY { 16, 16, 16, 16, 16, 16, 16 }
+#define PIO_PINS_PER_PORT 16
// Allocator data: define your free memory zones here in two arrays
// (start address and end address)
-#define STACK_SIZE 256
#define SRAM_SIZE ( 64 * 1024 )
#define MEM_START_ADDRESS { ( void* )end }
-#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + SRAM_SIZE - STACK_SIZE - 1 ) }
+#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) }
-// *****************************************************************************
-// CPU constants that should be exposed to the eLua "cpu" module
-
-#include "stm32f10x_gpio.h"
-
-#if 0
-#define PLATFORM_CPU_CONSTANTS\
- _C( INT_GPIOA ),\
- _C( INT_GPIOB ),\
- _C( INT_GPIOC ),\
- _C( INT_GPIOD ),\
- _C( INT_GPIOE ),\
- _C( INT_UART0 ),\
- _C( INT_UART1 ),\
- _C( INT_SSI0 ),\
- _C( INT_I2C0 ),\
- _C( INT_PWM_FAULT ),\
- _C( INT_PWM0 ),\
- _C( INT_PWM1 ),\
- _C( INT_PWM2 ),\
- _C( INT_QEI0 ),\
- _C( INT_ADC0 ),\
- _C( INT_ADC1 ),\
- _C( INT_ADC2 ),\
- _C( INT_ADC3 ),\
- _C( INT_WATCHDOG ),\
- _C( INT_TIMER0A ),\
- _C( INT_TIMER0B ),\
- _C( INT_TIMER1A ),\
- _C( INT_TIMER1B ),\
- _C( INT_TIMER2A ),\
- _C( INT_TIMER2B ),\
- _C( INT_COMP0 ),\
- _C( INT_COMP1 ),\
- _C( INT_COMP2 ),\
- _C( INT_SYSCTL ),\
- _C( INT_FLASH ),\
- _C( INT_GPIOF ),\
- _C( INT_GPIOG ),\
- _C( INT_GPIOH ),\
- _C( INT_UART2 ),\
- _C( INT_SSI1 ),\
- _C( INT_TIMER3A ),\
- _C( INT_TIMER3B ),\
- _C( INT_I2C1 ),\
- _C( INT_QEI1 ),\
- _C( INT_CAN0 ),\
- _C( INT_CAN1 ),\
- _C( INT_CAN2 ),\
- _C( INT_ETH ),\
- _C( INT_HIBERNATE ),\
- _C( INT_USB0 ),\
- _C( INT_PWM3 ),\
- _C( INT_UDMA ),\
- _C( INT_UDMAERR )
-#endif
-
#endif // #ifndef __PLATFORM_CONF_H__
+
Added: branches/eagle_mmc/src/platform/stm32/stacks.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stacks.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stacks.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,9 @@
+// Stack size definitions
+
+#ifndef __STACKS_H__
+#define __STACKS_H__
+
+#define STACK_SIZE 2048
+#define STACK_SIZE_TOTAL ( STACK_SIZE )
+
+#endif
Added: branches/eagle_mmc/src/platform/stm32/startup_stm32f10x_hd.s
===================================================================
--- branches/eagle_mmc/src/platform/stm32/startup_stm32f10x_hd.s 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/startup_stm32f10x_hd.s 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_hd.s
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure external SRAM mounted on STM3210E-EVAL board
+ * to be used as data memory (optional, to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ *******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global SystemInit_ExtMemCtl_Dummy
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+.equ Initial_spTop, 0x20000400
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+ bl SystemInit_ExtMemCtl
+/* restore original stack pointer */
+ LDR r0, =_estack
+ MSR msp, r0
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief Dummy SystemInit_ExtMemCtl function
+ * @param None
+ * @retval : None
+*/
+ .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits
+SystemInit_ExtMemCtl_Dummy:
+ bx lr
+ .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word Initial_spTop
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FSMC_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x High Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+ .weak SystemInit_ExtMemCtl
+ .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy
+
Property changes on: branches/eagle_mmc/src/platform/stm32/startup_stm32f10x_hd.s
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/stm32/stm32.ld
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stm32.ld 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stm32.ld 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,244 +1,69 @@
-/*
-Default linker script for STM32F10x_512K_64K
-Copyright RAISONANCE S.A.S. 2008
-*/
-
-/* include the common STM32F10x sub-script */
-
-/* Common part of the linker scripts for STM32 devices*/
-
-
-/* default stack sizes.
-
-These are used by the startup in order to allocate stacks for the different modes.
-*/
-
-__Stack_Size = 2048 ;
-
-PROVIDE ( _Stack_Size = __Stack_Size ) ;
-
-__Stack_Init = _estack - __Stack_Size ;
-
-/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
-PROVIDE ( _Stack_Init = __Stack_Init ) ;
-
-/*
-There will be a link error if there is not this amount of RAM free at the end.
-*/
-_Minimum_Stack_Size = 0x100 ;
-
-
-/* include the memory spaces definitions sub-script */
-/*
-Linker subscript for STM32F10x definitions with 512K Flash and 64K RAM */
-
-/* Memory Spaces Definitions */
-
-MEMORY
-{
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
- EXTSRAM (xrw) : ORIGIN = 0x68000000, LENGTH = 8192K
- FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
- FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-}
-
-/* higher address of the user mode stack */
-_estack = 0x20010000;
-
-
-
-/* include the sections management sub-script for FLASH mode */
-
-/* Sections Definitions */
-
-SECTIONS
-{
- /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
- .flashtext :
- {
- . = ALIGN(4);
- *(.flashtext) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* the program code is stored in the .text section, which goes to Flash */
- .text :
- {
- . = ALIGN(4);
- PROVIDE(stext = .);
- *(.text) /* remaining code */
- *(.text.*) /* remaining code */
- *(.rodata) /* read-only data (constants) */
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
-
- . = ALIGN(4);
- _etext = .;
- PROVIDE(etext = .);
- /* This is used by the startup in order to initialize the .data secion */
- _sidata = _etext;
- } >FLASH
-
-
-
- /* This is the initialized data section
- The program executes knowing that the data is in the RAM
- but the loader puts the initial values in the FLASH (inidata).
- It is one task of the startup to copy the initial values from FLASH to RAM. */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _sdata = . ;
-
- *(.data)
- *(.data.*)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _edata = . ;
- } >RAM
-
-
-
- /* This is the uninitialized data section */
- .bss :
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .;
-
- *(.bss)
- *(.bss.*)
- *(COMMON)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
- } >RAM
-
- PROVIDE ( end = _ebss );
- PROVIDE ( _end = _ebss );
-
- /* This is the user stack section
- This is just to check that there is enough RAM left for the User mode stack
- It should generate an error if it's full.
- */
- ._usrstack :
- {
- . = ALIGN(4);
- _susrstack = . ;
-
- . = . + _Minimum_Stack_Size ;
-
- . = ALIGN(4);
- _eusrstack = . ;
- } >RAM
-
-
-
- /* this is the FLASH Bank1 */
- /* the C or assembly source must explicitly place the code or data there
- using the "section" attribute */
- .b1text :
- {
- *(.b1text) /* remaining code */
- *(.b1rodata) /* read-only data (constants) */
- *(.b1rodata*)
- } >FLASHB1
-
- /* this is the EXTMEM */
- /* the C or assembly source must explicitly place the code or data there
- using the "section" attribute */
-
- /* EXTMEM Bank0 */
- .eb0text :
- {
- *(.eb0text) /* remaining code */
- *(.eb0rodata) /* read-only data (constants) */
- *(.eb0rodata*)
- } >EXTMEMB0
-
- /* EXTMEM Bank1 */
- .eb1text :
- {
- *(.eb1text) /* remaining code */
- *(.eb1rodata) /* read-only data (constants) */
- *(.eb1rodata*)
- } >EXTMEMB1
-
- /* EXTMEM Bank2 */
- .eb2text :
- {
- *(.eb2text) /* remaining code */
- *(.eb2rodata) /* read-only data (constants) */
- *(.eb2rodata*)
- } >EXTMEMB2
-
- /* EXTMEM Bank0 */
- .eb3text :
- {
- *(.eb3text) /* remaining code */
- *(.eb3rodata) /* read-only data (constants) */
- *(.eb3rodata*)
- } >EXTMEMB3
-
-
-
- /* after that it's only debugging information. */
-
- /* remove the debugging information from the standard libraries */
- DISCARD :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 64k
+ flash (RX) : ORIGIN = 0x08000000, LENGTH = 512k
+}
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _text = .;
+ PROVIDE(stext = .);
+ KEEP(*(.isr_vector))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ . = ALIGN(4);
+ _etext = .;
+ _sidata = _etext;
+ PROVIDE(etext = .);
+ _fini = . ;
+ *(.fini)
+
+ } >flash
+
+ .data : AT (_etext)
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ *(.ramfunc .ramfunc.* .fastrun .fastrun.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(4);
+ _edata = .;
+ } >sram
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
+ .bss (NOLOAD) : {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ } >sram
+
+ end = .;
+ PROVIDE( _estack = 0x20010000 );
+}
+
Added: branches/eagle_mmc/src/platform/stm32/stm32f10x.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stm32f10x.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stm32f10x.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,7851 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F10x Connectivity line, High
+ * density, Medium density and Low density devices.
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x
+ * @{
+ */
+
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
+ #define STM32F10X_HD /*!< STM32F10X_HD: STM32 High density devices */
+ //#define STM32F10X_CL /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High density devices are STM32F101xx and STM32F103xx microcontrollers where
+ the Flash memory density ranges between 256 and 512 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_STDPERIPH_DRIVER
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_Value
+ #ifdef STM32F10X_CL
+ #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else
+ #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_Value */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
+
+#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+ */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
+ | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
+ | __STM32F10X_STDPERIPH_VERSION_SUB2)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+
+#ifdef STM32F10X_LD
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_LD */
+
+#ifdef STM32F10X_MD
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_MD */
+
+#ifdef STM32F10X_HD
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_CL
+ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
+#endif /* STM32F10X_CL */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+
+#ifndef __cplusplus
+// typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+#endif
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint16_t DR1;
+ uint16_t RESERVED1;
+ __IO uint16_t DR2;
+ uint16_t RESERVED2;
+ __IO uint16_t DR3;
+ uint16_t RESERVED3;
+ __IO uint16_t DR4;
+ uint16_t RESERVED4;
+ __IO uint16_t DR5;
+ uint16_t RESERVED5;
+ __IO uint16_t DR6;
+ uint16_t RESERVED6;
+ __IO uint16_t DR7;
+ uint16_t RESERVED7;
+ __IO uint16_t DR8;
+ uint16_t RESERVED8;
+ __IO uint16_t DR9;
+ uint16_t RESERVED9;
+ __IO uint16_t DR10;
+ uint16_t RESERVED10;
+ __IO uint16_t RTCCR;
+ uint16_t RESERVED11;
+ __IO uint16_t CR;
+ uint16_t RESERVED12;
+ __IO uint16_t CSR;
+ uint16_t RESERVED13[5];
+ __IO uint16_t DR11;
+ uint16_t RESERVED14;
+ __IO uint16_t DR12;
+ uint16_t RESERVED15;
+ __IO uint16_t DR13;
+ uint16_t RESERVED16;
+ __IO uint16_t DR14;
+ uint16_t RESERVED17;
+ __IO uint16_t DR15;
+ uint16_t RESERVED18;
+ __IO uint16_t DR16;
+ uint16_t RESERVED19;
+ __IO uint16_t DR17;
+ uint16_t RESERVED20;
+ __IO uint16_t DR18;
+ uint16_t RESERVED21;
+ __IO uint16_t DR19;
+ uint16_t RESERVED22;
+ __IO uint16_t DR20;
+ uint16_t RESERVED23;
+ __IO uint16_t DR21;
+ uint16_t RESERVED24;
+ __IO uint16_t DR22;
+ uint16_t RESERVED25;
+ __IO uint16_t DR23;
+ uint16_t RESERVED26;
+ __IO uint16_t DR24;
+ uint16_t RESERVED27;
+ __IO uint16_t DR25;
+ uint16_t RESERVED28;
+ __IO uint16_t DR26;
+ uint16_t RESERVED29;
+ __IO uint16_t DR27;
+ uint16_t RESERVED30;
+ __IO uint16_t DR28;
+ uint16_t RESERVED31;
+ __IO uint16_t DR29;
+ uint16_t RESERVED32;
+ __IO uint16_t DR30;
+ uint16_t RESERVED33;
+ __IO uint16_t DR31;
+ uint16_t RESERVED34;
+ __IO uint16_t DR32;
+ uint16_t RESERVED35;
+ __IO uint16_t DR33;
+ uint16_t RESERVED36;
+ __IO uint16_t DR34;
+ uint16_t RESERVED37;
+ __IO uint16_t DR35;
+ uint16_t RESERVED38;
+ __IO uint16_t DR36;
+ uint16_t RESERVED39;
+ __IO uint16_t DR37;
+ uint16_t RESERVED40;
+ __IO uint16_t DR38;
+ uint16_t RESERVED41;
+ __IO uint16_t DR39;
+ uint16_t RESERVED42;
+ __IO uint16_t DR40;
+ uint16_t RESERVED43;
+ __IO uint16_t DR41;
+ uint16_t RESERVED44;
+ __IO uint16_t DR42;
+ uint16_t RESERVED45;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+#ifndef STM32F10X_CL
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+ CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR;
+ __IO uint8_t IDR;
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CR;
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ uint32_t RESERVED8[567];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ uint32_t RESERVED9[9];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2;
+ __IO uint32_t SR2;
+ __IO uint32_t PMEM2;
+ __IO uint32_t PATT2;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR2;
+} FSMC_Bank2_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR3;
+ __IO uint32_t SR3;
+ __IO uint32_t PMEM3;
+ __IO uint32_t PATT3;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR3;
+} FSMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+} AFIO_TypeDef;
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t OAR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OAR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DR;
+ uint16_t RESERVED4;
+ __IO uint16_t SR1;
+ uint16_t RESERVED5;
+ __IO uint16_t SR2;
+ uint16_t RESERVED6;
+ __IO uint16_t CCR;
+ uint16_t RESERVED7;
+ __IO uint16_t TRISE;
+ uint16_t RESERVED8;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR;
+ __IO uint32_t PR;
+ __IO uint32_t RLR;
+ __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+#ifdef STM32F10X_CL
+ __IO uint32_t AHBRSTR;
+ __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint16_t CRH;
+ uint16_t RESERVED0;
+ __IO uint16_t CRL;
+ uint16_t RESERVED1;
+ __IO uint16_t PRLH;
+ uint16_t RESERVED2;
+ __IO uint16_t PRLL;
+ uint16_t RESERVED3;
+ __IO uint16_t DIVH;
+ uint16_t RESERVED4;
+ __IO uint16_t DIVL;
+ uint16_t RESERVED5;
+ __IO uint16_t CNTH;
+ uint16_t RESERVED6;
+ __IO uint16_t CNTL;
+ uint16_t RESERVED7;
+ __IO uint16_t ALRH;
+ uint16_t RESERVED8;
+ __IO uint16_t ALRL;
+ uint16_t RESERVED9;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SR;
+ uint16_t RESERVED2;
+ __IO uint16_t DR;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPR;
+ uint16_t RESERVED4;
+ __IO uint16_t RXCRCR;
+ uint16_t RESERVED5;
+ __IO uint16_t TXCRCR;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFGR;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPR;
+ uint16_t RESERVED8;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SMCR;
+ uint16_t RESERVED2;
+ __IO uint16_t DIER;
+ uint16_t RESERVED3;
+ __IO uint16_t SR;
+ uint16_t RESERVED4;
+ __IO uint16_t EGR;
+ uint16_t RESERVED5;
+ __IO uint16_t CCMR1;
+ uint16_t RESERVED6;
+ __IO uint16_t CCMR2;
+ uint16_t RESERVED7;
+ __IO uint16_t CCER;
+ uint16_t RESERVED8;
+ __IO uint16_t CNT;
+ uint16_t RESERVED9;
+ __IO uint16_t PSC;
+ uint16_t RESERVED10;
+ __IO uint16_t ARR;
+ uint16_t RESERVED11;
+ __IO uint16_t RCR;
+ uint16_t RESERVED12;
+ __IO uint16_t CCR1;
+ uint16_t RESERVED13;
+ __IO uint16_t CCR2;
+ uint16_t RESERVED14;
+ __IO uint16_t CCR3;
+ uint16_t RESERVED15;
+ __IO uint16_t CCR4;
+ uint16_t RESERVED16;
+ __IO uint16_t BDTR;
+ uint16_t RESERVED17;
+ __IO uint16_t DCR;
+ uint16_t RESERVED18;
+ __IO uint16_t DMAR;
+ uint16_t RESERVED19;
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR;
+ uint16_t RESERVED0;
+ __IO uint16_t DR;
+ uint16_t RESERVED1;
+ __IO uint16_t BRR;
+ uint16_t RESERVED2;
+ __IO uint16_t CR1;
+ uint16_t RESERVED3;
+ __IO uint16_t CR2;
+ uint16_t RESERVED4;
+ __IO uint16_t CR3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTPR;
+ uint16_t RESERVED6;
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFR;
+ __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
+
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
+
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
+ #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
+ #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
+ #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
+ #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+
+ #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+ #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+ #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
+ #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+#else
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+ #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
+ #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
+ #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
+ #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
+ #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
+ #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
+#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
+#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_HD
+ #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */
+ #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */
+ #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
+ #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
+#endif /* STM32F10X_HD */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
+ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#endif /* STM32F10X_HD */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
+ #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
+#endif
+
+#ifdef STM32F10X_HD
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
+ #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_CL
+ #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
+ #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
+ #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
+ #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
+#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_HD
+ #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
+ #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
+ #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
+ #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
+#endif /* STM32F10X_HD */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+ #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+ #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+ #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#endif /* STM32F10X_HD */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
+ #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+ #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
+ #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
+ #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+ #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
+ #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
+ #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
+ #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
+ #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
+ #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
+ #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
+ #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
+ #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
+ #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
+ #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
+ #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
+ #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
+ #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
+ #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
+ #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
+ #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
+ #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
+ #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
+
+ #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
+ #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR1 register *******************/
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR2 register *******************/
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR3 register *******************/
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CCR4 register *******************/
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
+
+/****************** Bit definition for DMA_CCR5 register *******************/
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CCR6 register *******************/
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR7 register *******************/
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
+
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
+
+/****************** Bit definition for DMA_CNDTR1 register ******************/
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR2 register ******************/
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR3 register ******************/
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR4 register ******************/
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR5 register ******************/
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR6 register ******************/
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR7 register ******************/
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR1 register *******************/
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR2 register *******************/
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR3 register *******************/
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR4 register *******************/
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR5 register *******************/
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR6 register *******************/
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR7 register *******************/
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR1 register *******************/
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+/****************** Bit definition for DMA_CMAR2 register *******************/
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+/****************** Bit definition for DMA_CMAR3 register *******************/
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+
+/****************** Bit definition for DMA_CMAR4 register *******************/
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+/****************** Bit definition for DMA_CMAR5 register *******************/
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+/****************** Bit definition for DMA_CMAR6 register *******************/
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+/****************** Bit definition for DMA_CMAR7 register *******************/
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+
+#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */
+#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */
+#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */
+#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */
+#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!<Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/*!<Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
+
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
+
+/*!<Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
+
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
+#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */
+#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */
+
+#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */
+#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */
+#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */
+#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */
+#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */
+#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */
+#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */
+#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */
+#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */
+#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */
+#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */
+
+#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */
+#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
+#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
+#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */
+#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */
+#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
+
+#ifdef STM32F10X_CL
+/******************************************************************************/
+/* Ethernet MAC Registers bits definitions */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+ #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32f10x_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Property changes on: branches/eagle_mmc/src/platform/stm32/stm32f10x.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/stm32/stm32f10x_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stm32f10x_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stm32f10x_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,174 +1,76 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_conf.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : Library configuration file.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file Project/Template/stm32f10x_conf.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief Library configuration file.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CONF_H
#define __STM32F10x_CONF_H
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_type.h"
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+/* #include "stm32f10x_bkp.h" */
+#include "stm32f10x_can.h"
+/* #include "stm32f10x_crc.h" */
+/* #include "stm32f10x_dac.h" */
+/* #include "stm32f10x_dbgmcu.h" */
+#include "stm32f10x_dma.h"
+// #include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+/* #include "stm32f10x_i2c.h" */
+/* #include "stm32f10x_iwdg.h" */
+/* #include "stm32f10x_pwr.h" */
+#include "stm32f10x_rcc.h"
+/* #include "stm32f10x_rtc.h" */
+/* #include "stm32f10x_sdio.h" */
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+/* #include "stm32f10x_wwdg.h" */
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
- the "assert_param" macro in the firmware library code (see "Exported macro"
- section below) */
-/* #define DEBUG 1*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+ Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT 1 */
-/* Comment the line below to disable the specific peripheral inclusion */
-/************************************* ADC ************************************/
-#define _ADC
-#define _ADC1
-#define _ADC2
-#define _ADC3
-
-/************************************* BKP ************************************/
-#define _BKP
-
-/************************************* CAN ************************************/
-#define _CAN
-
-/************************************* CRC ************************************/
-#define _CRC
-
-/************************************* DAC ************************************/
-#define _DAC
-
-/************************************* DBGMCU *********************************/
-#define _DBGMCU
-
-/************************************* DMA ************************************/
-#define _DMA
-#define _DMA1_Channel1
-#define _DMA1_Channel2
-#define _DMA1_Channel3
-#define _DMA1_Channel4
-#define _DMA1_Channel5
-#define _DMA1_Channel6
-#define _DMA1_Channel7
-#define _DMA2_Channel1
-#define _DMA2_Channel2
-#define _DMA2_Channel3
-#define _DMA2_Channel4
-#define _DMA2_Channel5
-
-/************************************* EXTI ***********************************/
-#define _EXTI
-
-/************************************* FLASH and Option Bytes *****************/
-#define _FLASH
-/* Uncomment the line below to enable FLASH program/erase/protections functions,
- otherwise only FLASH configuration (latency, prefetch, half cycle) functions
- are enabled */
-/* #define _FLASH_PROG */
-
-/************************************* FSMC ***********************************/
-#define _FSMC
-
-/************************************* GPIO ***********************************/
-#define _GPIO
-#define _GPIOA
-#define _GPIOB
-#define _GPIOC
-#define _GPIOD
-#define _GPIOE
-#define _GPIOF
-#define _GPIOG
-#define _AFIO
-
-/************************************* I2C ************************************/
-#define _I2C
-#define _I2C1
-#define _I2C2
-
-/************************************* IWDG ***********************************/
-#define _IWDG
-
-/************************************* NVIC ***********************************/
-#define _NVIC
-
-/************************************* PWR ************************************/
-#define _PWR
-
-/************************************* RCC ************************************/
-#define _RCC
-
-/************************************* RTC ************************************/
-#define _RTC
-
-/************************************* SDIO ***********************************/
-#define _SDIO
-
-/************************************* SPI ************************************/
-#define _SPI
-#define _SPI1
-#define _SPI2
-#define _SPI3
-
-/************************************* SysTick ********************************/
-#define _SysTick
-
-/************************************* TIM ************************************/
-#define _TIM
-#define _TIM1
-#define _TIM2
-#define _TIM3
-#define _TIM4
-#define _TIM5
-#define _TIM6
-#define _TIM7
-#define _TIM8
-
-/************************************* USART **********************************/
-#define _USART
-#define _USART1
-#define _USART2
-#define _USART3
-#define _UART4
-#define _UART5
-
-/************************************* WWDG ***********************************/
-#define _WWDG
-
-/* In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application */
-#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
-
-/* In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value */
-#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */
-
/* Exported macro ------------------------------------------------------------*/
-#ifdef DEBUG
-/*******************************************************************************
-* Macro Name : assert_param
-* Description : The assert_param macro is used for function's parameters check.
-* It is used only if the library is compiled in DEBUG mode.
-* Input : - expr: If expr is false, it calls assert_failed function
-* which reports the name of the source file and the source
-* line number of the call that failed.
-* If expr is true, it returns no value.
-* Return : None
-*******************************************************************************/
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(u8* file, u32 line);
+ void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
-#endif /* DEBUG */
+#endif /* USE_FULL_ASSERT */
#endif /* __STM32F10x_CONF_H */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/stm32f10x_it.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stm32f10x_it.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stm32f10x_it.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,24 +1,31 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_it.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : Main Interrupt Service Routines.
-* This file provides template for all exceptions handler
-* and peripherals interrupt service routine.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file Project/Template/stm32f10x_it.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief Main Interrupt Service Routines.
+ * This file provides template for all exceptions handler and
+ * peripherals interrupt service routine.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_it.h"
-#include "platform.h"
#include "systick.h"
+/** @addtogroup Template_Project
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -27,804 +34,145 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/*******************************************************************************
-* Function Name : NMIException
-* Description : This function handles NMI exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void NMIException(void)
-{
-}
+/******************************************************************************/
+/* Cortex-M3 Processor Exceptions Handlers */
+/******************************************************************************/
-/*******************************************************************************
-* Function Name : HardFaultException
-* Description : This function handles Hard Fault exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void HardFaultException(void)
+/**
+ * @brief This function handles NMI exception.
+ * @param None
+ * @retval None
+ */
+void NMI_Handler(void)
{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- platform_uart_send(0, ' ');
- platform_uart_send(0, 'H');
- platform_uart_send(0, 'F');
- platform_uart_send(0, '!');
- }
}
-/*******************************************************************************
-* Function Name : MemManageException
-* Description : This function handles Memory Manage exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void MemManageException(void)
+/**
+ * @brief This function handles Hard Fault exception.
+ * @param None
+ * @retval None
+ */
+void HardFault_Handler(void)
{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- platform_uart_send(0, ' ');
- platform_uart_send(0, 'M');
- platform_uart_send(0, 'M');
- platform_uart_send(0, '!');
- }
-}
-
-/*******************************************************************************
-* Function Name : BusFaultException
-* Description : This function handles Bus Fault exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void BusFaultException(void)
+/* Go to infinite loop when Hard Fault exception occurs */
+while (1)
{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- platform_uart_send(0, ' ');
- platform_uart_send(0, 'B');
- platform_uart_send(0, 'F');
- platform_uart_send(0, '!');
- }
+ platform_uart_send(0, ' ');
+ platform_uart_send(0, 'H');
+ platform_uart_send(0, 'F');
+ platform_uart_send(0, '!');
}
-
-/*******************************************************************************
-* Function Name : UsageFaultException
-* Description : This function handles Usage Fault exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void UsageFaultException(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- platform_uart_send(0, ' ');
- platform_uart_send(0, 'U');
- platform_uart_send(0, 'F');
- platform_uart_send(0, '!');
- }
}
-/*******************************************************************************
-* Function Name : DebugMonitor
-* Description : This function handles Debug Monitor exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DebugMonitor(void)
+/**
+ * @brief This function handles Memory Manage exception.
+ * @param None
+ * @retval None
+ */
+void MemManage_Handler(void)
{
-}
-
-/*******************************************************************************
-* Function Name : SVCHandler
-* Description : This function handles SVCall exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SVCHandler(void)
+/* Go to infinite loop when Memory Manage exception occurs */
+while (1)
{
+ platform_uart_send(0, ' ');
+ platform_uart_send(0, 'M');
+ platform_uart_send(0, 'M');
+ platform_uart_send(0, '!');
}
-
-/*******************************************************************************
-* Function Name : PendSVC
-* Description : This function handles PendSVC exception.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void PendSVC(void)
-{
}
-/*******************************************************************************
-* Function Name : SysTickHandler
-* Description : This function handles SysTick Handler.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SysTickHandler(void)
+/**
+ * @brief This function handles Bus Fault exception.
+ * @param None
+ * @retval None
+ */
+void BusFault_Handler(void)
{
- /* Decrement the TimingDelay variable */
- Decrement_TimingDelay();
-}
-
-/*******************************************************************************
-* Function Name : WWDG_IRQHandler
-* Description : This function handles WWDG interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void WWDG_IRQHandler(void)
+/* Go to infinite loop when Bus Fault exception occurs */
+while (1)
{
+ platform_uart_send(0, ' ');
+ platform_uart_send(0, 'B');
+ platform_uart_send(0, 'F');
+ platform_uart_send(0, '!');
}
-
-/*******************************************************************************
-* Function Name : PVD_IRQHandler
-* Description : This function handles PVD interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void PVD_IRQHandler(void)
-{
}
-/*******************************************************************************
-* Function Name : TAMPER_IRQHandler
-* Description : This function handles Tamper interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TAMPER_IRQHandler(void)
+/**
+ * @brief This function handles Usage Fault exception.
+ * @param None
+ * @retval None
+ */
+void UsageFault_Handler(void)
{
-}
-
-/*******************************************************************************
-* Function Name : RTC_IRQHandler
-* Description : This function handles RTC global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTC_IRQHandler(void)
+/* Go to infinite loop when Usage Fault exception occurs */
+while (1)
{
+ platform_uart_send(0, ' ');
+ platform_uart_send(0, 'U');
+ platform_uart_send(0, 'F');
+ platform_uart_send(0, '!');
}
-
-/*******************************************************************************
-* Function Name : FLASH_IRQHandler
-* Description : This function handles Flash interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void FLASH_IRQHandler(void)
-{
}
-/*******************************************************************************
-* Function Name : RCC_IRQHandler
-* Description : This function handles RCC interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RCC_IRQHandler(void)
+/**
+ * @brief This function handles SVCall exception.
+ * @param None
+ * @retval None
+ */
+void SVC_Handler(void)
{
}
-/*******************************************************************************
-* Function Name : EXTI0_IRQHandler
-* Description : This function handles External interrupt Line 0 request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI0_IRQHandler(void)
+/**
+ * @brief This function handles Debug Monitor exception.
+ * @param None
+ * @retval None
+ */
+void DebugMon_Handler(void)
{
}
-/*******************************************************************************
-* Function Name : EXTI1_IRQHandler
-* Description : This function handles External interrupt Line 1 request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI1_IRQHandler(void)
+/**
+ * @brief This function handles PendSVC exception.
+ * @param None
+ * @retval None
+ */
+void PendSV_Handler(void)
{
}
-/*******************************************************************************
-* Function Name : EXTI2_IRQHandler
-* Description : This function handles External interrupt Line 2 request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI2_IRQHandler(void)
+/**
+ * @brief This function handles SysTick Handler.
+ * @param None
+ * @retval None
+ */
+void SysTick_Handler(void)
{
+ /* Decrement the TimingDelay variable */
+ Decrement_TimingDelay();
}
-/*******************************************************************************
-* Function Name : EXTI3_IRQHandler
-* Description : This function handles External interrupt Line 3 request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI3_IRQHandler(void)
-{
-}
+/******************************************************************************/
+/* STM32F10x Peripherals Interrupt Handlers */
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
+/* available peripheral interrupt handler's name please refer to the startup */
+/* file (startup_stm32f10x_xx.s). */
+/******************************************************************************/
-/*******************************************************************************
-* Function Name : EXTI4_IRQHandler
-* Description : This function handles External interrupt Line 4 request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI4_IRQHandler(void)
+/**
+ * @brief This function handles PPP interrupt request.
+ * @param None
+ * @retval None
+ */
+/*void PPP_IRQHandler(void)
{
-}
+}*/
-/*******************************************************************************
-* Function Name : DMA1_Channel1_IRQHandler
-* Description : This function handles DMA1 Channel 1 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel1_IRQHandler(void)
-{
-}
+/**
+ * @}
+ */
+extern void DMA1_Channel1_IRQHandler(void);
+extern void USART1_IRQHandler(void);
-/*******************************************************************************
-* Function Name : DMA1_Channel2_IRQHandler
-* Description : This function handles DMA1 Channel 2 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel2_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA1_Channel3_IRQHandler
-* Description : This function handles DMA1 Channel 3 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel3_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA1_Channel4_IRQHandler
-* Description : This function handles DMA1 Channel 4 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel4_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA1_Channel5_IRQHandler
-* Description : This function handles DMA1 Channel 5 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel5_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA1_Channel6_IRQHandler
-* Description : This function handles DMA1 Channel 6 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel6_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA1_Channel7_IRQHandler
-* Description : This function handles DMA1 Channel 7 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA1_Channel7_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : ADC1_2_IRQHandler
-* Description : This function handles ADC1 and ADC2 global interrupts requests.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC1_2_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : USB_HP_CAN_TX_IRQHandler
-* Description : This function handles USB High Priority or CAN TX interrupts
-* requests.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void USB_HP_CAN_TX_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : USB_LP_CAN_RX0_IRQHandler
-* Description : This function handles USB Low Priority or CAN RX0 interrupts
-* requests.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void USB_LP_CAN_RX0_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : CAN_RX1_IRQHandler
-* Description : This function handles CAN RX1 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void CAN_RX1_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : CAN_SCE_IRQHandler
-* Description : This function handles CAN SCE interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void CAN_SCE_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : EXTI9_5_IRQHandler
-* Description : This function handles External lines 9 to 5 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI9_5_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM1_BRK_IRQHandler
-* Description : This function handles TIM1 Break interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM1_BRK_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM1_UP_IRQHandler
-* Description : This function handles TIM1 overflow and update interrupt
-* request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM1_UP_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM1_TRG_COM_IRQHandler
-* Description : This function handles TIM1 Trigger and commutation interrupts
-* requests.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM1_TRG_COM_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM1_CC_IRQHandler
-* Description : This function handles TIM1 capture compare interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM1_CC_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM2_IRQHandler
-* Description : This function handles TIM2 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM2_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM3_IRQHandler
-* Description : This function handles TIM3 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM3_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM4_IRQHandler
-* Description : This function handles TIM4 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM4_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : I2C1_EV_IRQHandler
-* Description : This function handles I2C1 Event interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C1_EV_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : I2C1_ER_IRQHandler
-* Description : This function handles I2C1 Error interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C1_ER_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : I2C2_EV_IRQHandler
-* Description : This function handles I2C2 Event interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C2_EV_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : I2C2_ER_IRQHandler
-* Description : This function handles I2C2 Error interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void I2C2_ER_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : SPI1_IRQHandler
-* Description : This function handles SPI1 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI1_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : SPI2_IRQHandler
-* Description : This function handles SPI2 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI2_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : USART1_IRQHandler
-* Description : This function handles USART1 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART1_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : USART2_IRQHandler
-* Description : This function handles USART2 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART2_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : USART3_IRQHandler
-* Description : This function handles USART3 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void USART3_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : EXTI15_10_IRQHandler
-* Description : This function handles External lines 15 to 10 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void EXTI15_10_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : RTCAlarm_IRQHandler
-* Description : This function handles RTC Alarm interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void RTCAlarm_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : USBWakeUp_IRQHandler
-* Description : This function handles USB WakeUp interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void USBWakeUp_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM8_BRK_IRQHandler
-* Description : This function handles TIM8 Break interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM8_BRK_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM8_UP_IRQHandler
-* Description : This function handles TIM8 overflow and update interrupt
-* request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM8_UP_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM8_TRG_COM_IRQHandler
-* Description : This function handles TIM8 Trigger and commutation interrupts
-* requests.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM8_TRG_COM_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM8_CC_IRQHandler
-* Description : This function handles TIM8 capture compare interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM8_CC_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : ADC3_IRQHandler
-* Description : This function handles ADC3 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void ADC3_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : FSMC_IRQHandler
-* Description : This function handles FSMC global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void FSMC_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : SDIO_IRQHandler
-* Description : This function handles SDIO global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SDIO_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM5_IRQHandler
-* Description : This function handles TIM5 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM5_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : SPI3_IRQHandler
-* Description : This function handles SPI3 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SPI3_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : UART4_IRQHandler
-* Description : This function handles UART4 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void UART4_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : UART5_IRQHandler
-* Description : This function handles UART5 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void UART5_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM6_IRQHandler
-* Description : This function handles TIM6 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM6_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : TIM7_IRQHandler
-* Description : This function handles TIM7 global interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void TIM7_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA2_Channel1_IRQHandler
-* Description : This function handles DMA2 Channel 1 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA2_Channel1_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA2_Channel2_IRQHandler
-* Description : This function handles DMA2 Channel 2 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA2_Channel2_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA2_Channel3_IRQHandler
-* Description : This function handles DMA2 Channel 3 interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA2_Channel3_IRQHandler(void)
-{
-}
-
-/*******************************************************************************
-* Function Name : DMA2_Channel4_5_IRQHandler
-* Description : This function handles DMA2 Channel 4 and DMA2 Channel 5
-* interrupt request.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void DMA2_Channel4_5_IRQHandler(void)
-{
-}
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Modified: branches/eagle_mmc/src/platform/stm32/stm32f10x_it.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stm32f10x_it.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stm32f10x_it.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,100 +1,47 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_it.h
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : This file contains the headers of the interrupt handlers.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
+/**
+ ******************************************************************************
+ * @file ADC/3ADCs_DMA/stm32f10x_it.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IT_H
#define __STM32F10x_IT_H
/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_lib.h"
+#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
-void NMIException(void);
-void HardFaultException(void);
-void MemManageException(void);
-void BusFaultException(void);
-void UsageFaultException(void);
-void DebugMonitor(void);
-void SVCHandler(void);
-void PendSVC(void);
-void SysTickHandler(void);
-void WWDG_IRQHandler(void);
-void PVD_IRQHandler(void);
-void TAMPER_IRQHandler(void);
-void RTC_IRQHandler(void);
-void FLASH_IRQHandler(void);
-void RCC_IRQHandler(void);
-void EXTI0_IRQHandler(void);
-void EXTI1_IRQHandler(void);
-void EXTI2_IRQHandler(void);
-void EXTI3_IRQHandler(void);
-void EXTI4_IRQHandler(void);
-void DMA1_Channel1_IRQHandler(void);
-void DMA1_Channel2_IRQHandler(void);
-void DMA1_Channel3_IRQHandler(void);
-void DMA1_Channel4_IRQHandler(void);
-void DMA1_Channel5_IRQHandler(void);
-void DMA1_Channel6_IRQHandler(void);
-void DMA1_Channel7_IRQHandler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
void ADC1_2_IRQHandler(void);
-void USB_HP_CAN_TX_IRQHandler(void);
-void USB_LP_CAN_RX0_IRQHandler(void);
-void CAN_RX1_IRQHandler(void);
-void CAN_SCE_IRQHandler(void);
-void EXTI9_5_IRQHandler(void);
-void TIM1_BRK_IRQHandler(void);
-void TIM1_UP_IRQHandler(void);
-void TIM1_TRG_COM_IRQHandler(void);
-void TIM1_CC_IRQHandler(void);
-void TIM2_IRQHandler(void);
-void TIM3_IRQHandler(void);
-void TIM4_IRQHandler(void);
-void I2C1_EV_IRQHandler(void);
-void I2C1_ER_IRQHandler(void);
-void I2C2_EV_IRQHandler(void);
-void I2C2_ER_IRQHandler(void);
-void SPI1_IRQHandler(void);
-void SPI2_IRQHandler(void);
-void USART1_IRQHandler(void);
-void USART2_IRQHandler(void);
-void USART3_IRQHandler(void);
-void EXTI15_10_IRQHandler(void);
-void RTCAlarm_IRQHandler(void);
-void USBWakeUp_IRQHandler(void);
-void TIM8_BRK_IRQHandler(void);
-void TIM8_UP_IRQHandler(void);
-void TIM8_TRG_COM_IRQHandler(void);
-void TIM8_CC_IRQHandler(void);
-void ADC3_IRQHandler(void);
-void FSMC_IRQHandler(void);
-void SDIO_IRQHandler(void);
-void TIM5_IRQHandler(void);
-void SPI3_IRQHandler(void);
-void UART4_IRQHandler(void);
-void UART5_IRQHandler(void);
-void TIM6_IRQHandler(void);
-void TIM7_IRQHandler(void);
-void DMA2_Channel1_IRQHandler(void);
-void DMA2_Channel2_IRQHandler(void);
-void DMA2_Channel3_IRQHandler(void);
-void DMA2_Channel4_5_IRQHandler(void);
-
+void DMA1_Channel1_IRQHandler(void);
+void USART1_IRQHandler(void);
#endif /* __STM32F10x_IT_H */
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Deleted: branches/eagle_mmc/src/platform/stm32/stm32f10x_vector.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/stm32f10x_vector.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/stm32f10x_vector.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,215 +0,0 @@
-/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
-* File Name : stm32f10x_vector.c
-* Author : MCD Application Team
-* Version : V2.0.3
-* Date : 09/22/2008
-* Description : STM32F10x vector table for RIDE7 toolchain.
-* This module performs:
-* - Set the initial SP
-* - Set the initial PC == Reset_Handler,
-* - Set the vector table entries with the exceptions ISR address,
-* - Configure external SRAM mounted on STM3210E-EVAL board
-* to be used as data memory (optional, to be enabled by user)
-* - Branches to main in the C library (which eventually
-* calls main()).
-* After Reset the Cortex-M3 processor is in Thread mode,
-* priority is Privileged, and the Stack is set to Main.
-********************************************************************************
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_lib.h"
-#include "stm32f10x_it.h"
-
-/* Private typedef -----------------------------------------------------------*/
-typedef void( *intfunc )( void );
-typedef union { intfunc __fun; void * __ptr; } intvec_elem;
-
-/* Private define ------------------------------------------------------------*/
-/* Uncomment the following line if you need to use external SRAM mounted on
- STM3210E-EVAL board as data memory */
-
-/* #define DATA_IN_ExtSRAM */
-
-/* Private macro -------------------------------------------------------------*/
-extern unsigned long _etext;
-/* start address for the initialization values of the .data section.
-defined in linker script */
-extern unsigned long _sidata;
-
-/* start address for the .data section. defined in linker script */
-extern unsigned long _sdata;
-
-/* end address for the .data section. defined in linker script */
-extern unsigned long _edata;
-
-/* start address for the .bss section. defined in linker script */
-extern unsigned long _sbss;
-
-/* end address for the .bss section. defined in linker script */
-extern unsigned long _ebss;
-
-/* init value for the stack pointer. defined in linker script */
-extern void _estack;
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-void Reset_Handler(void) __attribute__((__interrupt__));
-extern int main(void);
-/* Private functions ---------------------------------------------------------*/
-
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) =
-{
- &_estack, /* The initial stack pointer*/
- Reset_Handler, /* The reset handler*/
- NMIException,
- HardFaultException,
- MemManageException,
- BusFaultException,
- UsageFaultException,
- 0, 0, 0, 0, /* Reserved */
- SVCHandler,
- DebugMonitor,
- 0, /* Reserved */
- PendSVC,
- SysTickHandler,
- WWDG_IRQHandler,
- PVD_IRQHandler,
- TAMPER_IRQHandler,
- RTC_IRQHandler,
- FLASH_IRQHandler,
- RCC_IRQHandler,
- EXTI0_IRQHandler,
- EXTI1_IRQHandler,
- EXTI2_IRQHandler,
- EXTI3_IRQHandler,
- EXTI4_IRQHandler,
- DMA1_Channel1_IRQHandler,
- DMA1_Channel2_IRQHandler,
- DMA1_Channel3_IRQHandler,
- DMA1_Channel4_IRQHandler,
- DMA1_Channel5_IRQHandler,
- DMA1_Channel6_IRQHandler,
- DMA1_Channel7_IRQHandler,
- ADC1_2_IRQHandler,
- USB_HP_CAN_TX_IRQHandler,
- USB_LP_CAN_RX0_IRQHandler,
- CAN_RX1_IRQHandler,
- CAN_SCE_IRQHandler,
- EXTI9_5_IRQHandler,
- TIM1_BRK_IRQHandler,
- TIM1_UP_IRQHandler,
- TIM1_TRG_COM_IRQHandler,
- TIM1_CC_IRQHandler,
- TIM2_IRQHandler,
- TIM3_IRQHandler,
- TIM4_IRQHandler,
- I2C1_EV_IRQHandler,
- I2C1_ER_IRQHandler,
- I2C2_EV_IRQHandler,
- I2C2_ER_IRQHandler,
- SPI1_IRQHandler,
- SPI2_IRQHandler,
- USART1_IRQHandler,
- USART2_IRQHandler,
- USART3_IRQHandler,
- EXTI15_10_IRQHandler,
- RTCAlarm_IRQHandler,
- USBWakeUp_IRQHandler,
- TIM8_BRK_IRQHandler,
- TIM8_UP_IRQHandler,
- TIM8_TRG_COM_IRQHandler,
- TIM8_CC_IRQHandler,
- ADC3_IRQHandler,
- FSMC_IRQHandler,
- SDIO_IRQHandler,
- TIM5_IRQHandler,
- SPI3_IRQHandler,
- UART4_IRQHandler,
- UART5_IRQHandler,
- TIM6_IRQHandler,
- TIM7_IRQHandler,
- DMA2_Channel1_IRQHandler,
- DMA2_Channel2_IRQHandler,
- DMA2_Channel3_IRQHandler,
- DMA2_Channel4_5_IRQHandler,
-};
-
-/*******************************************************************************
-* Function Name : Reset_Handler
-* Description : This is the code that gets called when the processor first
-* starts execution following a reset event. Only the absolutely
-* necessary set is performed, after which the application
-* supplied main() routine is called.
-* Input :
-* Output :
-* Return :
-*******************************************************************************/
-void Reset_Handler(void)
-{
-unsigned long *pulSrc, *pulDest;
-
-#ifdef DATA_IN_ExtSRAM
-
-/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses*/
-
- /* Enable FSMC clock */
- *(vu32 *)0x40021014 = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- *(vu32 *)0x40021018 = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- *(vu32 *)0x40011400 = 0x44BB44BB;
- *(vu32 *)0x40011404 = 0xBBBBBBBB;
-
- *(vu32 *)0x40011800 = 0xB44444BB;
- *(vu32 *)0x40011804 = 0xBBBBBBBB;
-
- *(vu32 *)0x40011C00 = 0x44BBBBBB;
- *(vu32 *)0x40011C04 = 0xBBBB4444;
-
- *(vu32 *)0x40012000 = 0x44BBBBBB;
- *(vu32 *)0x40012004 = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- *(vu32 *)0xA0000010 = 0x00001011;
- *(vu32 *)0xA0000014 = 0x00000200;
-
-#endif /*DATA_IN_ExtSRAM*/
-
-
-/* Copy the data segment initializers from flash to SRAM */
- pulSrc = &_sidata;
- for(pulDest = &_sdata; pulDest < &_edata; )
- {
- *(pulDest++) = *(pulSrc++);
- }
-/* Zero fill the bss segment. */
- for(pulDest = &_sbss; pulDest < &_ebss; )
- {
- *(pulDest++) = 0;
- }
-
-/* Call the application's entry point.*/
- main();
-}
-
-
-/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
-
-
Added: branches/eagle_mmc/src/platform/stm32/system_stm32f10x.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/system_stm32f10x.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/system_stm32f10x.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,930 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.c
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+/* #define SYSCLK_FREQ_HSE HSE_Value */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density devices) as data memory */
+#ifdef STM32F10X_HD
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F10X_HD */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_24MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_36MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_48MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_56MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_72MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */
+#else /*!< HSI Selected as System Clock source */
+ const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifndef STM32F10X_CL
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#else
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#endif /* STM32F10X_CL */
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_Value <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Property changes on: branches/eagle_mmc/src/platform/stm32/system_stm32f10x.c
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/eagle_mmc/src/platform/stm32/system_stm32f10x.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/system_stm32f10x.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/system_stm32f10x.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,100 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.1.0
+ * @date 06/19/2009
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
+extern const uint32_t SystemFrequency_SysClk; /*!< System clock */
+extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */
+extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */
+extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
Property changes on: branches/eagle_mmc/src/platform/stm32/system_stm32f10x.h
___________________________________________________________________
Name: svn:executable
+ *
Modified: branches/eagle_mmc/src/platform/stm32/systick.c
===================================================================
--- branches/eagle_mmc/src/platform/stm32/systick.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/systick.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,66 +1,20 @@
-#include <stdio.h>
-
-#include "stm32f10x_lib.h"
-#include "stm32f10x_systick.h"
-
-static vu32 TimingDelay = 0;
-
-/*******************************************************************************
-* Function Name : SysTick_Config
-* Description : Configure a SysTick Base time to 10 ms.
-* Input : None
-* Output : None
-* Return : None
-*******************************************************************************/
-void SysTick_Config(void)
-{
- /* Configure HCLK clock as SysTick clock source */
- SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
-
- /* SysTick interrupt each 100 Hz with HCLK equal to 72MHz */
- SysTick_SetReload(720000);
-
- /* Enable the SysTick Interrupt */
- SysTick_ITConfig(ENABLE);
-}
-
-/*******************************************************************************
-* Function Name : Delay
-* Description : Inserts a delay time.
-* Input : nCount: specifies the delay time length (time base 10 ms).
-* Output : None
-* Return : None
-*******************************************************************************/
-void Delay(u32 nCount)
-{
- printf("Delay(%d)\n", nCount);
- TimingDelay = nCount;
-
- /* Enable the SysTick Counter */
- SysTick_CounterCmd(SysTick_Counter_Enable);
-
- while(TimingDelay != 0)
- {
- }
-
- /* Disable the SysTick Counter */
- SysTick_CounterCmd(SysTick_Counter_Disable);
-
- /* Clear the SysTick Counter */
- SysTick_CounterCmd(SysTick_Counter_Clear);
-}
-
-/*******************************************************************************
-* Function Name : Decrement_TimingDelay
-* Description : Decrements the TimingDelay variable.
-* Input : None
-* Output : TimingDelay
-* Return : None
-*******************************************************************************/
-void Decrement_TimingDelay(void)
-{
- if (TimingDelay != 0x00)
- {
- TimingDelay--;
- }
-}
+#include <stdio.h>
+
+#include "stm32f10x.h"
+
+static vu32 TimingDelay = 0;
+
+/*******************************************************************************
+* Function Name : Decrement_TimingDelay
+* Description : Decrements the TimingDelay variable.
+* Input : None
+* Output : TimingDelay
+* Return : None
+*******************************************************************************/
+void Decrement_TimingDelay(void)
+{
+ if (TimingDelay != 0x00)
+ {
+ TimingDelay--;
+ }
+}
Modified: branches/eagle_mmc/src/platform/stm32/systick.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/systick.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/systick.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,8 +1,7 @@
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
-void SysTick_Config(void);
-void Delay(u32 nCount);
+/* void Delay(u32 nCount);*/
void Decrement_TimingDelay(void);
#endif
\ No newline at end of file
Modified: branches/eagle_mmc/src/platform/stm32/type.h
===================================================================
--- branches/eagle_mmc/src/platform/stm32/type.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/stm32/type.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -1,7 +1,7 @@
#ifndef __TYPE_H__
#define __TYPE_H__
-#include "stm32f10x_type.h"
+#include "stm32f10x.h"
#ifndef NULL
#define NULL ((void *)0)
Modified: branches/eagle_mmc/src/platform/str7/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/str7/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/str7/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -24,15 +24,15 @@
# Toolset data
tools[ 'str7' ] = {}
-tools[ 'str7' ][ 'cccom' ] = "arm-elf-gcc -mcpu=arm7tdmi %s %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( modeflag, opt, local_include, cdefs )
-tools[ 'str7' ][ 'linkcom' ] = "arm-elf-gcc -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,entry -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( modeflag, ldscript, local_libs )
-tools[ 'str7' ][ 'ascom' ] = "arm-elf-gcc -x assembler-with-cpp %s -mcpu=arm7tdmi %s %s -Wall -c $SOURCE -o $TARGET" % ( local_include, modeflag, cdefs )
+tools[ 'str7' ][ 'cccom' ] = "%s -mcpu=arm7tdmi %s %s $_CPPINCFLAGS -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, opt, cdefs )
+tools[ 'str7' ][ 'linkcom' ] = "%s -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,entry -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], modeflag, ldscript, local_libs )
+tools[ 'str7' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=arm7tdmi %s %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, cdefs )
# Programming function for LPC2888
def progfunc_str7( target, source, env ):
outname = output + ".elf"
- os.system( "arm-elf-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( "arm-elf-objcopy -O binary %s %s.bin" % ( outname, output ) )
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
tools[ 'str7' ][ 'progfunc' ] = progfunc_str7
Modified: branches/eagle_mmc/src/platform/str7/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/str7/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/str7/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -20,11 +20,9 @@
#define CON_UART_ID 1
#define CON_UART_SPEED 38400
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
@@ -55,6 +53,7 @@
#define NUM_TIMER 4
#define NUM_PWM 3
#define NUM_ADC 0
+#define NUM_CAN 0
// CPU frequency (needed by the CPU module, 0 if not used)
#define CPU_FREQUENCY 0
Modified: branches/eagle_mmc/src/platform/str7/str711fr2.lds
===================================================================
--- branches/eagle_mmc/src/platform/str7/str711fr2.lds 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/str7/str711fr2.lds 2009-07-30 18:10:13 UTC (rev 371)
@@ -27,6 +27,8 @@
. = ALIGN(4);
_efixed = .;
PROVIDE(etext = .);
+ _fini = .;
+ *(.fini)
} >flash
.relocate : AT (_efixed)
@@ -40,6 +42,18 @@
_erelocate = .;
} >sram
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
.bss (NOLOAD) : {
_szero = .;
*(.bss .bss.*)
Modified: branches/eagle_mmc/src/platform/str9/conf.py
===================================================================
--- branches/eagle_mmc/src/platform/str9/conf.py 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/str9/conf.py 2009-07-30 18:10:13 UTC (rev 371)
@@ -26,15 +26,15 @@
# Toolset data
tools[ 'str9' ] = {}
-tools[ 'str9' ][ 'cccom' ] = "arm-elf-gcc -mcpu=arm966e-s -mfpu=fpa %s %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, modeflag, cdefs )
-tools[ 'str9' ][ 'linkcom' ] = "arm-elf-gcc -mcpu=arm966e-s -mfpu=fpa -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,_startup -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( modeflag, ldscript, local_libs )
-tools[ 'str9' ][ 'ascom' ] = "arm-elf-gcc -x assembler-with-cpp %s -mcpu=arm966e-s -mfpu=fpa %s %s -Wall -c $SOURCE -o $TARGET" % ( local_include, modeflag, cdefs )
+tools[ 'str9' ][ 'cccom' ] = "%s -mcpu=arm966e-s -mfpu=fpa %s $_CPPINCFLAGS %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile'], opt, modeflag, cdefs )
+tools[ 'str9' ][ 'linkcom' ] = "%s -mcpu=arm966e-s -mfpu=fpa -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,_startup -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( toolset[ 'compile' ], modeflag, ldscript, local_libs )
+tools[ 'str9' ][ 'ascom' ] = "%s -x assembler-with-cpp $_CPPINCFLAGS -mcpu=arm966e-s -mfpu=fpa %s %s -Wall -c $SOURCE -o $TARGET" % ( toolset[ 'compile' ], modeflag, cdefs )
# Programming function for LPC2888
def progfunc_str9( target, source, env ):
outname = output + ".elf"
- os.system( "arm-elf-size %s" % outname )
+ os.system( "%s %s" % ( toolset[ 'size' ], outname ) )
print "Generating binary image..."
- os.system( "arm-elf-objcopy -O binary %s %s.bin" % ( outname, output ) )
+ os.system( "%s -O binary %s %s.bin" % ( toolset[ 'bin' ], outname, output ) )
tools[ 'str9' ][ 'progfunc' ] = progfunc_str9
Modified: branches/eagle_mmc/src/platform/str9/platform_conf.h
===================================================================
--- branches/eagle_mmc/src/platform/str9/platform_conf.h 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/str9/platform_conf.h 2009-07-30 18:10:13 UTC (rev 371)
@@ -21,11 +21,9 @@
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
-#define XMODEM_TIMER_ID 0
-#define TERM_TIMER_ID 0
+#define CON_TIMER_ID 0
#define TERM_LINES 25
#define TERM_COLS 80
-#define TERM_TIMEOUT 100000
// *****************************************************************************
// Configuration data
@@ -41,6 +39,7 @@
#define NUM_TIMER 4
#define NUM_PWM 0
#define NUM_ADC 0
+#define NUM_CAN 0
// CPU frequency (needed by the CPU module, 0 if not used)
u32 SCU_GetMCLKFreqValue();
Modified: branches/eagle_mmc/src/platform/str9/str912fw44.lds
===================================================================
--- branches/eagle_mmc/src/platform/str9/str912fw44.lds 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/platform/str9/str912fw44.lds 2009-07-30 18:10:13 UTC (rev 371)
@@ -25,6 +25,8 @@
. = ALIGN(4);
_efixed = .;
PROVIDE(etext = .);
+ _fini = .;
+ *(.fini)
} >flash
.relocate : AT (_efixed)
@@ -37,6 +39,18 @@
_erelocate = .;
} >sram
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >sram
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } >sram
+ __exidx_end = .;
+
.bss (NOLOAD) : {
_szero = .;
*(.bss .bss.*)
Added: branches/eagle_mmc/src/salloc.c
===================================================================
--- branches/eagle_mmc/src/salloc.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/salloc.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,282 @@
+// A very simple, quite inneficient, yet very small memory allocator
+// It can do both fixed block and variable block allocation
+
+#ifdef USE_SIMPLE_ALLOCATOR
+
+#include <stddef.h>
+#include <string.h>
+#include "platform.h"
+#include "platform_conf.h"
+#include "type.h"
+
+// Macros for the dynamic size allocator
+// Dynamic structure: pointer to next, pointer to prev
+// First bit of pointer is 0 if block free, 1 if block taken
+// Pointer must be multiplied by DYN_MIN_SIZE to get actual address
+// There are two 'guards' (at the beginning and at the end)
+#define DYN_SIZE_MULT 8
+#define DYN_SIZE_MULT_SHIFT 3
+#define DYN_HEADER_SIZE 8
+#define DYN_MIN_SPLIT_SIZE 16
+
+static u8 s_initialized;
+
+// ****************************************************************************
+// Utility functions for the dynamic memory allocator
+
+// Get actual size
+static size_t s_act_size( size_t size )
+{
+ if( size & ( DYN_SIZE_MULT - 1 ) )
+ size = ( ( size >> DYN_SIZE_MULT_SHIFT ) + 1 ) << DYN_SIZE_MULT_SHIFT;
+ return size;
+}
+
+// Get next block
+static char* s_get_next_block( char* ptr )
+{
+ return ( char* )( ( *( u32* )ptr & 0x7FFFFFFF ) << DYN_SIZE_MULT_SHIFT );
+}
+
+// Set next block
+static void s_set_next_block( char* ptr, char* next )
+{
+ u32 *temp = ( u32* )ptr;
+
+ *temp = ( *temp & 0x80000000 ) | ( ( u32 )next >> DYN_SIZE_MULT_SHIFT );
+}
+
+// Get prev block
+static char* s_get_prev_block( char* ptr )
+{
+ return ( char* )( ( *( ( u32* )ptr + 1 ) & 0x7FFFFFFF ) << DYN_SIZE_MULT_SHIFT );
+}
+
+// Set prev block
+static void s_set_prev_block( char* ptr, char* prev )
+{
+ u32 *temp = ( u32* )ptr + 1;
+
+ *temp = ( *temp & 0x80000000 ) | ( ( u32 )prev >> DYN_SIZE_MULT_SHIFT );
+}
+
+// Get block size
+static size_t s_get_block_size( char* ptr )
+{
+ char* next = s_get_next_block( ptr );
+
+ return next != NULL ? ( size_t )( next - ptr ) : 0;
+}
+
+// Mark block as taken
+static void s_mark_block_taken( char* where )
+{
+ *( u32* )where |= 0x80000000;
+}
+
+// Mark block as free
+static void s_mark_block_free( char* where )
+{
+ *( u32* )where &= 0x7FFFFFFF;
+}
+
+// Is the block free?
+static int s_is_block_free( char* where )
+{
+ return ( *( u32* )where & 0x80000000 ) == 0;
+}
+
+// Create a new block with the given neighbours
+static void s_create_new_block( char* where, char* next, char* prev )
+{
+ u32* temp = ( u32* )where;
+
+ *temp ++ = ( u32 )next >> DYN_SIZE_MULT_SHIFT;
+ *temp = ( u32 )prev >> DYN_SIZE_MULT_SHIFT;
+}
+
+// Tries to compact free blocks
+static void s_compact_free( char* ptr )
+{
+ char *temp1, *temp2;
+
+ s_mark_block_free( ptr );
+ // Look for free blocks before and after, concatenate if possible
+ temp1 = temp2 = ptr;
+ while( s_is_block_free( temp1 ) )
+ temp1 = s_get_prev_block( temp1 );
+ temp1 = s_get_next_block( temp1 );
+ while( s_is_block_free( temp2 ) )
+ temp2 = s_get_next_block( temp2 );
+ if( temp1 != ptr || s_get_prev_block( temp2 ) != ptr )
+ {
+ s_set_next_block( temp1, temp2 );
+ s_set_prev_block( temp2, temp1 );
+ }
+}
+
+// Utility function: find a free block in the dynamic memory part
+// Returns pointer to block for success, NULL for error
+static void* s_get_free_block( size_t size, void* pstart )
+{
+ char *temp, *pblock = NULL, *next;
+ size_t minsize = ( size_t )~0, bsize;
+
+ if( !size )
+ return NULL;
+ size = s_act_size( size + DYN_HEADER_SIZE );
+ temp = s_get_next_block( pstart );
+ // Best-fit only for now
+ while( temp )
+ {
+ if( s_is_block_free( temp ) )
+ {
+ bsize = s_get_block_size( temp );
+ if( ( size <= bsize ) && ( bsize < minsize ) )
+ {
+ minsize = bsize;
+ pblock = temp;
+ }
+ }
+ temp = s_get_next_block( temp );
+ }
+ if( pblock == NULL )
+ return NULL;
+ s_mark_block_taken( pblock );
+ if( minsize > size && ( minsize - size ) >= DYN_MIN_SPLIT_SIZE )
+ {
+ temp = pblock + size;
+ next = s_get_next_block( pblock );
+ s_set_prev_block( temp, pblock );
+ s_set_next_block( temp, next );
+ s_set_prev_block( next, temp );
+ s_set_next_block( pblock, temp );
+ s_compact_free( temp );
+ }
+ return pblock + DYN_HEADER_SIZE;
+}
+
+// Utility function: free a memory block
+static void s_free_block( char* ptr )
+{
+ ptr -= DYN_HEADER_SIZE;
+ s_compact_free( ptr );
+}
+
+// Get 'real' block size
+static size_t s_get_actual_block_size( char* ptr )
+{
+ return s_get_block_size( ptr - DYN_HEADER_SIZE ) - DYN_HEADER_SIZE;
+}
+
+// Shrinks the given block to its new size
+static void s_shrink_block( char* pblock, size_t size )
+{
+ char *temp, *next;
+
+ pblock -= DYN_HEADER_SIZE;
+ size = s_act_size( size + DYN_HEADER_SIZE );
+ if( size >= s_get_block_size( pblock ) || ( s_get_block_size( pblock ) - size ) < DYN_MIN_SPLIT_SIZE )
+ return;
+ temp = pblock + size;
+ next = s_get_next_block( pblock );
+ s_set_prev_block( temp, pblock );
+ s_set_next_block( temp, next );
+ s_set_prev_block( next, temp );
+ s_set_next_block( pblock, temp );
+ s_compact_free( temp );
+}
+
+static void s_init()
+{
+ unsigned i = 0;
+ size_t memspace;
+ char *crt, *g1, *g2, *pstart;
+
+ while( ( pstart = platform_get_first_free_ram( i ) ) != NULL )
+ {
+ memset( pstart, 0, memspace = ( u32 )platform_get_last_free_ram( i ) - ( u32 )pstart );
+ g1 = ( char* )pstart;
+ crt = g1 + DYN_SIZE_MULT;
+ g2 = g1 + memspace - DYN_SIZE_MULT;
+ s_create_new_block( g1, crt, NULL );
+ s_create_new_block( crt, g2, g1 );
+ s_create_new_block( g2, NULL, crt );
+ s_mark_block_taken( g1 );
+ s_mark_block_taken( g2 );
+ s_mark_block_free( crt );
+ i ++;
+ }
+ s_initialized = 1;
+}
+
+// ****************************************************************************
+
+void* smalloc( size_t size )
+{
+ unsigned i = 0;
+ void *ptr = NULL, *pstart;
+
+ if( !s_initialized )
+ s_init();
+ while( ( pstart = platform_get_first_free_ram( i ++ ) ) != NULL )
+ if( ( ptr = s_get_free_block( size, pstart ) ) != NULL )
+ break;
+ return ptr;
+}
+
+void sfree( void* ptr )
+{
+ if( !ptr || !s_initialized )
+ return;
+ s_free_block( ptr );
+}
+
+void* scalloc( size_t nmemb, size_t size )
+{
+ void* ptr;
+
+ if( !s_initialized )
+ s_init();
+ if( ( ptr = smalloc( nmemb * size ) ) != NULL )
+ memset( ptr, 0, nmemb * size );
+ return ptr;
+}
+
+void* srealloc( void* ptr, size_t size )
+{
+ void* newptr = NULL;
+
+ if( !s_initialized )
+ s_init();
+ // Special cases:
+ // realloc with ptr == NULL -> malloc
+ // realloc with size == 0 -> free
+ if( ptr == NULL )
+ return smalloc( size );
+ else if( size == 0 )
+ {
+ sfree( ptr );
+ return NULL;
+ }
+
+ // Test new size versus the old size
+ if( s_get_actual_block_size( ptr ) == size )
+ return ptr;
+ else if( size < s_get_actual_block_size( ptr ) )
+ {
+ s_shrink_block( ptr, size );
+ return ptr;
+ }
+ else
+ {
+ if( ( newptr = smalloc( size ) ) == NULL )
+ return NULL;
+ memmove( newptr, ptr, s_get_actual_block_size( ptr ) );
+ sfree( ptr );
+ }
+ return newptr;
+}
+
+#endif // #ifdef USE_SIMPLE_ALLOCATOR
+
Modified: branches/eagle_mmc/src/shell.c
===================================================================
--- branches/eagle_mmc/src/shell.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/shell.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -145,8 +145,9 @@
while( *p == '\x1A' )
p --;
p ++;
- printf( "done, got %ld bytes\n", p - shell_prog );
-
+
+ printf( "done, got %u bytes\n", ( unsigned )( p - shell_prog ) );
+
// Execute
if( ( L = lua_open() ) == NULL )
{
Modified: branches/eagle_mmc/src/term.c
===================================================================
--- branches/eagle_mmc/src/term.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/term.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -141,7 +141,7 @@
if( ( ch = term_in( mode ) ) == -1 )
return -1;
else
- return term_translate( ( u8 )ch );
+ return term_translate( ch );
}
void term_init( unsigned lines, unsigned cols, p_term_out term_out_func,
Modified: branches/eagle_mmc/src/xmodem.c
===================================================================
--- branches/eagle_mmc/src/xmodem.c 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/src/xmodem.c 2009-07-30 18:10:13 UTC (rev 371)
@@ -38,23 +38,23 @@
#include "platform_conf.h"
#ifdef BUILD_XMODEM
-#define PACKET_SIZE 128
+#define PXM_ACKET_SIZE 128
static p_xm_send_func xmodem_out_func;
static p_xm_recv_func xmodem_in_func;
// Line control codes
-#define SOH 0x01
-#define ACK 0x06
-#define NAK 0x15
-#define CAN 0x18
-#define EOT 0x04
+#define XM_SOH 0x01
+#define XM_ACK 0x06
+#define XM_NAK 0x15
+#define XM_CAN 0x18
+#define XM_EOT 0x04
// Arguments to xmodem_flush
#define XMODEM_FLUSH_ONLY 0
-#define XMODEM_FLUSH_AND_CAN 1
+#define XMODEM_FLUSH_AND_XM_CAN 1
// Delay in "flush packet" mode
-#define XMODEM_PACKET_DELAY 10000UL
+#define XMODEM_PXM_ACKET_DELAY 10000UL
void xmodem_init( p_xm_send_func send_func, p_xm_recv_func recv_func )
{
@@ -65,12 +65,12 @@
// Utility function: flush the receive buffer
static void xmodem_flush( int how )
{
- while( xmodem_in_func( XMODEM_PACKET_DELAY ) != -1 );
- if( how == XMODEM_FLUSH_AND_CAN )
+ while( xmodem_in_func( XMODEM_PXM_ACKET_DELAY ) != -1 );
+ if( how == XMODEM_FLUSH_AND_XM_CAN )
{
- xmodem_out_func( CAN );
- xmodem_out_func( CAN );
- xmodem_out_func( CAN );
+ xmodem_out_func( XM_CAN );
+ xmodem_out_func( XM_CAN );
+ xmodem_out_func( XM_CAN );
}
}
@@ -82,7 +82,7 @@
int ch;
// Read packet
- for( j = 0; j < PACKET_SIZE + 4; j ++ )
+ for( j = 0; j < PXM_ACKET_SIZE + 4; j ++ )
{
if( ( ch = xmodem_in_func( XMODEM_TIMEOUT ) ) == -1 )
goto err;
@@ -95,7 +95,7 @@
if( *pbuf ++ != ( unsigned char )~blocknum )
goto err;
// Check CRC
- for( size = chk = 0; size < PACKET_SIZE; size++, pbuf ++ )
+ for( size = chk = 0; size < PXM_ACKET_SIZE; size++, pbuf ++ )
{
chk = chk ^ *pbuf << 8;
for( j = 0; j < 8; j ++ )
@@ -114,7 +114,7 @@
return 1;
err:
- xmodem_out_func( NAK );
+ xmodem_out_func( XM_NAK );
return 0;
}
@@ -124,7 +124,7 @@
long xmodem_receive( char **dest )
{
int starting = 1, ch;
- unsigned char packnum = 1, buf[ PACKET_SIZE + 4 ];
+ unsigned char packnum = 1, buf[ PXM_ACKET_SIZE + 4 ];
unsigned retries = XMODEM_RETRY_LIMIT;
u32 limit = XMODEM_INITIAL_BUFFER_SIZE, size = 0;
void *p;
@@ -133,19 +133,19 @@
{
if( starting )
xmodem_out_func( 'C' );
- if( ( ( ch = xmodem_in_func( XMODEM_TIMEOUT ) ) == -1 ) || ( ch != SOH && ch != EOT && ch != CAN ) )
+ if( ( ( ch = xmodem_in_func( XMODEM_TIMEOUT ) ) == -1 ) || ( ch != XM_SOH && ch != XM_EOT && ch != XM_CAN ) )
continue;
- if( ch == EOT )
+ if( ch == XM_EOT )
{
// End of transmission
- xmodem_out_func( ACK );
+ xmodem_out_func( XM_ACK );
xmodem_flush( XMODEM_FLUSH_ONLY );
return size;
}
- else if( ch == CAN )
+ else if( ch == XM_CAN )
{
// The remote part ended the transmission
- xmodem_out_func( ACK );
+ xmodem_out_func( XM_ACK );
xmodem_flush( XMODEM_FLUSH_ONLY );
return XMODEM_ERROR_REMOTECANCEL;
}
@@ -159,25 +159,25 @@
packnum ++;
// Got a valid packet
- if( size + PACKET_SIZE > limit )
+ if( size + PXM_ACKET_SIZE > limit )
{
limit += XMODEM_INCREMENT_AMMOUNT;
if( ( p = realloc( *dest, limit ) ) == NULL )
{
// Not enough memory, force cancel and return
- xmodem_flush( XMODEM_FLUSH_AND_CAN );
+ xmodem_flush( XMODEM_FLUSH_AND_XM_CAN );
return XMODEM_ERROR_OUTOFMEM;
}
*dest = ( char* )p;
}
// Acknowledge and consume packet
- xmodem_out_func( ACK );
- memcpy( *dest + size, buf + 2, PACKET_SIZE );
- size += PACKET_SIZE;
+ xmodem_out_func( XM_ACK );
+ memcpy( *dest + size, buf + 2, PXM_ACKET_SIZE );
+ size += PXM_ACKET_SIZE;
}
// Exceeded retry count
- xmodem_flush( XMODEM_FLUSH_AND_CAN );
+ xmodem_flush( XMODEM_FLUSH_AND_XM_CAN );
return XMODEM_ERROR_RETRYEXCEED;
}
Added: branches/eagle_mmc/test/test-rpc.lua
===================================================================
--- branches/eagle_mmc/test/test-rpc.lua 2009-07-30 13:04:10 UTC (rev 370)
+++ branches/eagle_mmc/test/test-rpc.lua 2009-07-30 18:10:13 UTC (rev 371)
@@ -0,0 +1,51 @@
+function error_handler (message)
+ io.write ("MY ERROR: " .. message .. "\n");
+end
+
+rpc.on_error (error_handler);
+
+--slave,err = rpc.connect ("/dev/tty.usbserial-FTE3HV7L");
+slave,err = rpc.connect ("/dev/tty.usbserial-ftCYPMYJ");
+-- slave,err = rpc.connect("/dev/tty.usbserial-04110857B")
+--slave,err = rpc.connect ("/dev/ttys0");
+
+print("Platform: " .. slave.pd.platform())
+print("CPU: " .. slave.pd.cpu())
+print("Board: " .. slave.pd.board())
+print("CPU Clock: " .. slave.cpu.clock()/1000000 .. " MHz")
+
+function mirror( input ) return input end
+function squareval(x) return x*x end
+test_local = {1, 2, 3, 4, "234"}
+test_local.sval = 23
+
+slave.mirror = mirror
+
+-- reflect parameters off mirror
+-- also requires that function serialization works
+assert(slave.mirror(42) == 42, "integer return failed")
+assert(slave.mirror("The quick brown fox jumps over the lazy dog") == "The quick brown fox jumps over the lazy dog", "string return failed")
+assert(string.dump(slave.mirror(squareval)) == string.dump(squareval), "function return failed")
+assert(slave.mirror(true) == true, "bool return failed")
+
+slave.test = test_local
+
+-- get remote table
+assert(slave.test:get(), "couldn't get remote table")
+
+-- check that we can get entry on remote table
+assert(test_local.sval == slave.test:get().sval, "table field not equivalent")
+
+adc = slave.adc
+
+adc.setblocking(0,1)
+adc.setclock(0, 64 ,2)
+
+adc.sample(0,128)
+-- print(slave.collectgarbage("count"))
+for i=1,128 do
+ retsamp = adc.getsample(0)
+ if not (retsamp == nil) then
+ print(retsamp)
+ end
+end
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